bsp/ti_herc/reg_emif.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides EMIF interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from EMIF.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_EMIF
0050 #define LIBBSP_ARM_TMS570_EMIF
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t MIDR;              /*Module ID Register*/
0056   uint32_t AWCC;              /*Asynchronous Wait Cycle Configuration Register*/
0057   uint32_t SDCR;              /*SDRAM Configuration Register*/
0058   uint32_t SDRCR;             /*SDRAM Refresh Control Register*/
0059   uint32_t CE2CFG;            /*Asynchronous 1 Configuration Register*/
0060   uint32_t CE3CFG;            /*Asynchronous 2 Configuration Register*/
0061   uint32_t CE4CFG;            /*Asynchronous 3 Configuration Register*/
0062   uint32_t CE5CFG;            /*Asynchronous 4 Configuration Register*/
0063   uint32_t SDTIMR;            /*SDRAM Timing Register*/
0064   uint8_t reserved1 [24];
0065   uint32_t SDSRETR;           /*SDRAM Self Refresh Exit Timing Register*/
0066   uint32_t INTRAW;            /*EMIF Interrupt Raw Register*/
0067   uint32_t INTMSK;            /*EMIF Interrupt Mask Register*/
0068   uint32_t INTMSKSET;         /*EMIF Interrupt Mask Set Register*/
0069   uint32_t INTMSKCLR;         /*EMIF Interrupt Mask Clear Register*/
0070   uint8_t reserved2 [24];
0071   uint32_t PMCR;              /*Page Mode Control Register*/
0072 } tms570_emif_t;
0073
0074
0075 /*----------------------TMS570_EMIF_MIDR----------------------*/
0076 /* field: REV - Module ID of EMIF. See the device-specific data manual. */
0077 /* Whole 32 bits */
0078
0079 /*----------------------TMS570_EMIF_AWCC----------------------*/
0080 /* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
0081 #define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
0082
0083 /* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
0084 #define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
0085
0086 /* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
0087 #define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
0088 #define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23)
0089 #define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23)
0090
0091 /* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */
0092 #define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21)
0093 #define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21)
0094 #define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21)
0095
0096 /* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */
0097 #define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19)
0098 #define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19)
0099 #define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19)
0100
0101 /* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */
0102 #define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17)
0103 #define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17)
0104 #define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
0105
0106 /* field: MAX_EXT_WAIT - Maximum extended wait cycles. */
0107 #define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7)
0108 #define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7)
0109 #define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0110
0111
0112 /*----------------------TMS570_EMIF_SDCR----------------------*/
0113 /* field: SR - Self-Refresh mode bit. */
0114 #define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
0115
0116 /* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
0117 #define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
0118
0119 /* field: PDWR - Perform refreshes during power down. */
0120 #define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
0121
0122 /* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
0123 #define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
0124
0125 /* field: CL - CAS Latency. */
0126 #define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
0127 #define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11)
0128 #define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
0129
0130 /* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
0131 #define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
0132
0133 /* field: IBANK - Internal SDRAM Bank size. */
0134 #define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
0135 #define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6)
0136 #define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0137
0138 /* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */
0139 #define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2)
0140 #define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2)
0141 #define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0142
0143
0144 /*---------------------TMS570_EMIF_SDRCR---------------------*/
0145 /* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
0146 #define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
0147 #define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
0148 #define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
0149
0150
0151 /*---------------------TMS570_EMIF_CE2CFG---------------------*/
0152 /* field: SS - Select Strobe bit. */
0153 #define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
0154
0155 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
0156 #define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
0157
0158 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0159 #define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
0160 #define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
0161 #define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
0162
0163 /* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0164 #define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
0165 #define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
0166 #define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0167
0168 /* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0169 #define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
0170 #define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
0171 #define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
0172
0173 /* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0174 #define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
0175 #define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
0176 #define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
0177
0178 /* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0179 #define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
0180 #define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
0181 #define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
0182
0183 /* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0184 #define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
0185 #define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
0186 #define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0187
0188 /* field: TA - Minimum Turn-Around time. */
0189 #define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3)
0190 #define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
0191 #define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
0192
0193 /* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
0194 #define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1)
0195 #define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
0196 #define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0197
0198
0199 /*---------------------TMS570_EMIF_CE3CFG---------------------*/
0200 /* field: SS - Select Strobe bit. */
0201 #define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
0202
0203 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
0204 #define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
0205
0206 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0207 #define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
0208 #define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
0209 #define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
0210
0211 /* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0212 #define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
0213 #define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
0214 #define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0215
0216 /* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0217 #define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
0218 #define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
0219 #define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
0220
0221 /* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0222 #define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
0223 #define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
0224 #define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
0225
0226 /* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0227 #define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
0228 #define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
0229 #define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
0230
0231 /* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0232 #define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
0233 #define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
0234 #define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0235
0236 /* field: TA - Minimum Turn-Around time. */
0237 #define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3)
0238 #define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
0239 #define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
0240
0241 /* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
0242 #define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1)
0243 #define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
0244 #define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0245
0246
0247 /*---------------------TMS570_EMIF_CE4CFG---------------------*/
0248 /* field: SS - Select Strobe bit. */
0249 #define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
0250
0251 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
0252 #define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
0253
0254 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0255 #define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
0256 #define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
0257 #define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
0258
0259 /* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0260 #define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
0261 #define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
0262 #define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0263
0264 /* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0265 #define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
0266 #define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
0267 #define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
0268
0269 /* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0270 #define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
0271 #define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
0272 #define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
0273
0274 /* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0275 #define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
0276 #define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
0277 #define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
0278
0279 /* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0280 #define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
0281 #define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
0282 #define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0283
0284 /* field: TA - Minimum Turn-Around time. */
0285 #define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3)
0286 #define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
0287 #define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
0288
0289 /* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
0290 #define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1)
0291 #define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
0292 #define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0293
0294
0295 /*---------------------TMS570_EMIF_CE5CFG---------------------*/
0296 /* field: SS - Select Strobe bit. */
0297 #define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
0298
0299 /* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
0300 #define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
0301
0302 /* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0303 #define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
0304 #define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
0305 #define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
0306
0307 /* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0308 #define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
0309 #define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
0310 #define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
0311
0312 /* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0313 #define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
0314 #define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
0315 #define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
0316
0317 /* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0318 #define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
0319 #define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
0320 #define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
0321
0322 /* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0323 #define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
0324 #define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
0325 #define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
0326
0327 /* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
0328 #define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
0329 #define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
0330 #define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0331
0332 /* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */
0333 #define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3)
0334 #define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
0335 #define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
0336
0337 /* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
0338 #define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1)
0339 #define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
0340 #define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0341
0342
0343 /*---------------------TMS570_EMIF_SDTIMR---------------------*/
0344 /* field: T_RFC - Specifies the Trfc value of the SDRAM. */
0345 #define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
0346 #define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
0347 #define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31)
0348
0349 /* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */
0350 #define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26)
0351 #define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26)
0352 #define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
0353
0354 /* field: T_RCD - Specifies the Trcd value of the SDRAM. */
0355 #define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22)
0356 #define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22)
0357 #define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
0358
0359 /* field: T_WR - Specifies the Twr value of the SDRAM. */
0360 #define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18)
0361 #define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18)
0362 #define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0363
0364 /* field: T_RAS - Specifies the Tras value of the SDRAM. */
0365 #define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15)
0366 #define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15)
0367 #define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
0368
0369 /* field: T_RC - Specifies the Trc value of the SDRAM. */
0370 #define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11)
0371 #define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11)
0372 #define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
0373
0374 /* field: T_RRD - Specifies the Trrd value of the SDRAM. */
0375 #define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6)
0376 #define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6)
0377 #define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0378
0379
0380 /*--------------------TMS570_EMIF_SDSRETR--------------------*/
0381 /* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
0382 #define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
0383 #define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
0384 #define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0385
0386
0387 /*---------------------TMS570_EMIF_INTRAW---------------------*/
0388 /* field: WR - Wait Rise. */
0389 #define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
0390
0391 /* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
0392 #define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
0393
0394 /* field: AT - Asynchronous Timeout. */
0395 #define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
0396
0397
0398 /*---------------------TMS570_EMIF_INTMSK---------------------*/
0399 /* field: WR_MASKED - Wait Rise Masked. */
0400 #define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
0401
0402 /* field: LT_MASKED - Masked Line Trap. */
0403 #define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
0404
0405 /* field: AT_MASKED - Asynchronous Timeout Masked. */
0406 #define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
0407
0408
0409 /*-------------------TMS570_EMIF_INTMSKSET-------------------*/
0410 /* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
0411 #define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
0412
0413 /* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
0414 #define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
0415
0416 /* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
0417 #define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
0418
0419
0420 /*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
0421 /* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
0422 #define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
0423
0424 /* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
0425 #define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
0426
0427 /* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
0428 #define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
0429
0430
0431 /*----------------------TMS570_EMIF_PMCR----------------------*/
0432 /* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
0433 #define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
0434 #define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
0435 #define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
0436
0437 /* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
0438 #define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
0439
0440 /* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
0441 #define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
0442
0443 /* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
0444 #define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
0445 #define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23)
0446 #define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
0447
0448 /* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
0449 #define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
0450
0451 /* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
0452 #define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
0453
0454 /* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
0455 #define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
0456 #define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15)
0457 #define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
0458
0459 /* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
0460 #define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
0461
0462 /* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
0463 #define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
0464
0465 /* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
0466 #define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
0467 #define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7)
0468 #define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
0469
0470 /* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
0471 #define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
0472
0473 /* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
0474 #define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
0475
0476
0477
0478 #endif /* LIBBSP_ARM_TMS570_EMIF */