bsp/ti_herc/reg_emacm.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides EMACM interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from EMACM.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_EMACM
0050 #define LIBBSP_ARM_TMS570_EMACM
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t TXREVID;           /*Transmit Revision ID Register*/
0056   uint32_t TXCONTROL;         /*Transmit Control Register*/
0057   uint32_t TXTEARDOWN;        /*Transmit Teardown Register*/
0058   uint8_t reserved1 [4];
0059   uint32_t RXREVID;           /*Receive Revision ID Register*/
0060   uint32_t RXCONTROL;         /*Receive Control Register*/
0061   uint32_t RXTEARDOWN;        /*Receive Teardown Register*/
0062   uint8_t reserved2 [100];
0063   uint32_t TXINTSTATRAW;      /*Transmit Interrupt Status (Unmasked) Register*/
0064   uint32_t TXINTSTATMASKED;   /*Transmit Interrupt Status (Masked) Register*/
0065   uint32_t TXINTMASKSET;      /*Transmit Interrupt Mask Set Register*/
0066   uint32_t TXINTMASKCLEAR;    /*Transmit Interrupt Clear Register*/
0067   uint32_t MACINVECTOR;       /*MAC Input Vector Register*/
0068   uint32_t MACEOIVECTOR;      /*MAC End Of Interrupt Vector Register*/
0069   uint8_t reserved3 [8];
0070   uint32_t RXINTSTATRAW;      /*Receive Interrupt Status (Unmasked) Register*/
0071   uint32_t RXINTSTATMASKED;   /*Receive Interrupt Status (Masked) Register*/
0072   uint32_t RXINTMASKSET;      /*Receive Interrupt Mask Set Register*/
0073   uint32_t RXINTMASKCLEAR;    /*Receive Interrupt Mask Clear Register*/
0074   uint32_t MACINTSTATRAW;     /*MAC Interrupt Status (Unmasked) Register*/
0075   uint32_t MACINTSTATMASKED;  /*MAC Interrupt Status (Masked) Register*/
0076   uint32_t MACINTMASKSET;     /*MAC Interrupt Mask Set Register*/
0077   uint32_t MACINTMASKCLEAR;   /*MAC Interrupt Mask Clear Register*/
0078   uint8_t reserved4 [64];
0079   uint32_t RXMBPENABLE;       /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/
0080   uint32_t RXUNICASTSET;      /*Receive Unicast Enable Set Register*/
0081   uint32_t RXUNICASTCLEAR;    /*Receive Unicast Clear Register*/
0082   uint32_t RXMAXLEN;          /*Receive Maximum Length Register*/
0083   uint32_t RXBUFFEROFFSET;    /*Receive Buffer Offset Register*/
0084   uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/
0085   uint8_t reserved5 [8];
0086   uint32_t RXFLOWTHRESH[8];   /*Receive Channel Flow Control Threshold Register*/
0087   uint32_t RXFREEBUFFER[8];   /*Receive Channel Free Buffer Count Register*/
0088   uint32_t MACCONTROL;        /*MAC Control Register*/
0089   uint32_t MACSTATUS;         /*MAC Status Register*/
0090   uint32_t EMCONTROL;         /*Emulation Control Register*/
0091   uint32_t FIFOCONTROL;       /*FIFO Control Register*/
0092   uint32_t MACCONFIG;         /*MAC Configuration Register*/
0093   uint32_t SOFTRESET;         /*Soft Reset Register*/
0094   uint8_t reserved6 [88];
0095   uint32_t MACSRCADDRLO;      /*MAC Source Address Low Bytes Register*/
0096   uint32_t MACSRCADDRHI;      /*MAC Source Address High Bytes Register*/
0097   uint32_t MACHASH1;          /*MAC Hash Address Register 1*/
0098   uint32_t MACHASH2;          /*MAC Hash Address Register 2*/
0099   uint32_t BOFFTEST;          /*Back Off Test Register*/
0100   uint32_t TPACETEST;         /*Transmit Pacing Algorithm Test Register*/
0101   uint32_t RXPAUSE;           /*Receive Pause Timer Register*/
0102   uint32_t TXPAUSE;           /*Transmit Pause Timer Register*/
0103   uint8_t reserved7 [784];
0104   uint32_t MACADDRLO;         /*MAC Address Low Bytes Register*/
0105   uint32_t MACADDRHI;         /*MAC Address High Bytes Register*/
0106   uint32_t MACINDEX;          /*MAC Index Register*/
0107   uint8_t reserved8 [244];
0108   uint32_t TXHDP[8];          /*Transmit Channel DMA Head Descriptor Pointer Register*/
0109   uint32_t RXHDP[8];          /*Receive Channel DMA Head Descriptor Pointer Register*/
0110   uint32_t TXCP[8];           /*Transmit Channel Completion Pointer Register*/
0111   uint32_t RXCP[8];           /*Receive Channel Completion Pointer Register*/
0112 } tms570_emacm_t;
0113
0114
0115 /*--------------------TMS570_EMACM_TXREVID--------------------*/
0116 /* field: TXREV - Transmit module revision */
0117 /* Whole 32 bits */
0118
0119 /*-------------------TMS570_EMACM_TXCONTROL-------------------*/
0120 /* field: TXEN - Transmit enable */
0121 #define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
0122
0123
0124 /*------------------TMS570_EMACM_TXTEARDOWN------------------*/
0125 /* field: TXTDNCH - Transmit teardown channel. */
0126 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
0127 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
0128 #define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0129
0130
0131 /*--------------------TMS570_EMACM_RXREVID--------------------*/
0132 /* field: RXREV - Receive module revision */
0133 /* Whole 32 bits */
0134
0135 /*-------------------TMS570_EMACM_RXCONTROL-------------------*/
0136 /* field: RXEN - Receive enable */
0137 #define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
0138
0139
0140 /*------------------TMS570_EMACM_RXTEARDOWN------------------*/
0141 /* field: RXTDNCH - Receive teardown channel. */
0142 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
0143 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
0144 #define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0145
0146
0147 /*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
0148 /* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
0149 #define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
0150
0151 /* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
0152 #define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
0153
0154 /* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
0155 #define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
0156
0157 /* field: TX4PEND - X4PEND raw interrupt read (before mask) */
0158 #define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
0159
0160 /* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
0161 #define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
0162
0163 /* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
0164 #define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
0165
0166 /* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
0167 #define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
0168
0169 /* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
0170 #define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
0171
0172
0173 /*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
0174 /* field: TX7PEND - TX7PEND masked interrupt read */
0175 #define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
0176
0177 /* field: TX6PEND - TX6PEND masked interrupt read */
0178 #define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
0179
0180 /* field: TX5PEND - TX5PEND masked interrupt read */
0181 #define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
0182
0183 /* field: TX4PEND - TX4PEND masked interrupt read */
0184 #define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
0185
0186 /* field: TX3PEND - TX3PEND masked interrupt read */
0187 #define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
0188
0189 /* field: TX2PEND - TX2PEND masked interrupt read */
0190 #define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
0191
0192 /* field: TX1PEND - TX1PEND masked interrupt read */
0193 #define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
0194
0195 /* field: TX0PEND - TX0PEND masked interrupt read */
0196 #define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
0197
0198
0199 /*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
0200 /* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0201 #define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
0202
0203 /* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0204 #define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
0205
0206 /* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0207 #define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
0208
0209 /* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0210 #define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
0211
0212 /* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0213 #define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
0214
0215 /* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0216 #define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
0217
0218 /* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0219 #define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
0220
0221 /* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0222 #define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
0223
0224
0225 /*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
0226 /* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0227 #define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
0228
0229 /* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0230 #define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
0231
0232 /* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0233 #define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
0234
0235 /* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0236 #define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
0237
0238 /* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0239 #define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
0240
0241 /* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0242 #define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
0243
0244 /* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0245 #define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
0246
0247 /* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0248 #define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
0249
0250
0251 /*------------------TMS570_EMACM_MACINVECTOR------------------*/
0252 /* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
0253 #define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
0254
0255 /* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
0256 #define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
0257
0258 /* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
0259 #define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
0260
0261 /* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
0262 #define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
0263
0264 /* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
0265 #define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
0266 #define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23)
0267 #define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0268
0269 /* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */
0270 #define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15)
0271 #define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15)
0272 #define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0273
0274 /* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */
0275 #define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7)
0276 #define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7)
0277 #define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0278
0279
0280 /*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
0281 /* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
0282 #define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
0283 #define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
0284 #define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0285
0286
0287 /*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
0288 /* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
0289 #define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
0290
0291 /* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
0292 #define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
0293
0294 /* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
0295 #define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
0296
0297 /* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
0298 #define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
0299
0300 /* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
0301 #define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
0302
0303 /* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
0304 #define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
0305
0306 /* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
0307 #define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
0308
0309 /* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
0310 #define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
0311
0312 /* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
0313 #define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
0314
0315 /* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
0316 #define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
0317
0318 /* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
0319 #define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
0320
0321 /* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
0322 #define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
0323
0324 /* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
0325 #define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
0326
0327 /* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
0328 #define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
0329
0330 /* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
0331 #define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
0332
0333 /* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
0334 #define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
0335
0336
0337 /*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
0338 /* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
0339 #define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
0340
0341 /* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
0342 #define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
0343
0344 /* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
0345 #define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
0346
0347 /* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
0348 #define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
0349
0350 /* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
0351 #define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
0352
0353 /* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
0354 #define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
0355
0356 /* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
0357 #define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
0358
0359 /* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
0360 #define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
0361
0362 /* field: RX7PEND - RX7PEND masked interrupt read */
0363 #define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
0364
0365 /* field: RX6PEND - RX6PEND masked interrupt read */
0366 #define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
0367
0368 /* field: RX5PEND - RX5PEND masked interrupt read */
0369 #define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
0370
0371 /* field: RX4PEND - RX4PEND masked interrupt read */
0372 #define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
0373
0374 /* field: RX3PEND - RX3PEND masked interrupt read */
0375 #define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
0376
0377 /* field: RX2PEND - RX2PEND masked interrupt read */
0378 #define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
0379
0380 /* field: RX1PEND - RX1PEND masked interrupt read */
0381 #define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
0382
0383 /* field: RX0PEND - RX0PEND masked interrupt read */
0384 #define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
0385
0386
0387 /*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
0388 /* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0389 #define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
0390
0391 /* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0392 #define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
0393
0394 /* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0395 #define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
0396
0397 /* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0398 #define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
0399
0400 /* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0401 #define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
0402
0403 /* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0404 #define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
0405
0406 /* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0407 #define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
0408
0409 /* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0410 #define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
0411
0412 /* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0413 #define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
0414
0415 /* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0416 #define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
0417
0418 /* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0419 #define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
0420
0421 /* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0422 #define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
0423
0424 /* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0425 #define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
0426
0427 /* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0428 #define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
0429
0430 /* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0431 #define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
0432
0433 /* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
0434 #define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
0435
0436
0437 /*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
0438 /* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
0439 #define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
0440
0441 /* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
0442 #define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
0443
0444 /* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
0445 #define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
0446
0447 /* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
0448 #define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
0449
0450 /* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
0451 #define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
0452
0453 /* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
0454 #define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
0455
0456 /* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
0457 #define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
0458
0459 /* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
0460 #define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
0461
0462 /* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0463 #define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
0464
0465 /* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0466 #define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
0467
0468 /* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0469 #define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
0470
0471 /* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0472 #define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
0473
0474 /* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0475 #define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
0476
0477 /* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0478 #define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
0479
0480 /* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0481 #define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
0482
0483 /* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
0484 #define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
0485
0486
0487 /*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
0488 /* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
0489 #define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
0490
0491 /* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
0492 #define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
0493
0494
0495 /*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
0496 /* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
0497 #define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
0498
0499 /* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
0500 #define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
0501
0502
0503 /*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
0504 /* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0505 #define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
0506
0507 /* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
0508 #define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
0509
0510
0511 /*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
0512 /* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0513 #define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
0514
0515 /* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
0516 #define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
0517
0518
0519 /*------------------TMS570_EMACM_RXMBPENABLE------------------*/
0520 /* field: RXPASSCRC - Pass receive CRC enable bit */
0521 #define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
0522
0523 /* field: RXQOSEN - Receive quality of service enable bit */
0524 #define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
0525
0526 /* field: RXNOCHAIN - Receive no buffer chaining bit */
0527 #define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
0528
0529 /* field: RXCMFEN - Receive copy MAC control frames enable bit. */
0530 #define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
0531
0532 /* field: RXCSFEN - Receive copy short frames enable bit. */
0533 #define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
0534
0535 /* field: RXCEFEN - Receive copy error frames enable bit. */
0536 #define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
0537
0538 /* field: RXCAFEN - Receive copy all frames enable bit. */
0539 #define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
0540
0541 /* field: RXPROMCH - Receive promiscuous channel select */
0542 #define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
0543 #define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18)
0544 #define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0545
0546 /* field: RXBROADEN - Receive broadcast enable. */
0547 #define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
0548
0549 /* field: RXBROADCH - Receive broadcast channel select */
0550 #define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
0551 #define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10)
0552 #define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0553
0554 /* field: RXMULTEN - RX multicast enable. */
0555 #define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
0556
0557
0558 /*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
0559 /* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0560 #define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
0561
0562 /* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0563 #define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
0564
0565 /* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0566 #define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
0567
0568 /* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0569 #define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
0570
0571 /* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0572 #define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
0573
0574 /* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0575 #define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
0576
0577 /* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0578 #define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
0579
0580 /* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
0581 #define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
0582
0583
0584 /*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
0585 /* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0586 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
0587
0588 /* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0589 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
0590
0591 /* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0592 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
0593
0594 /* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0595 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
0596
0597 /* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0598 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
0599
0600 /* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0601 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
0602
0603 /* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0604 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
0605
0606 /* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
0607 #define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
0608
0609
0610 /*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
0611 /* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
0612 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
0613 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
0614 #define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0615
0616
0617 /*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
0618 /* field: RXBUFFEROFFSET - Receive buffer offset value. */
0619 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
0620 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
0621 #define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0622
0623
0624 /*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
0625 /* field: RXFILTERTHRESH - Receive filter low threshold. */
0626 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
0627 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
0628 #define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0629
0630
0631 /*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
0632 /* field: RXnFLOWTHRESH - Receive flow threshold. */
0633 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
0634 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
0635 #define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0636
0637
0638 /*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
0639 /* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
0640 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
0641 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
0642 #define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0643
0644
0645 /*------------------TMS570_EMACM_MACCONTROL------------------*/
0646 /* field: RMIISPEED - RMII interface transmit and receive speed select. */
0647 #define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
0648
0649 /* field: RXOFFLENBLOCK - Receive offset / length word write block. */
0650 #define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
0651
0652 /* field: RXOWNERSHIP - Receive ownership write bit value. */
0653 #define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
0654
0655 /* field: CMDIDLE - Command Idle bit */
0656 #define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
0657
0658 /* field: TXSHORTGAPEN - Transmit Short Gap Enable */
0659 #define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
0660
0661 /* field: TXPTYPE - Transmit queue priority type */
0662 #define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
0663
0664 /* field: TXPACE - Transmit pacing enable bit */
0665 #define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
0666
0667 /* field: GMIIEN - GMII enable bit */
0668 #define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
0669
0670 /* field: TXFLOWEN - Transmit flow control enable bit. */
0671 #define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
0672
0673 /* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
0674 #define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
0675
0676 /* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
0677 #define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
0678
0679 /* field: FULLDUPLEX - Full duplex mode. */
0680 #define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
0681
0682
0683 /*-------------------TMS570_EMACM_MACSTATUS-------------------*/
0684 /* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
0685 #define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
0686
0687 /* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
0688 #define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
0689 #define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23)
0690 #define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
0691
0692 /* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */
0693 #define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18)
0694 #define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18)
0695 #define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0696
0697 /* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */
0698 #define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15)
0699 #define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15)
0700 #define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
0701
0702 /* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */
0703 #define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10)
0704 #define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10)
0705 #define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0706
0707 /* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
0708 #define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
0709
0710 /* field: RXFLOWACT - Receive flow control active bit. */
0711 #define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
0712
0713 /* field: TXFLOWACT - Transmit flow control active bit. */
0714 #define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
0715
0716
0717 /*-------------------TMS570_EMACM_EMCONTROL-------------------*/
0718 /* field: SOFT - Emulation soft bit. */
0719 #define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
0720
0721 /* field: FREE - Emulation free bit. */
0722 #define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
0723
0724
0725 /*------------------TMS570_EMACM_FIFOCONTROL------------------*/
0726 /* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
0727 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
0728 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
0729 #define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
0730
0731
0732 /*-------------------TMS570_EMACM_MACCONFIG-------------------*/
0733 /* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
0734 #define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
0735 #define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
0736 #define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0737
0738 /* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */
0739 #define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23)
0740 #define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23)
0741 #define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0742
0743 /* field: ADDRESSTYPE - Address type */
0744 #define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15)
0745 #define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
0746 #define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0747
0748 /* field: MACCFIG - MAC configuration value */
0749 #define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7)
0750 #define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7)
0751 #define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0752
0753
0754 /*-------------------TMS570_EMACM_SOFTRESET-------------------*/
0755 /* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
0756 #define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
0757
0758
0759 /*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
0760 /* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
0761 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
0762 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
0763 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0764
0765 /* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */
0766 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7)
0767 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
0768 #define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0769
0770
0771 /*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
0772 /* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
0773 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
0774 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
0775 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0776
0777 /* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */
0778 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23)
0779 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
0780 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0781
0782 /* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */
0783 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15)
0784 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
0785 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0786
0787 /* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */
0788 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7)
0789 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
0790 #define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0791
0792
0793 /*-------------------TMS570_EMACM_MACHASH1-------------------*/
0794 /* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
0795 /* Whole 32 bits */
0796
0797 /*-------------------TMS570_EMACM_MACHASH2-------------------*/
0798 /* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
0799 /* Whole 32 bits */
0800
0801 /*-------------------TMS570_EMACM_BOFFTEST-------------------*/
0802 /* field: RNDNUM - Backoff random number generator. */
0803 #define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
0804 #define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
0805 #define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
0806
0807 /* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */
0808 #define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15)
0809 #define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15)
0810 #define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
0811
0812 /* field: TXBACKOFF - Backoff count. */
0813 #define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9)
0814 #define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9)
0815 #define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0816
0817
0818 /*-------------------TMS570_EMACM_TPACETEST-------------------*/
0819 /* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
0820 #define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
0821 #define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
0822 #define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0823
0824
0825 /*--------------------TMS570_EMACM_RXPAUSE--------------------*/
0826 /* field: PAUSETIMER - Receive pause timer value. */
0827 #define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
0828 #define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
0829 #define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0830
0831
0832 /*--------------------TMS570_EMACM_TXPAUSE--------------------*/
0833 /* field: PAUSETIMER - Transmit pause timer value. */
0834 #define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
0835 #define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
0836 #define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0837
0838
0839 /*-------------------TMS570_EMACM_MACADDRLO-------------------*/
0840 /* field: VALID - Address valid bit. */
0841 #define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
0842
0843 /* field: MATCHFILT - Match or filter bit */
0844 #define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
0845
0846 /* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
0847 #define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
0848 #define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18)
0849 #define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0850
0851 /* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */
0852 #define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15)
0853 #define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
0854 #define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0855
0856 /* field: MACADDR1 - MAC address bits 15-8 (byte 1) */
0857 #define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7)
0858 #define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
0859 #define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0860
0861
0862 /*-------------------TMS570_EMACM_MACADDRHI-------------------*/
0863 /* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
0864 #define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
0865 #define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
0866 #define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
0867
0868 /* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */
0869 #define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23)
0870 #define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
0871 #define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
0872
0873 /* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */
0874 #define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15)
0875 #define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
0876 #define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0877
0878 /* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */
0879 #define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7)
0880 #define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
0881 #define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
0882
0883
0884 /*-------------------TMS570_EMACM_MACINDEX-------------------*/
0885 /* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
0886 #define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
0887 #define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
0888 #define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0889
0890
0891 /*---------------------TMS570_EMACM_TXHDP---------------------*/
0892 /* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
0893 /* Whole 32 bits */
0894
0895 /*---------------------TMS570_EMACM_RXHDP---------------------*/
0896 /* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
0897 /* Whole 32 bits */
0898
0899 /*---------------------TMS570_EMACM_TXCP---------------------*/
0900 /* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
0901 /* Whole 32 bits */
0902
0903 /*---------------------TMS570_EMACM_RXCP---------------------*/
0904 /* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
0905 /* Whole 32 bits */
0906
0907
0908 #endif /* LIBBSP_ARM_TMS570_EMACM */