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File indexing completed on 2025-05-11 08:23:38
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @ingroup RTEMSBSPsARMTMS570 0007 * 0008 * @brief This header file provides EMACC interfaces. 0009 */ 0010 0011 /* The header file is generated by make_header.py from EMACC.json */ 0012 /* Current script's version can be found at: */ 0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ 0014 0015 /* 0016 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> 0017 * 0018 * Czech Technical University in Prague 0019 * Zikova 1903/4 0020 * 166 36 Praha 6 0021 * Czech Republic 0022 * 0023 * All rights reserved. 0024 * 0025 * Redistribution and use in source and binary forms, with or without 0026 * modification, are permitted provided that the following conditions are met: 0027 * 0028 * 1. Redistributions of source code must retain the above copyright notice, this 0029 * list of conditions and the following disclaimer. 0030 * 2. Redistributions in binary form must reproduce the above copyright notice, 0031 * this list of conditions and the following disclaimer in the documentation 0032 * and/or other materials provided with the distribution. 0033 * 0034 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 0035 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 0036 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 0037 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 0038 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 0039 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 0040 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 0041 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 0042 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 0043 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0044 * 0045 * The views and conclusions contained in the software and documentation are those 0046 * of the authors and should not be interpreted as representing official policies, 0047 * either expressed or implied, of the FreeBSD Project. 0048 */ 0049 #ifndef LIBBSP_ARM_TMS570_EMACC 0050 #define LIBBSP_ARM_TMS570_EMACC 0051 0052 #include <bsp/utility.h> 0053 0054 typedef struct{ 0055 uint32_t REVID; /*EMAC Control Module Revision ID Register*/ 0056 uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/ 0057 uint8_t reserved1 [4]; 0058 uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/ 0059 uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/ 0060 uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ 0061 uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ 0062 uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/ 0063 uint8_t reserved2 [32]; 0064 uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/ 0065 uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/ 0066 uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/ 0067 uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/ 0068 uint8_t reserved3 [32]; 0069 uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/ 0070 uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/ 0071 } tms570_emacc_t; 0072 0073 0074 /*---------------------TMS570_EMACC_REVID---------------------*/ 0075 /* field: REV - Identifies the EMAC Control Module revision. */ 0076 /* Whole 32 bits */ 0077 0078 /*-------------------TMS570_EMACC_SOFTRESET-------------------*/ 0079 /* field: RESET - Software reset bit for the EMAC Control Module. */ 0080 #define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0) 0081 0082 0083 /*------------------TMS570_EMACC_INTCONTROL------------------*/ 0084 /* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */ 0085 #define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17) 0086 0087 /* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */ 0088 #define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16) 0089 0090 /* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */ 0091 #define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11) 0092 #define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11) 0093 #define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11) 0094 0095 0096 /*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/ 0097 /* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */ 0098 #define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7) 0099 0100 /* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */ 0101 #define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6) 0102 0103 /* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */ 0104 #define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5) 0105 0106 /* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */ 0107 #define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4) 0108 0109 /* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */ 0110 #define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3) 0111 0112 /* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */ 0113 #define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2) 0114 0115 /* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */ 0116 #define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1) 0117 0118 /* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */ 0119 #define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0) 0120 0121 0122 /*--------------------TMS570_EMACC_C0RXEN--------------------*/ 0123 /* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */ 0124 #define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7) 0125 0126 /* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */ 0127 #define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6) 0128 0129 /* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */ 0130 #define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5) 0131 0132 /* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */ 0133 #define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4) 0134 0135 /* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */ 0136 #define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3) 0137 0138 /* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */ 0139 #define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2) 0140 0141 /* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */ 0142 #define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1) 0143 0144 /* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */ 0145 #define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0) 0146 0147 0148 /*--------------------TMS570_EMACC_C0TXEN--------------------*/ 0149 /* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */ 0150 #define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7) 0151 0152 /* field: TXCH6EN - TXCH6EN */ 0153 #define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6) 0154 0155 /* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */ 0156 #define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5) 0157 0158 /* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */ 0159 #define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4) 0160 0161 /* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */ 0162 #define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3) 0163 0164 /* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */ 0165 #define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2) 0166 0167 /* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */ 0168 #define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1) 0169 0170 /* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */ 0171 #define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0) 0172 0173 0174 /*-------------------TMS570_EMACC_C0MISCEN-------------------*/ 0175 /* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */ 0176 #define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3) 0177 0178 /* field: HOSTPENDEN - HOSTPENDEN */ 0179 #define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2) 0180 0181 /* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */ 0182 #define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1) 0183 0184 /* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */ 0185 #define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0) 0186 0187 0188 /*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/ 0189 /* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */ 0190 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7) 0191 0192 /* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */ 0193 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6) 0194 0195 /* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */ 0196 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5) 0197 0198 /* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */ 0199 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4) 0200 0201 /* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */ 0202 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3) 0203 0204 /* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */ 0205 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2) 0206 0207 /* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */ 0208 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1) 0209 0210 /* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */ 0211 #define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0) 0212 0213 0214 /*-------------------TMS570_EMACC_C0RXSTAT-------------------*/ 0215 /* field: RXCH7STAT - RXCH7STAT */ 0216 #define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7) 0217 0218 /* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */ 0219 #define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6) 0220 0221 /* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */ 0222 #define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5) 0223 0224 /* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */ 0225 #define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4) 0226 0227 /* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */ 0228 #define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3) 0229 0230 /* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */ 0231 #define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2) 0232 0233 /* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */ 0234 #define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1) 0235 0236 /* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */ 0237 #define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0) 0238 0239 0240 /*-------------------TMS570_EMACC_C0TXSTAT-------------------*/ 0241 /* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */ 0242 #define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7) 0243 0244 /* field: TXCH6STAT - TXCH6STAT */ 0245 #define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6) 0246 0247 /* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */ 0248 #define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5) 0249 0250 /* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */ 0251 #define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4) 0252 0253 /* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */ 0254 #define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3) 0255 0256 /* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */ 0257 #define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2) 0258 0259 /* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */ 0260 #define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1) 0261 0262 /* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */ 0263 #define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0) 0264 0265 0266 /*------------------TMS570_EMACC_C0MISCSTAT------------------*/ 0267 /* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */ 0268 #define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3) 0269 0270 /* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */ 0271 #define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2) 0272 0273 /* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */ 0274 #define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1) 0275 0276 /* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */ 0277 #define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0) 0278 0279 0280 /*-------------------TMS570_EMACC_C0RXIMAX-------------------*/ 0281 /* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */ 0282 #define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5) 0283 #define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) 0284 #define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) 0285 0286 0287 /*-------------------TMS570_EMACC_C0TXIMAX-------------------*/ 0288 /* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */ 0289 #define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5) 0290 #define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5) 0291 #define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5) 0292 0293 0294 0295 #endif /* LIBBSP_ARM_TMS570_EMACC */
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