bsp/ti_herc/reg_dmm.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides DMM interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from DMM.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_DMM
0050 #define LIBBSP_ARM_TMS570_DMM
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t GLBCTRL;           /*DMM Global Control Register*/
0056   uint32_t INTSET;            /*DMM Interrupt Set Register*/
0057   uint32_t INTCLR;            /*DMM Interrupt Clear Register*/
0058   uint32_t INTLVL;            /*DMM Interrupt Level Register*/
0059   uint32_t INTFLG;            /*DMM Interrupt Flag Register*/
0060   uint32_t OFF1;              /*DMM Interrupt Offset 1 Register*/
0061   uint32_t OFF2;              /*DMM Interrupt Offset 2 Register*/
0062   uint32_t DDMDEST;           /*DMM Direct Data Mode Destination Register*/
0063   uint32_t DDMBL;             /*DMM Direct Data Mode Blocksize Register*/
0064   uint32_t DDMPT;             /*DMM Direct Data Mode Pointer Register*/
0065   uint32_t INTPT;             /*DMM Direct Data Mode Interrupt Pointer Register*/
0066   uint32_t DEST0REG1;         /*DMM Destination 0 Region 1*/
0067   uint32_t DEST0BL1;          /*DMM Destination 0 Blocksize 1*/
0068   uint32_t DEST0REG2;         /*DMM Destination 0 Region 2*/
0069   uint32_t DEST0BL2;          /*DMM Destination 0 Blocksize 2*/
0070   uint32_t DEST1REG1;         /*DMM Destination 1 Region 1*/
0071   uint32_t DEST1BL1;          /*DMM Destination 1 Blocksize 1*/
0072   uint32_t DEST1REG2;         /*DMM Destination 1 Region 2*/
0073   uint32_t DEST1BL2;          /*DMM Destination 1 Blocksize 2*/
0074   uint32_t DEST2REG1;         /*DMM Destination 2 Region 1*/
0075   uint32_t DEST2BL1;          /*DMM Destination 2 Blocksize 1*/
0076   uint32_t DEST2REG2;         /*DMM Destination 2 Region 2*/
0077   uint32_t DEST2BL2;          /*DMM Destination 2 Blocksize 2*/
0078   uint32_t DEST3REG1;         /*DMM Destination 3 Region 1*/
0079   uint32_t DEST3BL1;          /*DMM Destination 3 Blocksize 1*/
0080   uint32_t DEST3REG2;         /*DMM Destination 3 Region 2*/
0081   uint32_t DEST3BL2;          /*DMM Destination 3 Blocksize 2*/
0082   uint32_t PC0;               /*DMM Pin Control 0*/
0083   uint32_t PC1;               /*DMM Pin Control 1*/
0084   uint32_t PC2;               /*DMM Pin Control 2*/
0085   uint32_t PC3;               /*DMM Pin Control 3*/
0086   uint32_t PC4;               /*DMM Pin Control 4*/
0087   uint32_t PC5;               /*DMM Pin Control 5*/
0088   uint32_t PC6;               /*DMM Pin Control 6*/
0089   uint32_t PC7;               /*DMM Pin Control 7*/
0090   uint32_t PC8;               /*DMM Pin Control 8*/
0091 } tms570_dmm_t;
0092
0093
0094 /*---------------------TMS570_DMM_GLBCTRL---------------------*/
0095 /* field: BUSY - Busy indicator. */
0096 #define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24)
0097
0098 /* field: CONTCLK - Continuous DMMCLK input. */
0099 #define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18)
0100
0101 /* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
0102 #define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17)
0103
0104 /* field: RESET - Reset. */
0105 #define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16)
0106
0107 /* field: DDM_WIDTH - Packet Width in direct data mode. */
0108 #define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10)
0109 #define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10)
0110 #define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
0111
0112 /* field: TM_DMM - Packet Format. */
0113 #define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8)
0114
0115 /* field: ON_OFF - Switch module on or off */
0116 #define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
0117 #define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
0118 #define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0119
0120
0121 /*---------------------TMS570_DMM_INTSET---------------------*/
0122 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
0123 #define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17)
0124
0125 /* field: EO_BUFF - EO_BUFF */
0126 #define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16)
0127
0128 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
0129 #define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15)
0130
0131 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
0132 #define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14)
0133
0134 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
0135 #define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13)
0136
0137 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
0138 #define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12)
0139
0140 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
0141 #define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11)
0142
0143 /* field: DEST1REG1 - DEST1REG1 */
0144 #define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10)
0145
0146 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
0147 #define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9)
0148
0149 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
0150 #define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8)
0151
0152 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
0153 #define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7)
0154
0155 /* field: BUFF_OVF - Buffer Overflow. */
0156 #define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6)
0157
0158 /* field: SRC_OVF - Source Overflow. */
0159 #define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5)
0160
0161 /* field: DEST3_ERR - Destination 3 Error. */
0162 #define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4)
0163
0164 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
0165 #define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3)
0166
0167 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
0168 #define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2)
0169
0170 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
0171 #define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1)
0172
0173 /* field: PACKET_ERR_INT - Packet Error. */
0174 #define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0)
0175
0176
0177 /*---------------------TMS570_DMM_INTCLR---------------------*/
0178 /* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
0179 #define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17)
0180
0181 /* field: EO_BUFF - End of Buffer Interrupt Set. */
0182 #define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16)
0183
0184 /* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
0185 #define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15)
0186
0187 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
0188 #define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14)
0189
0190 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
0191 #define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13)
0192
0193 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
0194 #define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12)
0195
0196 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
0197 #define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11)
0198
0199 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
0200 #define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10)
0201
0202 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
0203 #define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9)
0204
0205 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
0206 #define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8)
0207
0208 /* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
0209 #define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7)
0210
0211 /* field: BUFF_OVF - Buffer Overflow. */
0212 #define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6)
0213
0214 /* field: SRC_OVF - Source Overflow. */
0215 #define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5)
0216
0217 /* field: DEST3_ERR - Destination 3 Error. */
0218 #define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4)
0219
0220 /* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
0221 #define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3)
0222
0223 /* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
0224 #define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2)
0225
0226 /* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
0227 #define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1)
0228
0229 /* field: PACKET_ERR_INT - Packet Error. */
0230 #define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0)
0231
0232
0233 /*---------------------TMS570_DMM_INTLVL---------------------*/
0234 /* field: PROG_BUFF - Programmable Buffer Interrupt Level */
0235 #define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17)
0236
0237 /* field: EO_BUFF - End of Buffer Interrupt Level */
0238 #define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16)
0239
0240 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
0241 #define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15)
0242
0243 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
0244 #define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14)
0245
0246 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
0247 #define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13)
0248
0249 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
0250 #define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12)
0251
0252 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
0253 #define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11)
0254
0255 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
0256 #define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10)
0257
0258 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
0259 #define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9)
0260
0261 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
0262 #define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8)
0263
0264 /* field: BUSERROR - BMM Bus Error Response */
0265 #define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7)
0266
0267 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
0268 #define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6)
0269
0270 /* field: SRC_OVF - Source Overflow Interrupt Level */
0271 #define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5)
0272
0273 /* field: DEST3_ERR - Destination 3 Error Interrupt Level */
0274 #define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4)
0275
0276 /* field: DEST2_ERR - Destination 2 Error Interrupt Level */
0277 #define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3)
0278
0279 /* field: DEST1_ERR - Destination 1 Error Interrupt Level */
0280 #define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2)
0281
0282 /* field: DEST0_ERR - Destination 0 Error Interrupt Level */
0283 #define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1)
0284
0285 /* field: PACKET_ERR_INT - Packet Error Interrupt Level */
0286 #define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0)
0287
0288
0289 /*---------------------TMS570_DMM_INTFLG---------------------*/
0290 /* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
0291 #define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17)
0292
0293 /* field: EO_BUFF - End of Buffer Interrupt Flag */
0294 #define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16)
0295
0296 /* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
0297 #define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15)
0298
0299 /* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
0300 #define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14)
0301
0302 /* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
0303 #define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13)
0304
0305 /* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
0306 #define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12)
0307
0308 /* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
0309 #define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11)
0310
0311 /* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
0312 #define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10)
0313
0314 /* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
0315 #define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9)
0316
0317 /* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
0318 #define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8)
0319
0320 /* field: BUSERROR - BMM Bus Error Response. */
0321 #define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7)
0322
0323 /* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
0324 #define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6)
0325
0326 /* field: SRC_OVF - Source Overflow Interrupt Flag */
0327 #define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5)
0328
0329 /* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
0330 #define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4)
0331
0332 /* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
0333 #define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3)
0334
0335 /* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
0336 #define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2)
0337
0338 /* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
0339 #define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1)
0340
0341 /* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
0342 #define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0)
0343
0344
0345 /*----------------------TMS570_DMM_OFF1----------------------*/
0346 /* field: OFFSET - User and privilege mode (read): */
0347 #define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
0348 #define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
0349 #define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0350
0351
0352 /*----------------------TMS570_DMM_OFF2----------------------*/
0353 /* field: OFFSET - User and privilege mode (read): */
0354 #define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
0355 #define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
0356 #define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0357
0358
0359 /*---------------------TMS570_DMM_DDMDEST---------------------*/
0360 /* field: STARTADDR - These bits define the starting address of the buffer. */
0361 /* Whole 32 bits */
0362
0363 /*----------------------TMS570_DMM_DDMBL----------------------*/
0364 /* field: BLOCKSIZE - These bits define the size of the buffer region */
0365 #define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
0366 #define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
0367 #define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0368
0369
0370 /*----------------------TMS570_DMM_DDMPT----------------------*/
0371 /* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
0372 #define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
0373 #define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14)
0374 #define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
0375
0376
0377 /*----------------------TMS570_DMM_INTPT----------------------*/
0378 /* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
0379 #define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
0380 #define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14)
0381 #define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
0382
0383
0384 /*--------------------TMS570_DMM_DESTxREG1--------------------*/
0385 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
0386 #define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31)
0387 #define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
0388 #define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
0389
0390 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
0391 #define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
0392 #define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
0393 #define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
0394
0395
0396 /*--------------------TMS570_DMM_DESTxBL1--------------------*/
0397 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
0398 #define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
0399 #define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
0400 #define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0401
0402
0403 /*--------------------TMS570_DMM_DESTxREG2--------------------*/
0404 /* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
0405 #define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31)
0406 #define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
0407 #define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
0408
0409 /* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
0410 #define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
0411 #define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
0412 #define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
0413
0414
0415 /*--------------------TMS570_DMM_DESTxBL2--------------------*/
0416 /* field: BLOCKSIZE - These bits define the length of the buffer region. */
0417 #define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
0418 #define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
0419 #define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0420
0421
0422 /*-----------------------TMS570_DMM_PC0-----------------------*/
0423 /* field: ENAFUNC - Functional mode of DMMENA pin. */
0424 #define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18)
0425
0426 /* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
0427 #define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17)
0428 #define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17)
0429 #define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0430
0431 /* field: CLKFUNC - Functional mode of DMMCLK pin. */
0432 #define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1)
0433
0434 /* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
0435 #define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0)
0436
0437
0438 /*-----------------------TMS570_DMM_PC1-----------------------*/
0439 /* field: ENADIR - Direction of DMMENA pin. */
0440 #define TMS570_DMM_PC1_ENADIR BSP_BIT32(18)
0441
0442 /* field: DATAxDIR - Direction of DMMDATA[x] pin. */
0443 #define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17)
0444 #define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17)
0445 #define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0446
0447 /* field: CLKDIR - Direction of DMMCLK pin. */
0448 #define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1)
0449
0450 /* field: SYNCDIR - Direction of DMMSYNC pin. */
0451 #define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0)
0452
0453
0454 /*-----------------------TMS570_DMM_PC2-----------------------*/
0455 /* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
0456 #define TMS570_DMM_PC2_ENAIN BSP_BIT32(18)
0457
0458 /* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
0459 #define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17)
0460 #define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17)
0461 #define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0462
0463 /* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
0464 #define TMS570_DMM_PC2_CLKIN BSP_BIT32(1)
0465
0466 /* field: SYNCIN - DMMSYNC input. */
0467 #define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0)
0468
0469
0470 /*-----------------------TMS570_DMM_PC3-----------------------*/
0471 /* field: ENAOUT - Output state of DMMENA pin. */
0472 #define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18)
0473
0474 /* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
0475 #define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17)
0476 #define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17)
0477 #define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0478
0479 /* field: CLKOUT - Output state of DMMCLK pin. */
0480 #define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1)
0481
0482 /* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
0483 #define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0)
0484
0485
0486 /*-----------------------TMS570_DMM_PC4-----------------------*/
0487 /* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
0488 #define TMS570_DMM_PC4_ENASET BSP_BIT32(18)
0489
0490 /* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
0491 #define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17)
0492 #define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17)
0493 #define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0494
0495 /* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
0496 #define TMS570_DMM_PC4_CLKSET BSP_BIT32(1)
0497
0498 /* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
0499 #define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0)
0500
0501
0502 /*-----------------------TMS570_DMM_PC5-----------------------*/
0503 /* field: ENACLR - Sets output state of DMMENA pin to logic low. */
0504 #define TMS570_DMM_PC5_ENACLR BSP_BIT32(18)
0505
0506 /* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
0507 #define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17)
0508 #define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17)
0509 #define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0510
0511 /* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
0512 #define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1)
0513
0514 /* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
0515 #define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0)
0516
0517
0518 /*-----------------------TMS570_DMM_PC6-----------------------*/
0519 /* field: ENAPDR - Open Drain enable. */
0520 #define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18)
0521
0522 /* field: DATAxPDR - Open Drain enable. */
0523 #define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17)
0524 #define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17)
0525 #define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0526
0527 /* field: CLKPDR - Open Drain enable. */
0528 #define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1)
0529
0530 /* field: SYNCPDR - Open Drain enable. */
0531 #define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0)
0532
0533
0534 /*-----------------------TMS570_DMM_PC7-----------------------*/
0535 /* field: ENAPDIS - Pull disable. */
0536 #define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18)
0537
0538 /* field: DATAxPDIS - Pull disable. */
0539 #define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17)
0540 #define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17)
0541 #define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0542
0543 /* field: CLKPDIS - Pull disable. */
0544 #define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1)
0545
0546 /* field: SYNCPDIS - Pull disable. */
0547 #define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0)
0548
0549
0550 /*-----------------------TMS570_DMM_PC8-----------------------*/
0551 /* field: ENAPSEL - Pull disable. */
0552 #define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18)
0553
0554 /* field: DATAxPSEL - Pull disable. */
0555 #define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17)
0556 #define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17)
0557 #define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
0558
0559 /* field: CLKPSEL - Pull disable. */
0560 #define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1)
0561
0562 /* field: SYNCPSEL - Pull disable. */
0563 #define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0)
0564
0565
0566
0567 #endif /* LIBBSP_ARM_TMS570_DMM */