bsp/ti_herc/reg_dma.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides DMA interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from DMA.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_DMA
0050 #define LIBBSP_ARM_TMS570_DMA
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t STARTADD;          /*DMA Memory Protection Region start Address Register*/
0056   uint32_t ENDADD;            /*DMA Memory Protection Region End Address Register*/
0057 } tms570_memory_prot_t;
0058
0059 typedef struct{
0060   uint32_t GCTRL;             /*Global Control Register*/
0061   uint32_t PEND;              /*Channel Pending Register*/
0062   uint8_t reserved1 [4];
0063   uint32_t DMASTAT;           /*DMA Status Register*/
0064   uint8_t reserved2 [4];
0065   uint32_t HWCHENAS;          /*HW Channel Enable Set and Status Register*/
0066   uint8_t reserved3 [4];
0067   uint32_t HWCHENAR;          /*HW Channel Enable Reset and Status Register*/
0068   uint8_t reserved4 [4];
0069   uint32_t SWCHENAS;          /*SW Channel Enable Set and Status Register*/
0070   uint8_t reserved5 [4];
0071   uint32_t SWCHENAR;          /*SW Channel Enable Reset and Status Register*/
0072   uint8_t reserved6 [4];
0073   uint32_t CHPRIOS;           /*Channel Priority Set Register*/
0074   uint8_t reserved7 [4];
0075   uint32_t CHPRIOR;           /*Channel Priority Reset Register*/
0076   uint8_t reserved8 [4];
0077   uint32_t GCHIENAS;          /*Global Channel Interrupt Enable Set Register*/
0078   uint8_t reserved9 [4];
0079   uint32_t GCHIENAR;          /*Global Channel Interrupt Enable Reset Register*/
0080   uint8_t reserved10 [4];
0081   uint32_t DREQASI[4];        /*DMA Request Assignment Register 0*/
0082   uint8_t reserved11 [48];
0083   uint32_t PAR0;              /*Port Assignment Register 0*/
0084   uint32_t PAR1;              /*Port Assignment Register 1*/
0085   uint8_t reserved12 [24];
0086   uint32_t FTCMAP;            /*FTC Interrupt Mapping Register*/
0087   uint8_t reserved13 [4];
0088   uint32_t LFSMAP;            /*LFS Interrupt Mapping Register*/
0089   uint8_t reserved14 [4];
0090   uint32_t HBCMAP;            /*HBC Interrupt Mapping Register*/
0091   uint8_t reserved15 [4];
0092   uint32_t BTCMAP;            /*BTC Interrupt Mapping Register*/
0093   uint8_t reserved16 [4];
0094   uint32_t BERMAP;            /*BER Interrupt Mapping Register*/
0095   uint8_t reserved17 [4];
0096   uint32_t FTCINTENAS;        /*FTC Interrupt Enable Set*/
0097   uint8_t reserved18 [4];
0098   uint32_t FTCINTENAR;        /*FTC Interrupt Enable Reset*/
0099   uint8_t reserved19 [4];
0100   uint32_t LFSINTENAS;        /*LFS Interrupt Enable Set*/
0101   uint8_t reserved20 [4];
0102   uint32_t LFSINTENAR;        /*LFS Interrupt Enable Reset*/
0103   uint8_t reserved21 [4];
0104   uint32_t HBCINTENAS;        /*HBC Interrupt Enable Set*/
0105   uint8_t reserved22 [4];
0106   uint32_t HBCINTENAR;        /*HBC Interrupt Enable Reset*/
0107   uint8_t reserved23 [4];
0108   uint32_t BTCINTENAS;        /*BTC Interrupt Enable Set*/
0109   uint8_t reserved24 [4];
0110   uint32_t BTCINTENAR;        /*BTC Interrupt Enable Reset*/
0111   uint8_t reserved25 [4];
0112   uint32_t GINTFLAG;          /*Global Interrupt Flag Register*/
0113   uint8_t reserved26 [4];
0114   uint32_t FTCFLAG;           /*FTC Interrupt Flag Register*/
0115   uint8_t reserved27 [4];
0116   uint32_t LFSFLAG;           /*LFS Interrupt Flag Register*/
0117   uint8_t reserved28 [4];
0118   uint32_t HBCFLAG;           /*HBC Interrupt Flag Register*/
0119   uint8_t reserved29 [4];
0120   uint32_t BTCFLAG;           /*BTC Interrupt Flag Register*/
0121   uint8_t reserved30 [4];
0122   uint32_t BERFLAG;           /*BER Interrupt Flag Register*/
0123   uint8_t reserved31 [4];
0124   uint32_t FTCAOFFSET;        /*FTCA Interrupt Channel Offset Register*/
0125   uint32_t LFSAOFFSET;        /*LFSA Interrupt Channel Offset Register*/
0126   uint32_t HBCAOFFSET;        /*HBCA Interrupt Channel Offset Register*/
0127   uint32_t BTCAOFFSET;        /*BTCA Interrupt Channel Offset Register*/
0128   uint32_t BERAOFFSET;        /*BERA Interrupt Channel Offset Register*/
0129   uint32_t FTCBOFFSET;        /*FTCB Interrupt Channel Offset Register*/
0130   uint32_t LFSBOFFSET;        /*LFSB Interrupt Channel Offset Register*/
0131   uint32_t HBCBOFFSET;        /*HBCB Interrupt Channel Offset Register*/
0132   uint32_t BTCBOFFSET;        /*BTCB Interrupt Channel Offset Register*/
0133   uint32_t BERBOFFSET;        /*BERB Interrupt Channel Offset Register*/
0134   uint8_t reserved32 [4];
0135   uint32_t PTCRL;             /*Port Control Register*/
0136   uint32_t RTCTRL;            /*RAM Test Control Register*/
0137   uint32_t DCTRL;             /*Debug Control*/
0138   uint32_t WPR;               /*Watch Point Register*/
0139   uint32_t WMR;               /*Watch Mask Register*/
0140   uint8_t reserved33 [12];
0141   uint32_t PBACSADDR;         /*Port B Active Channel Source Address Register*/
0142   uint32_t PBACDADDR;         /*Port B Active Channel Destination Address Register*/
0143   uint32_t PBACTC;            /*Port B Active Channel Transfer Count Register*/
0144   uint8_t reserved34 [4];
0145   uint32_t DMAPCR;            /*Parity Control Register*/
0146   uint32_t DMAPAR;            /*DMA Parity Error Address Register*/
0147   uint32_t DMAMPCTRL;         /*DMA Memory Protection Control Register*/
0148   uint32_t DMAMPST;           /*DMA Memory Protection Status Register*/
0149   tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/
0150 } tms570_dma_t;
0151
0152
0153 /*--------------------TMS570_DMA_STARTADD--------------------*/
0154 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
0155 /* Whole 32 bits */
0156
0157 /*---------------------TMS570_DMA_ENDADD---------------------*/
0158 /* field: ENDADDRESS - End Address defines the address at which the region ends. */
0159 /* Whole 32 bits */
0160
0161 /*----------------------TMS570_DMA_GCTRL----------------------*/
0162 /* field: DMA_EN - DMA enable bit. */
0163 #define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
0164
0165 /* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
0166 #define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
0167
0168 /* field: DEBUG_MODE - Debug Mode. */
0169 #define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
0170 #define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
0171 #define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0172
0173 /* field: DMA_RES - DMA software reset */
0174 #define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
0175
0176
0177 /*----------------------TMS570_DMA_PEND----------------------*/
0178 /* field: PEND - Channel pending register. */
0179 #define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
0180 #define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
0181 #define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0182
0183
0184 /*---------------------TMS570_DMA_DMASTAT---------------------*/
0185 /* field: STCH - Status of DMA channels. */
0186 #define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
0187 #define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
0188 #define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0189
0190
0191 /*--------------------TMS570_DMA_HWCHENAS--------------------*/
0192 /* field: HWCHENA - Hardware channel enable bit. */
0193 #define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
0194 #define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0195 #define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0196
0197
0198 /*--------------------TMS570_DMA_HWCHENAR--------------------*/
0199 /* field: HWCHDIS - HW channel disable bit. */
0200 #define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
0201 #define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0202 #define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0203
0204
0205 /*--------------------TMS570_DMA_SWCHENAS--------------------*/
0206 /* field: SWCHENA - SW channel enable bit. */
0207 #define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
0208 #define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0209 #define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0210
0211
0212 /*--------------------TMS570_DMA_SWCHENAR--------------------*/
0213 /* field: SWCHDIS - SW channel disable bit. */
0214 #define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
0215 #define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0216 #define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0217
0218
0219 /*---------------------TMS570_DMA_CHPRIOS---------------------*/
0220 /* field: CPS - Channel priority set bit. */
0221 #define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
0222 #define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
0223 #define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0224
0225
0226 /*---------------------TMS570_DMA_CHPRIOR---------------------*/
0227 /* field: CPR - Channel priority reset bit. */
0228 #define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
0229 #define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
0230 #define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0231
0232
0233 /*--------------------TMS570_DMA_GCHIENAS--------------------*/
0234 /* field: GCHIE - Global channel interrupt enable bit. */
0235 #define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
0236 #define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
0237 #define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0238
0239
0240 /*--------------------TMS570_DMA_GCHIENAR--------------------*/
0241 /* field: GCHID - Global channel interrupt disable bit. */
0242 #define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
0243 #define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
0244 #define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0245
0246
0247 /*---------------------TMS570_DMA_DREQASI---------------------*/
0248 /* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
0249 #define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
0250 #define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
0251 #define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29)
0252
0253 /* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */
0254 #define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21)
0255 #define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21)
0256 #define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
0257
0258 /* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */
0259 #define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13)
0260 #define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13)
0261 #define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
0262
0263 /* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */
0264 #define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5)
0265 #define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5)
0266 #define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0267
0268
0269 /*----------------------TMS570_DMA_PAR0----------------------*/
0270 /* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
0271 #define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
0272 #define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
0273 #define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
0274
0275 /* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */
0276 #define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26)
0277 #define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26)
0278 #define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
0279
0280 /* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */
0281 #define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22)
0282 #define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22)
0283 #define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
0284
0285 /* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */
0286 #define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18)
0287 #define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18)
0288 #define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0289
0290 /* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */
0291 #define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14)
0292 #define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14)
0293 #define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
0294
0295 /* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */
0296 #define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10)
0297 #define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10)
0298 #define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0299
0300 /* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */
0301 #define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6)
0302 #define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6)
0303 #define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0304
0305 /* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */
0306 #define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2)
0307 #define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2)
0308 #define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0309
0310
0311 /*----------------------TMS570_DMA_PAR1----------------------*/
0312 /* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
0313 #define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
0314 #define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
0315 #define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
0316
0317 /* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */
0318 #define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26)
0319 #define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26)
0320 #define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
0321
0322 /* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */
0323 #define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22)
0324 #define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22)
0325 #define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
0326
0327 /* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */
0328 #define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18)
0329 #define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18)
0330 #define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
0331
0332 /* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */
0333 #define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14)
0334 #define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14)
0335 #define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
0336
0337 /* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */
0338 #define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10)
0339 #define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10)
0340 #define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
0341
0342 /* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */
0343 #define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6)
0344 #define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6)
0345 #define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
0346
0347 /* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */
0348 #define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2)
0349 #define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2)
0350 #define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0351
0352
0353 /*---------------------TMS570_DMA_FTCMAP---------------------*/
0354 /* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
0355 #define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
0356 #define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
0357 #define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0358
0359
0360 /*---------------------TMS570_DMA_LFSMAP---------------------*/
0361 /* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
0362 #define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
0363 #define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
0364 #define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0365
0366
0367 /*---------------------TMS570_DMA_HBCMAP---------------------*/
0368 /* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
0369 #define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
0370 #define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
0371 #define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0372
0373
0374 /*---------------------TMS570_DMA_BTCMAP---------------------*/
0375 /* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
0376 #define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
0377 #define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
0378 #define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0379
0380
0381 /*---------------------TMS570_DMA_BERMAP---------------------*/
0382 /* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
0383 #define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
0384 #define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
0385 #define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0386
0387
0388 /*-------------------TMS570_DMA_FTCINTENAS-------------------*/
0389 /* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
0390 #define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
0391 #define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0392 #define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0393
0394
0395 /*-------------------TMS570_DMA_FTCINTENAR-------------------*/
0396 /* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
0397 #define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
0398 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0399 #define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0400
0401
0402 /*-------------------TMS570_DMA_LFSINTENAS-------------------*/
0403 /* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
0404 #define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
0405 #define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0406 #define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0407
0408
0409 /*-------------------TMS570_DMA_LFSINTENAR-------------------*/
0410 /* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
0411 #define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
0412 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0413 #define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0414
0415
0416 /*-------------------TMS570_DMA_HBCINTENAS-------------------*/
0417 /* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
0418 #define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
0419 #define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0420 #define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0421
0422
0423 /*-------------------TMS570_DMA_HBCINTENAR-------------------*/
0424 /* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
0425 #define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
0426 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0427 #define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0428
0429
0430 /*-------------------TMS570_DMA_BTCINTENAS-------------------*/
0431 /* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
0432 #define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
0433 #define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
0434 #define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0435
0436
0437 /*-------------------TMS570_DMA_BTCINTENAR-------------------*/
0438 /* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
0439 #define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
0440 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
0441 #define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0442
0443
0444 /*--------------------TMS570_DMA_GINTFLAG--------------------*/
0445 /* field: GINT - Global interrupt flags. */
0446 #define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
0447 #define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
0448 #define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0449
0450
0451 /*---------------------TMS570_DMA_FTCFLAG---------------------*/
0452 /* field: FTCI - Frame transfer complete (FTC) flags. */
0453 #define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
0454 #define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
0455 #define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0456
0457
0458 /*---------------------TMS570_DMA_LFSFLAG---------------------*/
0459 /* field: LFSI - Last frame started (LFS) flags. */
0460 #define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
0461 #define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
0462 #define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0463
0464
0465 /*---------------------TMS570_DMA_HBCFLAG---------------------*/
0466 /* field: HBCI - Half block transfer (HBC) complete flags. */
0467 #define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
0468 #define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
0469 #define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0470
0471
0472 /*---------------------TMS570_DMA_BTCFLAG---------------------*/
0473 /* field: BTCI - Block transfer complete (BTC) flags. */
0474 #define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
0475 #define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
0476 #define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0477
0478
0479 /*---------------------TMS570_DMA_BERFLAG---------------------*/
0480 /* field: BERI - Bus error (BER) flags. */
0481 #define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
0482 #define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
0483 #define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0484
0485
0486 /*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
0487 /* field: sbz - These bits should always be programmed as zero. */
0488 #define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
0489 #define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
0490 #define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
0491
0492 /* field: FTCA - Channel causing FTC interrupt Group A. */
0493 #define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5)
0494 #define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
0495 #define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0496
0497
0498 /*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
0499 /* field: LFSA - Channel causing LFS interrupt Group A. */
0500 #define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
0501 #define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
0502 #define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0503
0504
0505 /*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
0506 /* field: HBCA - Channel causing HBC interrupt Group A. */
0507 #define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
0508 #define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
0509 #define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0510
0511
0512 /*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
0513 /* field: BTCA - Channel causing BTC interrupt Group A. */
0514 #define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
0515 #define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
0516 #define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0517
0518
0519 /*-------------------TMS570_DMA_BERAOFFSET-------------------*/
0520 /* field: BERA - Channel causing BER interrupt Group A. */
0521 #define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
0522 #define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
0523 #define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0524
0525
0526 /*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
0527 /* field: FTCB - Channel causing FTC interrupt Group B. */
0528 #define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
0529 #define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
0530 #define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0531
0532
0533 /*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
0534 /* field: LFSB - Channel causing LFS interrupt Group B. */
0535 #define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
0536 #define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
0537 #define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0538
0539
0540 /*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
0541 /* field: HBCB - Channel causing HBC interrupt Group B. */
0542 #define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
0543 #define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
0544 #define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0545
0546
0547 /*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
0548 /* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
0549 #define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
0550 #define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
0551 #define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0552
0553
0554 /*-------------------TMS570_DMA_BERBOFFSET-------------------*/
0555 /* field: BERB - Channel causing BER interrupt Group B. */
0556 #define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
0557 #define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
0558 #define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
0559
0560
0561 /*----------------------TMS570_DMA_PTCRL----------------------*/
0562 /* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
0563 #define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
0564
0565 /* field: BYB - Bypass FIFO B. */
0566 #define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
0567
0568 /* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
0569 #define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
0570
0571 /* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
0572 #define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
0573
0574
0575 /*---------------------TMS570_DMA_RTCTRL---------------------*/
0576 /* field: RTC - RAM Test Control. */
0577 #define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
0578
0579
0580 /*----------------------TMS570_DMA_DCTRL----------------------*/
0581 /* field: CHNUM - Channel Number. */
0582 #define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
0583 #define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
0584 #define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
0585
0586 /* field: DMADBGS - DMA debug status. */
0587 #define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
0588
0589 /* field: DBGEN - Debug Enable. */
0590 #define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
0591
0592
0593 /*-----------------------TMS570_DMA_WPR-----------------------*/
0594 /* field: WP - Watch point. */
0595 /* Whole 32 bits */
0596
0597 /*-----------------------TMS570_DMA_WMR-----------------------*/
0598 /* field: WM - Watch mask. */
0599 /* Whole 32 bits */
0600
0601 /*--------------------TMS570_DMA_PBACSADDR--------------------*/
0602 /* field: PBACSA - Port B Active Channel Source Address. */
0603 /* Whole 32 bits */
0604
0605 /*--------------------TMS570_DMA_PBACDADDR--------------------*/
0606 /* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
0607 /* Whole 32 bits */
0608
0609 /*---------------------TMS570_DMA_PBACTC---------------------*/
0610 /* field: PBFTCOUNT - Port B active channel frame count. */
0611 #define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
0612 #define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
0613 #define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28)
0614
0615 /* field: PBETCOUNT - Port B active channel element count. */
0616 #define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12)
0617 #define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12)
0618 #define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
0619
0620
0621 /*---------------------TMS570_DMA_DMAPCR---------------------*/
0622 /* field: ERRA - Error action. */
0623 #define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
0624
0625 /* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
0626 #define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
0627
0628 /* field: PARITY_ENA - Parity error detection enable. */
0629 #define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
0630 #define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0631 #define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0632
0633
0634 /*---------------------TMS570_DMA_DMAPAR---------------------*/
0635 /* field: EDFLAG - Parity Error Detection Flag. */
0636 #define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
0637
0638 /* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
0639 #define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
0640 #define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11)
0641 #define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0642
0643
0644 /*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
0645 /* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
0646 #define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
0647
0648 /* field: INT3ENA - Interrupt enable of region 3. */
0649 #define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
0650
0651 /* field: REG3AP - Region 3 access permission. */
0652 #define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
0653 #define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26)
0654 #define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
0655
0656 /* field: REG3ENA - Region 3 enable. */
0657 #define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
0658
0659 /* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
0660 #define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
0661
0662 /* field: INT2ENA - Interrupt enable of region 2. */
0663 #define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
0664
0665 /* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
0666 #define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
0667 #define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18)
0668 #define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
0669
0670 /* field: REG2ENA - Region 2 enable. */
0671 #define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
0672
0673 /* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
0674 #define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
0675
0676 /* field: INT1ENA - Interrupt enable of region 1. */
0677 #define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
0678
0679 /* field: REG1AP - Region 1 access permission. */
0680 #define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
0681 #define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10)
0682 #define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
0683
0684 /* field: REG1ENA - Region 1 enable. */
0685 #define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
0686
0687 /* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
0688 #define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
0689
0690 /* field: INT0ENA - Interrupt enable of region 0. */
0691 #define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
0692
0693 /* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
0694 #define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
0695 #define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2)
0696 #define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
0697
0698 /* field: REG0ENA - Region 0 enable. */
0699 #define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
0700
0701
0702 /*---------------------TMS570_DMA_DMAMPST---------------------*/
0703 /* field: REG3FT - Region 3 fault. */
0704 #define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
0705
0706 /* field: REG2FT - Region 2 fault. */
0707 #define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
0708
0709 /* field: REG1FT - Region 1 fault. */
0710 #define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
0711
0712 /* field: REG0FT - Region 0 fault. */
0713 #define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
0714
0715
0716 /*--------------------TMS570_DMA_DMAMPROS--------------------*/
0717 /* field: STARTADDRESS - Start Address defines the address at which the region begins. */
0718 /* Whole 32 bits */
0719
0720
0721 #endif /* LIBBSP_ARM_TMS570_DMA */