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File indexing completed on 2025-05-11 08:23:38
0001 /* SPDX-License-Identifier: BSD-2-Clause */ 0002 0003 /** 0004 * @file 0005 * 0006 * @ingroup RTEMSBSPsARMTMS570 0007 * 0008 * @brief This header file provides CRC interfaces. 0009 */ 0010 0011 /* The header file is generated by make_header.py from CRC.json */ 0012 /* Current script's version can be found at: */ 0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */ 0014 0015 /* 0016 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com> 0017 * 0018 * Czech Technical University in Prague 0019 * Zikova 1903/4 0020 * 166 36 Praha 6 0021 * Czech Republic 0022 * 0023 * All rights reserved. 0024 * 0025 * Redistribution and use in source and binary forms, with or without 0026 * modification, are permitted provided that the following conditions are met: 0027 * 0028 * 1. Redistributions of source code must retain the above copyright notice, this 0029 * list of conditions and the following disclaimer. 0030 * 2. Redistributions in binary form must reproduce the above copyright notice, 0031 * this list of conditions and the following disclaimer in the documentation 0032 * and/or other materials provided with the distribution. 0033 * 0034 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 0035 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 0036 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 0037 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 0038 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 0039 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 0040 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 0041 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 0042 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 0043 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 0044 * 0045 * The views and conclusions contained in the software and documentation are those 0046 * of the authors and should not be interpreted as representing official policies, 0047 * either expressed or implied, of the FreeBSD Project. 0048 */ 0049 #ifndef LIBBSP_ARM_TMS570_CRC 0050 #define LIBBSP_ARM_TMS570_CRC 0051 0052 #include <bsp/utility.h> 0053 0054 typedef struct{ 0055 uint32_t CTRL0; /*CRC Global Control Register*/ 0056 uint8_t reserved1 [4]; 0057 uint32_t CTRL1; /*CRC Global Control Register 1*/ 0058 uint8_t reserved2 [4]; 0059 uint32_t CTRL2; /*CRC Global Control Register 2*/ 0060 uint8_t reserved3 [4]; 0061 uint32_t INTS; /*CRC Interrupt Enable Set Register*/ 0062 uint8_t reserved4 [4]; 0063 uint32_t INTR; /*CRC Interrupt Enable Reset Register*/ 0064 uint8_t reserved5 [4]; 0065 uint32_t STATUS; /*CRC Interrupt Status Register*/ 0066 uint8_t reserved6 [4]; 0067 uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/ 0068 uint8_t reserved7 [4]; 0069 uint32_t BUSY; /*CRC Busy Register*/ 0070 uint8_t reserved8 [4]; 0071 uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/ 0072 uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/ 0073 uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/ 0074 uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/ 0075 uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/ 0076 uint8_t reserved9 [12]; 0077 uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/ 0078 uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/ 0079 uint32_t REGL1; /*Channel 1 CRC Value Low Register*/ 0080 uint32_t REGH1; /*Channel 1 CRC Value High Register*/ 0081 uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/ 0082 uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/ 0083 uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/ 0084 uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/ 0085 uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/ 0086 uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/ 0087 uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/ 0088 uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/ 0089 uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/ 0090 uint8_t reserved10 [12]; 0091 uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/ 0092 uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/ 0093 uint32_t REGL2; /*Channel 2 CRC Value Low Register*/ 0094 uint32_t REGH2; /*Channel 2 CRC Value High Register*/ 0095 uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/ 0096 uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/ 0097 uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/ 0098 uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/ 0099 uint8_t reserved11 [128]; 0100 uint32_t BUS_SEL; /*Data Bus Selection Register*/ 0101 } tms570_crc_t; 0102 0103 0104 /*----------------------TMS570_CRC_CTRL0----------------------*/ 0105 /* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ 0106 #define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8) 0107 0108 /* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */ 0109 #define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0) 0110 0111 0112 /*----------------------TMS570_CRC_CTRL1----------------------*/ 0113 /* field: PWDN - Power Down. */ 0114 #define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0) 0115 0116 0117 /*----------------------TMS570_CRC_CTRL2----------------------*/ 0118 /* field: CH2_MODE - Channel 2 Mode Selection */ 0119 #define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9) 0120 #define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9) 0121 #define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9) 0122 0123 /* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */ 0124 #define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4) 0125 0126 /* field: CH1_MODE - Channel 1 Mode Selection */ 0127 #define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1) 0128 #define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1) 0129 #define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1) 0130 0131 0132 /*----------------------TMS570_CRC_INTS----------------------*/ 0133 /* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */ 0134 #define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12) 0135 0136 /* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */ 0137 #define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11) 0138 0139 /* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */ 0140 #define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10) 0141 0142 /* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */ 0143 #define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9) 0144 0145 /* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */ 0146 #define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8) 0147 0148 /* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */ 0149 #define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4) 0150 0151 /* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */ 0152 #define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3) 0153 0154 /* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */ 0155 #define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2) 0156 0157 /* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */ 0158 #define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1) 0159 0160 /* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */ 0161 #define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0) 0162 0163 0164 /*----------------------TMS570_CRC_INTR----------------------*/ 0165 /* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */ 0166 #define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12) 0167 0168 /* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */ 0169 #define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11) 0170 0171 /* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */ 0172 #define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10) 0173 0174 /* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */ 0175 #define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9) 0176 0177 /* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */ 0178 #define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8) 0179 0180 /* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */ 0181 #define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4) 0182 0183 /* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */ 0184 #define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3) 0185 0186 /* field: CH1_OVERENR - CH1_OVERENR */ 0187 #define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2) 0188 0189 /* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */ 0190 #define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1) 0191 0192 /* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */ 0193 #define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0) 0194 0195 0196 /*---------------------TMS570_CRC_STATUS---------------------*/ 0197 /* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */ 0198 #define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12) 0199 0200 /* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */ 0201 #define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11) 0202 0203 /* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */ 0204 #define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10) 0205 0206 /* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */ 0207 #define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9) 0208 0209 /* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */ 0210 #define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8) 0211 0212 /* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */ 0213 #define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4) 0214 0215 /* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */ 0216 #define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3) 0217 0218 /* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */ 0219 #define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2) 0220 0221 /* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */ 0222 #define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1) 0223 0224 /* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */ 0225 #define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0) 0226 0227 0228 /*------------------TMS570_CRC_INT_OFFS_REG------------------*/ 0229 /* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */ 0230 #define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7) 0231 #define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7) 0232 #define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7) 0233 0234 0235 /*----------------------TMS570_CRC_BUSY----------------------*/ 0236 /* field: CH2_BUSY - CH2_BUSY. */ 0237 #define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8) 0238 0239 /* field: CH1_BUSY - CH1_BUSY. */ 0240 #define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0) 0241 0242 0243 /*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/ 0244 /* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */ 0245 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19) 0246 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19) 0247 #define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) 0248 0249 0250 /*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/ 0251 /* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */ 0252 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15) 0253 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15) 0254 #define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) 0255 0256 0257 /*-------------------TMS570_CRC_CURSEC_REG1-------------------*/ 0258 /* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */ 0259 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15) 0260 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15) 0261 #define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) 0262 0263 0264 /*--------------------TMS570_CRC_WDTOPLD1--------------------*/ 0265 /* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */ 0266 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23) 0267 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) 0268 #define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) 0269 0270 0271 /*--------------------TMS570_CRC_BCTOPLD1--------------------*/ 0272 /* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */ 0273 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23) 0274 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23) 0275 #define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) 0276 0277 0278 /*------------------TMS570_CRC_PSA_SIGREGL1------------------*/ 0279 /* field: PSASIG1 - Channel 1 PSA Signature Low Register. */ 0280 /* Whole 32 bits */ 0281 0282 /*------------------TMS570_CRC_PSA_SIGREGH1------------------*/ 0283 /* field: PSASIG1 - register. */ 0284 /* Whole 32 bits */ 0285 0286 /*----------------------TMS570_CRC_REGL1----------------------*/ 0287 /* field: CRC1 - Channel 1 CRC Value Low Register. */ 0288 /* Whole 32 bits */ 0289 0290 /*----------------------TMS570_CRC_REGH1----------------------*/ 0291 /* field: CRC1 - Channel 1 CRC Value Low Register. */ 0292 /* Whole 32 bits */ 0293 0294 /*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/ 0295 /* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */ 0296 /* Whole 32 bits */ 0297 0298 /*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/ 0299 /* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */ 0300 /* Whole 32 bits */ 0301 0302 /*------------------TMS570_CRC_RAW_DATAREGL1------------------*/ 0303 /* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */ 0304 /* Whole 32 bits */ 0305 0306 /*------------------TMS570_CRC_RAW_DATAREGH1------------------*/ 0307 /* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */ 0308 /* Whole 32 bits */ 0309 0310 /*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/ 0311 /* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */ 0312 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19) 0313 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19) 0314 #define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19) 0315 0316 0317 /*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/ 0318 /* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */ 0319 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15) 0320 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15) 0321 #define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) 0322 0323 0324 /*-------------------TMS570_CRC_CURSEC_REG2-------------------*/ 0325 /* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */ 0326 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15) 0327 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15) 0328 #define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15) 0329 0330 0331 /*--------------------TMS570_CRC_WDTOPLD2--------------------*/ 0332 /* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */ 0333 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23) 0334 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) 0335 #define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) 0336 0337 0338 /*--------------------TMS570_CRC_BCTOPLD2--------------------*/ 0339 /* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */ 0340 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23) 0341 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23) 0342 #define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23) 0343 0344 0345 /*------------------TMS570_CRC_PSA_SIGREGL2------------------*/ 0346 /* field: PSASIG2 - Channel 2 PSA Signature Low Register. */ 0347 /* Whole 32 bits */ 0348 0349 /*------------------TMS570_CRC_PSA_SIGREGH2------------------*/ 0350 /* field: PSASIG2 - Channel 2 PSA Signature High Register. */ 0351 /* Whole 32 bits */ 0352 0353 /*----------------------TMS570_CRC_REGL2----------------------*/ 0354 /* field: CRC2 - stored at CRC2[31:0] register. */ 0355 /* Whole 32 bits */ 0356 0357 /*----------------------TMS570_CRC_REGH2----------------------*/ 0358 /* field: CRC2 - Channel 2 CRC Value High Register. */ 0359 /* Whole 32 bits */ 0360 0361 /*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/ 0362 /* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */ 0363 /* Whole 32 bits */ 0364 0365 /*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/ 0366 /* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */ 0367 /* Whole 32 bits */ 0368 0369 /*------------------TMS570_CRC_RAW_DATAREGL2------------------*/ 0370 /* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */ 0371 /* Whole 32 bits */ 0372 0373 /*------------------TMS570_CRC_RAW_DATAREGH2------------------*/ 0374 /* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */ 0375 /* Whole 32 bits */ 0376 0377 /*---------------------TMS570_CRC_BUS_SEL---------------------*/ 0378 /* field: MEn - Enable/disables the tracing of Peripheral Bus Master */ 0379 #define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2) 0380 0381 /* field: DTCMEn - Enable/disables the tracing of data TCM */ 0382 #define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1) 0383 0384 /* field: ITCMEn - Enable/disables the tracing of instruction TCM */ 0385 #define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0) 0386 0387 0388 0389 #endif /* LIBBSP_ARM_TMS570_CRC */
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