bsp/ti_herc/reg_adc.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides ADC interfaces.
0009  */
0010
0011 /* The header file is generated by make_header.py from ADC.json */
0012 /* Current script's version can be found at: */
0013 /* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
0014
0015 /*
0016  * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
0017  *
0018  * Czech Technical University in Prague
0019  * Zikova 1903/4
0020  * 166 36 Praha 6
0021  * Czech Republic
0022  *
0023  * All rights reserved.
0024  *
0025  * Redistribution and use in source and binary forms, with or without
0026  * modification, are permitted provided that the following conditions are met:
0027  *
0028  * 1. Redistributions of source code must retain the above copyright notice, this
0029  *    list of conditions and the following disclaimer.
0030  * 2. Redistributions in binary form must reproduce the above copyright notice,
0031  *    this list of conditions and the following disclaimer in the documentation
0032  *    and/or other materials provided with the distribution.
0033  *
0034  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
0035  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0036  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0037  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
0038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0044  *
0045  * The views and conclusions contained in the software and documentation are those
0046  * of the authors and should not be interpreted as representing official policies,
0047  * either expressed or implied, of the FreeBSD Project.
0048 */
0049 #ifndef LIBBSP_ARM_TMS570_ADC
0050 #define LIBBSP_ARM_TMS570_ADC
0051
0052 #include <bsp/utility.h>
0053
0054 typedef struct{
0055   uint32_t BUF0;              /*Group 0-2 result buffer 0 register*/
0056   uint32_t BUF1;              /*Group 0-2 result buffer 1 register*/
0057   uint32_t BUF2;              /*Group 0-2 result buffer 2 register*/
0058   uint32_t BUF3;              /*Group 0-2 result buffer 3 register*/
0059   uint32_t BUF4;              /*Group 0-2 result buffer 4 register*/
0060   uint32_t BUF5;              /*Group 0-2 result buffer 5 register*/
0061   uint32_t BUF6;              /*Group 0-2 result buffer 6 register*/
0062   uint32_t BUF7;              /*Group 0-2 result buffer 7 register*/
0063 } tms570_gxbuf_t;
0064
0065 typedef struct{
0066   uint32_t RSTCR;             /*ADC Reset Control Register*/
0067   uint32_t OPMODECR;          /*ADC Operating Mode Control Register*/
0068   uint32_t CLOCKCR;           /*ADC Clock Control Register*/
0069   uint32_t CALCR;             /*ADC Calibration Mode Control Register*/
0070   uint32_t GxMODECR[3];       /*ADC Event Group Operating Mode Control Register*/
0071   uint32_t EVSRC;             /*ADC Trigger Source Select Register*/
0072   uint32_t G1SRC;             /*ADC Group1 Trigger Source Select Register*/
0073   uint32_t G2SRC;             /*ADC Group2 Trigger Source Select Register*/
0074   uint32_t GxINTENA[3];       /*ADC Event Interrupt Enable Control Register*/
0075   uint32_t GxINTFLG[3];       /*ADC Event Group Interrupt Flag Register*/
0076   uint32_t GxINTCR[3];        /*ADC Event Group Threshold Interrupt Control Register*/
0077   uint32_t EVDMACR;           /*ADC Event Group DMA Control Register*/
0078   uint32_t G1DMACR;           /*ADC Group1 DMA Control Register*/
0079   uint32_t G2DMACR;           /*ADC Group2 DMA Control Register*/
0080   uint32_t BNDCR;             /*ADC Results Memory Configuration Register*/
0081   uint32_t BNDEND;            /*ADC Results Memory Size Configuration Register*/
0082   uint32_t EVSAMP;            /*ADC Event Group Sampling Time Configuration Register*/
0083   uint32_t G1SAMP;            /*ADC Group1 Sampling Time Configuration Register()*/
0084   uint32_t G2SAMP;            /*ADC Group2 Sampling Time Configuration Register*/
0085   uint32_t EVSR;              /*ADC Event Group Status Register*/
0086   uint32_t G1SR;              /*ADC Group1 Status Register*/
0087   uint32_t G2SR;              /*ADC Group2 Status Register*/
0088   uint32_t GxSEL[3];          /*ADC Event Group Channel Select Register*/
0089   uint32_t CALR;              /*ADC Calibration and Error Offset Correction Register*/
0090   uint32_t SMSTATE;           /*ADC State Machine Status Register*/
0091   uint32_t LASTCONV;          /*ADC Channel Last Conversion Value Register*/
0092   tms570_gxbuf_t GxBUF[3];    /*ADC Event Group Results Emulation FIFO Register*/
0093   uint32_t EVEMUBUFFER;       /*ADC Event Group Results Emulation FIFO Register*/
0094   uint32_t G1EMUBUFFER;       /*ADC Group1 Results Emulation FIFO Register*/
0095   uint32_t G2EMUBUFFER;       /*ADC Group2 Results Emulation FIFO Register*/
0096   uint32_t EVTDIR;            /*ADC ADEVT Pin Direction Control Register*/
0097   uint32_t EVTOUT;            /*ADC ADEVT Pin Output Value Control Register*/
0098   uint32_t EVTIN;             /*ADC ADEVT Pin Input Value Register*/
0099   uint32_t EVTSET;            /*ADC ADEVT Pin Set Register*/
0100   uint32_t EVTCLR;            /*ADC ADEVT Pin Clear Register*/
0101   uint32_t EVTPDR;            /*ADC ADEVT Pin Open Drain Enable Register*/
0102   uint32_t EVTPDIS;           /*ADC ADEVT Pin Pull Control Disable Register*/
0103   uint32_t EVTPSEL;           /*ADC ADEVT Pin Pull Control Select Register*/
0104   uint32_t EVSAMPDISEN;       /*ADC Event Group Sample Cap Discharge Control Register*/
0105   uint32_t G1SAMPDISEN;       /*ADC Group1 Sample Cap Discharge Control Register*/
0106   uint32_t G2SAMPDISEN;       /*ADC Group2 Sample Cap Discharge Control Register*/
0107   uint32_t MAGINTCR1;         /*ADC Magnitude Compare Interrupt Control Register 2*/
0108   uint32_t MAGINT1MASK;       /*ADC Magnitude Compare Mask Register 0*/
0109   uint32_t MAGINTCR2;         /*ADC Magnitude Compare Interrupt Control Register 2*/
0110   uint32_t MAGINT2MASK;       /*ADC Magnitude Compare Mask Register 0*/
0111   uint32_t MAGINTCR3;         /*ADC Magnitude Compare Interrupt Control Register 2*/
0112   uint32_t MAGINT3MASK;       /*ADC Magnitude Compare Mask Register 0*/
0113   uint8_t reserved1 [24];
0114   uint32_t MAGTHRINTENASET;   /*ADC Magnitude Compare Interrupt Enable Set Register*/
0115   uint32_t MAGTHRINTENACLR;   /*ADC Magnitude Compare Interrupt Enable Clear Register*/
0116   uint32_t MAGTHRINTFLG;      /*ADC Magnitude Compare Interrupt Flag Register*/
0117   uint32_t MAGTHRINTOFFSET;   /*ADC Magnitude Compare Interrupt Offset Register*/
0118   uint32_t GxFIFORESETCR[3];  /*ADC Event Group FIFO Reset Control Register*/
0119   uint32_t EVRAMWRADDR;       /*ADC Event Group RAM Write Address Register*/
0120   uint32_t G1RAMWRADDR;       /*ADC Group1 RAM Write Address Register*/
0121   uint32_t G2RAMWRADDR;       /*ADC Group2 RAM Write Address Register*/
0122   uint32_t PARCR;             /*ADC Parity Control Register*/
0123   uint32_t PARADDR;           /*ADC Parity Error Address Register*/
0124   uint32_t PWRUPDLYCTRL;      /*ADC Power-Up Delay Control Register*/
0125 } tms570_adc_t;
0126
0127
0128 /*----------------------TMS570_ADC_BUFx----------------------*/
0129 /* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
0130 #define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
0131
0132 /* field: G2_CHID_10bit_mode - Group2 Channel Id. */
0133 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
0134 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
0135 #define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
0136
0137 /* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
0138 #define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
0139 #define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
0140 #define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0141
0142 /* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
0143 #define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
0144
0145 /* field: G2_CHID_12bit_mode - Group2 Channel Id. */
0146 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
0147 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
0148 #define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
0149
0150 /* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
0151 #define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
0152 #define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
0153 #define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0154
0155
0156 /*----------------------TMS570_ADC_RSTCR----------------------*/
0157 /* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
0158 #define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
0159
0160
0161 /*--------------------TMS570_ADC_OPMODECR--------------------*/
0162 /* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
0163 #define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
0164
0165
0166 /*---------------------TMS570_ADC_CLOCKCR---------------------*/
0167 /* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
0168 #define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
0169 #define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
0170 #define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
0171
0172
0173 /*----------------------TMS570_ADC_CALCR----------------------*/
0174 /* field: SELF_TEST - ADC Self Test Enable. */
0175 #define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
0176
0177 /* field: CAL_ST - ADC Calibration Conversion Start. */
0178 #define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
0179
0180 /* field: BRIDGE_EN - Bridge Enable. */
0181 #define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
0182
0183 /* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
0184 #define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
0185
0186 /* field: CAL_EN - ADC Calibration Enable. */
0187 #define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
0188
0189
0190 /*--------------------TMS570_ADC_GxMODECR--------------------*/
0191 /* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
0192 #define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
0193
0194 /* field: EV_DATA_FMT - Event Group Read Data Format. */
0195 #define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
0196 #define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9)
0197 #define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
0198
0199
0200 /*----------------------TMS570_ADC_EVSRC----------------------*/
0201 /* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
0202 #define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
0203
0204 /* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
0205 #define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
0206
0207 /* field: EV_SRC - Event Group Trigger Source. */
0208 #define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
0209 #define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
0210 #define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0211
0212
0213 /*----------------------TMS570_ADC_G1SRC----------------------*/
0214 /* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
0215 #define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
0216
0217 /* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
0218 #define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
0219
0220 /* field: G1_SRC - Group1 Trigger Source. */
0221 #define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
0222 #define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
0223 #define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0224
0225
0226 /*----------------------TMS570_ADC_G2SRC----------------------*/
0227 /* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
0228 #define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
0229
0230 /* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
0231 #define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
0232
0233 /* field: G2_SRC - Group2 Trigger Source. */
0234 #define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
0235 #define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
0236 #define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0237
0238
0239 /*--------------------TMS570_ADC_GxINTENA--------------------*/
0240 /* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
0241 #define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
0242
0243 /* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
0244 #define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
0245
0246 /* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
0247 #define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
0248
0249
0250 /*--------------------TMS570_ADC_GxINTFLG--------------------*/
0251 /* field: EV_END - Event Group Conversion End. */
0252 #define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
0253
0254 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
0255 #define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
0256
0257 /* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
0258 #define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
0259
0260 /* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
0261 #define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
0262
0263
0264 /*---------------------TMS570_ADC_GxINTCR---------------------*/
0265 /* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
0266 #define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
0267 #define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
0268 #define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15)
0269
0270 /* field: EV_THR - Event Group Threshold Counter. */
0271 #define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8)
0272 #define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8)
0273 #define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0274
0275
0276 /*---------------------TMS570_ADC_EVDMACR---------------------*/
0277 /* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
0278 #define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
0279 #define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
0280 #define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
0281
0282 /* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
0283 #define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
0284
0285 /* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
0286 #define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
0287
0288 /* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
0289 #define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
0290
0291
0292 /*---------------------TMS570_ADC_G1DMACR---------------------*/
0293 /* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
0294 #define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
0295 #define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
0296 #define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
0297
0298 /* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
0299 #define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
0300
0301 /* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
0302 #define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
0303
0304 /* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
0305 #define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
0306
0307
0308 /*---------------------TMS570_ADC_G2DMACR---------------------*/
0309 /* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
0310 #define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
0311 #define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
0312 #define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
0313
0314 /* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
0315 #define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
0316
0317 /* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
0318 #define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
0319
0320 /* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
0321 #define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
0322
0323
0324 /*----------------------TMS570_ADC_BNDCR----------------------*/
0325 /* field: BNDA - Buffer Boundary A. */
0326 #define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
0327 #define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
0328 #define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
0329
0330 /* field: BNDB - Buffer Boundary B. */
0331 #define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8)
0332 #define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8)
0333 #define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0334
0335
0336 /*---------------------TMS570_ADC_BNDEND---------------------*/
0337 /* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
0338 #define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
0339
0340 /* field: BNDEND - Buffer Boundary End. */
0341 #define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
0342 #define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2)
0343 #define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0344
0345
0346 /*---------------------TMS570_ADC_EVSAMP---------------------*/
0347 /* field: EV_ACQ - Event Group Acquisition Time. */
0348 #define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
0349 #define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
0350 #define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0351
0352
0353 /*---------------------TMS570_ADC_G1SAMP---------------------*/
0354 /* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
0355 #define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
0356 #define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
0357 #define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0358
0359
0360 /*---------------------TMS570_ADC_G2SAMP---------------------*/
0361 /* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
0362 #define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
0363 #define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
0364 #define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0365
0366
0367 /*----------------------TMS570_ADC_EVSR----------------------*/
0368 /* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
0369 #define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
0370
0371 /* field: EV_BUSY - Event Group Conversion Busy. */
0372 #define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
0373
0374 /* field: EV_STOP - Event Group Conversion Stopped. */
0375 #define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
0376
0377 /* field: EV_END - Event Group Conversions Ended. */
0378 #define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
0379
0380
0381 /*----------------------TMS570_ADC_G1SR----------------------*/
0382 /* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
0383 #define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
0384
0385 /* field: G1_BUSY - Group1 Conversion Busy. */
0386 #define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
0387
0388 /* field: G1_STOP - Group1 Conversion Stopped. */
0389 #define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
0390
0391 /* field: G1_END - Group1 Conversions Ended. */
0392 #define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
0393
0394
0395 /*----------------------TMS570_ADC_G2SR----------------------*/
0396 /* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
0397 #define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
0398
0399 /* field: G2_BUSY - Group2 Conversion Busy. */
0400 #define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
0401
0402 /* field: G2_STOP - Group2 Conversion Stopped. */
0403 #define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
0404
0405 /* field: G2_END - Group2 Conversions Ended. */
0406 #define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
0407
0408
0409 /*----------------------TMS570_ADC_GxSEL----------------------*/
0410 /* field: EV_SEL - Event Group channels selected. */
0411 #define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
0412 #define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
0413 #define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
0414
0415
0416 /*----------------------TMS570_ADC_CALR----------------------*/
0417 /* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
0418 #define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
0419 #define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
0420 #define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
0421
0422
0423 /*---------------------TMS570_ADC_SMSTATE---------------------*/
0424 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
0425 #define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
0426 #define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
0427 #define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
0428
0429
0430 /*--------------------TMS570_ADC_LASTCONV--------------------*/
0431 /* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
0432 #define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
0433 #define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
0434 #define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
0435
0436
0437 /*----------------------TMS570_ADC_GxBUF----------------------*/
0438 /* field: ADEVT_DIR - ADEVT Pin Direction. */
0439 #define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
0440
0441
0442 /*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
0443 /* field: ADEVT_DIR - ADEVT Pin Direction. */
0444 #define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
0445
0446
0447 /*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
0448 /* field: ADEVT_DIR - ADEVT Pin Direction. */
0449 #define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
0450
0451
0452 /*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
0453 /* field: ADEVT_DIR - ADEVT Pin Direction. */
0454 #define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
0455
0456
0457 /*---------------------TMS570_ADC_EVTDIR---------------------*/
0458 /* field: ADEVT_DIR - ADEVT Pin Direction. */
0459 #define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
0460
0461
0462 /*---------------------TMS570_ADC_EVTOUT---------------------*/
0463 /* field: ADEVT_OUT - ADEVT Pin Output Value. */
0464 #define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
0465
0466
0467 /*----------------------TMS570_ADC_EVTIN----------------------*/
0468 /* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
0469 #define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
0470
0471
0472 /*---------------------TMS570_ADC_EVTSET---------------------*/
0473 /* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
0474 #define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
0475
0476
0477 /*---------------------TMS570_ADC_EVTCLR---------------------*/
0478 /* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
0479 #define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
0480
0481
0482 /*---------------------TMS570_ADC_EVTPDR---------------------*/
0483 /* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
0484 #define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
0485
0486
0487 /*---------------------TMS570_ADC_EVTPDIS---------------------*/
0488 /* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
0489 #define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
0490
0491
0492 /*---------------------TMS570_ADC_EVTPSEL---------------------*/
0493 /* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
0494 #define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
0495
0496
0497 /*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
0498 /* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
0499 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
0500 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
0501 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0502
0503 /* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
0504 #define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
0505
0506
0507 /*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
0508 /* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
0509 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
0510 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
0511 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0512
0513 /* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
0514 #define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
0515
0516
0517 /*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
0518 /* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
0519 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
0520 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
0521 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
0522
0523 /* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
0524 #define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
0525
0526
0527 /*--------------------TMS570_ADC_MAGINTCRx--------------------*/
0528 /* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
0529 #define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
0530 #define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
0531 #define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
0532
0533 /* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
0534 #define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
0535 #define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
0536 #define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
0537
0538 /* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
0539 #define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
0540 #define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
0541 #define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
0542
0543 /* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
0544 #define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
0545
0546 /* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
0547 #define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
0548
0549
0550 /*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
0551 /* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
0552 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
0553 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
0554 #define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0555
0556
0557 /*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
0558 /* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
0559 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
0560 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
0561 #define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0562
0563
0564 /*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
0565 /* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
0566 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
0567 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
0568 #define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0569
0570
0571 /*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
0572 /* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
0573 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
0574 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
0575 #define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
0576
0577
0578 /*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
0579 /* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
0580 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
0581 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
0582 #define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0583
0584
0585 /*------------------TMS570_ADC_GxFIFORESETCR------------------*/
0586 /* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
0587 #define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
0588
0589
0590 /*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
0591 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
0592 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
0593 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
0594 #define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0595
0596
0597 /*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
0598 /* field: G1_RAM_ADDR - Group1 results memory write pointer. */
0599 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
0600 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
0601 #define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0602
0603
0604 /*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
0605 /* field: G2_RAM_ADDR - Group2 results memory write pointer. */
0606 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
0607 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
0608 #define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
0609
0610
0611 /*----------------------TMS570_ADC_PARCR----------------------*/
0612 /* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
0613 #define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
0614
0615 /* field: PARITY_ENA - PARITY ENA */
0616 #define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
0617 #define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
0618 #define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
0619
0620
0621 /*---------------------TMS570_ADC_PARADDR---------------------*/
0622 /* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
0623 #define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
0624 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
0625 #define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
0626
0627
0628 /*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
0629 /* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
0630 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
0631 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
0632 #define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
0633
0634
0635
0636 #endif /* LIBBSP_ARM_TMS570_ADC */