include/bsp/irq.h

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMTMS570
0007  *
0008  * @brief This header file provides TMS570 interrupt definitions.
0009  */
0010
0011 /*
0012  * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com>
0013  *
0014  * Google Summer of Code 2014 at
0015  * Czech Technical University in Prague
0016  * Zikova 1903/4
0017  * 166 36 Praha 6
0018  * Czech Republic
0019  *
0020  * Redistribution and use in source and binary forms, with or without
0021  * modification, are permitted provided that the following conditions
0022  * are met:
0023  * 1. Redistributions of source code must retain the above copyright
0024  *    notice, this list of conditions and the following disclaimer.
0025  * 2. Redistributions in binary form must reproduce the above copyright
0026  *    notice, this list of conditions and the following disclaimer in the
0027  *    documentation and/or other materials provided with the distribution.
0028  *
0029  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0030  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0031  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0032  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0033  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0034  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0035  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0036  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0037  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0038  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0039  * POSSIBILITY OF SUCH DAMAGE.
0040  */
0041
0042 #ifndef LIBBSP_ARM_TMS570_IRQ_H
0043 #define LIBBSP_ARM_TMS570_IRQ_H
0044
0045 #ifndef ASM
0046 #include <rtems.h>
0047 #include <rtems/irq.h>
0048 #include <rtems/irq-extension.h>
0049 #endif
0050
0051 #define TMS570_IRQ_ESM_HIGH 0
0052 #define TMS570_IRQ_RESERVED_0 1
0053 #define TMS570_IRQ_TIMER_0 2
0054 #define TMS570_IRQ_TIMER_1 3
0055 #define TMS570_IRQ_TIMER_2 4
0056 #define TMS570_IRQ_TIMER_3 5
0057 #define TMS570_IRQ_RTI_OVERFLOW_0 6
0058 #define TMS570_IRQ_RTI_OVERFLOW_1 7
0059 #define TMS570_IRQ_RTI_TIMEBASE 8
0060 #define TMS570_IRQ_GIO_HIGH 9
0061 #define TMS570_IRQ_HET_HIGH 10
0062 #define TMS570_IRQ_HET_TU_HIGH 11
0063 #define TMS570_IRQ_MIBSPI1_HIGH 12
0064 #define TMS570_IRQ_SCI_LEVEL_0 13
0065 #define TMS570_IRQ_ADC1_EVENT 14
0066 #define TMS570_IRQ_ADC1_GROUP_1 15
0067 #define TMS570_IRQ_CAN1_HIGH 16
0068 #define TMS570_IRQ_RESERVED_1 17
0069 #define TMS570_IRQ_FLEXRAY_HIGH 18
0070 #define TMS570_IRQ_CRC_1 19
0071 #define TMS570_IRQ_ESM_LOW 20
0072 #define TMS570_IRQ_SSI 21
0073 #define TMS570_IRQ_PMU 22
0074 #define TMS570_IRQ_GIO_LOW 23
0075 #define TMS570_IRQ_HET_LOW 24
0076 #define TMS570_IRQ_HET_TU_LOW 25
0077 #define TMS570_IRQ_MIBSPI1_LOW 26
0078 #define TMS570_IRQ_SCI_LEVEL_1 27
0079 #define TMS570_IRQ_ADC1_GROUP_2 28
0080 #define TMS570_IRQ_CAN1_LOW 29
0081 #define TMS570_IRQ_RESERVED_2 30
0082 #define TMS570_IRQ_ADC1_MAG 31
0083 #define TMS570_IRQ_FLEXRAY_LOW 32
0084 #define TMS570_IRQ_DMA_FTCA 33
0085 #define TMS570_IRQ_DMA_LFSA 34
0086 #define TMS570_IRQ_CAN2_HIGH 35
0087 #define TMS570_IRQ_DMM_HIGH 36
0088 #define TMS570_IRQ_MIBSPI3_HIGH 37
0089 #define TMS570_IRQ_MIBSPI3_LOW 38
0090 #define TMS570_IRQ_DMA_HBCA 39
0091 #define TMS570_IRQ_DMA_BTCA 40
0092 #define TMS570_IRQ_DMA_BERA 41
0093 #define TMS570_IRQ_CAN2_LOW 42
0094 #define TMS570_IRQ_DMM_LOW 43
0095 #define TMS570_IRQ_CAN1_IF3 44
0096 #define TMS570_IRQ_CAN3_HIGH 45
0097 #define TMS570_IRQ_CAN2_IF3 46
0098 #define TMS570_IRQ_FPU 47
0099 #define TMS570_IRQ_FLEXRAY_TU 48
0100 #define TMS570_IRQ_SPI4_HIGH 49
0101 #define TMS570_IRQ_ADC2_EVENT 50
0102 #define TMS570_IRQ_ADC2_GROUP_1 51
0103 #define TMS570_IRQ_FLEXRAY_T0C 52
0104 #define TMS570_IRQ_MIBSPIP5_HIGH 53
0105 #define TMS570_IRQ_SPI4_LOW 54
0106 #define TMS570_IRQ_CAN3_LOW 55
0107 #define TMS570_IRQ_MIBSPIP5_LOW 56
0108 #define TMS570_IRQ_ADC2_GROUP_2 57
0109 #define TMS570_IRQ_FLEXRAY_TU_ERROR 58
0110 #define TMS570_IRQ_ADC2_MAG 59
0111 #define TMS570_IRQ_CAN3_IF3 60
0112 #define TMS570_IRQ_FSM_DONE 61
0113 #define TMS570_IRQ_FLEXRAY_T1C 62
0114 #define TMS570_IRQ_HET2_LEVEL_0 63
0115 #define TMS570_IRQ_SCI2_LEVEL_0 64
0116 #define TMS570_IRQ_HET_TU2_LEVEL_0 65
0117 #define TMS570_IRQ_IC2_INTERRUPT 66
0118 #define TMS570_IRQ_HET2_LEVEL_1 73
0119 #define TMS570_IRQ_SCI2_LEVEL_1 74
0120 #define TMS570_IRQ_HET_TU2_LEVEL_1 75
0121 #define TMS570_IRQ_EMAC_MISC 76
0122 #define TMS570_IRQ_EMAC_TX   77
0123 #define TMS570_IRQ_EMAC_THRESH 78
0124 #define TMS570_IRQ_EMAC_RX   79
0125 #define TMS570_IRQ_HWAG1_INT_REQ_H 80
0126 #define TMS570_IRQ_HWAG2_INT_REQ_H 81
0127 #define TMS570_IRQ_DCC_DONE_INTERRUPT 82
0128 #define TMS570_IRQ_DCC2_DONE_INTERRUPT 83
0129 #define TMS570_IRQ_HWAG1_INT_REQ_L 88
0130 #define TMS570_IRQ_HWAG2_INT_REQ_L 89
0131 #define BSP_INTERRUPT_VECTOR_COUNT 95
0132
0133 #define TMS570_IRQ_PRIORITY_VALUE_MIN 0U
0134 #define TMS570_IRQ_PRIORITY_VALUE_MAX 0U
0135
0136 #define TMS570_IRQ_PRIORITY_COUNT ( TMS570_IRQ_PRIORITY_VALUE_MAX + 1U )
0137 #define TMS570_IRQ_PRIORITY_HIGHEST TMS570_IRQ_PRIORITY_VALUE_MIN
0138 #define TMS570_IRQ_PRIORITY_LOWEST TMS570_IRQ_PRIORITY_VALUE_MAX
0139
0140 #ifndef ASM
0141
0142 /**
0143  * @brief Sets the priority of the interrupt vector.
0144  *
0145  * The priority is defined by the VIM interrupt channel.  Firstly, the VIM
0146  * Interrupt Control (CHANCTRL) registers are searched to get the current
0147  * channel associated with the interrupt vector.  The interrupt vector of the
0148  * channel associated with the priority is assigned to this channel.  The
0149  * specified interrupt vector is assigned to the channel associated with the
0150  * priority.  So, this function swaps the channels of two interrupt vectors.
0151  *
0152  * @param vector is the number of the interrupt vector to set the priority.
0153  *
0154  * @param priority is the priority to set.
0155  *
0156  * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
0157  *
0158  * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
0159  *   number specified by ``vector``.
0160  *
0161  * @retval ::RTEMS_INVALID_PRIORITY The interrupt priority specified in
0162  *   ``priority`` was invalid.
0163  */
0164 rtems_status_code tms570_irq_set_priority(
0165   rtems_vector_number vector,
0166   uint32_t            priority
0167 );
0168
0169 /**
0170  * @brief Gets the priority of the interrupt vector.
0171  *
0172  * The priority is defined by the VIM interrupt channel.  The VIM Interrupt
0173  * Control (CHANCTRL) registers are searched to get the channel associated with
0174  * the interrupt vector.
0175  *
0176  * @param vector is the number of the interrupt vector to set the priority.
0177  *
0178  * @param priority is the priority to set.
0179  *
0180  * @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
0181  *
0182  * @retval ::RTEMS_INVALID_ADDRESS The ``priority`` parameter was NULL.
0183  *
0184  * @retval ::RTEMS_INVALID_ID There was no interrupt vector associated with the
0185  *   number specified by ``vector``.
0186  *
0187  * @retval ::RTEMS_NOT_DEFINED The interrupt has no associated priority.
0188  */
0189 rtems_status_code tms570_irq_get_priority(
0190   rtems_vector_number  vector,
0191   uint32_t            *priority
0192 );
0193
0194 #endif /* ASM */
0195
0196 /** @} */
0197
0198 #endif /* LIBBSP_ARM_TMS570_IRQ_H */