stm32h7/start/mpu-config.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /*
0004  * Copyright (C) 2020 embedded brains GmbH & Co. KG
0005  *
0006  * Redistribution and use in source and binary forms, with or without
0007  * modification, are permitted provided that the following conditions
0008  * are met:
0009  * 1. Redistributions of source code must retain the above copyright
0010  *    notice, this list of conditions and the following disclaimer.
0011  * 2. Redistributions in binary form must reproduce the above copyright
0012  *    notice, this list of conditions and the following disclaimer in the
0013  *    documentation and/or other materials provided with the distribution.
0014  *
0015  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0016  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0017  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0018  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0019  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0020  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0021  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0022  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0023  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0024  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0025  * POSSIBILITY OF SUCH DAMAGE.
0026  */
0027
0028 #include <bsp/linker-symbols.h>
0029 #include <stm32h7/memory.h>
0030 #include <stm32h7/mpu-config.h>
0031
0032 const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] = {
0033     {
0034       .begin = stm32h7_memory_sram_axi_begin,
0035       .end = stm32h7_memory_sram_axi_end,
0036       .rasr = ARMV7M_MPU_RASR_XN
0037         | ARMV7M_MPU_RASR_AP(0x3)
0038         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0039         | ARMV7M_MPU_RASR_ENABLE,
0040     }, {
0041       .begin = stm32h7_memory_sdram_1_begin,
0042       .end = stm32h7_memory_sdram_1_end,
0043       .rasr = ARMV7M_MPU_RASR_XN
0044         | ARMV7M_MPU_RASR_AP(0x3)
0045         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0046         | ARMV7M_MPU_RASR_ENABLE,
0047     }, {
0048       .begin = stm32h7_memory_sdram_2_begin,
0049       .end = stm32h7_memory_sdram_2_end,
0050       .rasr = ARMV7M_MPU_RASR_XN
0051         | ARMV7M_MPU_RASR_AP(0x3)
0052         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0053         | ARMV7M_MPU_RASR_ENABLE,
0054     }, {
0055       .begin = bsp_section_start_begin,
0056       .end = bsp_section_text_end,
0057       .rasr = ARMV7M_MPU_RASR_AP(0x5)
0058         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0059         | ARMV7M_MPU_RASR_ENABLE,
0060     }, {
0061       .begin = bsp_section_rodata_begin,
0062       .end = bsp_section_rodata_end,
0063       .rasr = ARMV7M_MPU_RASR_XN
0064         | ARMV7M_MPU_RASR_AP(0x5)
0065         | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
0066         | ARMV7M_MPU_RASR_ENABLE,
0067     }, {
0068       .begin = bsp_section_nocache_begin,
0069       .end = bsp_section_nocachenoload_end,
0070       .rasr = ARMV7M_MPU_RASR_XN
0071         | ARMV7M_MPU_RASR_AP(0x3)
0072         | ARMV7M_MPU_RASR_TEX(0x2)
0073         | ARMV7M_MPU_RASR_ENABLE,
0074     }, {
0075       .begin = stm32h7_memory_null_begin,
0076       .end = stm32h7_memory_null_end,
0077       .rasr = ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_ENABLE,
0078     }
0079   };
0080
0081 const size_t stm32h7_config_mpu_region_count =
0082   RTEMS_ARRAY_SIZE(stm32h7_config_mpu_region);