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File indexing completed on 2025-05-11 08:23:38 

0001 /**
0002   ******************************************************************************
0003   * @file    system_stm32h7xx.c
0004   * @author  MCD Application Team
0005   * @brief   CMSIS Cortex-M Device Peripheral Access Layer System Source File.
0006   *
0007   *   This file provides two functions and one global variable to be called from 
0008   *   user application:
0009   *      - SystemInit(): This function is called at startup just after reset and 
0010   *                      before branch to main program. This call is made inside
0011   *                      the "startup_stm32h7xx.s" file.
0012   *
0013   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
0014   *                                  by the user application to setup the SysTick 
0015   *                                  timer or configure other parameters.
0016   *                                     
0017   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
0018   *                                 be called whenever the core clock is changed
0019   *                                 during program execution.
0020   *
0021   *
0022   ******************************************************************************
0023   * @attention
0024   *
0025   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
0026   * All rights reserved.</center></h2>
0027   *
0028   * This software component is licensed by ST under BSD 3-Clause license,
0029   * the "License"; You may not use this file except in compliance with the
0030   * License. You may obtain a copy of the License at:
0031   *                        opensource.org/licenses/BSD-3-Clause
0032   *
0033   ******************************************************************************
0034   */
0035 
0036 #include <stm32h7xx_hal.h>
0037 
0038 #define DATA_IN_ExtSRAM
0039 #define DATA_IN_ExtSDRAM
0040 
0041 void  SystemInit_ExtMemCtl(void)
0042 {
0043 
0044   #define  FMC_BMAP_Value    0x02000000    /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
0045 
0046   __IO uint32_t  tmp = 0;
0047 
0048 
0049   /********** SDRAM + SRAM ***********************************************************************/
0050 
0051   #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
0052 
0053   register uint32_t       tmpreg = 0, timeout = 0xFFFF;
0054   register __IO uint32_t  index;
0055   
0056   /*-- I/O Ports Configuration ------------------------------------------------------*/
0057 
0058   /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
0059   RCC->AHB4ENR |= 0x000001F8;
0060   
0061   /* Delay after an RCC peripheral clock enabling */
0062   tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
0063   
0064   /* Connect PDx pins to FMC Alternate function */     
0065   GPIOD->AFR[0]  = 0x00CC00CC;
0066   GPIOD->AFR[1]  = 0xCCCCCCCC;
0067   /* Configure PDx pins in Alternate function mode */  
0068   GPIOD->MODER   = 0xAAAAFAFA;
0069   /* Configure PDx pins speed to 100 MHz */  
0070   GPIOD->OSPEEDR = 0xFFFF0F0F;
0071   /* Configure PDx pins Output type to push-pull */  
0072   GPIOD->OTYPER  = 0x00000000;
0073   /* Configure PDx pins in Pull-up */
0074   GPIOD->PUPDR   = 0x55550505;
0075 
0076   /* Connect PEx pins to FMC Alternate function */
0077   GPIOE->AFR[0]  = 0xC00CC0CC;
0078   GPIOE->AFR[1]  = 0xCCCCCCCC;
0079   /* Configure PEx pins in Alternate function mode */ 
0080   GPIOE->MODER   = 0xAAAABEBA;
0081   /* Configure PEx pins speed to 100 MHz */ 
0082   GPIOE->OSPEEDR = 0xFFFFC3CF;
0083   /* Configure PEx pins Output type to push-pull */  
0084   GPIOE->OTYPER  = 0x00000000;
0085   /* Configure PEx pins in Pull-up */
0086   GPIOE->PUPDR   = 0x55554145;
0087 
0088   /* Connect PFx pins to FMC Alternate function */
0089   GPIOF->AFR[0]  = 0x00CCCCCC;
0090   GPIOF->AFR[1]  = 0xCCCCC000;
0091   /* Configure PFx pins in Alternate function mode */   
0092   GPIOF->MODER   = 0xAABFFAAA;
0093   /* Configure PFx pins speed to 100 MHz */ 
0094   GPIOF->OSPEEDR = 0xFFC00FFF;
0095   /* Configure PFx pins Output type to push-pull */  
0096   GPIOF->OTYPER  = 0x00000000;
0097   /* Configure PFx pins in Pull-up */
0098   GPIOF->PUPDR   = 0x55400555;
0099 
0100   /* Connect PGx pins to FMC Alternate function */
0101   GPIOG->AFR[0]  = 0x00CCCCCC;
0102   GPIOG->AFR[1]  = 0xC0000C0C;
0103   /* Configure PGx pins in Alternate function mode */ 
0104   GPIOG->MODER   = 0xBFEEFAAA;
0105   /* Configure PGx pins speed to 100 MHz */ 
0106   GPIOG->OSPEEDR = 0xC0330FFF;
0107   /* Configure PGx pins Output type to push-pull */  
0108   GPIOG->OTYPER  = 0x00000000;
0109   /* Configure PGx pins in Pull-up */ 
0110   GPIOG->PUPDR   = 0x40110555;
0111   
0112   /* Connect PHx pins to FMC Alternate function */
0113   GPIOH->AFR[0]  = 0xCCC00000;
0114   GPIOH->AFR[1]  = 0xCCCCCCCC;
0115   /* Configure PHx pins in Alternate function mode */ 
0116   GPIOH->MODER   = 0xAAAAABFF;
0117   /* Configure PHx pins speed to 100 MHz */ 
0118   GPIOH->OSPEEDR = 0xFFFFFC00;
0119   /* Configure PHx pins Output type to push-pull */  
0120   GPIOH->OTYPER  = 0x00000000;
0121   /* Configure PHx pins in Pull-up */
0122   GPIOH->PUPDR   = 0x55555400;
0123   
0124   /* Connect PIx pins to FMC Alternate function */
0125   GPIOI->AFR[0]  = 0xCCCCCCCC;
0126   GPIOI->AFR[1]  = 0x00000CC0;
0127   /* Configure PIx pins in Alternate function mode */ 
0128   GPIOI->MODER   = 0xFFEBAAAA;
0129   /* Configure PIx pins speed to 100 MHz */ 
0130   GPIOI->OSPEEDR = 0x003CFFFF;
0131   /* Configure PIx pins Output type to push-pull */  
0132   GPIOI->OTYPER  = 0x00000000;
0133   /* Configure PIx pins in Pull-up */
0134   GPIOI->PUPDR   = 0x00145555;
0135 
0136   /*-- FMC Configuration ------------------------------------------------------*/
0137 
0138   /* Enable the FMC/FSMC interface clock */
0139   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0140   
0141   /* Configure and enable Bank1_SRAM2 */
0142   FMC_Bank1_R->BTCR[4]  = 0x00001091;
0143   FMC_Bank1_R->BTCR[5]  = 0x00110212;
0144   FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
0145   
0146   /* SDRAM Timing and access interface configuration */
0147 
0148   /*SDBank               = FMC_SDRAM_BANK2
0149 
0150     ColumnBitsNumber     = FMC_SDRAM_COLUMN_BITS_NUM_9           CC
0151     RowBitsNumber        = FMC_SDRAM_ROW_BITS_NUM_12             RR
0152     MemoryDataWidth      = FMC_SDRAM_MEM_BUS_WIDTH_32            MM
0153     InternalBankNumber   = FMC_SDRAM_INTERN_BANKS_NUM_4          N
0154     CASLatency           = FMC_SDRAM_CAS_LATENCY_2               LL   // 2 oder 3, s.u.
0155     WriteProtection      = FMC_SDRAM_WRITE_PROTECTION_DISABLE    W
0156     SDClockPeriod        = FMC_SDRAM_CLOCK_PERIOD_2              KK
0157     ReadBurst            = FMC_SDRAM_RBURST_ENABLE               B
0158     ReadPipeDelay        = FMC_SDRAM_RPIPE_DELAY_0               PP
0159   
0160     LoadToActiveDelay    = 2  -> 1     LLLL     TMRD
0161     ExitSelfRefreshDelay = 6  -> 5     EEEE     TXSR
0162     SelfRefreshTime      = 4  -> 3     SSSS     TRAS
0163     RowCycleDelay        = 6  -> 5     RRRR     TRC
0164     WriteRecoveryTime    = 2  -> 1     WWWW     TWR
0165     RPDelay              = 2  -> 1     PPPP     TRP
0166     RCDDelay             = 2  -> 1     CCCC     TRCD              */
0167   #if 0
0168   FMC_Bank5_6_R->SDCR[0] = 0x00005965;  // 0000 0000 0000 0000 0101 1001 0110 0101  Bank 1
0169                                         //                      PPB KKWL LNMM RRCC
0170   FMC_Bank5_6_R->SDCR[1] = 0x00005965;  // 0000 0000 0000 0000 0101 1001 0110 0101  Bank 2  // CAS Latency = 2
0171                                         //                            WL LNMM RRCC
0172 
0173   FMC_Bank5_6_R->SDTR[0] = 0x00105000;  // 0000 0000 0001 0000 0101 0000 0000 0000  Bank 1  // Original,
0174                                         //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 2 (s.o.)
0175   FMC_Bank5_6_R->SDTR[1] = 0x01010351;  // 0000 0001 0000 0001 0000 0011 0101 0001  Bank 2
0176                                         //      CCCC      WWWW      SSSS EEEE LLLL
0177   #endif
0178   #if 0
0179   FMC_Bank5_6_R->SDTR[0] = 0x00206000;  // 0000 0000 0010 0000 0110 0000 0000 0000  Bank 1  // Original + 1 bei allen Werten,
0180                                         //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 3 (s.o.)
0181   FMC_Bank5_6_R->SDTR[1] = 0x02020462;  // 0000 0010 0000 0010 0000 0100 0110 0010  Bank 2
0182                                         //      CCCC      WWWW      SSSS EEEE LLLL
0183   #endif
0184 
0185   #if 0
0186   FMC_Bank5_6_R->SDTR[0] = 0x00209000;  // 0000 0000 0010 0000 1001 0000 0000 0000  Bank 1  // Versuch anhand ISSI-Datenblatt,
0187                                         //      CCCC PPPP WWWW RRRR SSSS EEEE LLLL          // mit CAS Latency = 3 (s.o.)
0188   FMC_Bank5_6_R->SDTR[1] = 0x020306B1;  // 0000 0010 0000 0011 0000 0110 1011 0001  Bank 2
0189                                         //      CCCC      WWWW      SSSS EEEE LLLL
0190   #endif
0191   FMC_Bank5_6_R->SDCR[0] = 0x00001800;
0192   FMC_Bank5_6_R->SDCR[1] = 0x00000165;
0193   FMC_Bank5_6_R->SDTR[0] = 0x00105000;
0194   FMC_Bank5_6_R->SDTR[1] = 0x01010351;
0195   
0196   /* SDRAM initialization sequence */
0197 
0198   /* Clock enable command */ 
0199   FMC_Bank5_6_R->SDCMR = 0x00000009; 
0200   tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0201   while ((tmpreg != 0) && (timeout-- > 0))
0202   {
0203     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0204   }
0205 
0206   /* Delay */
0207   for (index=0; index<1000; index++);
0208   
0209   /* PALL command */ 
0210   FMC_Bank5_6_R->SDCMR = 0x0000000A;    
0211   timeout = 0xFFFF;
0212   while ((tmpreg != 0) && (timeout-- > 0))
0213   {
0214     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0215   }
0216   
0217   FMC_Bank5_6_R->SDCMR = 0x000000EB;
0218   timeout = 0xFFFF;
0219   while ((tmpreg != 0) && (timeout-- > 0))
0220   {
0221     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0222   }
0223 
0224   FMC_Bank5_6_R->SDCMR = 0x0004400C;
0225   timeout = 0xFFFF;
0226   while ((tmpreg != 0) && (timeout-- > 0))
0227   {
0228     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0229   }
0230 
0231   /* Set refresh count */
0232   tmpreg = FMC_Bank5_6_R->SDRTR;
0233   FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
0234 
0235   /* Disable write protection */
0236   tmpreg = FMC_Bank5_6_R->SDCR[1]; 
0237   FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
0238 
0239   /* Configure FMC Bank Mapping */
0240   FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
0241 
0242    /* FMC controller Enable */
0243   FMC_Bank1_R->BTCR[0] |= 0x80000000;
0244   
0245 
0246   /********** SDRAM only *************************************************************************/
0247 
0248   #elif defined (DATA_IN_ExtSDRAM)
0249 
0250   register uint32_t  tmpreg = 0, timeout = 0xFFFF;
0251   register __IO      uint32_t index;
0252 
0253   /*-- I/O Ports Configuration ------------------------------------------------------*/
0254 
0255   /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
0256   RCC->AHB4ENR |= 0x000001F8;
0257   
0258   /* Connect PDx pins to FMC Alternate function */
0259   GPIOD->AFR[0]  = 0x000000CC;
0260   GPIOD->AFR[1]  = 0xCC000CCC;
0261   /* Configure PDx pins in Alternate function mode */  
0262   GPIOD->MODER   = 0xAFEAFFFA;
0263   /* Configure PDx pins speed to 100 MHz */  
0264   GPIOD->OSPEEDR = 0xF03F000F;
0265   /* Configure PDx pins Output type to push-pull */  
0266   GPIOD->OTYPER  = 0x00000000;
0267   /* Configure PDx pins in Pull-up */
0268   GPIOD->PUPDR   = 0x50150005;
0269    
0270   /* Connect PEx pins to FMC Alternate function */
0271   GPIOE->AFR[0]  = 0xC00000CC;
0272   GPIOE->AFR[1]  = 0xCCCCCCCC;
0273   /* Configure PEx pins in Alternate function mode */ 
0274   GPIOE->MODER   = 0xAAAABFFA;
0275   /* Configure PEx pins speed to 100 MHz */ 
0276   GPIOE->OSPEEDR = 0xFFFFC00F;
0277   /* Configure PEx pins Output type to push-pull */  
0278   GPIOE->OTYPER  = 0x00000000;
0279   /* Configure PEx pins in Pull-up */
0280   GPIOE->PUPDR   = 0x55554005;
0281   
0282   /* Connect PFx pins to FMC Alternate function */
0283   GPIOF->AFR[0]  = 0x00CCCCCC;
0284   GPIOF->AFR[1]  = 0xCCCCC000;
0285   /* Configure PFx pins in Alternate function mode */   
0286   GPIOF->MODER   = 0xAABFFAAA;
0287   /* Configure PFx pins speed to 100 MHz */ 
0288   GPIOF->OSPEEDR = 0xFFC00FFF;
0289   /* Configure PFx pins Output type to push-pull */  
0290   GPIOF->OTYPER  = 0x00000000;
0291   /* Configure PFx pins in Pull-up */
0292   GPIOF->PUPDR   = 0x55400555;
0293   
0294   /* Connect PGx pins to FMC Alternate function */
0295   GPIOG->AFR[0]  = 0x00CCCCCC;
0296   GPIOG->AFR[1]  = 0xC000000C;
0297   /* Configure PGx pins in Alternate function mode */ 
0298   GPIOG->MODER   = 0xBFFEFAAA;
0299  /* Configure PGx pins speed to 100 MHz */ 
0300   GPIOG->OSPEEDR = 0xC0030FFF;
0301   /* Configure PGx pins Output type to push-pull */  
0302   GPIOG->OTYPER  = 0x00000000;
0303   /* Configure PGx pins in Pull-up */ 
0304   GPIOG->PUPDR   = 0x40010555;
0305   
0306   /* Connect PHx pins to FMC Alternate function */
0307   GPIOH->AFR[0]  = 0xCCC00000;
0308   GPIOH->AFR[1]  = 0xCCCCCCCC;
0309   /* Configure PHx pins in Alternate function mode */ 
0310   GPIOH->MODER   = 0xAAAAABFF;
0311   /* Configure PHx pins speed to 100 MHz */ 
0312   GPIOH->OSPEEDR = 0xFFFFFC00;
0313   /* Configure PHx pins Output type to push-pull */  
0314   GPIOH->OTYPER  = 0x00000000;
0315   /* Configure PHx pins in Pull-up */
0316   GPIOH->PUPDR   = 0x55555400;
0317   
0318   /* Connect PIx pins to FMC Alternate function */
0319   GPIOI->AFR[0]  = 0xCCCCCCCC;
0320   GPIOI->AFR[1]  = 0x00000CC0;
0321   /* Configure PIx pins in Alternate function mode */ 
0322   GPIOI->MODER   = 0xFFEBAAAA;
0323   /* Configure PIx pins speed to 100 MHz */ 
0324   GPIOI->OSPEEDR = 0x003CFFFF;
0325   /* Configure PIx pins Output type to push-pull */  
0326   GPIOI->OTYPER  = 0x00000000;
0327   /* Configure PIx pins in Pull-up */
0328   GPIOI->PUPDR   = 0x00145555;
0329   
0330   /*-- FMC Configuration ------------------------------------------------------*/
0331 
0332   /* Enable the FMC interface clock */
0333   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0334 
0335   /* SDRAM Timing and access interface configuration */
0336 
0337   /*LoadToActiveDelay    = 2
0338     ExitSelfRefreshDelay = 6
0339     SelfRefreshTime      = 4
0340     RowCycleDelay        = 6
0341     WriteRecoveryTime    = 2
0342     RPDelay              = 2
0343     RCDDelay             = 2
0344     SDBank               = FMC_SDRAM_BANK2
0345     ColumnBitsNumber     = FMC_SDRAM_COLUMN_BITS_NUM_9 
0346     RowBitsNumber        = FMC_SDRAM_ROW_BITS_NUM_12
0347     MemoryDataWidth      = FMC_SDRAM_MEM_BUS_WIDTH_32
0348     InternalBankNumber   = FMC_SDRAM_INTERN_BANKS_NUM_4
0349     CASLatency           = FMC_SDRAM_CAS_LATENCY_2
0350     WriteProtection      = FMC_SDRAM_WRITE_PROTECTION_DISABLE
0351     SDClockPeriod        = FMC_SDRAM_CLOCK_PERIOD_2
0352     ReadBurst            = FMC_SDRAM_RBURST_ENABLE
0353     ReadPipeDelay        = FMC_SDRAM_RPIPE_DELAY_0*/
0354   
0355   FMC_Bank5_6_R->SDCR[0] = 0x00001800;
0356   FMC_Bank5_6_R->SDCR[1] = 0x00000165;
0357   FMC_Bank5_6_R->SDTR[0] = 0x00105000;
0358   FMC_Bank5_6_R->SDTR[1] = 0x01010351;
0359 
0360   /* SDRAM initialization sequence */
0361   /* Clock enable command */ 
0362   FMC_Bank5_6_R->SDCMR = 0x00000009; 
0363   tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0364   while ((tmpreg != 0) && (timeout-- > 0))
0365   {
0366     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0367   }
0368 
0369   /* Delay */
0370   for (index=0; index<1000; index++);
0371   
0372   /* PALL command */ 
0373     FMC_Bank5_6_R->SDCMR = 0x0000000A;  
0374   timeout = 0xFFFF;
0375   while ((tmpreg != 0) && (timeout-- > 0))
0376   {
0377     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0378   }
0379   
0380   FMC_Bank5_6_R->SDCMR = 0x000000EB;
0381   timeout = 0xFFFF;
0382   while ((tmpreg != 0) && (timeout-- > 0))
0383   {
0384     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0385   }
0386 
0387   FMC_Bank5_6_R->SDCMR = 0x0004400C;
0388   timeout = 0xFFFF;
0389   while ((tmpreg != 0) && (timeout-- > 0))
0390   {
0391     tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020; 
0392   } 
0393   /* Set refresh count */
0394   tmpreg = FMC_Bank5_6_R->SDRTR;
0395   FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
0396 
0397   /* Disable write protection */
0398   tmpreg = FMC_Bank5_6_R->SDCR[1]; 
0399   FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
0400 
0401   /* FMC controller Enable */
0402   FMC_Bank1_R->BTCR[0]  |= 0x80000000;
0403 
0404   /********** SRAM only **************************************************************************/
0405 
0406   #elif defined(DATA_IN_ExtSRAM)
0407 
0408   /*-- I/O Ports Configuration -----------------------------------------------------*/
0409 
0410   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
0411   RCC->AHB4ENR |= 0x00000078;
0412   
0413   /* Connect PDx pins to FMC Alternate function */     
0414   GPIOD->AFR[0]  = 0x00CC00CC;
0415   GPIOD->AFR[1]  = 0xCCCCCCCC;
0416   /* Configure PDx pins in Alternate function mode */  
0417   GPIOD->MODER   = 0xAAAAFABA;
0418   /* Configure PDx pins speed to 100 MHz */  
0419   GPIOD->OSPEEDR = 0xFFFF0F0F;
0420   /* Configure PDx pins Output type to push-pull */  
0421   GPIOD->OTYPER  = 0x00000000;
0422   /* Configure PDx pins in Pull-up */ 
0423   GPIOD->PUPDR   = 0x55550505;
0424 
0425   /* Connect PEx pins to FMC Alternate function */
0426   GPIOE->AFR[0]  = 0xC00CC0CC;
0427   GPIOE->AFR[1]  = 0xCCCCCCCC;
0428   /* Configure PEx pins in Alternate function mode */ 
0429   GPIOE->MODER   = 0xAAAABEBA;
0430   /* Configure PEx pins speed to 100 MHz */ 
0431   GPIOE->OSPEEDR = 0xFFFFC3CF;
0432   /* Configure PEx pins Output type to push-pull */  
0433   GPIOE->OTYPER  = 0x00000000;
0434   /* Configure PEx pins in Pull-up */
0435   GPIOE->PUPDR   = 0x55554145;
0436 
0437   /* Connect PFx pins to FMC Alternate function */
0438   GPIOF->AFR[0]  = 0x00CCCCCC;
0439   GPIOF->AFR[1]  = 0xCCCC0000;
0440   /* Configure PFx pins in Alternate function mode */   
0441   GPIOF->MODER   = 0xAAFFFAAA;
0442   /* Configure PFx pins speed to 100 MHz */ 
0443   GPIOF->OSPEEDR = 0xFF000FFF;
0444   /* Configure PFx pins Output type to push-pull */  
0445   GPIOF->OTYPER  = 0x00000000;
0446   /* Configure PFx pins in Pull-up */ 
0447   GPIOF->PUPDR   = 0x55000555;
0448 
0449   /* Connect PGx pins to FMC Alternate function */
0450   GPIOG->AFR[0]  = 0x00CCCCCC;
0451   GPIOG->AFR[1]  = 0x00000C00;
0452   /* Configure PGx pins in Alternate function mode */ 
0453   GPIOG->MODER   = 0xFFEFFAAA;
0454   /* Configure PGx pins speed to 100 MHz */ 
0455   GPIOG->OSPEEDR = 0x00300FFF;
0456   /* Configure PGx pins Output type to push-pull */  
0457   GPIOG->OTYPER  = 0x00000000;
0458   /* Configure PGx pins in Pull-up */ 
0459   GPIOG->PUPDR   = 0x00100555;
0460   
0461   /*-- FMC/FSMC Configuration --------------------------------------------------*/
0462 
0463   /* Enable the FMC/FSMC interface clock */
0464   (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
0465 
0466   /* Configure and enable Bank1_SRAM2 */
0467   FMC_Bank1_R->BTCR[4]  = 0x00001091;
0468   FMC_Bank1_R->BTCR[5]  = 0x00110212;
0469   FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;  
0470   
0471   /* FMC controller Enable */
0472   FMC_Bank1_R->BTCR[0] |= 0x80000000;  
0473 
0474   #endif /* DATA_IN_ExtSRAM */
0475   
0476   (void)(tmp);
0477 
0478 }
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