stm32h7/spi/spi3.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMSTM32H7
0007  *
0008  * @brief This source file contains the shared SPI3 peripheral configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifdef HAVE_CONFIG_H
0037 #include "config.h"
0038 #endif
0039
0040 #include <stm32h7/hal.h>
0041
0042 #ifdef SPI3
0043
0044 /*
0045  * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI3 can occupy:
0046  * AF5:
0047  *   MOSI D6
0048  * AF6:
0049  *   NSS A4
0050  *   NSS A15
0051  *   SCK B3
0052  *   SCK C10
0053  *   MISO B4
0054  *   MISO C11
0055  *   MOSI C12
0056  * AF7:
0057  *   MOSI B2
0058  *   MOSI B5
0059  */
0060 stm32h7_spi_context stm32h7_spi3_instance = {
0061   .spi = {
0062     .Instance = SPI3,
0063     /* Configure full-duplex SPI master with 8 bit data size */
0064     .Init.Mode = SPI_MODE_MASTER,
0065     .Init.Direction = SPI_DIRECTION_2LINES,
0066     .Init.DataSize = SPI_DATASIZE_8BIT,
0067     /* Configure mode 0 */
0068     .Init.CLKPolarity = SPI_POLARITY_LOW,
0069     .Init.CLKPhase = SPI_PHASE_1EDGE,
0070     /* Assume software-controlled-chip-select */
0071     .Init.NSS = SPI_NSS_SOFT,
0072     .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
0073     .Init.FirstBit = SPI_FIRSTBIT_MSB,
0074     .Init.TIMode = SPI_TIMODE_DISABLE,
0075     /* Disable CRC calculation */
0076     .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
0077     .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
0078     .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
0079     .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
0080     .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
0081     .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
0082     .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
0083     .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
0084     .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
0085     .Init.IOSwap = SPI_IO_SWAP_DISABLE
0086
0087   },
0088   .config = &stm32h7_spi3_config,
0089   .irq = SPI3_IRQn
0090 };
0091
0092 #endif /* SPI3 */