stm32h7/spi/spi2.c

0001 /* SPDX-License-Identifier: BSD-2-Clause */
0002
0003 /**
0004  * @file
0005  *
0006  * @ingroup RTEMSBSPsARMSTM32H7
0007  *
0008  * @brief This source file contains the shared SPI2 peripheral configuration.
0009  */
0010
0011 /*
0012  * Copyright (C) 2024 On-Line Applications Research (OAR) Corporation
0013  *
0014  * Redistribution and use in source and binary forms, with or without
0015  * modification, are permitted provided that the following conditions
0016  * are met:
0017  * 1. Redistributions of source code must retain the above copyright
0018  *    notice, this list of conditions and the following disclaimer.
0019  * 2. Redistributions in binary form must reproduce the above copyright
0020  *    notice, this list of conditions and the following disclaimer in the
0021  *    documentation and/or other materials provided with the distribution.
0022  *
0023  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
0024  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0025  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
0026  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
0027  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
0028  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
0029  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
0030  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
0031  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
0032  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0033  * POSSIBILITY OF SUCH DAMAGE.
0034  */
0035
0036 #ifdef HAVE_CONFIG_H
0037 #include "config.h"
0038 #endif
0039
0040 #include <stm32h7/hal.h>
0041
0042 #ifdef SPI2
0043
0044 /*
0045  * On most stm32h7 CPUs (at least 743/747/750/753/755/757/7b3), SPI2 can occupy:
0046  * AF5:
0047  *   NSS A11
0048  *   NSS B9
0049  *   NSS B12
0050  *   NSS I0
0051  *   SCK A9
0052  *   SCK A12
0053  *   SCK B10
0054  *   SCK B13
0055  *   SCK D3
0056  *   SCK I1
0057  *   MISO B14
0058  *   MISO C2
0059  *   MISO I2
0060  *   MOSI B15
0061  *   MOSI C1
0062  *   MOSI C3
0063  *   MOSI I3
0064  * AF7:
0065  *   NSS B4
0066  */
0067 stm32h7_spi_context stm32h7_spi2_instance = {
0068   .spi = {
0069     .Instance = SPI2,
0070     /* Configure full-duplex SPI master with 8 bit data size */
0071     .Init.Mode = SPI_MODE_MASTER,
0072     .Init.Direction = SPI_DIRECTION_2LINES,
0073     .Init.DataSize = SPI_DATASIZE_8BIT,
0074     /* Configure mode 0 */
0075     .Init.CLKPolarity = SPI_POLARITY_LOW,
0076     .Init.CLKPhase = SPI_PHASE_1EDGE,
0077     /* Assume software-controlled-chip-select */
0078     .Init.NSS = SPI_NSS_SOFT,
0079     .Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2,
0080     .Init.FirstBit = SPI_FIRSTBIT_MSB,
0081     .Init.TIMode = SPI_TIMODE_DISABLE,
0082     /* Disable CRC calculation */
0083     .Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE,
0084     .Init.NSSPMode = SPI_NSS_PULSE_DISABLE,
0085     .Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA,
0086     .Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
0087     .Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN,
0088     .Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE,
0089     .Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE,
0090     .Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE,
0091     .Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE,
0092     .Init.IOSwap = SPI_IO_SWAP_DISABLE
0093
0094   },
0095   .config = &stm32h7_spi2_config,
0096   .irq = SPI2_IRQn
0097 };
0098
0099 #endif /* SPI2 */