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File indexing completed on 2025-05-11 08:23:38
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_wwdg.h 0004 * @author MCD Application Team 0005 * @brief Header file of WWDG LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_WWDG_H 0021 #define STM32H7xx_LL_WWDG_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (WWDG1) || defined (WWDG2) 0035 0036 /** @defgroup WWDG_LL WWDG 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /* Private constants ---------------------------------------------------------*/ 0044 /* Private macros ------------------------------------------------------------*/ 0045 /* Exported types ------------------------------------------------------------*/ 0046 /* Exported constants --------------------------------------------------------*/ 0047 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants 0048 * @ingroup RTEMSBSPsARMSTM32H7 0049 * @{ 0050 */ 0051 0052 /** @defgroup WWDG_LL_EC_IT IT Defines 0053 * @ingroup RTEMSBSPsARMSTM32H7 0054 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions 0055 * @{ 0056 */ 0057 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI 0058 /** 0059 * @} 0060 */ 0061 0062 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER 0063 * @ingroup RTEMSBSPsARMSTM32H7 0064 * @{ 0065 */ 0066 #define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ 0067 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ 0068 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ 0069 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ 0070 #define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */ 0071 #define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */ 0072 #define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */ 0073 #define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */ 0074 /** 0075 * @} 0076 */ 0077 0078 /** 0079 * @} 0080 */ 0081 0082 /* Exported macro ------------------------------------------------------------*/ 0083 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros 0084 * @ingroup RTEMSBSPsARMSTM32H7 0085 * @{ 0086 */ 0087 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros 0088 * @ingroup RTEMSBSPsARMSTM32H7 0089 * @{ 0090 */ 0091 /** 0092 * @brief Write a value in WWDG register 0093 * @param __INSTANCE__ WWDG Instance 0094 * @param __REG__ Register to be written 0095 * @param __VALUE__ Value to be written in the register 0096 * @retval None 0097 */ 0098 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0099 0100 /** 0101 * @brief Read a value in WWDG register 0102 * @param __INSTANCE__ WWDG Instance 0103 * @param __REG__ Register to be read 0104 * @retval Register value 0105 */ 0106 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0107 /** 0108 * @} 0109 */ 0110 0111 /** 0112 * @} 0113 */ 0114 0115 /* Exported functions --------------------------------------------------------*/ 0116 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions 0117 * @ingroup RTEMSBSPsARMSTM32H7 0118 * @{ 0119 */ 0120 0121 /** @defgroup WWDG_LL_EF_Configuration Configuration 0122 * @ingroup RTEMSBSPsARMSTM32H7 0123 * @{ 0124 */ 0125 /** 0126 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. 0127 * @note It is enabled by setting the WDGA bit in the WWDG_CR register, 0128 * then it cannot be disabled again except by a reset. 0129 * This bit is set by software and only cleared by hardware after a reset. 0130 * When WDGA = 1, the watchdog can generate a reset. 0131 * @rmtoll CR WDGA LL_WWDG_Enable 0132 * @param WWDGx WWDG Instance 0133 * @retval None 0134 */ 0135 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) 0136 { 0137 SET_BIT(WWDGx->CR, WWDG_CR_WDGA); 0138 } 0139 0140 /** 0141 * @brief Checks if Window Watchdog is enabled 0142 * @rmtoll CR WDGA LL_WWDG_IsEnabled 0143 * @param WWDGx WWDG Instance 0144 * @retval State of bit (1 or 0). 0145 */ 0146 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) 0147 { 0148 return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); 0149 } 0150 0151 /** 0152 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) 0153 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset 0154 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles 0155 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) 0156 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) 0157 * @rmtoll CR T LL_WWDG_SetCounter 0158 * @param WWDGx WWDG Instance 0159 * @param Counter 0..0x7F (7 bit counter value) 0160 * @retval None 0161 */ 0162 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) 0163 { 0164 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); 0165 } 0166 0167 /** 0168 * @brief Return current Watchdog Counter Value (7 bits counter value) 0169 * @rmtoll CR T LL_WWDG_GetCounter 0170 * @param WWDGx WWDG Instance 0171 * @retval 7 bit Watchdog Counter value 0172 */ 0173 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) 0174 { 0175 return (READ_BIT(WWDGx->CR, WWDG_CR_T)); 0176 } 0177 0178 /** 0179 * @brief Set the time base of the prescaler (WDGTB). 0180 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter 0181 * is decremented every (4096 x 2expWDGTB) PCLK cycles 0182 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler 0183 * @param WWDGx WWDG Instance 0184 * @param Prescaler This parameter can be one of the following values: 0185 * @arg @ref LL_WWDG_PRESCALER_1 0186 * @arg @ref LL_WWDG_PRESCALER_2 0187 * @arg @ref LL_WWDG_PRESCALER_4 0188 * @arg @ref LL_WWDG_PRESCALER_8 0189 * @arg @ref LL_WWDG_PRESCALER_16 0190 * @arg @ref LL_WWDG_PRESCALER_32 0191 * @arg @ref LL_WWDG_PRESCALER_64 0192 * @arg @ref LL_WWDG_PRESCALER_128 0193 * @retval None 0194 */ 0195 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) 0196 { 0197 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); 0198 } 0199 0200 /** 0201 * @brief Return current Watchdog Prescaler Value 0202 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler 0203 * @param WWDGx WWDG Instance 0204 * @retval Returned value can be one of the following values: 0205 * @arg @ref LL_WWDG_PRESCALER_1 0206 * @arg @ref LL_WWDG_PRESCALER_2 0207 * @arg @ref LL_WWDG_PRESCALER_4 0208 * @arg @ref LL_WWDG_PRESCALER_8 0209 * @arg @ref LL_WWDG_PRESCALER_16 0210 * @arg @ref LL_WWDG_PRESCALER_32 0211 * @arg @ref LL_WWDG_PRESCALER_64 0212 * @arg @ref LL_WWDG_PRESCALER_128 0213 */ 0214 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) 0215 { 0216 return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); 0217 } 0218 0219 /** 0220 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). 0221 * @note This window value defines when write in the WWDG_CR register 0222 * to program Watchdog counter is allowed. 0223 * Watchdog counter value update must occur only when the counter value 0224 * is lower than the Watchdog window register value. 0225 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value 0226 * (in the control register) is refreshed before the downcounter has reached 0227 * the watchdog window register value. 0228 * Physically is possible to set the Window lower then 0x40 but it is not recommended. 0229 * To generate an immediate reset, it is possible to set the Counter lower than 0x40. 0230 * @rmtoll CFR W LL_WWDG_SetWindow 0231 * @param WWDGx WWDG Instance 0232 * @param Window 0x00..0x7F (7 bit Window value) 0233 * @retval None 0234 */ 0235 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) 0236 { 0237 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); 0238 } 0239 0240 /** 0241 * @brief Return current Watchdog Window Value (7 bits value) 0242 * @rmtoll CFR W LL_WWDG_GetWindow 0243 * @param WWDGx WWDG Instance 0244 * @retval 7 bit Watchdog Window value 0245 */ 0246 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) 0247 { 0248 return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); 0249 } 0250 0251 /** 0252 * @} 0253 */ 0254 0255 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management 0256 * @ingroup RTEMSBSPsARMSTM32H7 0257 * @{ 0258 */ 0259 /** 0260 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. 0261 * @note This bit is set by hardware when the counter has reached the value 0x40. 0262 * It must be cleared by software by writing 0. 0263 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. 0264 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP 0265 * @param WWDGx WWDG Instance 0266 * @retval State of bit (1 or 0). 0267 */ 0268 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) 0269 { 0270 return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); 0271 } 0272 0273 /** 0274 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) 0275 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP 0276 * @param WWDGx WWDG Instance 0277 * @retval None 0278 */ 0279 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) 0280 { 0281 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); 0282 } 0283 0284 /** 0285 * @} 0286 */ 0287 0288 /** @defgroup WWDG_LL_EF_IT_Management IT_Management 0289 * @ingroup RTEMSBSPsARMSTM32H7 0290 * @{ 0291 */ 0292 /** 0293 * @brief Enable the Early Wakeup Interrupt. 0294 * @note When set, an interrupt occurs whenever the counter reaches value 0x40. 0295 * This interrupt is only cleared by hardware after a reset 0296 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP 0297 * @param WWDGx WWDG Instance 0298 * @retval None 0299 */ 0300 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) 0301 { 0302 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); 0303 } 0304 0305 /** 0306 * @brief Check if Early Wakeup Interrupt is enabled 0307 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP 0308 * @param WWDGx WWDG Instance 0309 * @retval State of bit (1 or 0). 0310 */ 0311 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) 0312 { 0313 return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); 0314 } 0315 0316 /** 0317 * @} 0318 */ 0319 0320 /** 0321 * @} 0322 */ 0323 0324 /** 0325 * @} 0326 */ 0327 0328 #endif /* WWDG1 || WWDG2 */ 0329 0330 /** 0331 * @} 0332 */ 0333 0334 #ifdef __cplusplus 0335 } 0336 #endif 0337 0338 #endif /* STM32H7xx_LL_WWDG_H */
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