stm32h7/include/stm32h7xx_ll_utils.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_utils.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of UTILS LL module.
0006   ******************************************************************************
0007   * @attention
0008   * Copyright (c) 2017 STMicroelectronics.
0009   * All rights reserved.
0010   *
0011   * This software is licensed under terms that can be found in the LICENSE file in
0012   * the root directory of this software component.
0013   * If no LICENSE file comes with this software, it is provided AS-IS.
0014   *
0015   ******************************************************************************
0016   @verbatim
0017   ==============================================================================
0018                      ##### How to use this driver #####
0019   ==============================================================================
0020     [..]
0021     The LL UTILS driver contains a set of generic APIs that can be
0022     used by user:
0023       (+) Device electronic signature
0024       (+) Timing functions
0025       (+) PLL configuration functions
0026
0027   @endverbatim
0028   ******************************************************************************
0029   */
0030
0031 /* Define to prevent recursive inclusion -------------------------------------*/
0032 #ifndef STM32H7xx_LL_UTILS_H
0033 #define STM32H7xx_LL_UTILS_H
0034
0035 #ifdef __cplusplus
0036 extern "C" {
0037 #endif
0038
0039 /* Includes ------------------------------------------------------------------*/
0040 #include "stm32h7xx.h"
0041 #include "stm32h7xx_ll_system.h"
0042 #include "stm32h7xx_ll_bus.h"
0043
0044 /** @addtogroup STM32H7xx_LL_Driver
0045   * @{
0046   */
0047
0048 /** @defgroup UTILS_LL UTILS
0049   * @ingroup RTEMSBSPsARMSTM32H7
0050   * @{
0051   */
0052
0053 /* Private types -------------------------------------------------------------*/
0054 /* Private variables ---------------------------------------------------------*/
0055
0056 /* Private constants ---------------------------------------------------------*/
0057 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
0058   * @ingroup RTEMSBSPsARMSTM32H7
0059   * @{
0060   */
0061
0062 /* Max delay can be used in LL_mDelay */
0063 #define LL_MAX_DELAY                  0xFFFFFFFFU
0064
0065 /**
0066  * @brief Unique device ID register base address
0067  */
0068 #define UID_BASE_ADDRESS              UID_BASE
0069
0070 /**
0071  * @brief Flash size data register base address
0072  */
0073 #define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
0074
0075 /**
0076  * @brief Package data register base address
0077  */
0078 #define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
0079
0080 /**
0081   * @}
0082   */
0083
0084 /* Private macros ------------------------------------------------------------*/
0085 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
0086   * @ingroup RTEMSBSPsARMSTM32H7
0087   * @{
0088   */
0089 /**
0090   * @}
0091   */
0092 /* Exported types ------------------------------------------------------------*/
0093 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
0094   * @ingroup RTEMSBSPsARMSTM32H7
0095   * @{
0096   */
0097 /**
0098   * @brief  UTILS PLL structure definition
0099   */
0100 typedef struct
0101 {
0102   uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
0103                         This parameter must be a number between Min_Data = 0 and Max_Data = 63
0104
0105                         This feature can be modified afterwards using unitary function
0106                         @ref LL_RCC_PLL1_SetM(). */
0107
0108   uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
0109                         This parameter must be a number between Min_Data = 4 and Max_Data = 512
0110
0111                         This feature can be modified afterwards using unitary function
0112                         @ref LL_RCC_PLL1_SetN(). */
0113
0114   uint32_t PLLP;   /*!< Division for the main system clock.
0115                         This parameter must be a number between Min_Data = 2 and Max_Data = 128
0116                           odd division factors are not allowed
0117
0118                         This feature can be modified afterwards using unitary function
0119                         @ref LL_RCC_PLL1_SetP(). */
0120
0121   uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.
0122                         This parameter can be a value between 0 and 8191
0123
0124                         This feature can be modified afterwards using unitary function
0125                         @ref LL_RCC_PLL1_SetFRACN(). */
0126
0127   uint32_t VCO_Input;  /*!< PLL clock Input range.
0128                         This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
0129
0130                         This feature can be modified afterwards using unitary function
0131                         @ref LL_RCC_PLL1_SetVCOInputRange(). */
0132
0133   uint32_t VCO_Output;  /*!< PLL clock Output range.
0134                         This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
0135
0136                       This feature can be modified afterwards using unitary function
0137                       @ref LL_RCC_PLL1_SetVCOOutputRange(). */
0138
0139 } LL_UTILS_PLLInitTypeDef;
0140
0141 /**
0142   * @brief  UTILS System, AHB and APB buses clock configuration structure definition
0143   */
0144 typedef struct
0145 {
0146   uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
0147                                      This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
0148
0149                                      This feature can be modified afterwards using unitary function
0150                                      @ref LL_RCC_SetSysPrescaler(). */
0151
0152   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
0153                                        This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
0154
0155                                        This feature can be modified afterwards using unitary function
0156                                        @ref LL_RCC_SetAHBPrescaler(). */
0157
0158   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
0159                                        This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
0160
0161                                        This feature can be modified afterwards using unitary function
0162                                        @ref LL_RCC_SetAPB1Prescaler(). */
0163
0164   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
0165                                        This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
0166
0167                                        This feature can be modified afterwards using unitary function
0168                                        @ref LL_RCC_SetAPB2Prescaler(). */
0169
0170   uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
0171                                        This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
0172
0173                                        This feature can be modified afterwards using unitary function
0174                                        @ref LL_RCC_SetAPB3Prescaler(). */
0175
0176   uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
0177                                        This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
0178
0179                                        This feature can be modified afterwards using unitary function
0180                                        @ref LL_RCC_SetAPB4Prescaler(). */
0181
0182 } LL_UTILS_ClkInitTypeDef;
0183
0184 /**
0185   * @}
0186   */
0187
0188 /* Exported constants --------------------------------------------------------*/
0189 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
0190   * @ingroup RTEMSBSPsARMSTM32H7
0191   * @{
0192   */
0193
0194 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
0195   * @ingroup RTEMSBSPsARMSTM32H7
0196   * @{
0197   */
0198 #define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
0199 #define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
0200 /**
0201   * @}
0202   */
0203
0204 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
0205   * @ingroup RTEMSBSPsARMSTM32H7
0206   * @{
0207   */
0208 #if (STM32H7_DEV_ID == 0x450UL)
0209 #define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */
0210 #define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */
0211 #define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
0212 #define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
0213 #elif (STM32H7_DEV_ID == 0x480UL)
0214 #define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */
0215 #define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */
0216 #define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */
0217 #define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */
0218 #define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */
0219 #define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */
0220 #define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */
0221 #define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */
0222 #define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */
0223 #define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */
0224 #define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */
0225 #define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */
0226 #define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */
0227 #elif (STM32H7_DEV_ID == 0x483UL)
0228 #define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS         LL_SYSCFG_VFQFPN68_INDUS_PACKAGE         /*!< VFQFPN68 Industrial package type */
0229 #define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100       LL_SYSCFG_TFBGA100_LQFP100_PACKAGE       /*!< TFBGA100 or LQFP100 Legacy package type */
0230 #define LL_UTILS_PACKAGETYPE_LQFP100_INDUS          LL_SYSCFG_LQFP100_INDUS_PACKAGE          /*!< LQFP100 Industrial package type  */
0231 #define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS         LL_SYSCFG_TFBGA100_INDUS_PACKAGE         /*!< TFBGA100 Industrial package type */
0232 #define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS         LL_SYSCFG_WLCSP115_INDUS_PACKAGE         /*!< WLCSP115 Industrial package type */
0233 #define LL_UTILS_PACKAGETYPE_LQFP144                LL_SYSCFG_LQFP144_PACKAGE                /*!< LQFP144 Legacy package type      */
0234 #define LL_UTILS_PACKAGETYPE_UFBGA144               LL_SYSCFG_UFBGA144_PACKAGE               /*!< UFBGA144 Legacy package type     */
0235 #define LL_UTILS_PACKAGETYPE_LQFP144_INDUS          LL_SYSCFG_LQFP144_INDUS_PACKAGE          /*!< LQFP144 Industrial package type  */
0236 #define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS         LL_SYSCFG_UFBGA169_INDUS_PACKAGE         /*!< UFBGA169 Industrial package type */
0237 #define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS   LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE   /*!< UFBGA176+25 Industrial package type   */
0238 #define LL_UTILS_PACKAGETYPE_LQFP176_INDUS          LL_SYSCFG_LQFP176_INDUS_PACKAGE          /*!< LQFP176 Industrial package type  */
0239 #endif /* STM32H7_DEV_ID == 0x450UL */
0240 /**
0241   * @}
0242   */
0243
0244 /**
0245   * @}
0246   */
0247
0248 /* Exported macro ------------------------------------------------------------*/
0249
0250 /* Exported functions --------------------------------------------------------*/
0251 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
0252   * @ingroup RTEMSBSPsARMSTM32H7
0253   * @{
0254   */
0255
0256 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
0257   * @ingroup RTEMSBSPsARMSTM32H7
0258   * @{
0259   */
0260
0261 /**
0262   * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
0263   * @retval UID[31:0]
0264   */
0265 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
0266 {
0267   return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
0268 }
0269
0270 /**
0271   * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
0272   * @retval UID[63:32]
0273   */
0274 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
0275 {
0276   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
0277 }
0278
0279 /**
0280   * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
0281   * @retval UID[95:64]
0282   */
0283 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
0284 {
0285   return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
0286 }
0287
0288 /**
0289   * @brief  Get Flash memory size
0290   * @note   This bitfield indicates the size of the device Flash memory expressed in
0291   *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
0292   * @retval FLASH_SIZE[15:0]: Flash memory size
0293   */
0294 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
0295 {
0296   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
0297 }
0298
0299 /**
0300   * @brief  Get Package type
0301   * @retval Returned value can be one of the following values:
0302   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
0303   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
0304   *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
0305   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
0306   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
0307   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)
0308   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)
0309   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)
0310   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)
0311   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)
0312   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
0313   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)
0314   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)
0315   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)
0316   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)
0317   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)
0318   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)
0319   *         @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS   (*)
0320   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS   (*)
0321   *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS   (*)
0322   *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS   (*)
0323   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144   (*)
0324   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS   (*)
0325   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS   (*)
0326   *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS   (*)
0327   *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS   (*)
0328   *
0329   *        (*) Packages available on some STM32H7 lines only.
0330   * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
0331             the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
0332   */
0333 __STATIC_INLINE uint32_t LL_GetPackageType(void)
0334 {
0335 #if defined(SYSCFG_PKGR_PKG)
0336
0337   return LL_SYSCFG_GetPackage();
0338 #else
0339    return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
0340
0341 #endif  /* SYSCFG_PKGR_PKG */
0342 }
0343
0344 /**
0345   * @}
0346   */
0347
0348 /** @defgroup UTILS_LL_EF_DELAY DELAY
0349   * @ingroup RTEMSBSPsARMSTM32H7
0350   * @{
0351   */
0352
0353 /**
0354   * @brief  This function configures the Cortex-M SysTick source of the time base.
0355   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
0356   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
0357   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
0358   * @param  Ticks Frequency of Ticks (Hz)
0359   * @retval None
0360   */
0361 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
0362 {
0363   /* Configure the SysTick to have interrupt in 1ms time base */
0364   SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
0365   SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
0366   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
0367                    SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
0368 }
0369
0370 void        LL_Init1msTick(uint32_t CPU_Frequency);
0371 void        LL_mDelay(uint32_t Delay);
0372
0373 /**
0374   * @}
0375   */
0376
0377 /** @defgroup UTILS_EF_SYSTEM SYSTEM
0378   * @ingroup RTEMSBSPsARMSTM32H7
0379   * @{
0380   */
0381
0382 void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);
0383 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
0384                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
0385 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
0386                                          uint32_t HSEBypass,
0387                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
0388                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
0389 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
0390
0391 /**
0392   * @}
0393   */
0394
0395 /**
0396   * @}
0397   */
0398
0399 /**
0400   * @}
0401   */
0402
0403 /**
0404   * @}
0405   */
0406
0407 #ifdef __cplusplus
0408 }
0409 #endif
0410
0411 #endif /* STM32H7xx_LL_UTILS_H */
0412