LXR |
|
|
|
|||
File indexing completed on 2025-05-11 08:23:38
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_tim.h 0004 * @author MCD Application Team 0005 * @brief Header file of TIM LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef __STM32H7xx_LL_TIM_H 0021 #define __STM32H7xx_LL_TIM_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24) 0035 0036 /** @defgroup TIM_LL TIM 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 0044 * @ingroup RTEMSBSPsARMSTM32H7 0045 * @{ 0046 */ 0047 static const uint8_t OFFSET_TAB_CCMRx[] = 0048 { 0049 0x00U, /* 0: TIMx_CH1 */ 0050 0x00U, /* 1: TIMx_CH1N */ 0051 0x00U, /* 2: TIMx_CH2 */ 0052 0x00U, /* 3: TIMx_CH2N */ 0053 0x04U, /* 4: TIMx_CH3 */ 0054 0x04U, /* 5: TIMx_CH3N */ 0055 0x04U, /* 6: TIMx_CH4 */ 0056 0x3CU, /* 7: TIMx_CH5 */ 0057 0x3CU /* 8: TIMx_CH6 */ 0058 }; 0059 0060 static const uint8_t SHIFT_TAB_OCxx[] = 0061 { 0062 0U, /* 0: OC1M, OC1FE, OC1PE */ 0063 0U, /* 1: - NA */ 0064 8U, /* 2: OC2M, OC2FE, OC2PE */ 0065 0U, /* 3: - NA */ 0066 0U, /* 4: OC3M, OC3FE, OC3PE */ 0067 0U, /* 5: - NA */ 0068 8U, /* 6: OC4M, OC4FE, OC4PE */ 0069 0U, /* 7: OC5M, OC5FE, OC5PE */ 0070 8U /* 8: OC6M, OC6FE, OC6PE */ 0071 }; 0072 0073 static const uint8_t SHIFT_TAB_ICxx[] = 0074 { 0075 0U, /* 0: CC1S, IC1PSC, IC1F */ 0076 0U, /* 1: - NA */ 0077 8U, /* 2: CC2S, IC2PSC, IC2F */ 0078 0U, /* 3: - NA */ 0079 0U, /* 4: CC3S, IC3PSC, IC3F */ 0080 0U, /* 5: - NA */ 0081 8U, /* 6: CC4S, IC4PSC, IC4F */ 0082 0U, /* 7: - NA */ 0083 0U /* 8: - NA */ 0084 }; 0085 0086 static const uint8_t SHIFT_TAB_CCxP[] = 0087 { 0088 0U, /* 0: CC1P */ 0089 2U, /* 1: CC1NP */ 0090 4U, /* 2: CC2P */ 0091 6U, /* 3: CC2NP */ 0092 8U, /* 4: CC3P */ 0093 10U, /* 5: CC3NP */ 0094 12U, /* 6: CC4P */ 0095 16U, /* 7: CC5P */ 0096 20U /* 8: CC6P */ 0097 }; 0098 0099 static const uint8_t SHIFT_TAB_OISx[] = 0100 { 0101 0U, /* 0: OIS1 */ 0102 1U, /* 1: OIS1N */ 0103 2U, /* 2: OIS2 */ 0104 3U, /* 3: OIS2N */ 0105 4U, /* 4: OIS3 */ 0106 5U, /* 5: OIS3N */ 0107 6U, /* 6: OIS4 */ 0108 8U, /* 7: OIS5 */ 0109 10U /* 8: OIS6 */ 0110 }; 0111 /** 0112 * @} 0113 */ 0114 0115 /* Private constants ---------------------------------------------------------*/ 0116 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 0117 * @ingroup RTEMSBSPsARMSTM32H7 0118 * @{ 0119 */ 0120 0121 #if defined(TIM_BREAK_INPUT_SUPPORT) 0122 /* Defines used for the bit position in the register and perform offsets */ 0123 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) 0124 0125 /* Generic bit definitions for TIMx_AF1 register */ 0126 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ 0127 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ 0128 #endif /* TIM_BREAK_INPUT_SUPPORT */ 0129 0130 0131 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 0132 #define DT_DELAY_1 ((uint8_t)0x7F) 0133 #define DT_DELAY_2 ((uint8_t)0x3F) 0134 #define DT_DELAY_3 ((uint8_t)0x1F) 0135 #define DT_DELAY_4 ((uint8_t)0x1F) 0136 0137 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 0138 #define DT_RANGE_1 ((uint8_t)0x00) 0139 #define DT_RANGE_2 ((uint8_t)0x80) 0140 #define DT_RANGE_3 ((uint8_t)0xC0) 0141 #define DT_RANGE_4 ((uint8_t)0xE0) 0142 0143 0144 /** 0145 * @} 0146 */ 0147 0148 /* Private macros ------------------------------------------------------------*/ 0149 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 0150 * @ingroup RTEMSBSPsARMSTM32H7 0151 * @{ 0152 */ 0153 /** @brief Convert channel id into channel index. 0154 * @param __CHANNEL__ This parameter can be one of the following values: 0155 * @arg @ref LL_TIM_CHANNEL_CH1 0156 * @arg @ref LL_TIM_CHANNEL_CH1N 0157 * @arg @ref LL_TIM_CHANNEL_CH2 0158 * @arg @ref LL_TIM_CHANNEL_CH2N 0159 * @arg @ref LL_TIM_CHANNEL_CH3 0160 * @arg @ref LL_TIM_CHANNEL_CH3N 0161 * @arg @ref LL_TIM_CHANNEL_CH4 0162 * @arg @ref LL_TIM_CHANNEL_CH5 0163 * @arg @ref LL_TIM_CHANNEL_CH6 0164 * @retval none 0165 */ 0166 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 0167 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 0168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 0169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 0170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 0171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 0172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 0173 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 0174 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 0175 0176 /** @brief Calculate the deadtime sampling period(in ps). 0177 * @param __TIMCLK__ timer input clock frequency (in Hz). 0178 * @param __CKD__ This parameter can be one of the following values: 0179 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 0180 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 0181 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 0182 * @retval none 0183 */ 0184 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 0185 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 0186 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 0187 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 0188 /** 0189 * @} 0190 */ 0191 0192 0193 /* Exported types ------------------------------------------------------------*/ 0194 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0195 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 0196 * @ingroup RTEMSBSPsARMSTM32H7 0197 * @{ 0198 */ 0199 0200 /** 0201 * @brief TIM Time Base configuration structure definition. 0202 */ 0203 typedef struct 0204 { 0205 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 0206 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 0207 0208 This feature can be modified afterwards using unitary function 0209 @ref LL_TIM_SetPrescaler().*/ 0210 0211 uint32_t CounterMode; /*!< Specifies the counter mode. 0212 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 0213 0214 This feature can be modified afterwards using unitary function 0215 @ref LL_TIM_SetCounterMode().*/ 0216 0217 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 0218 Auto-Reload Register at the next update event. 0219 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 0220 Some timer instances may support 32 bits counters. In that case this parameter must 0221 be a number between 0x0000 and 0xFFFFFFFF. 0222 0223 This feature can be modified afterwards using unitary function 0224 @ref LL_TIM_SetAutoReload().*/ 0225 0226 uint32_t ClockDivision; /*!< Specifies the clock division. 0227 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 0228 0229 This feature can be modified afterwards using unitary function 0230 @ref LL_TIM_SetClockDivision().*/ 0231 0232 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 0233 reaches zero, an update event is generated and counting restarts 0234 from the RCR value (N). 0235 This means in PWM mode that (N+1) corresponds to: 0236 - the number of PWM periods in edge-aligned mode 0237 - the number of half PWM period in center-aligned mode 0238 GP timers: this parameter must be a number between Min_Data = 0x00 and 0239 Max_Data = 0xFF. 0240 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 0241 Max_Data = 0xFFFF. 0242 0243 This feature can be modified afterwards using unitary function 0244 @ref LL_TIM_SetRepetitionCounter().*/ 0245 } LL_TIM_InitTypeDef; 0246 0247 /** 0248 * @brief TIM Output Compare configuration structure definition. 0249 */ 0250 typedef struct 0251 { 0252 uint32_t OCMode; /*!< Specifies the output mode. 0253 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 0254 0255 This feature can be modified afterwards using unitary function 0256 @ref LL_TIM_OC_SetMode().*/ 0257 0258 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 0259 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 0260 0261 This feature can be modified afterwards using unitary functions 0262 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 0263 0264 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 0265 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 0266 0267 This feature can be modified afterwards using unitary functions 0268 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 0269 0270 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 0271 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 0272 0273 This feature can be modified afterwards using unitary function 0274 LL_TIM_OC_SetCompareCHx (x=1..6).*/ 0275 0276 uint32_t OCPolarity; /*!< Specifies the output polarity. 0277 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 0278 0279 This feature can be modified afterwards using unitary function 0280 @ref LL_TIM_OC_SetPolarity().*/ 0281 0282 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 0283 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 0284 0285 This feature can be modified afterwards using unitary function 0286 @ref LL_TIM_OC_SetPolarity().*/ 0287 0288 0289 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 0290 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 0291 0292 This feature can be modified afterwards using unitary function 0293 @ref LL_TIM_OC_SetIdleState().*/ 0294 0295 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 0296 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 0297 0298 This feature can be modified afterwards using unitary function 0299 @ref LL_TIM_OC_SetIdleState().*/ 0300 } LL_TIM_OC_InitTypeDef; 0301 0302 /** 0303 * @brief TIM Input Capture configuration structure definition. 0304 */ 0305 0306 typedef struct 0307 { 0308 0309 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 0310 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 0311 0312 This feature can be modified afterwards using unitary function 0313 @ref LL_TIM_IC_SetPolarity().*/ 0314 0315 uint32_t ICActiveInput; /*!< Specifies the input. 0316 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 0317 0318 This feature can be modified afterwards using unitary function 0319 @ref LL_TIM_IC_SetActiveInput().*/ 0320 0321 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 0322 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 0323 0324 This feature can be modified afterwards using unitary function 0325 @ref LL_TIM_IC_SetPrescaler().*/ 0326 0327 uint32_t ICFilter; /*!< Specifies the input capture filter. 0328 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 0329 0330 This feature can be modified afterwards using unitary function 0331 @ref LL_TIM_IC_SetFilter().*/ 0332 } LL_TIM_IC_InitTypeDef; 0333 0334 0335 /** 0336 * @brief TIM Encoder interface configuration structure definition. 0337 */ 0338 typedef struct 0339 { 0340 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 0341 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 0342 0343 This feature can be modified afterwards using unitary function 0344 @ref LL_TIM_SetEncoderMode().*/ 0345 0346 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 0347 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 0348 0349 This feature can be modified afterwards using unitary function 0350 @ref LL_TIM_IC_SetPolarity().*/ 0351 0352 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 0353 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 0354 0355 This feature can be modified afterwards using unitary function 0356 @ref LL_TIM_IC_SetActiveInput().*/ 0357 0358 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 0359 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 0360 0361 This feature can be modified afterwards using unitary function 0362 @ref LL_TIM_IC_SetPrescaler().*/ 0363 0364 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 0365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 0366 0367 This feature can be modified afterwards using unitary function 0368 @ref LL_TIM_IC_SetFilter().*/ 0369 0370 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 0371 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 0372 0373 This feature can be modified afterwards using unitary function 0374 @ref LL_TIM_IC_SetPolarity().*/ 0375 0376 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 0377 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 0378 0379 This feature can be modified afterwards using unitary function 0380 @ref LL_TIM_IC_SetActiveInput().*/ 0381 0382 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 0383 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 0384 0385 This feature can be modified afterwards using unitary function 0386 @ref LL_TIM_IC_SetPrescaler().*/ 0387 0388 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 0389 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 0390 0391 This feature can be modified afterwards using unitary function 0392 @ref LL_TIM_IC_SetFilter().*/ 0393 0394 } LL_TIM_ENCODER_InitTypeDef; 0395 0396 /** 0397 * @brief TIM Hall sensor interface configuration structure definition. 0398 */ 0399 typedef struct 0400 { 0401 0402 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 0403 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 0404 0405 This feature can be modified afterwards using unitary function 0406 @ref LL_TIM_IC_SetPolarity().*/ 0407 0408 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 0409 Prescaler must be set to get a maximum counter period longer than the 0410 time interval between 2 consecutive changes on the Hall inputs. 0411 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 0412 0413 This feature can be modified afterwards using unitary function 0414 @ref LL_TIM_IC_SetPrescaler().*/ 0415 0416 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 0417 This parameter can be a value of 0418 @ref TIM_LL_EC_IC_FILTER. 0419 0420 This feature can be modified afterwards using unitary function 0421 @ref LL_TIM_IC_SetFilter().*/ 0422 0423 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 0424 A positive pulse (TRGO event) is generated with a programmable delay every time 0425 a change occurs on the Hall inputs. 0426 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 0427 0428 This feature can be modified afterwards using unitary function 0429 @ref LL_TIM_OC_SetCompareCH2().*/ 0430 } LL_TIM_HALLSENSOR_InitTypeDef; 0431 0432 /** 0433 * @brief BDTR (Break and Dead Time) structure definition 0434 */ 0435 typedef struct 0436 { 0437 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 0438 This parameter can be a value of @ref TIM_LL_EC_OSSR 0439 0440 This feature can be modified afterwards using unitary function 0441 @ref LL_TIM_SetOffStates() 0442 0443 @note This bit-field cannot be modified as long as LOCK level 2 has been 0444 programmed. */ 0445 0446 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 0447 This parameter can be a value of @ref TIM_LL_EC_OSSI 0448 0449 This feature can be modified afterwards using unitary function 0450 @ref LL_TIM_SetOffStates() 0451 0452 @note This bit-field cannot be modified as long as LOCK level 2 has been 0453 programmed. */ 0454 0455 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 0456 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 0457 0458 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR 0459 register has been written, their content is frozen until the next reset.*/ 0460 0461 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 0462 switching-on of the outputs. 0463 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0464 0465 This feature can be modified afterwards using unitary function 0466 @ref LL_TIM_OC_SetDeadTime() 0467 0468 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been 0469 programmed. */ 0470 0471 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 0472 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 0473 0474 This feature can be modified afterwards using unitary functions 0475 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 0476 0477 @note This bit-field can not be modified as long as LOCK level 1 has been 0478 programmed. */ 0479 0480 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 0481 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY 0482 0483 This feature can be modified afterwards using unitary function 0484 @ref LL_TIM_ConfigBRK() 0485 0486 @note This bit-field can not be modified as long as LOCK level 1 has been 0487 programmed. */ 0488 0489 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 0490 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 0491 0492 This feature can be modified afterwards using unitary function 0493 @ref LL_TIM_ConfigBRK() 0494 0495 @note This bit-field can not be modified as long as LOCK level 1 has been 0496 programmed. */ 0497 0498 #if defined(TIM_BDTR_BKBID) 0499 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. 0500 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE 0501 0502 This feature can be modified afterwards using unitary functions 0503 @ref LL_TIM_ConfigBRK() 0504 0505 @note Bidirectional break input is only supported by advanced timers instances. 0506 0507 @note This bit-field can not be modified as long as LOCK level 1 has been 0508 programmed. */ 0509 0510 #endif /*TIM_BDTR_BKBID */ 0511 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 0512 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 0513 0514 This feature can be modified afterwards using unitary functions 0515 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 0516 0517 @note This bit-field can not be modified as long as LOCK level 1 has been 0518 programmed. */ 0519 0520 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 0521 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY 0522 0523 This feature can be modified afterwards using unitary function 0524 @ref LL_TIM_ConfigBRK2() 0525 0526 @note This bit-field can not be modified as long as LOCK level 1 has been 0527 programmed. */ 0528 0529 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 0530 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 0531 0532 This feature can be modified afterwards using unitary function 0533 @ref LL_TIM_ConfigBRK2() 0534 0535 @note This bit-field can not be modified as long as LOCK level 1 has been 0536 programmed. */ 0537 0538 #if defined(TIM_BDTR_BKBID) 0539 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. 0540 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE 0541 0542 This feature can be modified afterwards using unitary functions 0543 @ref LL_TIM_ConfigBRK2() 0544 0545 @note Bidirectional break input is only supported by advanced timers instances. 0546 0547 @note This bit-field can not be modified as long as LOCK level 1 has been 0548 programmed. */ 0549 0550 #endif /*TIM_BDTR_BKBID */ 0551 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 0552 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE 0553 0554 This feature can be modified afterwards using unitary functions 0555 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() 0556 0557 @note This bit-field can not be modified as long as LOCK level 1 has been 0558 programmed. */ 0559 } LL_TIM_BDTR_InitTypeDef; 0560 0561 /** 0562 * @} 0563 */ 0564 #endif /* USE_FULL_LL_DRIVER */ 0565 0566 /* Exported constants --------------------------------------------------------*/ 0567 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 0568 * @ingroup RTEMSBSPsARMSTM32H7 0569 * @{ 0570 */ 0571 0572 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 0573 * @ingroup RTEMSBSPsARMSTM32H7 0574 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 0575 * @{ 0576 */ 0577 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 0578 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 0579 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 0580 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 0581 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 0582 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ 0583 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ 0584 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 0585 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 0586 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 0587 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ 0588 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 0589 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 0590 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 0591 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 0592 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ 0593 /** 0594 * @} 0595 */ 0596 0597 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0598 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 0599 * @ingroup RTEMSBSPsARMSTM32H7 0600 * @{ 0601 */ 0602 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 0603 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 0604 /** 0605 * @} 0606 */ 0607 0608 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 0609 * @ingroup RTEMSBSPsARMSTM32H7 0610 * @{ 0611 */ 0612 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 0613 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 0614 /** 0615 * @} 0616 */ 0617 0618 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 0619 * @ingroup RTEMSBSPsARMSTM32H7 0620 * @{ 0621 */ 0622 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 0623 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ 0624 /** 0625 * @} 0626 */ 0627 #endif /* USE_FULL_LL_DRIVER */ 0628 0629 /** @defgroup TIM_LL_EC_IT IT Defines 0630 * @ingroup RTEMSBSPsARMSTM32H7 0631 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 0632 * @{ 0633 */ 0634 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 0635 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 0636 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 0637 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 0638 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 0639 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 0640 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 0641 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 0642 /** 0643 * @} 0644 */ 0645 0646 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 0647 * @ingroup RTEMSBSPsARMSTM32H7 0648 * @{ 0649 */ 0650 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 0651 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 0652 /** 0653 * @} 0654 */ 0655 0656 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 0657 * @ingroup RTEMSBSPsARMSTM32H7 0658 * @{ 0659 */ 0660 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 0661 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 0662 /** 0663 * @} 0664 */ 0665 0666 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 0667 * @ingroup RTEMSBSPsARMSTM32H7 0668 * @{ 0669 */ 0670 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ 0671 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 0672 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 0673 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 0674 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 0675 /** 0676 * @} 0677 */ 0678 0679 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 0680 * @ingroup RTEMSBSPsARMSTM32H7 0681 * @{ 0682 */ 0683 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 0684 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 0685 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 0686 /** 0687 * @} 0688 */ 0689 0690 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 0691 * @ingroup RTEMSBSPsARMSTM32H7 0692 * @{ 0693 */ 0694 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 0695 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 0696 /** 0697 * @} 0698 */ 0699 0700 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 0701 * @ingroup RTEMSBSPsARMSTM32H7 0702 * @{ 0703 */ 0704 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ 0705 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 0706 /** 0707 * @} 0708 */ 0709 0710 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 0711 * @ingroup RTEMSBSPsARMSTM32H7 0712 * @{ 0713 */ 0714 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ 0715 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 0716 /** 0717 * @} 0718 */ 0719 0720 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 0721 * @ingroup RTEMSBSPsARMSTM32H7 0722 * @{ 0723 */ 0724 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ 0725 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 0726 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 0727 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 0728 /** 0729 * @} 0730 */ 0731 0732 /** @defgroup TIM_LL_EC_CHANNEL Channel 0733 * @ingroup RTEMSBSPsARMSTM32H7 0734 * @{ 0735 */ 0736 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 0737 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 0738 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 0739 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 0740 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 0741 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 0742 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 0743 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 0744 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 0745 /** 0746 * @} 0747 */ 0748 0749 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0750 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 0751 * @ingroup RTEMSBSPsARMSTM32H7 0752 * @{ 0753 */ 0754 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 0755 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 0756 /** 0757 * @} 0758 */ 0759 #endif /* USE_FULL_LL_DRIVER */ 0760 0761 /** Legacy definitions for compatibility purpose 0762 @cond 0 0763 */ 0764 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 0765 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 0766 /** 0767 @endcond 0768 */ 0769 0770 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 0771 * @ingroup RTEMSBSPsARMSTM32H7 0772 * @{ 0773 */ 0774 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 0775 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 0776 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 0777 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 0778 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ 0779 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 0780 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 0781 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 0782 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ 0783 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ 0784 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ 0785 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 0786 #define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 0787 #define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ 0788 /** 0789 * @} 0790 */ 0791 0792 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 0793 * @ingroup RTEMSBSPsARMSTM32H7 0794 * @{ 0795 */ 0796 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 0797 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 0798 /** 0799 * @} 0800 */ 0801 0802 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 0803 * @ingroup RTEMSBSPsARMSTM32H7 0804 * @{ 0805 */ 0806 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 0807 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 0808 /** 0809 * @} 0810 */ 0811 0812 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 0813 * @ingroup RTEMSBSPsARMSTM32H7 0814 * @{ 0815 */ 0816 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 0817 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 0818 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 0819 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 0820 /** 0821 * @} 0822 */ 0823 0824 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 0825 * @ingroup RTEMSBSPsARMSTM32H7 0826 * @{ 0827 */ 0828 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 0829 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 0830 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 0831 /** 0832 * @} 0833 */ 0834 0835 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 0836 * @ingroup RTEMSBSPsARMSTM32H7 0837 * @{ 0838 */ 0839 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 0840 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 0841 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 0842 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 0843 /** 0844 * @} 0845 */ 0846 0847 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 0848 * @ingroup RTEMSBSPsARMSTM32H7 0849 * @{ 0850 */ 0851 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 0852 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 0853 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 0854 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 0855 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 0856 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 0857 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 0858 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 0859 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 0860 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 0861 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 0862 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 0863 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 0864 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 0865 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 0866 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 0867 /** 0868 * @} 0869 */ 0870 0871 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 0872 * @ingroup RTEMSBSPsARMSTM32H7 0873 * @{ 0874 */ 0875 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 0876 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 0877 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 0878 /** 0879 * @} 0880 */ 0881 0882 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 0883 * @ingroup RTEMSBSPsARMSTM32H7 0884 * @{ 0885 */ 0886 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ 0887 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ 0888 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 0889 /** 0890 * @} 0891 */ 0892 0893 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 0894 * @ingroup RTEMSBSPsARMSTM32H7 0895 * @{ 0896 */ 0897 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 0898 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 0899 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ 0900 /** 0901 * @} 0902 */ 0903 0904 /** @defgroup TIM_LL_EC_TRGO Trigger Output 0905 * @ingroup RTEMSBSPsARMSTM32H7 0906 * @{ 0907 */ 0908 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ 0909 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 0910 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 0911 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 0912 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 0913 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 0914 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 0915 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 0916 /** 0917 * @} 0918 */ 0919 0920 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 0921 * @ingroup RTEMSBSPsARMSTM32H7 0922 * @{ 0923 */ 0924 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 0925 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 0926 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ 0927 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ 0928 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ 0929 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ 0930 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ 0931 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ 0932 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ 0933 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ 0934 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ 0935 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ 0936 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 0937 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 0938 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 0939 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 0940 /** 0941 * @} 0942 */ 0943 0944 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 0945 * @ingroup RTEMSBSPsARMSTM32H7 0946 * @{ 0947 */ 0948 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ 0949 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 0950 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 0951 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 0952 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ 0953 /** 0954 * @} 0955 */ 0956 0957 /** @defgroup TIM_LL_EC_TS Trigger Selection 0958 * @ingroup RTEMSBSPsARMSTM32H7 0959 * @{ 0960 */ 0961 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 0962 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 0963 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 0964 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 0965 #define LL_TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) is used as trigger input */ 0966 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) is used as trigger input */ 0967 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) is used as trigger input */ 0968 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) is used as trigger input */ 0969 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) is used as trigger input */ 0970 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */ 0971 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */ 0972 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */ 0973 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */ 0974 #define LL_TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) is used as trigger input */ 0975 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 0976 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 0977 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 0978 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ 0979 /** 0980 * @} 0981 */ 0982 0983 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 0984 * @ingroup RTEMSBSPsARMSTM32H7 0985 * @{ 0986 */ 0987 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ 0988 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 0989 /** 0990 * @} 0991 */ 0992 0993 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 0994 * @ingroup RTEMSBSPsARMSTM32H7 0995 * @{ 0996 */ 0997 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ 0998 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 0999 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 1000 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 1001 /** 1002 * @} 1003 */ 1004 1005 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 1006 * @ingroup RTEMSBSPsARMSTM32H7 1007 * @{ 1008 */ 1009 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 1010 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 1011 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 1012 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 1013 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 1014 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 1015 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ 1016 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 1017 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */ 1018 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 1019 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */ 1020 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */ 1021 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */ 1022 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 1023 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 1024 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 1025 /** 1026 * @} 1027 */ 1028 1029 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ 1030 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ 1031 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ 1032 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ 1033 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ 1034 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ 1035 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ 1036 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ 1037 #define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ 1038 1039 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ 1040 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ 1041 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ 1042 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ 1043 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ 1044 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ 1045 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ 1046 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ 1047 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ 1048 1049 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ 1050 #define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ 1051 #define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ 1052 #define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ 1053 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ 1054 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ 1055 1056 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ 1057 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ 1058 1059 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ 1060 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ 1061 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ 1062 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ 1063 #define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ 1064 1065 #define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ 1066 #define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ 1067 #define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ 1068 1069 #define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ 1070 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ 1071 #define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ 1072 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ 1073 #define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ 1074 1075 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 1076 * @ingroup RTEMSBSPsARMSTM32H7 1077 * @{ 1078 */ 1079 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 1080 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 1081 /** 1082 * @} 1083 */ 1084 1085 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter 1086 * @ingroup RTEMSBSPsARMSTM32H7 1087 * @{ 1088 */ 1089 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 1090 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ 1091 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ 1092 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ 1093 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ 1094 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ 1095 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ 1096 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ 1097 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ 1098 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ 1099 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ 1100 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ 1101 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ 1102 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ 1103 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ 1104 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY 1110 * @ingroup RTEMSBSPsARMSTM32H7 1111 * @{ 1112 */ 1113 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 1114 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 1115 /** 1116 * @} 1117 */ 1118 1119 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER 1120 * @ingroup RTEMSBSPsARMSTM32H7 1121 * @{ 1122 */ 1123 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 1124 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ 1125 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ 1126 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ 1127 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ 1128 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ 1129 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ 1130 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ 1131 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ 1132 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ 1133 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ 1134 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ 1135 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ 1136 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ 1137 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ 1138 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ 1139 /** 1140 * @} 1141 */ 1142 1143 /** @defgroup TIM_LL_EC_OSSI OSSI 1144 * @ingroup RTEMSBSPsARMSTM32H7 1145 * @{ 1146 */ 1147 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 1148 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 1149 /** 1150 * @} 1151 */ 1152 1153 /** @defgroup TIM_LL_EC_OSSR OSSR 1154 * @ingroup RTEMSBSPsARMSTM32H7 1155 * @{ 1156 */ 1157 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 1158 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 1159 /** 1160 * @} 1161 */ 1162 1163 #if defined(TIM_BREAK_INPUT_SUPPORT) 1164 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT 1165 * @ingroup RTEMSBSPsARMSTM32H7 1166 * @{ 1167 */ 1168 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ 1169 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ 1170 /** 1171 * @} 1172 */ 1173 1174 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE 1175 * @ingroup RTEMSBSPsARMSTM32H7 1176 * @{ 1177 */ 1178 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */ 1179 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */ 1180 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */ 1181 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ 1182 /** 1183 * @} 1184 */ 1185 1186 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY 1187 * @ingroup RTEMSBSPsARMSTM32H7 1188 * @{ 1189 */ 1190 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */ 1191 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ 1192 /** 1193 * @} 1194 */ 1195 #endif /* TIM_BREAK_INPUT_SUPPORT */ 1196 1197 #if defined(TIM_BDTR_BKBID) 1198 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE 1199 * @ingroup RTEMSBSPsARMSTM32H7 1200 * @{ 1201 */ 1202 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 1203 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 1204 /** 1205 * @} 1206 */ 1207 1208 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE 1209 * @ingroup RTEMSBSPsARMSTM32H7 1210 * @{ 1211 */ 1212 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 1213 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 1214 /** 1215 * @} 1216 */ 1217 1218 /** Legacy definitions for compatibility purpose 1219 @cond 0 1220 */ 1221 #define LL_TIM_ReArmBRK(_PARAM_) 1222 #define LL_TIM_ReArmBRK2(_PARAM_) 1223 /** 1224 @endcond 1225 */ 1226 1227 #endif /*TIM_BDTR_BKBID */ 1228 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 1229 * @ingroup RTEMSBSPsARMSTM32H7 1230 * @{ 1231 */ 1232 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 1233 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 1234 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 1235 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 1236 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 1237 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 1238 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 1239 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 1240 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 1241 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 1242 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 1243 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 1244 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 1245 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 1246 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 1247 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 1248 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 1249 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 1250 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 1251 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 1252 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 1253 #if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE) 1254 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ 1255 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ 1256 #endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */ 1257 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_TISEL register is the DMA base address for DMA burst */ 1258 /** 1259 * @} 1260 */ 1261 1262 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 1263 * @ingroup RTEMSBSPsARMSTM32H7 1264 * @{ 1265 */ 1266 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ 1267 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 1268 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 1269 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 1270 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 1271 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 1272 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 1273 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 1274 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 1275 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 1276 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 1277 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 1278 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 1279 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 1280 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 1281 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 1282 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 1283 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 1284 /** 1285 * @} 1286 */ 1287 1288 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap 1289 * @ingroup RTEMSBSPsARMSTM32H7 1290 * @{ 1291 */ 1292 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */ 1293 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1 OUT */ 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap 1299 * @ingroup RTEMSBSPsARMSTM32H7 1300 * @{ 1301 */ 1302 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */ 1303 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP2 OUT */ 1304 /** 1305 * @} 1306 */ 1307 1308 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap 1309 * @ingroup RTEMSBSPsARMSTM32H7 1310 * @{ 1311 */ 1312 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */ 1313 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1 OUT */ 1314 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2 OUT */ 1315 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */ 1316 /** 1317 * @} 1318 */ 1319 1320 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap 1321 * @ingroup RTEMSBSPsARMSTM32H7 1322 * @{ 1323 */ 1324 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */ 1325 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1 OUT */ 1326 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2 OUT */ 1327 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */ 1328 /** 1329 * @} 1330 */ 1331 1332 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap 1333 * @ingroup RTEMSBSPsARMSTM32H7 1334 * @{ 1335 */ 1336 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */ 1337 #define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to CAN TMP */ 1338 #define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to CAN RTP */ 1339 /** 1340 * @} 1341 */ 1342 1343 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap 1344 * @ingroup RTEMSBSPsARMSTM32H7 1345 * @{ 1346 */ 1347 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /*!< TIM12 input 1 is connected to GPIO */ 1348 #define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 input 1 is connected to SPDIF FS */ 1349 /** 1350 * @} 1351 */ 1352 1353 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap 1354 * @ingroup RTEMSBSPsARMSTM32H7 1355 * @{ 1356 */ 1357 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ 1358 #define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 CH1 */ 1359 #define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 CH1 */ 1360 #define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */ 1361 #define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15 input 1 is connected to RCC LSE */ 1362 #define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI */ 1363 #define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */ 1364 /** 1365 * @} 1366 */ 1367 1368 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap 1369 * @ingroup RTEMSBSPsARMSTM32H7 1370 * @{ 1371 */ 1372 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ 1373 #define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to TIM2 CH2 */ 1374 #define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM3 CH2 */ 1375 #define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */ 1376 /** 1377 * @} 1378 */ 1379 1380 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap 1381 * @ingroup RTEMSBSPsARMSTM32H7 1382 * @{ 1383 */ 1384 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ 1385 #define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to RCC LSI */ 1386 #define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to RCC LSE */ 1387 #define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */ 1388 /** 1389 * @} 1390 */ 1391 1392 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap 1393 * @ingroup RTEMSBSPsARMSTM32H7 1394 * @{ 1395 */ 1396 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ 1397 #define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to SPDIF FS */ 1398 #define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */ 1399 #define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */ 1400 /** 1401 * @} 1402 */ 1403 1404 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap 1405 * @ingroup RTEMSBSPsARMSTM32H7 1406 * @{ 1407 */ 1408 #define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /*!< TIM23 input 4 is connected to GPIO */ 1409 #define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23 input 4 is connected to COMP1 OUT */ 1410 #define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23 input 4 is connected to COMP2 OUT */ 1411 #define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */ 1412 /** 1413 * @} 1414 */ 1415 1416 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap 1417 * @ingroup RTEMSBSPsARMSTM32H7 1418 * @{ 1419 */ 1420 #define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /*!< TIM24 input 1 is connected to GPIO */ 1421 #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */ 1422 #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */ 1423 #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */ 1424 /** 1425 * @} 1426 */ 1427 1428 #if defined(TIM_BREAK_INPUT_SUPPORT) 1429 /** Legacy definitions for compatibility purpose 1430 @cond 0 1431 */ 1432 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK 1433 /** 1434 @endcond 1435 */ 1436 #endif /* TIM_BREAK_INPUT_SUPPORT */ 1437 1438 /** 1439 * @} 1440 */ 1441 1442 /* Exported macro ------------------------------------------------------------*/ 1443 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 1444 * @ingroup RTEMSBSPsARMSTM32H7 1445 * @{ 1446 */ 1447 1448 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 1449 * @ingroup RTEMSBSPsARMSTM32H7 1450 * @{ 1451 */ 1452 /** 1453 * @brief Write a value in TIM register. 1454 * @param __INSTANCE__ TIM Instance 1455 * @param __REG__ Register to be written 1456 * @param __VALUE__ Value to be written in the register 1457 * @retval None 1458 */ 1459 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 1460 1461 /** 1462 * @brief Read a value in TIM register. 1463 * @param __INSTANCE__ TIM Instance 1464 * @param __REG__ Register to be read 1465 * @retval Register value 1466 */ 1467 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 1468 /** 1469 * @} 1470 */ 1471 1472 /** 1473 * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 1474 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 1475 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 1476 * to TIMx_CNT register bit 31) 1477 * @param __CNT__ Counter value 1478 * @retval UIF status bit 1479 */ 1480 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 1481 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 1482 1483 /** 1484 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 1485 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 1486 * @param __TIMCLK__ timer input clock frequency (in Hz) 1487 * @param __CKD__ This parameter can be one of the following values: 1488 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1489 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1490 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1491 * @param __DT__ deadtime duration (in ns) 1492 * @retval DTG[0:7] 1493 */ 1494 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 1495 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 1496 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 1497 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 1498 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 1499 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ 1500 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 1501 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 1502 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ 1503 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ 1504 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ 1505 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 1506 0U) 1507 1508 /** 1509 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 1510 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 1511 * @param __TIMCLK__ timer input clock frequency (in Hz) 1512 * @param __CNTCLK__ counter clock frequency (in Hz) 1513 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 1514 */ 1515 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 1516 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) 1517 1518 /** 1519 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 1520 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 1521 * @param __TIMCLK__ timer input clock frequency (in Hz) 1522 * @param __PSC__ prescaler 1523 * @param __FREQ__ output signal frequency (in Hz) 1524 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1525 */ 1526 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 1527 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) 1528 1529 /** 1530 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare 1531 * active/inactive delay. 1532 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 1533 * @param __TIMCLK__ timer input clock frequency (in Hz) 1534 * @param __PSC__ prescaler 1535 * @param __DELAY__ timer output compare active/inactive delay (in us) 1536 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 1537 */ 1538 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 1539 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 1540 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 1541 1542 /** 1543 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration 1544 * (when the timer operates in one pulse mode). 1545 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 1546 * @param __TIMCLK__ timer input clock frequency (in Hz) 1547 * @param __PSC__ prescaler 1548 * @param __DELAY__ timer output compare active/inactive delay (in us) 1549 * @param __PULSE__ pulse duration (in us) 1550 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 1551 */ 1552 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 1553 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 1554 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 1555 1556 /** 1557 * @brief HELPER macro retrieving the ratio of the input capture prescaler 1558 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 1559 * @param __ICPSC__ This parameter can be one of the following values: 1560 * @arg @ref LL_TIM_ICPSC_DIV1 1561 * @arg @ref LL_TIM_ICPSC_DIV2 1562 * @arg @ref LL_TIM_ICPSC_DIV4 1563 * @arg @ref LL_TIM_ICPSC_DIV8 1564 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 1565 */ 1566 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 1567 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 1568 1569 1570 /** 1571 * @} 1572 */ 1573 1574 /* Exported functions --------------------------------------------------------*/ 1575 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 1576 * @ingroup RTEMSBSPsARMSTM32H7 1577 * @{ 1578 */ 1579 1580 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 1581 * @ingroup RTEMSBSPsARMSTM32H7 1582 * @{ 1583 */ 1584 /** 1585 * @brief Enable timer counter. 1586 * @rmtoll CR1 CEN LL_TIM_EnableCounter 1587 * @param TIMx Timer instance 1588 * @retval None 1589 */ 1590 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 1591 { 1592 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 1593 } 1594 1595 /** 1596 * @brief Disable timer counter. 1597 * @rmtoll CR1 CEN LL_TIM_DisableCounter 1598 * @param TIMx Timer instance 1599 * @retval None 1600 */ 1601 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 1602 { 1603 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 1604 } 1605 1606 /** 1607 * @brief Indicates whether the timer counter is enabled. 1608 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 1609 * @param TIMx Timer instance 1610 * @retval State of bit (1 or 0). 1611 */ 1612 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) 1613 { 1614 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 1615 } 1616 1617 /** 1618 * @brief Enable update event generation. 1619 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 1620 * @param TIMx Timer instance 1621 * @retval None 1622 */ 1623 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 1624 { 1625 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 1626 } 1627 1628 /** 1629 * @brief Disable update event generation. 1630 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 1631 * @param TIMx Timer instance 1632 * @retval None 1633 */ 1634 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 1635 { 1636 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 1637 } 1638 1639 /** 1640 * @brief Indicates whether update event generation is enabled. 1641 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 1642 * @param TIMx Timer instance 1643 * @retval Inverted state of bit (0 or 1). 1644 */ 1645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) 1646 { 1647 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 1648 } 1649 1650 /** 1651 * @brief Set update event source 1652 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 1653 * generate an update interrupt or DMA request if enabled: 1654 * - Counter overflow/underflow 1655 * - Setting the UG bit 1656 * - Update generation through the slave mode controller 1657 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 1658 * overflow/underflow generates an update interrupt or DMA request if enabled. 1659 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 1660 * @param TIMx Timer instance 1661 * @param UpdateSource This parameter can be one of the following values: 1662 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1663 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1664 * @retval None 1665 */ 1666 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 1667 { 1668 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 1669 } 1670 1671 /** 1672 * @brief Get actual event update source 1673 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 1674 * @param TIMx Timer instance 1675 * @retval Returned value can be one of the following values: 1676 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 1677 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 1678 */ 1679 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) 1680 { 1681 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 1682 } 1683 1684 /** 1685 * @brief Set one pulse mode (one shot v.s. repetitive). 1686 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 1687 * @param TIMx Timer instance 1688 * @param OnePulseMode This parameter can be one of the following values: 1689 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1690 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1691 * @retval None 1692 */ 1693 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 1694 { 1695 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 1696 } 1697 1698 /** 1699 * @brief Get actual one pulse mode. 1700 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 1701 * @param TIMx Timer instance 1702 * @retval Returned value can be one of the following values: 1703 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 1704 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 1705 */ 1706 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) 1707 { 1708 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 1709 } 1710 1711 /** 1712 * @brief Set the timer counter counting mode. 1713 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1714 * check whether or not the counter mode selection feature is supported 1715 * by a timer instance. 1716 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 1717 * requires a timer reset to avoid unexpected direction 1718 * due to DIR bit readonly in center aligned mode. 1719 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 1720 * CR1 CMS LL_TIM_SetCounterMode 1721 * @param TIMx Timer instance 1722 * @param CounterMode This parameter can be one of the following values: 1723 * @arg @ref LL_TIM_COUNTERMODE_UP 1724 * @arg @ref LL_TIM_COUNTERMODE_DOWN 1725 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1726 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1727 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1728 * @retval None 1729 */ 1730 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 1731 { 1732 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 1733 } 1734 1735 /** 1736 * @brief Get actual counter mode. 1737 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 1738 * check whether or not the counter mode selection feature is supported 1739 * by a timer instance. 1740 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 1741 * CR1 CMS LL_TIM_GetCounterMode 1742 * @param TIMx Timer instance 1743 * @retval Returned value can be one of the following values: 1744 * @arg @ref LL_TIM_COUNTERMODE_UP 1745 * @arg @ref LL_TIM_COUNTERMODE_DOWN 1746 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 1747 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 1748 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 1749 */ 1750 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) 1751 { 1752 uint32_t counter_mode; 1753 1754 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); 1755 1756 if (counter_mode == 0U) 1757 { 1758 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1759 } 1760 1761 return counter_mode; 1762 } 1763 1764 /** 1765 * @brief Enable auto-reload (ARR) preload. 1766 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 1767 * @param TIMx Timer instance 1768 * @retval None 1769 */ 1770 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 1771 { 1772 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 1773 } 1774 1775 /** 1776 * @brief Disable auto-reload (ARR) preload. 1777 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 1778 * @param TIMx Timer instance 1779 * @retval None 1780 */ 1781 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 1782 { 1783 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 1784 } 1785 1786 /** 1787 * @brief Indicates whether auto-reload (ARR) preload is enabled. 1788 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 1789 * @param TIMx Timer instance 1790 * @retval State of bit (1 or 0). 1791 */ 1792 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) 1793 { 1794 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 1795 } 1796 1797 /** 1798 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators 1799 * (when supported) and the digital filters. 1800 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1801 * whether or not the clock division feature is supported by the timer 1802 * instance. 1803 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 1804 * @param TIMx Timer instance 1805 * @param ClockDivision This parameter can be one of the following values: 1806 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1807 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1808 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1809 * @retval None 1810 */ 1811 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 1812 { 1813 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 1814 } 1815 1816 /** 1817 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time 1818 * generators (when supported) and the digital filters. 1819 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 1820 * whether or not the clock division feature is supported by the timer 1821 * instance. 1822 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 1823 * @param TIMx Timer instance 1824 * @retval Returned value can be one of the following values: 1825 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 1826 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 1827 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 1828 */ 1829 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) 1830 { 1831 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 1832 } 1833 1834 /** 1835 * @brief Set the counter value. 1836 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1837 * whether or not a timer instance supports a 32 bits counter. 1838 * @rmtoll CNT CNT LL_TIM_SetCounter 1839 * @param TIMx Timer instance 1840 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1841 * @retval None 1842 */ 1843 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 1844 { 1845 WRITE_REG(TIMx->CNT, Counter); 1846 } 1847 1848 /** 1849 * @brief Get the counter value. 1850 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1851 * whether or not a timer instance supports a 32 bits counter. 1852 * @rmtoll CNT CNT LL_TIM_GetCounter 1853 * @param TIMx Timer instance 1854 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 1855 */ 1856 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) 1857 { 1858 return (uint32_t)(READ_REG(TIMx->CNT)); 1859 } 1860 1861 /** 1862 * @brief Get the current direction of the counter 1863 * @rmtoll CR1 DIR LL_TIM_GetDirection 1864 * @param TIMx Timer instance 1865 * @retval Returned value can be one of the following values: 1866 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 1867 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 1868 */ 1869 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) 1870 { 1871 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 1872 } 1873 1874 /** 1875 * @brief Set the prescaler value. 1876 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 1877 * @note The prescaler can be changed on the fly as this control register is buffered. The new 1878 * prescaler ratio is taken into account at the next update event. 1879 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 1880 * @rmtoll PSC PSC LL_TIM_SetPrescaler 1881 * @param TIMx Timer instance 1882 * @param Prescaler between Min_Data=0 and Max_Data=65535 1883 * @retval None 1884 */ 1885 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 1886 { 1887 WRITE_REG(TIMx->PSC, Prescaler); 1888 } 1889 1890 /** 1891 * @brief Get the prescaler value. 1892 * @rmtoll PSC PSC LL_TIM_GetPrescaler 1893 * @param TIMx Timer instance 1894 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 1895 */ 1896 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) 1897 { 1898 return (uint32_t)(READ_REG(TIMx->PSC)); 1899 } 1900 1901 /** 1902 * @brief Set the auto-reload value. 1903 * @note The counter is blocked while the auto-reload value is null. 1904 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1905 * whether or not a timer instance supports a 32 bits counter. 1906 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 1907 * @rmtoll ARR ARR LL_TIM_SetAutoReload 1908 * @param TIMx Timer instance 1909 * @param AutoReload between Min_Data=0 and Max_Data=65535 1910 * @retval None 1911 */ 1912 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 1913 { 1914 WRITE_REG(TIMx->ARR, AutoReload); 1915 } 1916 1917 /** 1918 * @brief Get the auto-reload value. 1919 * @rmtoll ARR ARR LL_TIM_GetAutoReload 1920 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 1921 * whether or not a timer instance supports a 32 bits counter. 1922 * @param TIMx Timer instance 1923 * @retval Auto-reload value 1924 */ 1925 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) 1926 { 1927 return (uint32_t)(READ_REG(TIMx->ARR)); 1928 } 1929 1930 /** 1931 * @brief Set the repetition counter value. 1932 * @note For advanced timer instances RepetitionCounter can be up to 65535. 1933 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1934 * whether or not a timer instance supports a repetition counter. 1935 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 1936 * @param TIMx Timer instance 1937 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. 1938 * @retval None 1939 */ 1940 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 1941 { 1942 WRITE_REG(TIMx->RCR, RepetitionCounter); 1943 } 1944 1945 /** 1946 * @brief Get the repetition counter value. 1947 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 1948 * whether or not a timer instance supports a repetition counter. 1949 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 1950 * @param TIMx Timer instance 1951 * @retval Repetition counter value 1952 */ 1953 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) 1954 { 1955 return (uint32_t)(READ_REG(TIMx->RCR)); 1956 } 1957 1958 /** 1959 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1960 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1961 * in an atomic way. 1962 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 1963 * @param TIMx Timer instance 1964 * @retval None 1965 */ 1966 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 1967 { 1968 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1969 } 1970 1971 /** 1972 * @brief Disable update interrupt flag (UIF) remapping. 1973 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 1974 * @param TIMx Timer instance 1975 * @retval None 1976 */ 1977 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 1978 { 1979 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 1980 } 1981 1982 /** 1983 * @brief Indicate whether update interrupt flag (UIF) copy is set. 1984 * @param Counter Counter value 1985 * @retval State of bit (1 or 0). 1986 */ 1987 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) 1988 { 1989 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); 1990 } 1991 1992 /** 1993 * @} 1994 */ 1995 1996 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 1997 * @ingroup RTEMSBSPsARMSTM32H7 1998 * @{ 1999 */ 2000 /** 2001 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 2002 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 2003 * they are updated only when a commutation event (COM) occurs. 2004 * @note Only on channels that have a complementary output. 2005 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 2006 * whether or not a timer instance is able to generate a commutation event. 2007 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 2008 * @param TIMx Timer instance 2009 * @retval None 2010 */ 2011 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 2012 { 2013 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 2014 } 2015 2016 /** 2017 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 2018 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 2019 * whether or not a timer instance is able to generate a commutation event. 2020 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 2021 * @param TIMx Timer instance 2022 * @retval None 2023 */ 2024 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 2025 { 2026 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 2027 } 2028 2029 /** 2030 * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. 2031 * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload 2032 * @param TIMx Timer instance 2033 * @retval State of bit (1 or 0). 2034 */ 2035 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) 2036 { 2037 return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); 2038 } 2039 2040 /** 2041 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 2042 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 2043 * whether or not a timer instance is able to generate a commutation event. 2044 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 2045 * @param TIMx Timer instance 2046 * @param CCUpdateSource This parameter can be one of the following values: 2047 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 2048 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 2049 * @retval None 2050 */ 2051 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 2052 { 2053 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 2054 } 2055 2056 /** 2057 * @brief Set the trigger of the capture/compare DMA request. 2058 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 2059 * @param TIMx Timer instance 2060 * @param DMAReqTrigger This parameter can be one of the following values: 2061 * @arg @ref LL_TIM_CCDMAREQUEST_CC 2062 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 2063 * @retval None 2064 */ 2065 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 2066 { 2067 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 2068 } 2069 2070 /** 2071 * @brief Get actual trigger of the capture/compare DMA request. 2072 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 2073 * @param TIMx Timer instance 2074 * @retval Returned value can be one of the following values: 2075 * @arg @ref LL_TIM_CCDMAREQUEST_CC 2076 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 2077 */ 2078 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) 2079 { 2080 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 2081 } 2082 2083 /** 2084 * @brief Set the lock level to freeze the 2085 * configuration of several capture/compare parameters. 2086 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2087 * the lock mechanism is supported by a timer instance. 2088 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 2089 * @param TIMx Timer instance 2090 * @param LockLevel This parameter can be one of the following values: 2091 * @arg @ref LL_TIM_LOCKLEVEL_OFF 2092 * @arg @ref LL_TIM_LOCKLEVEL_1 2093 * @arg @ref LL_TIM_LOCKLEVEL_2 2094 * @arg @ref LL_TIM_LOCKLEVEL_3 2095 * @retval None 2096 */ 2097 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 2098 { 2099 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 2100 } 2101 2102 /** 2103 * @brief Enable capture/compare channels. 2104 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 2105 * CCER CC1NE LL_TIM_CC_EnableChannel\n 2106 * CCER CC2E LL_TIM_CC_EnableChannel\n 2107 * CCER CC2NE LL_TIM_CC_EnableChannel\n 2108 * CCER CC3E LL_TIM_CC_EnableChannel\n 2109 * CCER CC3NE LL_TIM_CC_EnableChannel\n 2110 * CCER CC4E LL_TIM_CC_EnableChannel\n 2111 * CCER CC5E LL_TIM_CC_EnableChannel\n 2112 * CCER CC6E LL_TIM_CC_EnableChannel 2113 * @param TIMx Timer instance 2114 * @param Channels This parameter can be a combination of the following values: 2115 * @arg @ref LL_TIM_CHANNEL_CH1 2116 * @arg @ref LL_TIM_CHANNEL_CH1N 2117 * @arg @ref LL_TIM_CHANNEL_CH2 2118 * @arg @ref LL_TIM_CHANNEL_CH2N 2119 * @arg @ref LL_TIM_CHANNEL_CH3 2120 * @arg @ref LL_TIM_CHANNEL_CH3N 2121 * @arg @ref LL_TIM_CHANNEL_CH4 2122 * @arg @ref LL_TIM_CHANNEL_CH5 2123 * @arg @ref LL_TIM_CHANNEL_CH6 2124 * @retval None 2125 */ 2126 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 2127 { 2128 SET_BIT(TIMx->CCER, Channels); 2129 } 2130 2131 /** 2132 * @brief Disable capture/compare channels. 2133 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 2134 * CCER CC1NE LL_TIM_CC_DisableChannel\n 2135 * CCER CC2E LL_TIM_CC_DisableChannel\n 2136 * CCER CC2NE LL_TIM_CC_DisableChannel\n 2137 * CCER CC3E LL_TIM_CC_DisableChannel\n 2138 * CCER CC3NE LL_TIM_CC_DisableChannel\n 2139 * CCER CC4E LL_TIM_CC_DisableChannel\n 2140 * CCER CC5E LL_TIM_CC_DisableChannel\n 2141 * CCER CC6E LL_TIM_CC_DisableChannel 2142 * @param TIMx Timer instance 2143 * @param Channels This parameter can be a combination of the following values: 2144 * @arg @ref LL_TIM_CHANNEL_CH1 2145 * @arg @ref LL_TIM_CHANNEL_CH1N 2146 * @arg @ref LL_TIM_CHANNEL_CH2 2147 * @arg @ref LL_TIM_CHANNEL_CH2N 2148 * @arg @ref LL_TIM_CHANNEL_CH3 2149 * @arg @ref LL_TIM_CHANNEL_CH3N 2150 * @arg @ref LL_TIM_CHANNEL_CH4 2151 * @arg @ref LL_TIM_CHANNEL_CH5 2152 * @arg @ref LL_TIM_CHANNEL_CH6 2153 * @retval None 2154 */ 2155 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 2156 { 2157 CLEAR_BIT(TIMx->CCER, Channels); 2158 } 2159 2160 /** 2161 * @brief Indicate whether channel(s) is(are) enabled. 2162 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 2163 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 2164 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 2165 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 2166 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 2167 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 2168 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 2169 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 2170 * CCER CC6E LL_TIM_CC_IsEnabledChannel 2171 * @param TIMx Timer instance 2172 * @param Channels This parameter can be a combination of the following values: 2173 * @arg @ref LL_TIM_CHANNEL_CH1 2174 * @arg @ref LL_TIM_CHANNEL_CH1N 2175 * @arg @ref LL_TIM_CHANNEL_CH2 2176 * @arg @ref LL_TIM_CHANNEL_CH2N 2177 * @arg @ref LL_TIM_CHANNEL_CH3 2178 * @arg @ref LL_TIM_CHANNEL_CH3N 2179 * @arg @ref LL_TIM_CHANNEL_CH4 2180 * @arg @ref LL_TIM_CHANNEL_CH5 2181 * @arg @ref LL_TIM_CHANNEL_CH6 2182 * @retval State of bit (1 or 0). 2183 */ 2184 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) 2185 { 2186 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 2187 } 2188 2189 /** 2190 * @} 2191 */ 2192 2193 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 2194 * @ingroup RTEMSBSPsARMSTM32H7 2195 * @{ 2196 */ 2197 /** 2198 * @brief Configure an output channel. 2199 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 2200 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 2201 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 2202 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 2203 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 2204 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 2205 * CCER CC1P LL_TIM_OC_ConfigOutput\n 2206 * CCER CC2P LL_TIM_OC_ConfigOutput\n 2207 * CCER CC3P LL_TIM_OC_ConfigOutput\n 2208 * CCER CC4P LL_TIM_OC_ConfigOutput\n 2209 * CCER CC5P LL_TIM_OC_ConfigOutput\n 2210 * CCER CC6P LL_TIM_OC_ConfigOutput\n 2211 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 2212 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 2213 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 2214 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 2215 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 2216 * CR2 OIS6 LL_TIM_OC_ConfigOutput 2217 * @param TIMx Timer instance 2218 * @param Channel This parameter can be one of the following values: 2219 * @arg @ref LL_TIM_CHANNEL_CH1 2220 * @arg @ref LL_TIM_CHANNEL_CH2 2221 * @arg @ref LL_TIM_CHANNEL_CH3 2222 * @arg @ref LL_TIM_CHANNEL_CH4 2223 * @arg @ref LL_TIM_CHANNEL_CH5 2224 * @arg @ref LL_TIM_CHANNEL_CH6 2225 * @param Configuration This parameter must be a combination of all the following values: 2226 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 2227 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 2228 * @retval None 2229 */ 2230 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2231 { 2232 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2233 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2234 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 2235 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 2236 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 2237 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 2238 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 2239 } 2240 2241 /** 2242 * @brief Define the behavior of the output reference signal OCxREF from which 2243 * OCx and OCxN (when relevant) are derived. 2244 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 2245 * CCMR1 OC2M LL_TIM_OC_SetMode\n 2246 * CCMR2 OC3M LL_TIM_OC_SetMode\n 2247 * CCMR2 OC4M LL_TIM_OC_SetMode\n 2248 * CCMR3 OC5M LL_TIM_OC_SetMode\n 2249 * CCMR3 OC6M LL_TIM_OC_SetMode 2250 * @param TIMx Timer instance 2251 * @param Channel This parameter can be one of the following values: 2252 * @arg @ref LL_TIM_CHANNEL_CH1 2253 * @arg @ref LL_TIM_CHANNEL_CH2 2254 * @arg @ref LL_TIM_CHANNEL_CH3 2255 * @arg @ref LL_TIM_CHANNEL_CH4 2256 * @arg @ref LL_TIM_CHANNEL_CH5 2257 * @arg @ref LL_TIM_CHANNEL_CH6 2258 * @param Mode This parameter can be one of the following values: 2259 * @arg @ref LL_TIM_OCMODE_FROZEN 2260 * @arg @ref LL_TIM_OCMODE_ACTIVE 2261 * @arg @ref LL_TIM_OCMODE_INACTIVE 2262 * @arg @ref LL_TIM_OCMODE_TOGGLE 2263 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2264 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2265 * @arg @ref LL_TIM_OCMODE_PWM1 2266 * @arg @ref LL_TIM_OCMODE_PWM2 2267 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2268 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2269 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2270 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2271 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2272 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2273 * @retval None 2274 */ 2275 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 2276 { 2277 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2278 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2279 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 2280 } 2281 2282 /** 2283 * @brief Get the output compare mode of an output channel. 2284 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 2285 * CCMR1 OC2M LL_TIM_OC_GetMode\n 2286 * CCMR2 OC3M LL_TIM_OC_GetMode\n 2287 * CCMR2 OC4M LL_TIM_OC_GetMode\n 2288 * CCMR3 OC5M LL_TIM_OC_GetMode\n 2289 * CCMR3 OC6M LL_TIM_OC_GetMode 2290 * @param TIMx Timer instance 2291 * @param Channel This parameter can be one of the following values: 2292 * @arg @ref LL_TIM_CHANNEL_CH1 2293 * @arg @ref LL_TIM_CHANNEL_CH2 2294 * @arg @ref LL_TIM_CHANNEL_CH3 2295 * @arg @ref LL_TIM_CHANNEL_CH4 2296 * @arg @ref LL_TIM_CHANNEL_CH5 2297 * @arg @ref LL_TIM_CHANNEL_CH6 2298 * @retval Returned value can be one of the following values: 2299 * @arg @ref LL_TIM_OCMODE_FROZEN 2300 * @arg @ref LL_TIM_OCMODE_ACTIVE 2301 * @arg @ref LL_TIM_OCMODE_INACTIVE 2302 * @arg @ref LL_TIM_OCMODE_TOGGLE 2303 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 2304 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 2305 * @arg @ref LL_TIM_OCMODE_PWM1 2306 * @arg @ref LL_TIM_OCMODE_PWM2 2307 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 2308 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 2309 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 2310 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 2311 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 2312 * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 2313 */ 2314 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) 2315 { 2316 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2317 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2318 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 2319 } 2320 2321 /** 2322 * @brief Set the polarity of an output channel. 2323 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 2324 * CCER CC1NP LL_TIM_OC_SetPolarity\n 2325 * CCER CC2P LL_TIM_OC_SetPolarity\n 2326 * CCER CC2NP LL_TIM_OC_SetPolarity\n 2327 * CCER CC3P LL_TIM_OC_SetPolarity\n 2328 * CCER CC3NP LL_TIM_OC_SetPolarity\n 2329 * CCER CC4P LL_TIM_OC_SetPolarity\n 2330 * CCER CC5P LL_TIM_OC_SetPolarity\n 2331 * CCER CC6P LL_TIM_OC_SetPolarity 2332 * @param TIMx Timer instance 2333 * @param Channel This parameter can be one of the following values: 2334 * @arg @ref LL_TIM_CHANNEL_CH1 2335 * @arg @ref LL_TIM_CHANNEL_CH1N 2336 * @arg @ref LL_TIM_CHANNEL_CH2 2337 * @arg @ref LL_TIM_CHANNEL_CH2N 2338 * @arg @ref LL_TIM_CHANNEL_CH3 2339 * @arg @ref LL_TIM_CHANNEL_CH3N 2340 * @arg @ref LL_TIM_CHANNEL_CH4 2341 * @arg @ref LL_TIM_CHANNEL_CH5 2342 * @arg @ref LL_TIM_CHANNEL_CH6 2343 * @param Polarity This parameter can be one of the following values: 2344 * @arg @ref LL_TIM_OCPOLARITY_HIGH 2345 * @arg @ref LL_TIM_OCPOLARITY_LOW 2346 * @retval None 2347 */ 2348 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 2349 { 2350 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2351 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 2352 } 2353 2354 /** 2355 * @brief Get the polarity of an output channel. 2356 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 2357 * CCER CC1NP LL_TIM_OC_GetPolarity\n 2358 * CCER CC2P LL_TIM_OC_GetPolarity\n 2359 * CCER CC2NP LL_TIM_OC_GetPolarity\n 2360 * CCER CC3P LL_TIM_OC_GetPolarity\n 2361 * CCER CC3NP LL_TIM_OC_GetPolarity\n 2362 * CCER CC4P LL_TIM_OC_GetPolarity\n 2363 * CCER CC5P LL_TIM_OC_GetPolarity\n 2364 * CCER CC6P LL_TIM_OC_GetPolarity 2365 * @param TIMx Timer instance 2366 * @param Channel This parameter can be one of the following values: 2367 * @arg @ref LL_TIM_CHANNEL_CH1 2368 * @arg @ref LL_TIM_CHANNEL_CH1N 2369 * @arg @ref LL_TIM_CHANNEL_CH2 2370 * @arg @ref LL_TIM_CHANNEL_CH2N 2371 * @arg @ref LL_TIM_CHANNEL_CH3 2372 * @arg @ref LL_TIM_CHANNEL_CH3N 2373 * @arg @ref LL_TIM_CHANNEL_CH4 2374 * @arg @ref LL_TIM_CHANNEL_CH5 2375 * @arg @ref LL_TIM_CHANNEL_CH6 2376 * @retval Returned value can be one of the following values: 2377 * @arg @ref LL_TIM_OCPOLARITY_HIGH 2378 * @arg @ref LL_TIM_OCPOLARITY_LOW 2379 */ 2380 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 2381 { 2382 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2383 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 2384 } 2385 2386 /** 2387 * @brief Set the IDLE state of an output channel 2388 * @note This function is significant only for the timer instances 2389 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) 2390 * can be used to check whether or not a timer instance provides 2391 * a break input. 2392 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 2393 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2394 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 2395 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 2396 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 2397 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 2398 * CR2 OIS4 LL_TIM_OC_SetIdleState\n 2399 * CR2 OIS5 LL_TIM_OC_SetIdleState\n 2400 * CR2 OIS6 LL_TIM_OC_SetIdleState 2401 * @param TIMx Timer instance 2402 * @param Channel This parameter can be one of the following values: 2403 * @arg @ref LL_TIM_CHANNEL_CH1 2404 * @arg @ref LL_TIM_CHANNEL_CH1N 2405 * @arg @ref LL_TIM_CHANNEL_CH2 2406 * @arg @ref LL_TIM_CHANNEL_CH2N 2407 * @arg @ref LL_TIM_CHANNEL_CH3 2408 * @arg @ref LL_TIM_CHANNEL_CH3N 2409 * @arg @ref LL_TIM_CHANNEL_CH4 2410 * @arg @ref LL_TIM_CHANNEL_CH5 2411 * @arg @ref LL_TIM_CHANNEL_CH6 2412 * @param IdleState This parameter can be one of the following values: 2413 * @arg @ref LL_TIM_OCIDLESTATE_LOW 2414 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2415 * @retval None 2416 */ 2417 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) 2418 { 2419 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2420 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 2421 } 2422 2423 /** 2424 * @brief Get the IDLE state of an output channel 2425 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 2426 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2427 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 2428 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 2429 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 2430 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 2431 * CR2 OIS4 LL_TIM_OC_GetIdleState\n 2432 * CR2 OIS5 LL_TIM_OC_GetIdleState\n 2433 * CR2 OIS6 LL_TIM_OC_GetIdleState 2434 * @param TIMx Timer instance 2435 * @param Channel This parameter can be one of the following values: 2436 * @arg @ref LL_TIM_CHANNEL_CH1 2437 * @arg @ref LL_TIM_CHANNEL_CH1N 2438 * @arg @ref LL_TIM_CHANNEL_CH2 2439 * @arg @ref LL_TIM_CHANNEL_CH2N 2440 * @arg @ref LL_TIM_CHANNEL_CH3 2441 * @arg @ref LL_TIM_CHANNEL_CH3N 2442 * @arg @ref LL_TIM_CHANNEL_CH4 2443 * @arg @ref LL_TIM_CHANNEL_CH5 2444 * @arg @ref LL_TIM_CHANNEL_CH6 2445 * @retval Returned value can be one of the following values: 2446 * @arg @ref LL_TIM_OCIDLESTATE_LOW 2447 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 2448 */ 2449 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) 2450 { 2451 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2452 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 2453 } 2454 2455 /** 2456 * @brief Enable fast mode for the output channel. 2457 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 2458 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 2459 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 2460 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 2461 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 2462 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 2463 * CCMR3 OC6FE LL_TIM_OC_EnableFast 2464 * @param TIMx Timer instance 2465 * @param Channel This parameter can be one of the following values: 2466 * @arg @ref LL_TIM_CHANNEL_CH1 2467 * @arg @ref LL_TIM_CHANNEL_CH2 2468 * @arg @ref LL_TIM_CHANNEL_CH3 2469 * @arg @ref LL_TIM_CHANNEL_CH4 2470 * @arg @ref LL_TIM_CHANNEL_CH5 2471 * @arg @ref LL_TIM_CHANNEL_CH6 2472 * @retval None 2473 */ 2474 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2475 { 2476 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2477 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2478 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2479 2480 } 2481 2482 /** 2483 * @brief Disable fast mode for the output channel. 2484 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 2485 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 2486 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 2487 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 2488 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 2489 * CCMR3 OC6FE LL_TIM_OC_DisableFast 2490 * @param TIMx Timer instance 2491 * @param Channel This parameter can be one of the following values: 2492 * @arg @ref LL_TIM_CHANNEL_CH1 2493 * @arg @ref LL_TIM_CHANNEL_CH2 2494 * @arg @ref LL_TIM_CHANNEL_CH3 2495 * @arg @ref LL_TIM_CHANNEL_CH4 2496 * @arg @ref LL_TIM_CHANNEL_CH5 2497 * @arg @ref LL_TIM_CHANNEL_CH6 2498 * @retval None 2499 */ 2500 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 2501 { 2502 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2503 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2504 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 2505 2506 } 2507 2508 /** 2509 * @brief Indicates whether fast mode is enabled for the output channel. 2510 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 2511 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 2512 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 2513 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 2514 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 2515 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 2516 * @param TIMx Timer instance 2517 * @param Channel This parameter can be one of the following values: 2518 * @arg @ref LL_TIM_CHANNEL_CH1 2519 * @arg @ref LL_TIM_CHANNEL_CH2 2520 * @arg @ref LL_TIM_CHANNEL_CH3 2521 * @arg @ref LL_TIM_CHANNEL_CH4 2522 * @arg @ref LL_TIM_CHANNEL_CH5 2523 * @arg @ref LL_TIM_CHANNEL_CH6 2524 * @retval State of bit (1 or 0). 2525 */ 2526 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) 2527 { 2528 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2529 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2530 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 2531 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2532 } 2533 2534 /** 2535 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 2536 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 2537 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 2538 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 2539 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 2540 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 2541 * CCMR3 OC6PE LL_TIM_OC_EnablePreload 2542 * @param TIMx Timer instance 2543 * @param Channel This parameter can be one of the following values: 2544 * @arg @ref LL_TIM_CHANNEL_CH1 2545 * @arg @ref LL_TIM_CHANNEL_CH2 2546 * @arg @ref LL_TIM_CHANNEL_CH3 2547 * @arg @ref LL_TIM_CHANNEL_CH4 2548 * @arg @ref LL_TIM_CHANNEL_CH5 2549 * @arg @ref LL_TIM_CHANNEL_CH6 2550 * @retval None 2551 */ 2552 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2553 { 2554 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2555 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2556 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2557 } 2558 2559 /** 2560 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 2561 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 2562 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 2563 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 2564 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 2565 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 2566 * CCMR3 OC6PE LL_TIM_OC_DisablePreload 2567 * @param TIMx Timer instance 2568 * @param Channel This parameter can be one of the following values: 2569 * @arg @ref LL_TIM_CHANNEL_CH1 2570 * @arg @ref LL_TIM_CHANNEL_CH2 2571 * @arg @ref LL_TIM_CHANNEL_CH3 2572 * @arg @ref LL_TIM_CHANNEL_CH4 2573 * @arg @ref LL_TIM_CHANNEL_CH5 2574 * @arg @ref LL_TIM_CHANNEL_CH6 2575 * @retval None 2576 */ 2577 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 2578 { 2579 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2580 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2581 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 2582 } 2583 2584 /** 2585 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 2586 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 2587 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 2588 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 2589 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 2590 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 2591 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 2592 * @param TIMx Timer instance 2593 * @param Channel This parameter can be one of the following values: 2594 * @arg @ref LL_TIM_CHANNEL_CH1 2595 * @arg @ref LL_TIM_CHANNEL_CH2 2596 * @arg @ref LL_TIM_CHANNEL_CH3 2597 * @arg @ref LL_TIM_CHANNEL_CH4 2598 * @arg @ref LL_TIM_CHANNEL_CH5 2599 * @arg @ref LL_TIM_CHANNEL_CH6 2600 * @retval State of bit (1 or 0). 2601 */ 2602 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) 2603 { 2604 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2605 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2606 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 2607 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2608 } 2609 2610 /** 2611 * @brief Enable clearing the output channel on an external event. 2612 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 2613 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2614 * or not a timer instance can clear the OCxREF signal on an external event. 2615 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 2616 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 2617 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 2618 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 2619 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 2620 * CCMR3 OC6CE LL_TIM_OC_EnableClear 2621 * @param TIMx Timer instance 2622 * @param Channel This parameter can be one of the following values: 2623 * @arg @ref LL_TIM_CHANNEL_CH1 2624 * @arg @ref LL_TIM_CHANNEL_CH2 2625 * @arg @ref LL_TIM_CHANNEL_CH3 2626 * @arg @ref LL_TIM_CHANNEL_CH4 2627 * @arg @ref LL_TIM_CHANNEL_CH5 2628 * @arg @ref LL_TIM_CHANNEL_CH6 2629 * @retval None 2630 */ 2631 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2632 { 2633 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2634 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2635 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2636 } 2637 2638 /** 2639 * @brief Disable clearing the output channel on an external event. 2640 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2641 * or not a timer instance can clear the OCxREF signal on an external event. 2642 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 2643 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 2644 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 2645 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 2646 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 2647 * CCMR3 OC6CE LL_TIM_OC_DisableClear 2648 * @param TIMx Timer instance 2649 * @param Channel This parameter can be one of the following values: 2650 * @arg @ref LL_TIM_CHANNEL_CH1 2651 * @arg @ref LL_TIM_CHANNEL_CH2 2652 * @arg @ref LL_TIM_CHANNEL_CH3 2653 * @arg @ref LL_TIM_CHANNEL_CH4 2654 * @arg @ref LL_TIM_CHANNEL_CH5 2655 * @arg @ref LL_TIM_CHANNEL_CH6 2656 * @retval None 2657 */ 2658 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 2659 { 2660 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2661 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2662 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 2663 } 2664 2665 /** 2666 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 2667 * @note This function enables clearing the output channel on an external event. 2668 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 2669 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 2670 * or not a timer instance can clear the OCxREF signal on an external event. 2671 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 2672 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 2673 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 2674 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 2675 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 2676 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 2677 * @param TIMx Timer instance 2678 * @param Channel This parameter can be one of the following values: 2679 * @arg @ref LL_TIM_CHANNEL_CH1 2680 * @arg @ref LL_TIM_CHANNEL_CH2 2681 * @arg @ref LL_TIM_CHANNEL_CH3 2682 * @arg @ref LL_TIM_CHANNEL_CH4 2683 * @arg @ref LL_TIM_CHANNEL_CH5 2684 * @arg @ref LL_TIM_CHANNEL_CH6 2685 * @retval State of bit (1 or 0). 2686 */ 2687 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) 2688 { 2689 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2690 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2691 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 2692 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 2693 } 2694 2695 /** 2696 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of 2697 * the Ocx and OCxN signals). 2698 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 2699 * dead-time insertion feature is supported by a timer instance. 2700 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 2701 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 2702 * @param TIMx Timer instance 2703 * @param DeadTime between Min_Data=0 and Max_Data=255 2704 * @retval None 2705 */ 2706 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 2707 { 2708 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 2709 } 2710 2711 /** 2712 * @brief Set compare value for output channel 1 (TIMx_CCR1). 2713 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2714 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2715 * whether or not a timer instance supports a 32 bits counter. 2716 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2717 * output channel 1 is supported by a timer instance. 2718 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 2719 * @param TIMx Timer instance 2720 * @param CompareValue between Min_Data=0 and Max_Data=65535 2721 * @retval None 2722 */ 2723 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 2724 { 2725 WRITE_REG(TIMx->CCR1, CompareValue); 2726 } 2727 2728 /** 2729 * @brief Set compare value for output channel 2 (TIMx_CCR2). 2730 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2731 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2732 * whether or not a timer instance supports a 32 bits counter. 2733 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2734 * output channel 2 is supported by a timer instance. 2735 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 2736 * @param TIMx Timer instance 2737 * @param CompareValue between Min_Data=0 and Max_Data=65535 2738 * @retval None 2739 */ 2740 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 2741 { 2742 WRITE_REG(TIMx->CCR2, CompareValue); 2743 } 2744 2745 /** 2746 * @brief Set compare value for output channel 3 (TIMx_CCR3). 2747 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2748 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2749 * whether or not a timer instance supports a 32 bits counter. 2750 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2751 * output channel is supported by a timer instance. 2752 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 2753 * @param TIMx Timer instance 2754 * @param CompareValue between Min_Data=0 and Max_Data=65535 2755 * @retval None 2756 */ 2757 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 2758 { 2759 WRITE_REG(TIMx->CCR3, CompareValue); 2760 } 2761 2762 /** 2763 * @brief Set compare value for output channel 4 (TIMx_CCR4). 2764 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 2765 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2766 * whether or not a timer instance supports a 32 bits counter. 2767 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2768 * output channel 4 is supported by a timer instance. 2769 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 2770 * @param TIMx Timer instance 2771 * @param CompareValue between Min_Data=0 and Max_Data=65535 2772 * @retval None 2773 */ 2774 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 2775 { 2776 WRITE_REG(TIMx->CCR4, CompareValue); 2777 } 2778 2779 /** 2780 * @brief Set compare value for output channel 5 (TIMx_CCR5). 2781 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2782 * output channel 5 is supported by a timer instance. 2783 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 2784 * @param TIMx Timer instance 2785 * @param CompareValue between Min_Data=0 and Max_Data=65535 2786 * @retval None 2787 */ 2788 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 2789 { 2790 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); 2791 } 2792 2793 /** 2794 * @brief Set compare value for output channel 6 (TIMx_CCR6). 2795 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2796 * output channel 6 is supported by a timer instance. 2797 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 2798 * @param TIMx Timer instance 2799 * @param CompareValue between Min_Data=0 and Max_Data=65535 2800 * @retval None 2801 */ 2802 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 2803 { 2804 WRITE_REG(TIMx->CCR6, CompareValue); 2805 } 2806 2807 /** 2808 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 2809 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 2810 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2811 * whether or not a timer instance supports a 32 bits counter. 2812 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 2813 * output channel 1 is supported by a timer instance. 2814 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 2815 * @param TIMx Timer instance 2816 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2817 */ 2818 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) 2819 { 2820 return (uint32_t)(READ_REG(TIMx->CCR1)); 2821 } 2822 2823 /** 2824 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 2825 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 2826 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2827 * whether or not a timer instance supports a 32 bits counter. 2828 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 2829 * output channel 2 is supported by a timer instance. 2830 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 2831 * @param TIMx Timer instance 2832 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2833 */ 2834 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) 2835 { 2836 return (uint32_t)(READ_REG(TIMx->CCR2)); 2837 } 2838 2839 /** 2840 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 2841 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 2842 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2843 * whether or not a timer instance supports a 32 bits counter. 2844 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 2845 * output channel 3 is supported by a timer instance. 2846 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 2847 * @param TIMx Timer instance 2848 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2849 */ 2850 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) 2851 { 2852 return (uint32_t)(READ_REG(TIMx->CCR3)); 2853 } 2854 2855 /** 2856 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 2857 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 2858 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 2859 * whether or not a timer instance supports a 32 bits counter. 2860 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 2861 * output channel 4 is supported by a timer instance. 2862 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 2863 * @param TIMx Timer instance 2864 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2865 */ 2866 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) 2867 { 2868 return (uint32_t)(READ_REG(TIMx->CCR4)); 2869 } 2870 2871 /** 2872 * @brief Get compare value (TIMx_CCR5) set for output channel 5. 2873 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 2874 * output channel 5 is supported by a timer instance. 2875 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 2876 * @param TIMx Timer instance 2877 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2878 */ 2879 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) 2880 { 2881 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); 2882 } 2883 2884 /** 2885 * @brief Get compare value (TIMx_CCR6) set for output channel 6. 2886 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 2887 * output channel 6 is supported by a timer instance. 2888 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 2889 * @param TIMx Timer instance 2890 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 2891 */ 2892 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) 2893 { 2894 return (uint32_t)(READ_REG(TIMx->CCR6)); 2895 } 2896 2897 /** 2898 * @brief Select on which reference signal the OC5REF is combined to. 2899 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 2900 * whether or not a timer instance supports the combined 3-phase PWM mode. 2901 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 2902 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 2903 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 2904 * @param TIMx Timer instance 2905 * @param GroupCH5 This parameter can be a combination of the following values: 2906 * @arg @ref LL_TIM_GROUPCH5_NONE 2907 * @arg @ref LL_TIM_GROUPCH5_OC1REFC 2908 * @arg @ref LL_TIM_GROUPCH5_OC2REFC 2909 * @arg @ref LL_TIM_GROUPCH5_OC3REFC 2910 * @retval None 2911 */ 2912 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 2913 { 2914 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); 2915 } 2916 2917 /** 2918 * @} 2919 */ 2920 2921 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 2922 * @ingroup RTEMSBSPsARMSTM32H7 2923 * @{ 2924 */ 2925 /** 2926 * @brief Configure input channel. 2927 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 2928 * CCMR1 IC1PSC LL_TIM_IC_Config\n 2929 * CCMR1 IC1F LL_TIM_IC_Config\n 2930 * CCMR1 CC2S LL_TIM_IC_Config\n 2931 * CCMR1 IC2PSC LL_TIM_IC_Config\n 2932 * CCMR1 IC2F LL_TIM_IC_Config\n 2933 * CCMR2 CC3S LL_TIM_IC_Config\n 2934 * CCMR2 IC3PSC LL_TIM_IC_Config\n 2935 * CCMR2 IC3F LL_TIM_IC_Config\n 2936 * CCMR2 CC4S LL_TIM_IC_Config\n 2937 * CCMR2 IC4PSC LL_TIM_IC_Config\n 2938 * CCMR2 IC4F LL_TIM_IC_Config\n 2939 * CCER CC1P LL_TIM_IC_Config\n 2940 * CCER CC1NP LL_TIM_IC_Config\n 2941 * CCER CC2P LL_TIM_IC_Config\n 2942 * CCER CC2NP LL_TIM_IC_Config\n 2943 * CCER CC3P LL_TIM_IC_Config\n 2944 * CCER CC3NP LL_TIM_IC_Config\n 2945 * CCER CC4P LL_TIM_IC_Config\n 2946 * CCER CC4NP LL_TIM_IC_Config 2947 * @param TIMx Timer instance 2948 * @param Channel This parameter can be one of the following values: 2949 * @arg @ref LL_TIM_CHANNEL_CH1 2950 * @arg @ref LL_TIM_CHANNEL_CH2 2951 * @arg @ref LL_TIM_CHANNEL_CH3 2952 * @arg @ref LL_TIM_CHANNEL_CH4 2953 * @param Configuration This parameter must be a combination of all the following values: 2954 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 2955 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 2956 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 2957 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 2958 * @retval None 2959 */ 2960 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 2961 { 2962 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2963 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2964 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), 2965 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ 2966 << SHIFT_TAB_ICxx[iChannel]); 2967 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 2968 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 2969 } 2970 2971 /** 2972 * @brief Set the active input. 2973 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 2974 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 2975 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 2976 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 2977 * @param TIMx Timer instance 2978 * @param Channel This parameter can be one of the following values: 2979 * @arg @ref LL_TIM_CHANNEL_CH1 2980 * @arg @ref LL_TIM_CHANNEL_CH2 2981 * @arg @ref LL_TIM_CHANNEL_CH3 2982 * @arg @ref LL_TIM_CHANNEL_CH4 2983 * @param ICActiveInput This parameter can be one of the following values: 2984 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 2985 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 2986 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 2987 * @retval None 2988 */ 2989 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) 2990 { 2991 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 2992 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 2993 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 2994 } 2995 2996 /** 2997 * @brief Get the current active input. 2998 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 2999 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 3000 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 3001 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 3002 * @param TIMx Timer instance 3003 * @param Channel This parameter can be one of the following values: 3004 * @arg @ref LL_TIM_CHANNEL_CH1 3005 * @arg @ref LL_TIM_CHANNEL_CH2 3006 * @arg @ref LL_TIM_CHANNEL_CH3 3007 * @arg @ref LL_TIM_CHANNEL_CH4 3008 * @retval Returned value can be one of the following values: 3009 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 3010 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 3011 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 3012 */ 3013 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) 3014 { 3015 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3016 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 3017 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 3018 } 3019 3020 /** 3021 * @brief Set the prescaler of input channel. 3022 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 3023 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 3024 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 3025 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 3026 * @param TIMx Timer instance 3027 * @param Channel This parameter can be one of the following values: 3028 * @arg @ref LL_TIM_CHANNEL_CH1 3029 * @arg @ref LL_TIM_CHANNEL_CH2 3030 * @arg @ref LL_TIM_CHANNEL_CH3 3031 * @arg @ref LL_TIM_CHANNEL_CH4 3032 * @param ICPrescaler This parameter can be one of the following values: 3033 * @arg @ref LL_TIM_ICPSC_DIV1 3034 * @arg @ref LL_TIM_ICPSC_DIV2 3035 * @arg @ref LL_TIM_ICPSC_DIV4 3036 * @arg @ref LL_TIM_ICPSC_DIV8 3037 * @retval None 3038 */ 3039 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) 3040 { 3041 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3042 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 3043 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 3044 } 3045 3046 /** 3047 * @brief Get the current prescaler value acting on an input channel. 3048 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 3049 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 3050 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 3051 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 3052 * @param TIMx Timer instance 3053 * @param Channel This parameter can be one of the following values: 3054 * @arg @ref LL_TIM_CHANNEL_CH1 3055 * @arg @ref LL_TIM_CHANNEL_CH2 3056 * @arg @ref LL_TIM_CHANNEL_CH3 3057 * @arg @ref LL_TIM_CHANNEL_CH4 3058 * @retval Returned value can be one of the following values: 3059 * @arg @ref LL_TIM_ICPSC_DIV1 3060 * @arg @ref LL_TIM_ICPSC_DIV2 3061 * @arg @ref LL_TIM_ICPSC_DIV4 3062 * @arg @ref LL_TIM_ICPSC_DIV8 3063 */ 3064 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) 3065 { 3066 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3067 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 3068 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 3069 } 3070 3071 /** 3072 * @brief Set the input filter duration. 3073 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 3074 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 3075 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 3076 * CCMR2 IC4F LL_TIM_IC_SetFilter 3077 * @param TIMx Timer instance 3078 * @param Channel This parameter can be one of the following values: 3079 * @arg @ref LL_TIM_CHANNEL_CH1 3080 * @arg @ref LL_TIM_CHANNEL_CH2 3081 * @arg @ref LL_TIM_CHANNEL_CH3 3082 * @arg @ref LL_TIM_CHANNEL_CH4 3083 * @param ICFilter This parameter can be one of the following values: 3084 * @arg @ref LL_TIM_IC_FILTER_FDIV1 3085 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 3086 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 3087 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 3088 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 3089 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 3090 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 3091 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 3092 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 3093 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 3094 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 3095 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 3096 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 3097 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 3098 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 3099 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 3100 * @retval None 3101 */ 3102 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 3103 { 3104 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3105 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 3106 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 3107 } 3108 3109 /** 3110 * @brief Get the input filter duration. 3111 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 3112 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 3113 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 3114 * CCMR2 IC4F LL_TIM_IC_GetFilter 3115 * @param TIMx Timer instance 3116 * @param Channel This parameter can be one of the following values: 3117 * @arg @ref LL_TIM_CHANNEL_CH1 3118 * @arg @ref LL_TIM_CHANNEL_CH2 3119 * @arg @ref LL_TIM_CHANNEL_CH3 3120 * @arg @ref LL_TIM_CHANNEL_CH4 3121 * @retval Returned value can be one of the following values: 3122 * @arg @ref LL_TIM_IC_FILTER_FDIV1 3123 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 3124 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 3125 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 3126 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 3127 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 3128 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 3129 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 3130 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 3131 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 3132 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 3133 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 3134 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 3135 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 3136 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 3137 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 3138 */ 3139 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) 3140 { 3141 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3142 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 3143 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 3144 } 3145 3146 /** 3147 * @brief Set the input channel polarity. 3148 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 3149 * CCER CC1NP LL_TIM_IC_SetPolarity\n 3150 * CCER CC2P LL_TIM_IC_SetPolarity\n 3151 * CCER CC2NP LL_TIM_IC_SetPolarity\n 3152 * CCER CC3P LL_TIM_IC_SetPolarity\n 3153 * CCER CC3NP LL_TIM_IC_SetPolarity\n 3154 * CCER CC4P LL_TIM_IC_SetPolarity\n 3155 * CCER CC4NP LL_TIM_IC_SetPolarity 3156 * @param TIMx Timer instance 3157 * @param Channel This parameter can be one of the following values: 3158 * @arg @ref LL_TIM_CHANNEL_CH1 3159 * @arg @ref LL_TIM_CHANNEL_CH2 3160 * @arg @ref LL_TIM_CHANNEL_CH3 3161 * @arg @ref LL_TIM_CHANNEL_CH4 3162 * @param ICPolarity This parameter can be one of the following values: 3163 * @arg @ref LL_TIM_IC_POLARITY_RISING 3164 * @arg @ref LL_TIM_IC_POLARITY_FALLING 3165 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 3166 * @retval None 3167 */ 3168 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) 3169 { 3170 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3171 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 3172 ICPolarity << SHIFT_TAB_CCxP[iChannel]); 3173 } 3174 3175 /** 3176 * @brief Get the current input channel polarity. 3177 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 3178 * CCER CC1NP LL_TIM_IC_GetPolarity\n 3179 * CCER CC2P LL_TIM_IC_GetPolarity\n 3180 * CCER CC2NP LL_TIM_IC_GetPolarity\n 3181 * CCER CC3P LL_TIM_IC_GetPolarity\n 3182 * CCER CC3NP LL_TIM_IC_GetPolarity\n 3183 * CCER CC4P LL_TIM_IC_GetPolarity\n 3184 * CCER CC4NP LL_TIM_IC_GetPolarity 3185 * @param TIMx Timer instance 3186 * @param Channel This parameter can be one of the following values: 3187 * @arg @ref LL_TIM_CHANNEL_CH1 3188 * @arg @ref LL_TIM_CHANNEL_CH2 3189 * @arg @ref LL_TIM_CHANNEL_CH3 3190 * @arg @ref LL_TIM_CHANNEL_CH4 3191 * @retval Returned value can be one of the following values: 3192 * @arg @ref LL_TIM_IC_POLARITY_RISING 3193 * @arg @ref LL_TIM_IC_POLARITY_FALLING 3194 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 3195 */ 3196 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) 3197 { 3198 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 3199 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 3200 SHIFT_TAB_CCxP[iChannel]); 3201 } 3202 3203 /** 3204 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 3205 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 3206 * a timer instance provides an XOR input. 3207 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 3208 * @param TIMx Timer instance 3209 * @retval None 3210 */ 3211 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 3212 { 3213 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 3214 } 3215 3216 /** 3217 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 3218 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 3219 * a timer instance provides an XOR input. 3220 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 3221 * @param TIMx Timer instance 3222 * @retval None 3223 */ 3224 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 3225 { 3226 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 3227 } 3228 3229 /** 3230 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 3231 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 3232 * a timer instance provides an XOR input. 3233 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 3234 * @param TIMx Timer instance 3235 * @retval State of bit (1 or 0). 3236 */ 3237 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) 3238 { 3239 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 3240 } 3241 3242 /** 3243 * @brief Get captured value for input channel 1. 3244 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 3245 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3246 * whether or not a timer instance supports a 32 bits counter. 3247 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 3248 * input channel 1 is supported by a timer instance. 3249 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 3250 * @param TIMx Timer instance 3251 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3252 */ 3253 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) 3254 { 3255 return (uint32_t)(READ_REG(TIMx->CCR1)); 3256 } 3257 3258 /** 3259 * @brief Get captured value for input channel 2. 3260 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 3261 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3262 * whether or not a timer instance supports a 32 bits counter. 3263 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 3264 * input channel 2 is supported by a timer instance. 3265 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 3266 * @param TIMx Timer instance 3267 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3268 */ 3269 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) 3270 { 3271 return (uint32_t)(READ_REG(TIMx->CCR2)); 3272 } 3273 3274 /** 3275 * @brief Get captured value for input channel 3. 3276 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 3277 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3278 * whether or not a timer instance supports a 32 bits counter. 3279 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 3280 * input channel 3 is supported by a timer instance. 3281 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 3282 * @param TIMx Timer instance 3283 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3284 */ 3285 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) 3286 { 3287 return (uint32_t)(READ_REG(TIMx->CCR3)); 3288 } 3289 3290 /** 3291 * @brief Get captured value for input channel 4. 3292 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 3293 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 3294 * whether or not a timer instance supports a 32 bits counter. 3295 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 3296 * input channel 4 is supported by a timer instance. 3297 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 3298 * @param TIMx Timer instance 3299 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 3300 */ 3301 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) 3302 { 3303 return (uint32_t)(READ_REG(TIMx->CCR4)); 3304 } 3305 3306 /** 3307 * @} 3308 */ 3309 3310 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 3311 * @ingroup RTEMSBSPsARMSTM32H7 3312 * @{ 3313 */ 3314 /** 3315 * @brief Enable external clock mode 2. 3316 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 3317 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3318 * whether or not a timer instance supports external clock mode2. 3319 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 3320 * @param TIMx Timer instance 3321 * @retval None 3322 */ 3323 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 3324 { 3325 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3326 } 3327 3328 /** 3329 * @brief Disable external clock mode 2. 3330 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3331 * whether or not a timer instance supports external clock mode2. 3332 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 3333 * @param TIMx Timer instance 3334 * @retval None 3335 */ 3336 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 3337 { 3338 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 3339 } 3340 3341 /** 3342 * @brief Indicate whether external clock mode 2 is enabled. 3343 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3344 * whether or not a timer instance supports external clock mode2. 3345 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 3346 * @param TIMx Timer instance 3347 * @retval State of bit (1 or 0). 3348 */ 3349 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) 3350 { 3351 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 3352 } 3353 3354 /** 3355 * @brief Set the clock source of the counter clock. 3356 * @note when selected clock source is external clock mode 1, the timer input 3357 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 3358 * function. This timer input must be configured by calling 3359 * the @ref LL_TIM_IC_Config() function. 3360 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 3361 * whether or not a timer instance supports external clock mode1. 3362 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 3363 * whether or not a timer instance supports external clock mode2. 3364 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 3365 * SMCR ECE LL_TIM_SetClockSource 3366 * @param TIMx Timer instance 3367 * @param ClockSource This parameter can be one of the following values: 3368 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 3369 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 3370 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 3371 * @retval None 3372 */ 3373 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 3374 { 3375 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 3376 } 3377 3378 /** 3379 * @brief Set the encoder interface mode. 3380 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 3381 * whether or not a timer instance supports the encoder mode. 3382 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 3383 * @param TIMx Timer instance 3384 * @param EncoderMode This parameter can be one of the following values: 3385 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 3386 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 3387 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 3388 * @retval None 3389 */ 3390 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 3391 { 3392 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 3393 } 3394 3395 /** 3396 * @} 3397 */ 3398 3399 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 3400 * @ingroup RTEMSBSPsARMSTM32H7 3401 * @{ 3402 */ 3403 /** 3404 * @brief Set the trigger output (TRGO) used for timer synchronization . 3405 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 3406 * whether or not a timer instance can operate as a master timer. 3407 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 3408 * @param TIMx Timer instance 3409 * @param TimerSynchronization This parameter can be one of the following values: 3410 * @arg @ref LL_TIM_TRGO_RESET 3411 * @arg @ref LL_TIM_TRGO_ENABLE 3412 * @arg @ref LL_TIM_TRGO_UPDATE 3413 * @arg @ref LL_TIM_TRGO_CC1IF 3414 * @arg @ref LL_TIM_TRGO_OC1REF 3415 * @arg @ref LL_TIM_TRGO_OC2REF 3416 * @arg @ref LL_TIM_TRGO_OC3REF 3417 * @arg @ref LL_TIM_TRGO_OC4REF 3418 * @retval None 3419 */ 3420 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 3421 { 3422 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 3423 } 3424 3425 /** 3426 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 3427 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 3428 * whether or not a timer instance can be used for ADC synchronization. 3429 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 3430 * @param TIMx Timer Instance 3431 * @param ADCSynchronization This parameter can be one of the following values: 3432 * @arg @ref LL_TIM_TRGO2_RESET 3433 * @arg @ref LL_TIM_TRGO2_ENABLE 3434 * @arg @ref LL_TIM_TRGO2_UPDATE 3435 * @arg @ref LL_TIM_TRGO2_CC1F 3436 * @arg @ref LL_TIM_TRGO2_OC1 3437 * @arg @ref LL_TIM_TRGO2_OC2 3438 * @arg @ref LL_TIM_TRGO2_OC3 3439 * @arg @ref LL_TIM_TRGO2_OC4 3440 * @arg @ref LL_TIM_TRGO2_OC5 3441 * @arg @ref LL_TIM_TRGO2_OC6 3442 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 3443 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 3444 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 3445 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 3446 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 3447 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 3448 * @retval None 3449 */ 3450 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 3451 { 3452 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 3453 } 3454 3455 /** 3456 * @brief Set the synchronization mode of a slave timer. 3457 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3458 * a timer instance can operate as a slave timer. 3459 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 3460 * @param TIMx Timer instance 3461 * @param SlaveMode This parameter can be one of the following values: 3462 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 3463 * @arg @ref LL_TIM_SLAVEMODE_RESET 3464 * @arg @ref LL_TIM_SLAVEMODE_GATED 3465 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 3466 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 3467 * @retval None 3468 */ 3469 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 3470 { 3471 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 3472 } 3473 3474 /** 3475 * @brief Set the selects the trigger input to be used to synchronize the counter. 3476 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3477 * a timer instance can operate as a slave timer. 3478 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 3479 * @param TIMx Timer instance 3480 * @param TriggerInput This parameter can be one of the following values: 3481 * @arg @ref LL_TIM_TS_ITR0 3482 * @arg @ref LL_TIM_TS_ITR1 3483 * @arg @ref LL_TIM_TS_ITR2 3484 * @arg @ref LL_TIM_TS_ITR3 3485 * @arg @ref LL_TIM_TS_ITR4 3486 * @arg @ref LL_TIM_TS_ITR5 3487 * @arg @ref LL_TIM_TS_ITR6 3488 * @arg @ref LL_TIM_TS_ITR7 3489 * @arg @ref LL_TIM_TS_ITR8 (*) 3490 * @arg @ref LL_TIM_TS_ITR9 (*) 3491 * @arg @ref LL_TIM_TS_ITR10 (*) 3492 * @arg @ref LL_TIM_TS_ITR11 (*) 3493 * @arg @ref LL_TIM_TS_ITR12 (*) 3494 * @arg @ref LL_TIM_TS_ITR13 (*) 3495 * @arg @ref LL_TIM_TS_TI1F_ED 3496 * @arg @ref LL_TIM_TS_TI1FP1 3497 * @arg @ref LL_TIM_TS_TI2FP2 3498 * @arg @ref LL_TIM_TS_ETRF 3499 * 3500 * (*) Value not defined in all devices. 3501 * @retval None 3502 */ 3503 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 3504 { 3505 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 3506 } 3507 3508 /** 3509 * @brief Enable the Master/Slave mode. 3510 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3511 * a timer instance can operate as a slave timer. 3512 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 3513 * @param TIMx Timer instance 3514 * @retval None 3515 */ 3516 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 3517 { 3518 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3519 } 3520 3521 /** 3522 * @brief Disable the Master/Slave mode. 3523 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3524 * a timer instance can operate as a slave timer. 3525 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 3526 * @param TIMx Timer instance 3527 * @retval None 3528 */ 3529 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 3530 { 3531 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 3532 } 3533 3534 /** 3535 * @brief Indicates whether the Master/Slave mode is enabled. 3536 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 3537 * a timer instance can operate as a slave timer. 3538 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 3539 * @param TIMx Timer instance 3540 * @retval State of bit (1 or 0). 3541 */ 3542 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) 3543 { 3544 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 3545 } 3546 3547 /** 3548 * @brief Configure the external trigger (ETR) input. 3549 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 3550 * a timer instance provides an external trigger input. 3551 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 3552 * SMCR ETPS LL_TIM_ConfigETR\n 3553 * SMCR ETF LL_TIM_ConfigETR 3554 * @param TIMx Timer instance 3555 * @param ETRPolarity This parameter can be one of the following values: 3556 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 3557 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 3558 * @param ETRPrescaler This parameter can be one of the following values: 3559 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 3560 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 3561 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 3562 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 3563 * @param ETRFilter This parameter can be one of the following values: 3564 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 3565 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 3566 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 3567 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 3568 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 3569 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 3570 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 3571 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 3572 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 3573 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 3574 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 3575 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 3576 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 3577 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 3578 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 3579 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 3580 * @retval None 3581 */ 3582 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, 3583 uint32_t ETRFilter) 3584 { 3585 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 3586 } 3587 3588 /** 3589 * @brief Select the external trigger (ETR) input source. 3590 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or 3591 * not a timer instance supports ETR source selection. 3592 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource 3593 * @param TIMx Timer instance 3594 * @param ETRSource This parameter can be one of the following values: 3595 * For TIM1, the parameter is one of the following values: 3596 * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO 3597 * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output 3598 * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output 3599 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 3600 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 3601 * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 3602 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 3603 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 3604 * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 3605 * 3606 * For TIM2, the parameter is one of the following values: 3607 * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO 3608 * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output 3609 * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output 3610 * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE 3611 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A 3612 * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B 3613 * 3614 * For TIM3, the parameter is one of the following values: 3615 * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO 3616 * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output 3617 * 3618 * For TIM5, the parameter is one of the following values: 3619 * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO 3620 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) 3621 * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) 3622 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) 3623 * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) 3624 * 3625 * For TIM8, the parameter is one of the following values: 3626 * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO 3627 * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output 3628 * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output 3629 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 3630 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 3631 * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 3632 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 3633 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 3634 * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 3635 * 3636 * For TIM23, the parameter is one of the following values: (*) 3637 * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO 3638 * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output 3639 * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output 3640 * 3641 * For TIM24, the parameter is one of the following values: (*) 3642 * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO 3643 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A 3644 * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B 3645 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A 3646 * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B 3647 * 3648 * (*) Value not defined in all devices. 3649 * @retval None 3650 */ 3651 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) 3652 { 3653 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); 3654 } 3655 3656 /** 3657 * @} 3658 */ 3659 3660 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 3661 * @ingroup RTEMSBSPsARMSTM32H7 3662 * @{ 3663 */ 3664 /** 3665 * @brief Enable the break function. 3666 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3667 * a timer instance provides a break input. 3668 * @rmtoll BDTR BKE LL_TIM_EnableBRK 3669 * @param TIMx Timer instance 3670 * @retval None 3671 */ 3672 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 3673 { 3674 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3675 } 3676 3677 /** 3678 * @brief Disable the break function. 3679 * @rmtoll BDTR BKE LL_TIM_DisableBRK 3680 * @param TIMx Timer instance 3681 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3682 * a timer instance provides a break input. 3683 * @retval None 3684 */ 3685 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 3686 { 3687 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 3688 } 3689 3690 #if defined(TIM_BDTR_BKBID) 3691 /** 3692 * @brief Configure the break input. 3693 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3694 * a timer instance provides a break input. 3695 * @note Bidirectional mode is only supported by advanced timer instances. 3696 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not 3697 * a timer instance is an advanced-control timer. 3698 * @note In bidirectional mode (BKBID bit set), the Break input is configured both 3699 * in input mode and in open drain output mode. Any active Break event will 3700 * assert a low logic level on the Break input to indicate an internal break 3701 * event to external devices. 3702 * @note When bidirectional mode isn't supported, BreakAFMode must be set to 3703 * LL_TIM_BREAK_AFMODE_INPUT. 3704 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3705 * BDTR BKF LL_TIM_ConfigBRK\n 3706 * BDTR BKBID LL_TIM_ConfigBRK 3707 * @param TIMx Timer instance 3708 * @param BreakPolarity This parameter can be one of the following values: 3709 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 3710 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3711 * @param BreakFilter This parameter can be one of the following values: 3712 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3713 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3714 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3715 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3716 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3717 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3718 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3719 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3720 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3721 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3722 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 3723 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3724 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3725 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3726 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 3727 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3728 * @param BreakAFMode This parameter can be one of the following values: 3729 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT 3730 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL 3731 * @retval None 3732 */ 3733 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, 3734 uint32_t BreakAFMode) 3735 { 3736 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); 3737 } 3738 3739 #else 3740 /** 3741 * @brief Configure the break input. 3742 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3743 * a timer instance provides a break input. 3744 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 3745 * BDTR BKF LL_TIM_ConfigBRK 3746 * @param TIMx Timer instance 3747 * @param BreakPolarity This parameter can be one of the following values: 3748 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 3749 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 3750 * @param BreakFilter This parameter can be one of the following values: 3751 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 3752 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 3753 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 3754 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 3755 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 3756 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 3757 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 3758 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 3759 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 3760 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 3761 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 3762 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 3763 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 3764 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 3765 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 3766 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 3767 * @retval None 3768 */ 3769 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, 3770 uint32_t BreakFilter) 3771 { 3772 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 3773 } 3774 3775 #endif /* TIM_BDTR_BKBID */ 3776 #if defined(TIM_BDTR_BKBID) 3777 /** 3778 * @brief Disarm the break input (when it operates in bidirectional mode). 3779 * @note The break input can be disarmed only when it is configured in 3780 * bidirectional mode and when when MOE is reset. 3781 * @note Purpose is to be able to have the input voltage back to high-state, 3782 * whatever the time constant on the output . 3783 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK 3784 * @param TIMx Timer instance 3785 * @retval None 3786 */ 3787 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) 3788 { 3789 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); 3790 } 3791 3792 #endif /*TIM_BDTR_BKBID */ 3793 /** 3794 * @brief Enable the break 2 function. 3795 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3796 * a timer instance provides a second break input. 3797 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 3798 * @param TIMx Timer instance 3799 * @retval None 3800 */ 3801 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 3802 { 3803 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3804 } 3805 3806 /** 3807 * @brief Disable the break 2 function. 3808 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3809 * a timer instance provides a second break input. 3810 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 3811 * @param TIMx Timer instance 3812 * @retval None 3813 */ 3814 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 3815 { 3816 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 3817 } 3818 3819 #if defined(TIM_BDTR_BKBID) 3820 /** 3821 * @brief Configure the break 2 input. 3822 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3823 * a timer instance provides a second break input. 3824 * @note Bidirectional mode is only supported by advanced timer instances. 3825 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not 3826 * a timer instance is an advanced-control timer. 3827 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both 3828 * in input mode and in open drain output mode. Any active Break event will 3829 * assert a low logic level on the Break 2 input to indicate an internal break 3830 * event to external devices. 3831 * @note When bidirectional mode isn't supported, Break2AFMode must be set to 3832 * LL_TIM_BREAK2_AFMODE_INPUT. 3833 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 3834 * BDTR BK2F LL_TIM_ConfigBRK2\n 3835 * BDTR BK2BID LL_TIM_ConfigBRK2 3836 * @param TIMx Timer instance 3837 * @param Break2Polarity This parameter can be one of the following values: 3838 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3839 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3840 * @param Break2Filter This parameter can be one of the following values: 3841 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3842 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3843 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3844 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3845 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3846 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3847 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 3848 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3849 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3850 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3851 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 3852 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3853 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3854 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3855 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3856 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3857 * @param Break2AFMode This parameter can be one of the following values: 3858 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT 3859 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL 3860 * @retval None 3861 */ 3862 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, 3863 uint32_t Break2AFMode) 3864 { 3865 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); 3866 } 3867 3868 #else 3869 /** 3870 * @brief Configure the break 2 input. 3871 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 3872 * a timer instance provides a second break input. 3873 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 3874 * BDTR BK2F LL_TIM_ConfigBRK2 3875 * @param TIMx Timer instance 3876 * @param Break2Polarity This parameter can be one of the following values: 3877 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 3878 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 3879 * @param Break2Filter This parameter can be one of the following values: 3880 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 3881 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 3882 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 3883 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 3884 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 3885 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 3886 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 3887 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 3888 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 3889 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 3890 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 3891 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 3892 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 3893 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 3894 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 3895 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 3896 * @retval None 3897 */ 3898 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) 3899 { 3900 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 3901 } 3902 3903 #endif /*TIM_BDTR_BKBID */ 3904 #if defined(TIM_BDTR_BKBID) 3905 /** 3906 * @brief Disarm the break 2 input (when it operates in bidirectional mode). 3907 * @note The break 2 input can be disarmed only when it is configured in 3908 * bidirectional mode and when when MOE is reset. 3909 * @note Purpose is to be able to have the input voltage back to high-state, 3910 * whatever the time constant on the output. 3911 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 3912 * @param TIMx Timer instance 3913 * @retval None 3914 */ 3915 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) 3916 { 3917 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); 3918 } 3919 3920 #endif /*TIM_BDTR_BKBID */ 3921 /** 3922 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 3923 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3924 * a timer instance provides a break input. 3925 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 3926 * BDTR OSSR LL_TIM_SetOffStates 3927 * @param TIMx Timer instance 3928 * @param OffStateIdle This parameter can be one of the following values: 3929 * @arg @ref LL_TIM_OSSI_DISABLE 3930 * @arg @ref LL_TIM_OSSI_ENABLE 3931 * @param OffStateRun This parameter can be one of the following values: 3932 * @arg @ref LL_TIM_OSSR_DISABLE 3933 * @arg @ref LL_TIM_OSSR_ENABLE 3934 * @retval None 3935 */ 3936 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 3937 { 3938 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 3939 } 3940 3941 /** 3942 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 3943 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3944 * a timer instance provides a break input. 3945 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 3946 * @param TIMx Timer instance 3947 * @retval None 3948 */ 3949 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 3950 { 3951 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3952 } 3953 3954 /** 3955 * @brief Disable automatic output (MOE can be set only by software). 3956 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3957 * a timer instance provides a break input. 3958 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 3959 * @param TIMx Timer instance 3960 * @retval None 3961 */ 3962 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 3963 { 3964 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 3965 } 3966 3967 /** 3968 * @brief Indicate whether automatic output is enabled. 3969 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3970 * a timer instance provides a break input. 3971 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 3972 * @param TIMx Timer instance 3973 * @retval State of bit (1 or 0). 3974 */ 3975 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) 3976 { 3977 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 3978 } 3979 3980 /** 3981 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 3982 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3983 * software and is reset in case of break or break2 event 3984 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 3985 * a timer instance provides a break input. 3986 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 3987 * @param TIMx Timer instance 3988 * @retval None 3989 */ 3990 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 3991 { 3992 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 3993 } 3994 3995 /** 3996 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 3997 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 3998 * software and is reset in case of break or break2 event. 3999 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 4000 * a timer instance provides a break input. 4001 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 4002 * @param TIMx Timer instance 4003 * @retval None 4004 */ 4005 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 4006 { 4007 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 4008 } 4009 4010 /** 4011 * @brief Indicates whether outputs are enabled. 4012 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 4013 * a timer instance provides a break input. 4014 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 4015 * @param TIMx Timer instance 4016 * @retval State of bit (1 or 0). 4017 */ 4018 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) 4019 { 4020 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 4021 } 4022 4023 #if defined(TIM_BREAK_INPUT_SUPPORT) 4024 /** 4025 * @brief Enable the signals connected to the designated timer break input. 4026 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 4027 * or not a timer instance allows for break input selection. 4028 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n 4029 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n 4030 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n 4031 * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n 4032 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n 4033 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n 4034 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n 4035 * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource 4036 * @param TIMx Timer instance 4037 * @param BreakInput This parameter can be one of the following values: 4038 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 4039 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 4040 * @param Source This parameter can be one of the following values: 4041 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 4042 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 4043 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 4044 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 4045 * @retval None 4046 */ 4047 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 4048 { 4049 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 4050 SET_BIT(*pReg, Source); 4051 } 4052 4053 /** 4054 * @brief Disable the signals connected to the designated timer break input. 4055 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 4056 * or not a timer instance allows for break input selection. 4057 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n 4058 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n 4059 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n 4060 * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n 4061 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n 4062 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n 4063 * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n 4064 * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource 4065 * @param TIMx Timer instance 4066 * @param BreakInput This parameter can be one of the following values: 4067 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 4068 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 4069 * @param Source This parameter can be one of the following values: 4070 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 4071 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 4072 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 4073 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 4074 * @retval None 4075 */ 4076 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 4077 { 4078 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 4079 CLEAR_BIT(*pReg, Source); 4080 } 4081 4082 /** 4083 * @brief Set the polarity of the break signal for the timer break input. 4084 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 4085 * or not a timer instance allows for break input selection. 4086 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n 4087 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n 4088 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n 4089 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 4090 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n 4091 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity 4092 * @param TIMx Timer instance 4093 * @param BreakInput This parameter can be one of the following values: 4094 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 4095 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 4096 * @param Source This parameter can be one of the following values: 4097 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 4098 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 4099 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 4100 * @param Polarity This parameter can be one of the following values: 4101 * @arg @ref LL_TIM_BKIN_POLARITY_LOW 4102 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 4103 * @retval None 4104 */ 4105 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, 4106 uint32_t Polarity) 4107 { 4108 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); 4109 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); 4110 } 4111 #endif /* TIM_BREAK_INPUT_SUPPORT */ 4112 /** 4113 * @} 4114 */ 4115 4116 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 4117 * @ingroup RTEMSBSPsARMSTM32H7 4118 * @{ 4119 */ 4120 /** 4121 * @brief Configures the timer DMA burst feature. 4122 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 4123 * not a timer instance supports the DMA burst mode. 4124 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 4125 * DCR DBA LL_TIM_ConfigDMABurst 4126 * @param TIMx Timer instance 4127 * @param DMABurstBaseAddress This parameter can be one of the following values: 4128 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 4129 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 4130 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 4131 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 4132 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 4133 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 4134 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 4135 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 4136 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 4137 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 4138 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 4139 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 4140 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 4141 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 4142 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 4143 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 4144 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 4145 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 4146 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 4147 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 4148 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 4149 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 4150 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 4151 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL 4152 * 4153 * @param DMABurstLength This parameter can be one of the following values: 4154 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 4155 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 4156 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 4157 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 4158 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 4159 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 4160 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 4161 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 4162 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 4163 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 4164 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 4165 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 4166 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 4167 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 4168 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 4169 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 4170 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 4171 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 4172 * @retval None 4173 */ 4174 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 4175 { 4176 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 4177 } 4178 4179 /** 4180 * @} 4181 */ 4182 4183 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 4184 * @ingroup RTEMSBSPsARMSTM32H7 4185 * @{ 4186 */ 4187 /** 4188 * @brief Remap TIM inputs (input channel, internal/external triggers). 4189 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 4190 * a some timer inputs can be remapped. 4191 * TIM1: one of the following values: 4192 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO 4193 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output 4194 * 4195 * TIM2: one of the following values: 4196 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO 4197 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output 4198 * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output 4199 * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output 4200 * 4201 * TIM3: one of the following values: 4202 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO 4203 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output 4204 * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output 4205 * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output 4206 * 4207 * TIM5: one of the following values: 4208 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO 4209 * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP 4210 * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP 4211 * 4212 * TIM8: one of the following values: 4213 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO 4214 * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output 4215 * 4216 * TIM12: one of the following values: (*) 4217 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO 4218 * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS 4219 * 4220 * TIM15: one of the following values: 4221 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO 4222 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1 4223 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1 4224 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1 4225 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE 4226 * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI 4227 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2 4228 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO 4229 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2 4230 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2 4231 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2 4232 * 4233 * TIM16: one of the following values: 4234 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO 4235 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI 4236 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE 4237 * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt 4238 * 4239 * TIM17: one of the following values: 4240 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO 4241 * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) 4242 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz 4243 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 4244 * 4245 * TIM23: one of the following values: (*) 4246 * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO 4247 * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output 4248 * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output 4249 * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output 4250 * 4251 * TIM24: one of the following values: (*) 4252 * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO 4253 * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP 4254 * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP 4255 * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC 4256 * 4257 * (*) Value not defined in all devices. \n 4258 * @retval None 4259 */ 4260 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 4261 { 4262 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); 4263 } 4264 4265 /** 4266 * @} 4267 */ 4268 4269 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 4270 * @ingroup RTEMSBSPsARMSTM32H7 4271 * @{ 4272 */ 4273 /** 4274 * @brief Clear the update interrupt flag (UIF). 4275 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 4276 * @param TIMx Timer instance 4277 * @retval None 4278 */ 4279 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 4280 { 4281 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 4282 } 4283 4284 /** 4285 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 4286 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 4287 * @param TIMx Timer instance 4288 * @retval State of bit (1 or 0). 4289 */ 4290 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) 4291 { 4292 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 4293 } 4294 4295 /** 4296 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 4297 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 4298 * @param TIMx Timer instance 4299 * @retval None 4300 */ 4301 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 4302 { 4303 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 4304 } 4305 4306 /** 4307 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 4308 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 4309 * @param TIMx Timer instance 4310 * @retval State of bit (1 or 0). 4311 */ 4312 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) 4313 { 4314 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 4315 } 4316 4317 /** 4318 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 4319 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 4320 * @param TIMx Timer instance 4321 * @retval None 4322 */ 4323 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 4324 { 4325 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 4326 } 4327 4328 /** 4329 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 4330 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 4331 * @param TIMx Timer instance 4332 * @retval State of bit (1 or 0). 4333 */ 4334 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) 4335 { 4336 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 4337 } 4338 4339 /** 4340 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 4341 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 4342 * @param TIMx Timer instance 4343 * @retval None 4344 */ 4345 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 4346 { 4347 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 4348 } 4349 4350 /** 4351 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 4352 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 4353 * @param TIMx Timer instance 4354 * @retval State of bit (1 or 0). 4355 */ 4356 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) 4357 { 4358 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 4359 } 4360 4361 /** 4362 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 4363 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 4364 * @param TIMx Timer instance 4365 * @retval None 4366 */ 4367 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 4368 { 4369 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 4370 } 4371 4372 /** 4373 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 4374 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 4375 * @param TIMx Timer instance 4376 * @retval State of bit (1 or 0). 4377 */ 4378 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) 4379 { 4380 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 4381 } 4382 4383 /** 4384 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 4385 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 4386 * @param TIMx Timer instance 4387 * @retval None 4388 */ 4389 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 4390 { 4391 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 4392 } 4393 4394 /** 4395 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). 4396 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 4397 * @param TIMx Timer instance 4398 * @retval State of bit (1 or 0). 4399 */ 4400 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) 4401 { 4402 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 4403 } 4404 4405 /** 4406 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 4407 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 4408 * @param TIMx Timer instance 4409 * @retval None 4410 */ 4411 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 4412 { 4413 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 4414 } 4415 4416 /** 4417 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). 4418 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 4419 * @param TIMx Timer instance 4420 * @retval State of bit (1 or 0). 4421 */ 4422 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) 4423 { 4424 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 4425 } 4426 4427 /** 4428 * @brief Clear the commutation interrupt flag (COMIF). 4429 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 4430 * @param TIMx Timer instance 4431 * @retval None 4432 */ 4433 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 4434 { 4435 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 4436 } 4437 4438 /** 4439 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 4440 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 4441 * @param TIMx Timer instance 4442 * @retval State of bit (1 or 0). 4443 */ 4444 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) 4445 { 4446 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 4447 } 4448 4449 /** 4450 * @brief Clear the trigger interrupt flag (TIF). 4451 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 4452 * @param TIMx Timer instance 4453 * @retval None 4454 */ 4455 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 4456 { 4457 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 4458 } 4459 4460 /** 4461 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 4462 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 4463 * @param TIMx Timer instance 4464 * @retval State of bit (1 or 0). 4465 */ 4466 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) 4467 { 4468 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 4469 } 4470 4471 /** 4472 * @brief Clear the break interrupt flag (BIF). 4473 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 4474 * @param TIMx Timer instance 4475 * @retval None 4476 */ 4477 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 4478 { 4479 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 4480 } 4481 4482 /** 4483 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 4484 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 4485 * @param TIMx Timer instance 4486 * @retval State of bit (1 or 0). 4487 */ 4488 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) 4489 { 4490 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 4491 } 4492 4493 /** 4494 * @brief Clear the break 2 interrupt flag (B2IF). 4495 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 4496 * @param TIMx Timer instance 4497 * @retval None 4498 */ 4499 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 4500 { 4501 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 4502 } 4503 4504 /** 4505 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 4506 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 4507 * @param TIMx Timer instance 4508 * @retval State of bit (1 or 0). 4509 */ 4510 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) 4511 { 4512 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 4513 } 4514 4515 /** 4516 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 4517 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 4518 * @param TIMx Timer instance 4519 * @retval None 4520 */ 4521 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 4522 { 4523 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 4524 } 4525 4526 /** 4527 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set 4528 * (Capture/Compare 1 interrupt is pending). 4529 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 4530 * @param TIMx Timer instance 4531 * @retval State of bit (1 or 0). 4532 */ 4533 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) 4534 { 4535 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 4536 } 4537 4538 /** 4539 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 4540 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 4541 * @param TIMx Timer instance 4542 * @retval None 4543 */ 4544 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 4545 { 4546 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 4547 } 4548 4549 /** 4550 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set 4551 * (Capture/Compare 2 over-capture interrupt is pending). 4552 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 4553 * @param TIMx Timer instance 4554 * @retval State of bit (1 or 0). 4555 */ 4556 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) 4557 { 4558 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 4559 } 4560 4561 /** 4562 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 4563 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 4564 * @param TIMx Timer instance 4565 * @retval None 4566 */ 4567 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 4568 { 4569 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 4570 } 4571 4572 /** 4573 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set 4574 * (Capture/Compare 3 over-capture interrupt is pending). 4575 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 4576 * @param TIMx Timer instance 4577 * @retval State of bit (1 or 0). 4578 */ 4579 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) 4580 { 4581 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 4582 } 4583 4584 /** 4585 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 4586 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 4587 * @param TIMx Timer instance 4588 * @retval None 4589 */ 4590 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 4591 { 4592 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 4593 } 4594 4595 /** 4596 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set 4597 * (Capture/Compare 4 over-capture interrupt is pending). 4598 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 4599 * @param TIMx Timer instance 4600 * @retval State of bit (1 or 0). 4601 */ 4602 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) 4603 { 4604 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 4605 } 4606 4607 /** 4608 * @brief Clear the system break interrupt flag (SBIF). 4609 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 4610 * @param TIMx Timer instance 4611 * @retval None 4612 */ 4613 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 4614 { 4615 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 4616 } 4617 4618 /** 4619 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). 4620 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 4621 * @param TIMx Timer instance 4622 * @retval State of bit (1 or 0). 4623 */ 4624 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) 4625 { 4626 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 4627 } 4628 4629 /** 4630 * @} 4631 */ 4632 4633 /** @defgroup TIM_LL_EF_IT_Management IT-Management 4634 * @ingroup RTEMSBSPsARMSTM32H7 4635 * @{ 4636 */ 4637 /** 4638 * @brief Enable update interrupt (UIE). 4639 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 4640 * @param TIMx Timer instance 4641 * @retval None 4642 */ 4643 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 4644 { 4645 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 4646 } 4647 4648 /** 4649 * @brief Disable update interrupt (UIE). 4650 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 4651 * @param TIMx Timer instance 4652 * @retval None 4653 */ 4654 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) 4655 { 4656 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 4657 } 4658 4659 /** 4660 * @brief Indicates whether the update interrupt (UIE) is enabled. 4661 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 4662 * @param TIMx Timer instance 4663 * @retval State of bit (1 or 0). 4664 */ 4665 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) 4666 { 4667 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); 4668 } 4669 4670 /** 4671 * @brief Enable capture/compare 1 interrupt (CC1IE). 4672 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 4673 * @param TIMx Timer instance 4674 * @retval None 4675 */ 4676 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) 4677 { 4678 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 4679 } 4680 4681 /** 4682 * @brief Disable capture/compare 1 interrupt (CC1IE). 4683 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 4684 * @param TIMx Timer instance 4685 * @retval None 4686 */ 4687 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) 4688 { 4689 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 4690 } 4691 4692 /** 4693 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 4694 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 4695 * @param TIMx Timer instance 4696 * @retval State of bit (1 or 0). 4697 */ 4698 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) 4699 { 4700 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); 4701 } 4702 4703 /** 4704 * @brief Enable capture/compare 2 interrupt (CC2IE). 4705 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 4706 * @param TIMx Timer instance 4707 * @retval None 4708 */ 4709 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) 4710 { 4711 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 4712 } 4713 4714 /** 4715 * @brief Disable capture/compare 2 interrupt (CC2IE). 4716 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 4717 * @param TIMx Timer instance 4718 * @retval None 4719 */ 4720 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) 4721 { 4722 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 4723 } 4724 4725 /** 4726 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 4727 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 4728 * @param TIMx Timer instance 4729 * @retval State of bit (1 or 0). 4730 */ 4731 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) 4732 { 4733 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); 4734 } 4735 4736 /** 4737 * @brief Enable capture/compare 3 interrupt (CC3IE). 4738 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 4739 * @param TIMx Timer instance 4740 * @retval None 4741 */ 4742 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) 4743 { 4744 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 4745 } 4746 4747 /** 4748 * @brief Disable capture/compare 3 interrupt (CC3IE). 4749 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 4750 * @param TIMx Timer instance 4751 * @retval None 4752 */ 4753 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) 4754 { 4755 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 4756 } 4757 4758 /** 4759 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 4760 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 4761 * @param TIMx Timer instance 4762 * @retval State of bit (1 or 0). 4763 */ 4764 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) 4765 { 4766 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); 4767 } 4768 4769 /** 4770 * @brief Enable capture/compare 4 interrupt (CC4IE). 4771 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 4772 * @param TIMx Timer instance 4773 * @retval None 4774 */ 4775 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) 4776 { 4777 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 4778 } 4779 4780 /** 4781 * @brief Disable capture/compare 4 interrupt (CC4IE). 4782 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 4783 * @param TIMx Timer instance 4784 * @retval None 4785 */ 4786 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) 4787 { 4788 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 4789 } 4790 4791 /** 4792 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 4793 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 4794 * @param TIMx Timer instance 4795 * @retval State of bit (1 or 0). 4796 */ 4797 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) 4798 { 4799 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); 4800 } 4801 4802 /** 4803 * @brief Enable commutation interrupt (COMIE). 4804 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 4805 * @param TIMx Timer instance 4806 * @retval None 4807 */ 4808 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) 4809 { 4810 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 4811 } 4812 4813 /** 4814 * @brief Disable commutation interrupt (COMIE). 4815 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 4816 * @param TIMx Timer instance 4817 * @retval None 4818 */ 4819 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) 4820 { 4821 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 4822 } 4823 4824 /** 4825 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 4826 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 4827 * @param TIMx Timer instance 4828 * @retval State of bit (1 or 0). 4829 */ 4830 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) 4831 { 4832 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); 4833 } 4834 4835 /** 4836 * @brief Enable trigger interrupt (TIE). 4837 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 4838 * @param TIMx Timer instance 4839 * @retval None 4840 */ 4841 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) 4842 { 4843 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 4844 } 4845 4846 /** 4847 * @brief Disable trigger interrupt (TIE). 4848 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 4849 * @param TIMx Timer instance 4850 * @retval None 4851 */ 4852 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) 4853 { 4854 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 4855 } 4856 4857 /** 4858 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 4859 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 4860 * @param TIMx Timer instance 4861 * @retval State of bit (1 or 0). 4862 */ 4863 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) 4864 { 4865 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); 4866 } 4867 4868 /** 4869 * @brief Enable break interrupt (BIE). 4870 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 4871 * @param TIMx Timer instance 4872 * @retval None 4873 */ 4874 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) 4875 { 4876 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 4877 } 4878 4879 /** 4880 * @brief Disable break interrupt (BIE). 4881 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 4882 * @param TIMx Timer instance 4883 * @retval None 4884 */ 4885 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) 4886 { 4887 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 4888 } 4889 4890 /** 4891 * @brief Indicates whether the break interrupt (BIE) is enabled. 4892 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 4893 * @param TIMx Timer instance 4894 * @retval State of bit (1 or 0). 4895 */ 4896 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) 4897 { 4898 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); 4899 } 4900 4901 /** 4902 * @} 4903 */ 4904 4905 /** @defgroup TIM_LL_EF_DMA_Management DMA Management 4906 * @ingroup RTEMSBSPsARMSTM32H7 4907 * @{ 4908 */ 4909 /** 4910 * @brief Enable update DMA request (UDE). 4911 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 4912 * @param TIMx Timer instance 4913 * @retval None 4914 */ 4915 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) 4916 { 4917 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 4918 } 4919 4920 /** 4921 * @brief Disable update DMA request (UDE). 4922 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 4923 * @param TIMx Timer instance 4924 * @retval None 4925 */ 4926 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) 4927 { 4928 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 4929 } 4930 4931 /** 4932 * @brief Indicates whether the update DMA request (UDE) is enabled. 4933 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 4934 * @param TIMx Timer instance 4935 * @retval State of bit (1 or 0). 4936 */ 4937 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) 4938 { 4939 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); 4940 } 4941 4942 /** 4943 * @brief Enable capture/compare 1 DMA request (CC1DE). 4944 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 4945 * @param TIMx Timer instance 4946 * @retval None 4947 */ 4948 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) 4949 { 4950 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 4951 } 4952 4953 /** 4954 * @brief Disable capture/compare 1 DMA request (CC1DE). 4955 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 4956 * @param TIMx Timer instance 4957 * @retval None 4958 */ 4959 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) 4960 { 4961 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 4962 } 4963 4964 /** 4965 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 4966 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 4967 * @param TIMx Timer instance 4968 * @retval State of bit (1 or 0). 4969 */ 4970 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) 4971 { 4972 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); 4973 } 4974 4975 /** 4976 * @brief Enable capture/compare 2 DMA request (CC2DE). 4977 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 4978 * @param TIMx Timer instance 4979 * @retval None 4980 */ 4981 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) 4982 { 4983 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 4984 } 4985 4986 /** 4987 * @brief Disable capture/compare 2 DMA request (CC2DE). 4988 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 4989 * @param TIMx Timer instance 4990 * @retval None 4991 */ 4992 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) 4993 { 4994 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 4995 } 4996 4997 /** 4998 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 4999 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 5000 * @param TIMx Timer instance 5001 * @retval State of bit (1 or 0). 5002 */ 5003 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) 5004 { 5005 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); 5006 } 5007 5008 /** 5009 * @brief Enable capture/compare 3 DMA request (CC3DE). 5010 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 5011 * @param TIMx Timer instance 5012 * @retval None 5013 */ 5014 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) 5015 { 5016 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 5017 } 5018 5019 /** 5020 * @brief Disable capture/compare 3 DMA request (CC3DE). 5021 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 5022 * @param TIMx Timer instance 5023 * @retval None 5024 */ 5025 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) 5026 { 5027 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 5028 } 5029 5030 /** 5031 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 5032 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 5033 * @param TIMx Timer instance 5034 * @retval State of bit (1 or 0). 5035 */ 5036 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) 5037 { 5038 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); 5039 } 5040 5041 /** 5042 * @brief Enable capture/compare 4 DMA request (CC4DE). 5043 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 5044 * @param TIMx Timer instance 5045 * @retval None 5046 */ 5047 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) 5048 { 5049 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 5050 } 5051 5052 /** 5053 * @brief Disable capture/compare 4 DMA request (CC4DE). 5054 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 5055 * @param TIMx Timer instance 5056 * @retval None 5057 */ 5058 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) 5059 { 5060 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 5061 } 5062 5063 /** 5064 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 5065 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 5066 * @param TIMx Timer instance 5067 * @retval State of bit (1 or 0). 5068 */ 5069 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) 5070 { 5071 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); 5072 } 5073 5074 /** 5075 * @brief Enable commutation DMA request (COMDE). 5076 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 5077 * @param TIMx Timer instance 5078 * @retval None 5079 */ 5080 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) 5081 { 5082 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 5083 } 5084 5085 /** 5086 * @brief Disable commutation DMA request (COMDE). 5087 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 5088 * @param TIMx Timer instance 5089 * @retval None 5090 */ 5091 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) 5092 { 5093 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 5094 } 5095 5096 /** 5097 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 5098 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 5099 * @param TIMx Timer instance 5100 * @retval State of bit (1 or 0). 5101 */ 5102 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) 5103 { 5104 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); 5105 } 5106 5107 /** 5108 * @brief Enable trigger interrupt (TDE). 5109 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 5110 * @param TIMx Timer instance 5111 * @retval None 5112 */ 5113 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) 5114 { 5115 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 5116 } 5117 5118 /** 5119 * @brief Disable trigger interrupt (TDE). 5120 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 5121 * @param TIMx Timer instance 5122 * @retval None 5123 */ 5124 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) 5125 { 5126 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 5127 } 5128 5129 /** 5130 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 5131 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 5132 * @param TIMx Timer instance 5133 * @retval State of bit (1 or 0). 5134 */ 5135 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) 5136 { 5137 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); 5138 } 5139 5140 /** 5141 * @} 5142 */ 5143 5144 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 5145 * @ingroup RTEMSBSPsARMSTM32H7 5146 * @{ 5147 */ 5148 /** 5149 * @brief Generate an update event. 5150 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 5151 * @param TIMx Timer instance 5152 * @retval None 5153 */ 5154 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) 5155 { 5156 SET_BIT(TIMx->EGR, TIM_EGR_UG); 5157 } 5158 5159 /** 5160 * @brief Generate Capture/Compare 1 event. 5161 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 5162 * @param TIMx Timer instance 5163 * @retval None 5164 */ 5165 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) 5166 { 5167 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 5168 } 5169 5170 /** 5171 * @brief Generate Capture/Compare 2 event. 5172 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 5173 * @param TIMx Timer instance 5174 * @retval None 5175 */ 5176 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) 5177 { 5178 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 5179 } 5180 5181 /** 5182 * @brief Generate Capture/Compare 3 event. 5183 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 5184 * @param TIMx Timer instance 5185 * @retval None 5186 */ 5187 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) 5188 { 5189 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 5190 } 5191 5192 /** 5193 * @brief Generate Capture/Compare 4 event. 5194 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 5195 * @param TIMx Timer instance 5196 * @retval None 5197 */ 5198 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) 5199 { 5200 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 5201 } 5202 5203 /** 5204 * @brief Generate commutation event. 5205 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 5206 * @param TIMx Timer instance 5207 * @retval None 5208 */ 5209 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) 5210 { 5211 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 5212 } 5213 5214 /** 5215 * @brief Generate trigger event. 5216 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 5217 * @param TIMx Timer instance 5218 * @retval None 5219 */ 5220 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) 5221 { 5222 SET_BIT(TIMx->EGR, TIM_EGR_TG); 5223 } 5224 5225 /** 5226 * @brief Generate break event. 5227 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 5228 * @param TIMx Timer instance 5229 * @retval None 5230 */ 5231 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) 5232 { 5233 SET_BIT(TIMx->EGR, TIM_EGR_BG); 5234 } 5235 5236 /** 5237 * @brief Generate break 2 event. 5238 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 5239 * @param TIMx Timer instance 5240 * @retval None 5241 */ 5242 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) 5243 { 5244 SET_BIT(TIMx->EGR, TIM_EGR_B2G); 5245 } 5246 5247 /** 5248 * @} 5249 */ 5250 5251 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 5252 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 5253 * @ingroup RTEMSBSPsARMSTM32H7 5254 * @{ 5255 */ 5256 5257 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); 5258 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); 5259 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); 5260 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 5261 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 5262 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 5263 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); 5264 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 5265 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 5266 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 5267 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 5268 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 5269 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 5270 /** 5271 * @} 5272 */ 5273 #endif /* USE_FULL_LL_DRIVER */ 5274 5275 /** 5276 * @} 5277 */ 5278 5279 /** 5280 * @} 5281 */ 5282 5283 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */ 5284 5285 /** 5286 * @} 5287 */ 5288 5289 #ifdef __cplusplus 5290 } 5291 #endif 5292 5293 #endif /* __STM32H7xx_LL_TIM_H */
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.3.7 LXR engine. The LXR team |
|