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File indexing completed on 2025-05-11 08:23:38
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_system.h 0004 * @author MCD Application Team 0005 * @brief Header file of SYSTEM LL module. 0006 * 0007 ****************************************************************************** 0008 * @attention 0009 * 0010 * Copyright (c) 2017 STMicroelectronics. 0011 * All rights reserved. 0012 * 0013 * This software is licensed under terms that can be found in the LICENSE file 0014 * in the root directory of this software component. 0015 * If no LICENSE file comes with this software, it is provided AS-IS. 0016 * 0017 ****************************************************************************** 0018 @verbatim 0019 ============================================================================== 0020 ##### How to use this driver ##### 0021 ============================================================================== 0022 [..] 0023 The LL SYSTEM driver contains a set of generic APIs that can be 0024 used by user: 0025 (+) Some of the FLASH features need to be handled in the SYSTEM file. 0026 (+) Access to DBGCMU registers 0027 (+) Access to SYSCFG registers 0028 0029 @endverbatim 0030 ****************************************************************************** 0031 */ 0032 0033 /* Define to prevent recursive inclusion -------------------------------------*/ 0034 #ifndef __STM32H7xx_LL_SYSTEM_H 0035 #define __STM32H7xx_LL_SYSTEM_H 0036 0037 #ifdef __cplusplus 0038 extern "C" { 0039 #endif 0040 0041 /* Includes ------------------------------------------------------------------*/ 0042 #include "stm32h7xx.h" 0043 0044 /** @addtogroup STM32H7xx_LL_Driver 0045 * @{ 0046 */ 0047 0048 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) 0049 0050 /** @defgroup SYSTEM_LL SYSTEM 0051 * @ingroup RTEMSBSPsARMSTM32H7 0052 * @{ 0053 */ 0054 0055 /* Private types -------------------------------------------------------------*/ 0056 /* Private variables ---------------------------------------------------------*/ 0057 0058 /* Private constants ---------------------------------------------------------*/ 0059 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 0060 * @ingroup RTEMSBSPsARMSTM32H7 0061 * @{ 0062 */ 0063 /** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status 0064 * @ingroup RTEMSBSPsARMSTM32H7 0065 * @{ 0066 */ 0067 #define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U 0068 #define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U 0069 #define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U 0070 #define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U 0071 #define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U 0072 #define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U 0073 #define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U 0074 #define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U 0075 /** 0076 * @} 0077 */ 0078 0079 /** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status 0080 * @ingroup RTEMSBSPsARMSTM32H7 0081 * @{ 0082 */ 0083 #define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U 0084 #define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U 0085 #define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U 0086 #define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U 0087 #define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U 0088 #define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U 0089 #define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U 0090 #define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U 0091 /** 0092 * @} 0093 */ 0094 /** 0095 * @} 0096 */ 0097 0098 /* Private macros ------------------------------------------------------------*/ 0099 0100 /* Exported types ------------------------------------------------------------*/ 0101 /* Exported constants --------------------------------------------------------*/ 0102 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 0103 * @ingroup RTEMSBSPsARMSTM32H7 0104 * @{ 0105 */ 0106 0107 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS 0108 * @ingroup RTEMSBSPsARMSTM32H7 0109 * @{ 0110 */ 0111 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ 0112 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ 0113 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ 0114 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ 0115 #if defined(I2C5) 0116 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */ 0117 #endif /*I2C5*/ 0118 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 0119 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 0120 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 0121 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 0122 /** 0123 * @} 0124 */ 0125 0126 /** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control 0127 * @ingroup RTEMSBSPsARMSTM32H7 0128 * @{ 0129 */ 0130 #if defined(SYSCFG_PMCR_BOOSTEN) 0131 #define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */ 0132 #endif /*SYSCFG_PMCR_BOOSTEN*/ 0133 #define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */ 0134 #define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */ 0135 #define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */ 0136 #define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */ 0137 /** 0138 * @} 0139 */ 0140 0141 #if defined(SYSCFG_PMCR_EPIS_SEL) 0142 /** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection 0143 * @ingroup RTEMSBSPsARMSTM32H7 0144 * @{ 0145 */ 0146 #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ 0147 #define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ 0148 /** 0149 * @} 0150 */ 0151 #endif /* SYSCFG_PMCR_EPIS_SEL */ 0152 0153 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT 0154 * @ingroup RTEMSBSPsARMSTM32H7 0155 * @{ 0156 */ 0157 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ 0158 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ 0159 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ 0160 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ 0161 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ 0162 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ 0163 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ 0164 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ 0165 #if defined(GPIOI) 0166 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ 0167 #endif /*GPIOI*/ 0168 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ 0169 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ 0170 /** 0171 * @} 0172 */ 0173 0174 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE 0175 * @ingroup RTEMSBSPsARMSTM32H7 0176 * @{ 0177 */ 0178 #define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ 0179 #define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ 0180 #define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ 0181 #define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ 0182 #define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ 0183 #define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ 0184 #define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ 0185 #define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ 0186 #define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ 0187 #define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ 0188 #define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ 0189 #define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ 0190 #define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ 0191 #define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ 0192 #define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ 0193 #define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ 0194 /** 0195 * @} 0196 */ 0197 0198 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK 0199 * @ingroup RTEMSBSPsARMSTM32H7 0200 * @{ 0201 */ 0202 #define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal 0203 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0204 0205 #define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal 0206 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0207 0208 #define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal 0209 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0210 0211 #define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal 0212 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0213 0214 #define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal 0215 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0216 0217 #if defined(SYSCFG_CFGR_SRAM3L) 0218 #define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal 0219 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0220 #endif /*SYSCFG_CFGR_SRAM3L*/ 0221 0222 #define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal 0223 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0224 0225 #define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal 0226 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0227 0228 #define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal 0229 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0230 0231 #define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal 0232 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0233 0234 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection 0235 with TIM1/8/15/16/17 and HRTIM Break Input 0236 and also the PVDE and PLS bits of the Power Control Interface */ 0237 #if defined(DUAL_CORE) 0238 #define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal 0239 with Break Input of TIM1/8/15/16/17 and HRTIM */ 0240 #endif /* DUAL_CORE */ 0241 /** 0242 * @} 0243 */ 0244 0245 /** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection 0246 * @ingroup RTEMSBSPsARMSTM32H7 0247 * @{ 0248 */ 0249 #define LL_SYSCFG_CELL_CODE 0U 0250 #define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS 0251 /** 0252 * @} 0253 */ 0254 0255 /** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes 0256 * @ingroup RTEMSBSPsARMSTM32H7 0257 * @{ 0258 */ 0259 #define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U 0260 #define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M 0261 /** 0262 * @} 0263 */ 0264 0265 #if defined (DUAL_CORE) 0266 /** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes 0267 * @ingroup RTEMSBSPsARMSTM32H7 0268 * @{ 0269 */ 0270 #define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U 0271 #define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M 0272 /** 0273 * @} 0274 */ 0275 #endif /* DUAL_CORE */ 0276 0277 /** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration 0278 * @ingroup RTEMSBSPsARMSTM32H7 0279 * @{ 0280 */ 0281 #define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U 0282 #define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U 0283 #define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U 0284 #define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U 0285 /** 0286 * @} 0287 */ 0288 #ifdef SYSCFG_UR17_TCM_AXI_CFG 0289 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package 0290 * @ingroup RTEMSBSPsARMSTM32H7 0291 * @{ 0292 */ 0293 #define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U 0294 #define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U 0295 #define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U 0296 #define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U 0297 /** 0298 * @} 0299 */ 0300 #endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */ 0301 #if defined(SYSCFG_PKGR_PKG) 0302 /** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package 0303 * @ingroup RTEMSBSPsARMSTM32H7 0304 * @{ 0305 */ 0306 #if (STM32H7_DEV_ID == 0x450UL) 0307 #define LL_SYSCFG_LQFP100_PACKAGE 0U 0308 #define LL_SYSCFG_TQFP144_PACKAGE 2U 0309 #define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U 0310 #define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U 0311 #elif (STM32H7_DEV_ID == 0x483UL) 0312 #define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U 0313 #define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U 0314 #define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U 0315 #define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U 0316 #define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U 0317 #define LL_SYSCFG_LQFP144_PACKAGE 5U 0318 #define LL_SYSCFG_UFBGA144_PACKAGE 6U 0319 #define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U 0320 #define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U 0321 #define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U 0322 #define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U 0323 #endif /* STM32H7_DEV_ID == 0x450UL */ 0324 /** 0325 * @} 0326 */ 0327 #endif /* SYSCFG_PKGR_PKG */ 0328 0329 /** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level 0330 * @ingroup RTEMSBSPsARMSTM32H7 0331 * @{ 0332 */ 0333 #define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U 0334 #define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 0335 #define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 0336 #define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH 0337 0338 /** 0339 * @} 0340 */ 0341 0342 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 0343 * @ingroup RTEMSBSPsARMSTM32H7 0344 * @{ 0345 */ 0346 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ 0347 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 0348 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 0349 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 0350 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 0351 /** 0352 * @} 0353 */ 0354 0355 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP 0356 * @ingroup RTEMSBSPsARMSTM32H7 0357 * @{ 0358 */ 0359 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */ 0360 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */ 0361 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */ 0362 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */ 0363 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */ 0364 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */ 0365 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */ 0366 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */ 0367 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */ 0368 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */ 0369 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 0370 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 0371 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ 0372 #if defined(I2C5) 0373 #define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */ 0374 #endif /*I2C5*/ 0375 /** 0376 * @} 0377 */ 0378 0379 0380 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP 0381 * @ingroup RTEMSBSPsARMSTM32H7 0382 * @{ 0383 */ 0384 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) 0385 #define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */ 0386 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 0387 #if defined(TIM23) 0388 #define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */ 0389 #endif /*TIM23*/ 0390 #if defined(TIM24) 0391 #define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */ 0392 #endif /*TIM24*/ 0393 /** 0394 * @} 0395 */ 0396 0397 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP 0398 * @ingroup RTEMSBSPsARMSTM32H7 0399 * @{ 0400 */ 0401 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */ 0402 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */ 0403 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */ 0404 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */ 0405 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */ 0406 #if defined(HRTIM1) 0407 #define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */ 0408 #endif /*HRTIM1*/ 0409 /** 0410 * @} 0411 */ 0412 0413 /** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP 0414 * @ingroup RTEMSBSPsARMSTM32H7 0415 * @{ 0416 */ 0417 #define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */ 0418 /** 0419 * @} 0420 */ 0421 0422 /** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP 0423 * @ingroup RTEMSBSPsARMSTM32H7 0424 * @{ 0425 */ 0426 #define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */ 0427 #define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */ 0428 #define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */ 0429 #define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */ 0430 #define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */ 0431 #define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */ 0432 #define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */ 0433 /** 0434 * @} 0435 */ 0436 0437 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 0438 * @ingroup RTEMSBSPsARMSTM32H7 0439 * @{ 0440 */ 0441 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ 0442 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ 0443 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ 0444 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ 0445 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ 0446 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ 0447 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ 0448 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ 0449 /** 0450 * @} 0451 */ 0452 0453 /** 0454 * @} 0455 */ 0456 0457 /* Exported macro ------------------------------------------------------------*/ 0458 0459 /* Exported functions --------------------------------------------------------*/ 0460 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 0461 * @ingroup RTEMSBSPsARMSTM32H7 0462 * @{ 0463 */ 0464 0465 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG 0466 * @ingroup RTEMSBSPsARMSTM32H7 0467 * @{ 0468 */ 0469 0470 #if defined(SYSCFG_PMCR_EPIS_SEL) 0471 /** 0472 * @brief Select Ethernet PHY interface 0473 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface 0474 * @param Interface This parameter can be one of the following values: 0475 * @arg @ref LL_SYSCFG_ETH_MII 0476 * @arg @ref LL_SYSCFG_ETH_RMII 0477 * @retval None 0478 */ 0479 __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) 0480 { 0481 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface); 0482 } 0483 0484 /** 0485 * @brief Get Ethernet PHY interface 0486 * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface 0487 * @retval Returned value can be one of the following values: 0488 * @arg @ref LL_SYSCFG_ETH_MII 0489 * @arg @ref LL_SYSCFG_ETH_RMII 0490 */ 0491 __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) 0492 { 0493 return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL)); 0494 } 0495 0496 #endif /* SYSCFG_PMCR_EPIS_SEL */ 0497 /** 0498 * @brief Open an Analog Switch 0499 * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch 0500 * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch 0501 * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch 0502 * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch 0503 * @param AnalogSwitch This parameter can be one of the following values: 0504 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch 0505 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch 0506 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch 0507 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch 0508 * @retval None 0509 */ 0510 __STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch) 0511 { 0512 SET_BIT(SYSCFG->PMCR, AnalogSwitch); 0513 } 0514 0515 /** 0516 * @brief Close an Analog Switch 0517 * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch 0518 * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch 0519 * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch 0520 * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch 0521 * @param AnalogSwitch This parameter can be one of the following values: 0522 * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch 0523 * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch 0524 * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch 0525 * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch 0526 * @retval None 0527 */ 0528 __STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch) 0529 { 0530 CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch); 0531 } 0532 #ifdef SYSCFG_PMCR_BOOSTEN 0533 /** 0534 * @brief Enable the Analog booster to reduce the total harmonic distortion 0535 * of the analog switch when the supply voltage is lower than 2.7 V 0536 * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster 0537 * @note Activating the booster allows to guaranty the analog switch AC performance 0538 * when the supply voltage is below 2.7 V: in this case, the analog switch 0539 * performance is the same on the full voltage range 0540 * @retval None 0541 */ 0542 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) 0543 { 0544 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; 0545 } 0546 0547 /** 0548 * @brief Disable the Analog booster 0549 * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster 0550 * @note Activating the booster allows to guaranty the analog switch AC performance 0551 * when the supply voltage is below 2.7 V: in this case, the analog switch 0552 * performance is the same on the full voltage range 0553 * @retval None 0554 */ 0555 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) 0556 { 0557 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; 0558 } 0559 #endif /*SYSCFG_PMCR_BOOSTEN*/ 0560 /** 0561 * @brief Enable the I2C fast mode plus driving capability. 0562 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n 0563 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus 0564 * @param ConfigFastModePlus This parameter can be a combination of the following values: 0565 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 0566 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 0567 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 0568 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 0569 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 0570 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 0571 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 0572 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) 0573 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) 0574 * 0575 * (*) value not defined in all devices 0576 * @retval None 0577 */ 0578 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) 0579 { 0580 SET_BIT(SYSCFG->PMCR, ConfigFastModePlus); 0581 } 0582 0583 /** 0584 * @brief Disable the I2C fast mode plus driving capability. 0585 * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n 0586 * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus 0587 * @param ConfigFastModePlus This parameter can be a combination of the following values: 0588 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 0589 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 0590 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) 0591 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) 0592 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 0593 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) 0594 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 0595 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 0596 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) 0597 * 0598 * (*) value not defined in all devices 0599 * @retval None 0600 */ 0601 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) 0602 { 0603 CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus); 0604 } 0605 0606 /** 0607 * @brief Configure source input for the EXTI external interrupt. 0608 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n 0609 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n 0610 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n 0611 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource 0612 * @param Port This parameter can be one of the following values: 0613 * @arg @ref LL_SYSCFG_EXTI_PORTA 0614 * @arg @ref LL_SYSCFG_EXTI_PORTB 0615 * @arg @ref LL_SYSCFG_EXTI_PORTC 0616 * @arg @ref LL_SYSCFG_EXTI_PORTD 0617 * @arg @ref LL_SYSCFG_EXTI_PORTE 0618 * @arg @ref LL_SYSCFG_EXTI_PORTF 0619 * @arg @ref LL_SYSCFG_EXTI_PORTG 0620 * @arg @ref LL_SYSCFG_EXTI_PORTH 0621 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 0622 * @arg @ref LL_SYSCFG_EXTI_PORTJ 0623 * @arg @ref LL_SYSCFG_EXTI_PORTK 0624 * 0625 * (*) value not defined in all devices 0626 * @param Line This parameter can be one of the following values: 0627 * @arg @ref LL_SYSCFG_EXTI_LINE0 0628 * @arg @ref LL_SYSCFG_EXTI_LINE1 0629 * @arg @ref LL_SYSCFG_EXTI_LINE2 0630 * @arg @ref LL_SYSCFG_EXTI_LINE3 0631 * @arg @ref LL_SYSCFG_EXTI_LINE4 0632 * @arg @ref LL_SYSCFG_EXTI_LINE5 0633 * @arg @ref LL_SYSCFG_EXTI_LINE6 0634 * @arg @ref LL_SYSCFG_EXTI_LINE7 0635 * @arg @ref LL_SYSCFG_EXTI_LINE8 0636 * @arg @ref LL_SYSCFG_EXTI_LINE9 0637 * @arg @ref LL_SYSCFG_EXTI_LINE10 0638 * @arg @ref LL_SYSCFG_EXTI_LINE11 0639 * @arg @ref LL_SYSCFG_EXTI_LINE12 0640 * @arg @ref LL_SYSCFG_EXTI_LINE13 0641 * @arg @ref LL_SYSCFG_EXTI_LINE14 0642 * @arg @ref LL_SYSCFG_EXTI_LINE15 0643 * @retval None 0644 */ 0645 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) 0646 { 0647 MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U)); 0648 } 0649 0650 /** 0651 * @brief Get the configured defined for specific EXTI Line 0652 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n 0653 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n 0654 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n 0655 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource 0656 * @param Line This parameter can be one of the following values: 0657 * @arg @ref LL_SYSCFG_EXTI_LINE0 0658 * @arg @ref LL_SYSCFG_EXTI_LINE1 0659 * @arg @ref LL_SYSCFG_EXTI_LINE2 0660 * @arg @ref LL_SYSCFG_EXTI_LINE3 0661 * @arg @ref LL_SYSCFG_EXTI_LINE4 0662 * @arg @ref LL_SYSCFG_EXTI_LINE5 0663 * @arg @ref LL_SYSCFG_EXTI_LINE6 0664 * @arg @ref LL_SYSCFG_EXTI_LINE7 0665 * @arg @ref LL_SYSCFG_EXTI_LINE8 0666 * @arg @ref LL_SYSCFG_EXTI_LINE9 0667 * @arg @ref LL_SYSCFG_EXTI_LINE10 0668 * @arg @ref LL_SYSCFG_EXTI_LINE11 0669 * @arg @ref LL_SYSCFG_EXTI_LINE12 0670 * @arg @ref LL_SYSCFG_EXTI_LINE13 0671 * @arg @ref LL_SYSCFG_EXTI_LINE14 0672 * @arg @ref LL_SYSCFG_EXTI_LINE15 0673 * @retval Returned value can be one of the following values: 0674 * @arg @ref LL_SYSCFG_EXTI_PORTA 0675 * @arg @ref LL_SYSCFG_EXTI_PORTB 0676 * @arg @ref LL_SYSCFG_EXTI_PORTC 0677 * @arg @ref LL_SYSCFG_EXTI_PORTD 0678 * @arg @ref LL_SYSCFG_EXTI_PORTE 0679 * @arg @ref LL_SYSCFG_EXTI_PORTF 0680 * @arg @ref LL_SYSCFG_EXTI_PORTG 0681 * @arg @ref LL_SYSCFG_EXTI_PORTH 0682 * @arg @ref LL_SYSCFG_EXTI_PORTI (*) 0683 * @arg @ref LL_SYSCFG_EXTI_PORTJ 0684 * @arg @ref LL_SYSCFG_EXTI_PORTK 0685 * (*) value not defined in all devices 0686 */ 0687 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) 0688 { 0689 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U)); 0690 } 0691 0692 /** 0693 * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs 0694 * @note this feature is available on STM32H7 rev.B and above 0695 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n 0696 * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n 0697 * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n 0698 * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n 0699 * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n 0700 * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n 0701 * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n 0702 * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n 0703 * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n 0704 * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n 0705 * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n 0706 * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs 0707 * @param Break This parameter can be a combination of the following values: 0708 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC 0709 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC 0710 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC 0711 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC 0712 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC 0713 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) 0714 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC 0715 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC 0716 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP 0717 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC 0718 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 0719 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) 0720 * @retval None 0721 * (*) value not defined in all devices 0722 */ 0723 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) 0724 { 0725 #if defined(DUAL_CORE) 0726 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 0727 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 0728 SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break); 0729 #elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) 0730 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 0731 SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 0732 SYSCFG_CFGR_PVDL, Break); 0733 #elif defined(SYSCFG_CFGR_AXISRAML) 0734 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 0735 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\ 0736 Break); 0737 #else 0738 MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\ 0739 SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ 0740 SYSCFG_CFGR_PVDL, Break); 0741 #endif /* DUAL_CORE */ 0742 } 0743 0744 /** 0745 * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs 0746 * @note this feature is available on STM32H7 rev.B and above 0747 * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n 0748 * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n 0749 * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n 0750 * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n 0751 * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n 0752 * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n 0753 * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n 0754 * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n 0755 * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n 0756 * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n 0757 * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n 0758 * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs 0759 * @retval Returned value can be can be a combination of the following values: 0760 * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC 0761 * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC 0762 * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC 0763 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC 0764 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC 0765 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) 0766 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC 0767 * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC 0768 * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP 0769 * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC 0770 * @arg @ref LL_SYSCFG_TIMBREAK_PVD 0771 * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) 0772 * (*) value not defined in all devices 0773 */ 0774 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) 0775 { 0776 #if defined(DUAL_CORE) 0777 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 0778 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ 0779 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 0780 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L)); 0781 #elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) 0782 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 0783 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ 0784 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 0785 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 0786 #elif defined (SYSCFG_CFGR_AXISRAML) 0787 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ 0788 SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ 0789 SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ 0790 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 0791 #else 0792 return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \ 0793 SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); 0794 #endif /* DUAL_CORE */ 0795 } 0796 0797 /** 0798 * @brief Enable the Compensation Cell 0799 * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell 0800 * @note The I/O compensation cell can be used only when the device supply 0801 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. 0802 * @retval None 0803 */ 0804 __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) 0805 { 0806 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); 0807 } 0808 0809 /** 0810 * @brief Disable the Compensation Cell 0811 * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell 0812 * @note The I/O compensation cell can be used only when the device supply 0813 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. 0814 * @retval None 0815 */ 0816 __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) 0817 { 0818 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); 0819 } 0820 0821 /** 0822 * @brief Check if the Compensation Cell is enabled 0823 * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell 0824 * @retval State of bit (1 or 0). 0825 */ 0826 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void) 0827 { 0828 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL); 0829 } 0830 0831 /** 0832 * @brief Get Compensation Cell ready Flag 0833 * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR 0834 * @retval State of bit (1 or 0). 0835 */ 0836 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) 0837 { 0838 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL); 0839 } 0840 0841 /** 0842 * @brief Enable the I/O speed optimization when the product voltage is low. 0843 * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize 0844 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0845 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0846 * might be destructive. 0847 * @retval None 0848 */ 0849 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void) 0850 { 0851 #if defined(SYSCFG_CCCSR_HSLV) 0852 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); 0853 #else 0854 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); 0855 #endif /* SYSCFG_CCCSR_HSLV */ 0856 } 0857 0858 #if defined(SYSCFG_CCCSR_HSLV1) 0859 /** 0860 * @brief Enable the I/O speed optimization when the product voltage is low. 0861 * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize 0862 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0863 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0864 * might be destructive. 0865 * @retval None 0866 */ 0867 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void) 0868 { 0869 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); 0870 } 0871 0872 /** 0873 * @brief Enable the I/O speed optimization when the product voltage is low. 0874 * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize 0875 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0876 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0877 * might be destructive. 0878 * @retval None 0879 */ 0880 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void) 0881 { 0882 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); 0883 } 0884 0885 /** 0886 * @brief Enable the I/O speed optimization when the product voltage is low. 0887 * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize 0888 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0889 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0890 * might be destructive. 0891 * @retval None 0892 */ 0893 __STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void) 0894 { 0895 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); 0896 } 0897 #endif /*SYSCFG_CCCSR_HSLV1*/ 0898 0899 0900 /** 0901 * @brief To Disable optimize the I/O speed when the product voltage is low. 0902 * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize 0903 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0904 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0905 * might be destructive. 0906 * @retval None 0907 */ 0908 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void) 0909 { 0910 #if defined(SYSCFG_CCCSR_HSLV) 0911 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); 0912 #else 0913 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); 0914 #endif /* SYSCFG_CCCSR_HSLV */ 0915 } 0916 0917 #if defined(SYSCFG_CCCSR_HSLV1) 0918 /** 0919 * @brief To Disable optimize the I/O speed when the product voltage is low. 0920 * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize 0921 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0922 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0923 * might be destructive. 0924 * @retval None 0925 */ 0926 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void) 0927 { 0928 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); 0929 } 0930 0931 /** 0932 * @brief To Disable optimize the I/O speed when the product voltage is low. 0933 * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize 0934 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0935 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0936 * might be destructive. 0937 * @retval None 0938 */ 0939 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void) 0940 { 0941 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); 0942 } 0943 0944 /** 0945 * @brief To Disable optimize the I/O speed when the product voltage is low. 0946 * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize 0947 * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the 0948 * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V 0949 * might be destructive. 0950 * @retval None 0951 */ 0952 __STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void) 0953 { 0954 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); 0955 } 0956 #endif /*SYSCFG_CCCSR_HSLV1*/ 0957 0958 /** 0959 * @brief Check if the I/O speed optimization is enabled 0960 * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization 0961 * @retval State of bit (1 or 0). 0962 */ 0963 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void) 0964 { 0965 #if defined(SYSCFG_CCCSR_HSLV) 0966 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL); 0967 #else 0968 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL); 0969 #endif /*SYSCFG_CCCSR_HSLV*/ 0970 } 0971 0972 #if defined(SYSCFG_CCCSR_HSLV1) 0973 /** 0974 * @brief Check if the I/O speed optimization is enabled 0975 * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization 0976 * @retval State of bit (1 or 0). 0977 */ 0978 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void) 0979 { 0980 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL); 0981 } 0982 0983 /** 0984 * @brief Check if the I/O speed optimization is enabled 0985 * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization 0986 * @retval State of bit (1 or 0). 0987 */ 0988 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void) 0989 { 0990 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL); 0991 } 0992 0993 /** 0994 * @brief Check if the I/O speed optimization is enabled 0995 * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization 0996 * @retval State of bit (1 or 0). 0997 */ 0998 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void) 0999 { 1000 return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL); 1001 } 1002 #endif /*SYSCFG_CCCSR_HSLV1*/ 1003 1004 /** 1005 * @brief Set the code selection for the I/O Compensation cell 1006 * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode 1007 * @param CompCode: Selects the code to be applied for the I/O compensation cell 1008 * This parameter can be one of the following values: 1009 * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) 1010 * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) 1011 * @retval None 1012 */ 1013 __STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode) 1014 { 1015 SET_BIT(SYSCFG->CCCSR, CompCode); 1016 } 1017 1018 /** 1019 * @brief Get the code selected for the I/O Compensation cell 1020 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode 1021 * @retval Returned value can be one of the following values: 1022 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) 1023 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) 1024 */ 1025 __STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void) 1026 { 1027 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS)); 1028 } 1029 1030 #ifdef SYSCFG_CCCSR_CS_MMC 1031 1032 /** 1033 * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail 1034 * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode 1035 * @retval Returned value can be one of the following values: 1036 * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) 1037 * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) 1038 */ 1039 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void) 1040 { 1041 return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC)); 1042 } 1043 #endif /*SYSCFG_CCCSR_CS_MMC*/ 1044 1045 /** 1046 * @brief Get I/O compensation cell value for PMOS transistors 1047 * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue 1048 * @retval Returned value is the I/O compensation cell value for PMOS transistors 1049 */ 1050 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void) 1051 { 1052 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV)); 1053 } 1054 1055 /** 1056 * @brief Get I/O compensation cell value for NMOS transistors 1057 * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue 1058 * @retval Returned value is the I/O compensation cell value for NMOS transistors 1059 */ 1060 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void) 1061 { 1062 return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV)); 1063 } 1064 1065 /** 1066 * @brief Set I/O compensation cell code for PMOS transistors 1067 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode 1068 * @param PMOSCode PMOS compensation code 1069 * This code is applied to the I/O compensation cell when the CS bit of the 1070 * SYSCFG_CMPCR is set 1071 * @retval None 1072 */ 1073 __STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode) 1074 { 1075 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode); 1076 } 1077 1078 /** 1079 * @brief Get I/O compensation cell code for PMOS transistors 1080 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode 1081 * @retval Returned value is the I/O compensation cell code for PMOS transistors 1082 */ 1083 __STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void) 1084 { 1085 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC)); 1086 } 1087 1088 #ifdef SYSCFG_CCCR_PCC_MMC 1089 1090 /** 1091 * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail 1092 * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode 1093 * @param PMOSCode PMOS compensation code 1094 * This code is applied to the I/O compensation cell when the CS bit of the 1095 * SYSCFG_CMPCR is set 1096 * @retval None 1097 */ 1098 __STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode) 1099 { 1100 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode); 1101 } 1102 1103 /** 1104 * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail 1105 * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode 1106 * @retval Returned value is the I/O compensation cell code for PMOS transistors 1107 */ 1108 __STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void) 1109 { 1110 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC)); 1111 } 1112 #endif /* SYSCFG_CCCR_PCC_MMC */ 1113 1114 /** 1115 * @brief Set I/O compensation cell code for NMOS transistors 1116 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode 1117 * @param NMOSCode NMOS compensation code 1118 * This code is applied to the I/O compensation cell when the CS bit of the 1119 * SYSCFG_CMPCR is set 1120 * @retval None 1121 */ 1122 __STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode) 1123 { 1124 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode); 1125 } 1126 1127 /** 1128 * @brief Get I/O compensation cell code for NMOS transistors 1129 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode 1130 * @retval Returned value is the I/O compensation cell code for NMOS transistors 1131 */ 1132 __STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void) 1133 { 1134 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC)); 1135 } 1136 1137 #ifdef SYSCFG_CCCR_NCC_MMC 1138 1139 /** 1140 * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail. 1141 * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode 1142 * @param NMOSCode: NMOS compensation code 1143 * This code is applied to the I/O compensation cell when the CS bit of the 1144 * SYSCFG_CMPCR is set 1145 * @retval None 1146 */ 1147 __STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode) 1148 { 1149 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode); 1150 } 1151 1152 /** 1153 * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail. 1154 * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode 1155 * @retval Returned value is the I/O compensation cell code for NMOS transistors 1156 */ 1157 __STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void) 1158 { 1159 return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC)); 1160 } 1161 #endif /*SYSCFG_CCCR_NCC_MMC*/ 1162 1163 #ifdef SYSCFG_PKGR_PKG 1164 /** 1165 * @brief Get the device package 1166 * @rmtoll PKGR PKG LL_SYSCFG_GetPackage 1167 * @retval Returned value can be one of the following values: 1168 * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*) 1169 * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*) 1170 * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*) 1171 * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*) 1172 * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*) 1173 * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*) 1174 * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**) 1175 * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**) 1176 * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**) 1177 * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**) 1178 * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**) 1179 * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**) 1180 * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**) 1181 * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**) 1182 * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**) 1183 * 1184 * (*) : For stm32h74xxx and stm32h75xxx family lines. 1185 * (**): For stm32h72xxx and stm32h73xxx family lines. 1186 */ 1187 __STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void) 1188 { 1189 return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG)); 1190 } 1191 #endif /*SYSCFG_PKGR_PKG*/ 1192 1193 #ifdef SYSCFG_UR0_RDP 1194 /** 1195 * @brief Get the Flash memory protection level 1196 * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel 1197 * @retval Returned value can be one of the following values: 1198 * 0xAA : RDP level 0 1199 * 0xCC : RDP level 2 1200 * Any other value : RDP level 1 1201 */ 1202 __STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void) 1203 { 1204 return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP)); 1205 } 1206 #ifdef SYSCFG_UR0_BKS 1207 /** 1208 * @brief Indicate if the Flash memory bank addresses are inverted or not 1209 * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped 1210 * @retval State of bit (1 or 0). 1211 */ 1212 __STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void) 1213 { 1214 return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL); 1215 } 1216 #endif /*SYSCFG_UR0_BKS*/ 1217 1218 /** 1219 * @brief Get the BOR Threshold Reset Level 1220 * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel 1221 * @retval Returned value can be one of the following values: 1222 * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL 1223 * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL 1224 * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL 1225 * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL 1226 */ 1227 __STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void) 1228 { 1229 return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH)); 1230 } 1231 /** 1232 * @brief BootCM7 address 0 configuration 1233 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0 1234 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 1235 * @retval None 1236 */ 1237 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress) 1238 { 1239 /* Configure CM7 BOOT ADD0 */ 1240 #if defined(DUAL_CORE) 1241 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos)); 1242 #else 1243 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos)); 1244 #endif /*DUAL_CORE*/ 1245 1246 } 1247 1248 /** 1249 * @brief Get BootCM7 address 0 1250 * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0 1251 * @retval Returned the CM7 Boot Address0 1252 */ 1253 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void) 1254 { 1255 /* Get CM7 BOOT ADD0 */ 1256 #if defined(DUAL_CORE) 1257 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos); 1258 #else 1259 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos); 1260 #endif /*DUAL_CORE*/ 1261 } 1262 1263 /** 1264 * @brief BootCM7 address 1 configuration 1265 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1 1266 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1 1267 * @retval None 1268 */ 1269 __STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress) 1270 { 1271 /* Configure CM7 BOOT ADD1 */ 1272 #if defined(DUAL_CORE) 1273 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress); 1274 #else 1275 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress); 1276 #endif /*DUAL_CORE*/ 1277 } 1278 1279 /** 1280 * @brief Get BootCM7 address 1 1281 * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1 1282 * @retval Returned the CM7 Boot Address0 1283 */ 1284 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void) 1285 { 1286 /* Get CM7 BOOT ADD0 */ 1287 #if defined(DUAL_CORE) 1288 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1)); 1289 #else 1290 return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1)); 1291 #endif /* DUAL_CORE */ 1292 } 1293 1294 #if defined(DUAL_CORE) 1295 /** 1296 * @brief BootCM4 address 0 configuration 1297 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0 1298 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 1299 * @retval None 1300 */ 1301 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress) 1302 { 1303 /* Configure CM4 BOOT ADD0 */ 1304 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos)); 1305 } 1306 1307 /** 1308 * @brief Get BootCM4 address 0 1309 * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0 1310 * @retval Returned the CM4 Boot Address0 1311 */ 1312 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void) 1313 { 1314 /* Get CM4 BOOT ADD0 */ 1315 return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos); 1316 } 1317 1318 /** 1319 * @brief BootCM4 address 1 configuration 1320 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1 1321 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1 1322 * @retval None 1323 */ 1324 __STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress) 1325 { 1326 /* Configure CM4 BOOT ADD1 */ 1327 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress); 1328 } 1329 1330 /** 1331 * @brief Get BootCM4 address 1 1332 * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1 1333 * @retval Returned the CM4 Boot Address0 1334 */ 1335 __STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void) 1336 { 1337 /* Get CM4 BOOT ADD0 */ 1338 return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1)); 1339 } 1340 #endif /*DUAL_CORE*/ 1341 1342 /** 1343 * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase 1344 * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable 1345 * @retval State of bit (1 or 0). 1346 */ 1347 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void) 1348 { 1349 return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL); 1350 } 1351 1352 /** 1353 * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase 1354 * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable 1355 * @retval State of bit (1 or 0). 1356 */ 1357 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void) 1358 { 1359 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL); 1360 } 1361 1362 /** 1363 * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected 1364 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected 1365 * @retval State of bit (1 or 0). 1366 */ 1367 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void) 1368 { 1369 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); 1370 } 1371 1372 /** 1373 * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected 1374 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected 1375 * @retval State of bit (1 or 0). 1376 */ 1377 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void) 1378 { 1379 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); 1380 } 1381 1382 /** 1383 * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected 1384 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected 1385 * @retval State of bit (1 or 0). 1386 */ 1387 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void) 1388 { 1389 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); 1390 } 1391 1392 /** 1393 * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected 1394 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected 1395 * @retval State of bit (1 or 0). 1396 */ 1397 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void) 1398 { 1399 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); 1400 } 1401 1402 /** 1403 * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected 1404 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected 1405 * @retval State of bit (1 or 0). 1406 */ 1407 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void) 1408 { 1409 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); 1410 } 1411 1412 /** 1413 * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected 1414 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected 1415 * @retval State of bit (1 or 0). 1416 */ 1417 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void) 1418 { 1419 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); 1420 } 1421 1422 /** 1423 * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected 1424 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected 1425 * @retval State of bit (1 or 0). 1426 */ 1427 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void) 1428 { 1429 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); 1430 } 1431 1432 /** 1433 * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected 1434 * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected 1435 * @retval State of bit (1 or 0). 1436 */ 1437 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void) 1438 { 1439 return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); 1440 } 1441 1442 /** 1443 * @brief Get the protected area start address for Flash bank 1 1444 * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress 1445 * @retval Returned the protected area start address for Flash bank 1 1446 */ 1447 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void) 1448 { 1449 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1)); 1450 } 1451 1452 /** 1453 * @brief Get the protected area end address for Flash bank 1 1454 * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress 1455 * @retval Returned the protected area end address for Flash bank 1 1456 */ 1457 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void) 1458 { 1459 return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1)); 1460 } 1461 1462 /** 1463 * @brief Get the secured area start address for Flash bank 1 1464 * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress 1465 * @retval Returned the secured area start address for Flash bank 1 1466 */ 1467 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void) 1468 { 1469 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1)); 1470 } 1471 1472 /** 1473 * @brief Get the secured area end address for Flash bank 1 1474 * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress 1475 * @retval Returned the secured area end address for Flash bank 1 1476 */ 1477 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void) 1478 { 1479 return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1)); 1480 } 1481 1482 #ifdef SYSCFG_UR8_MEPAD_BANK2 1483 /** 1484 * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase 1485 * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable 1486 * @retval State of bit (1 or 0). 1487 */ 1488 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void) 1489 { 1490 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL); 1491 } 1492 1493 /** 1494 * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase 1495 * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable 1496 * @retval State of bit (1 or 0). 1497 */ 1498 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void) 1499 { 1500 return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL); 1501 } 1502 #endif /*SYSCFG_UR8_MEPAD_BANK2*/ 1503 1504 #ifdef SYSCFG_UR9_WRPN_BANK2 1505 /** 1506 * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected 1507 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected 1508 * @retval State of bit (1 or 0). 1509 */ 1510 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void) 1511 { 1512 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); 1513 } 1514 1515 /** 1516 * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected 1517 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected 1518 * @retval State of bit (1 or 0). 1519 */ 1520 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void) 1521 { 1522 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); 1523 } 1524 1525 /** 1526 * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected 1527 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected 1528 * @retval State of bit (1 or 0). 1529 */ 1530 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void) 1531 { 1532 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); 1533 } 1534 1535 /** 1536 * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected 1537 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected 1538 * @retval State of bit (1 or 0). 1539 */ 1540 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void) 1541 { 1542 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); 1543 } 1544 1545 /** 1546 * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected 1547 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected 1548 * @retval State of bit (1 or 0). 1549 */ 1550 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void) 1551 { 1552 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); 1553 } 1554 1555 /** 1556 * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected 1557 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected 1558 * @retval State of bit (1 or 0). 1559 */ 1560 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void) 1561 { 1562 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); 1563 } 1564 1565 /** 1566 * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected 1567 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected 1568 * @retval State of bit (1 or 0). 1569 */ 1570 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void) 1571 { 1572 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); 1573 } 1574 1575 /** 1576 * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected 1577 * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected 1578 * @retval State of bit (1 or 0). 1579 */ 1580 __STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void) 1581 { 1582 return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); 1583 } 1584 1585 /** 1586 * @brief Get the protected area start address for Flash bank 2 1587 * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress 1588 * @retval Returned the protected area start address for Flash bank 2 1589 */ 1590 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void) 1591 { 1592 return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2)); 1593 } 1594 #endif /*SYSCFG_UR9_WRPN_BANK2*/ 1595 1596 #ifdef SYSCFG_UR10_PAEND_BANK2 1597 /** 1598 * @brief Get the protected area end address for Flash bank 2 1599 * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress 1600 * @retval Returned the protected area end address for Flash bank 2 1601 */ 1602 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void) 1603 { 1604 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2)); 1605 } 1606 1607 /** 1608 * @brief Get the secured area start address for Flash bank 2 1609 * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress 1610 * @retval Returned the secured area start address for Flash bank 2 1611 */ 1612 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void) 1613 { 1614 return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2)); 1615 } 1616 #endif /*SYSCFG_UR10_PAEND_BANK2*/ 1617 1618 #ifdef SYSCFG_UR11_SAEND_BANK2 1619 /** 1620 * @brief Get the secured area end address for Flash bank 2 1621 * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress 1622 * @retval Returned the secured area end address for Flash bank 2 1623 */ 1624 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void) 1625 { 1626 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2)); 1627 } 1628 #endif /*SYSCFG_UR11_SAEND_BANK2*/ 1629 1630 /** 1631 * @brief Get the Independent Watchdog 1 control mode (Software or Hardware) 1632 * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode 1633 * @retval Returned value can be one of the following values: 1634 * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE 1635 * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE 1636 */ 1637 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void) 1638 { 1639 return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M)); 1640 } 1641 1642 #if defined (DUAL_CORE) 1643 /** 1644 * @brief Get the Independent Watchdog 2 control mode (Software or Hardware) 1645 * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode 1646 * @retval Returned value can be one of the following values: 1647 * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE 1648 * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE 1649 */ 1650 __STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void) 1651 { 1652 return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M)); 1653 } 1654 #endif /* DUAL_CORE */ 1655 1656 /** 1657 * @brief Indicates the Secure mode status 1658 * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled 1659 * @retval State of bit (1 or 0). 1660 */ 1661 __STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void) 1662 { 1663 return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL); 1664 } 1665 1666 /** 1667 * @brief Indicates if a reset is generated when D1 domain enters DStandby mode 1668 * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset 1669 * @retval State of bit (1 or 0). 1670 */ 1671 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void) 1672 { 1673 return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL); 1674 } 1675 1676 /** 1677 * @brief Get the secured DTCM RAM size 1678 * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize 1679 * @retval Returned value can be one of the following values: 1680 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB 1681 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB 1682 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB 1683 * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB 1684 */ 1685 __STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void) 1686 { 1687 return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS)); 1688 } 1689 1690 /** 1691 * @brief Indicates if a reset is generated when D1 domain enters DStop mode 1692 * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset 1693 * @retval State of bit (1 or 0). 1694 */ 1695 __STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void) 1696 { 1697 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL); 1698 } 1699 1700 #if defined (DUAL_CORE) 1701 /** 1702 * @brief Indicates if a reset is generated when D2 domain enters DStandby mode 1703 * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset 1704 * @retval State of bit (1 or 0). 1705 */ 1706 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void) 1707 { 1708 return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL); 1709 } 1710 1711 /** 1712 * @brief Indicates if a reset is generated when D2 domain enters DStop mode 1713 * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset 1714 * @retval State of bit (1 or 0). 1715 */ 1716 __STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void) 1717 { 1718 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL); 1719 } 1720 #endif /* DUAL_CORE */ 1721 1722 /** 1723 * @brief Indicates if the independent watchdog is frozen in Standby mode 1724 * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode 1725 * @retval State of bit (1 or 0). 1726 */ 1727 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void) 1728 { 1729 return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL); 1730 } 1731 1732 /** 1733 * @brief Indicates if the independent watchdog is frozen in Stop mode 1734 * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode 1735 * @retval State of bit (1 or 0). 1736 */ 1737 __STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void) 1738 { 1739 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL); 1740 } 1741 1742 /** 1743 * @brief Indicates if the device private key is programmed 1744 * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed 1745 * @retval State of bit (1 or 0). 1746 */ 1747 __STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void) 1748 { 1749 return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL); 1750 } 1751 1752 /** 1753 * @brief Indicates if the Product is working on the full voltage range or not 1754 * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV 1755 * @note When the IOHSLV option bit is set the Product is working below 2.7 V. 1756 * When the IOHSLV option bit is reset the Product is working on the 1757 * full voltage range. 1758 * @retval State of bit (1 or 0). 1759 */ 1760 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) 1761 { 1762 return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL); 1763 } 1764 1765 #ifdef SYSCFG_UR17_TCM_AXI_CFG 1766 /** 1767 * @brief Get the size of ITCM-RAM and AXI-SRAM 1768 * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size 1769 * @retval Returned value can be one of the following values: 1770 * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB 1771 * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB 1772 * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB 1773 * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB 1774 */ 1775 __STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void) 1776 { 1777 return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG)); 1778 } 1779 #endif /*SYSCFG_UR17_TCM_AXI_CFG*/ 1780 1781 #ifdef SYSCFG_UR18_CPU_FREQ_BOOST 1782 /** 1783 * @brief Indicates if the CPU maximum frequency boost is enabled 1784 * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled 1785 * @retval State of bit (1 or 0). 1786 */ 1787 __STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void) 1788 { 1789 return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL); 1790 } 1791 #endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/ 1792 1793 #endif /*SYSCFG_UR0_RDP*/ 1794 1795 /** 1796 * @} 1797 */ 1798 1799 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 1800 * @ingroup RTEMSBSPsARMSTM32H7 1801 * @{ 1802 */ 1803 1804 /** 1805 * @brief Return the device identifier 1806 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 1807 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF 1808 */ 1809 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 1810 { 1811 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 1812 } 1813 1814 /** 1815 * @brief Return the device revision identifier 1816 * @note This field indicates the revision of the device. 1817 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 1818 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 1819 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF 1820 */ 1821 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 1822 { 1823 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 1824 } 1825 1826 /** 1827 * @brief Enable D1 Domain/CDomain debug during SLEEP mode 1828 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode 1829 * @retval None 1830 */ 1831 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void) 1832 { 1833 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); 1834 } 1835 1836 /** 1837 * @brief Disable D1 Domain/CDomain debug during SLEEP mode 1838 * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode 1839 * @retval None 1840 */ 1841 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void) 1842 { 1843 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); 1844 } 1845 1846 /** 1847 * @brief Enable D1 Domain/CDomain debug during STOP mode 1848 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode 1849 * @retval None 1850 */ 1851 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void) 1852 { 1853 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); 1854 } 1855 1856 /** 1857 * @brief Disable D1 Domain/CDomain debug during STOP mode 1858 * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode 1859 * @retval None 1860 */ 1861 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void) 1862 { 1863 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); 1864 } 1865 1866 /** 1867 * @brief Enable D1 Domain/CDomain debug during STANDBY mode 1868 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode 1869 * @retval None 1870 */ 1871 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void) 1872 { 1873 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); 1874 } 1875 1876 /** 1877 * @brief Disable D1 Domain/CDomain debug during STANDBY mode 1878 * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode 1879 * @retval None 1880 */ 1881 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void) 1882 { 1883 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); 1884 } 1885 1886 #if defined (DUAL_CORE) 1887 /** 1888 * @brief Enable D2 Domain debug during SLEEP mode 1889 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode 1890 * @retval None 1891 */ 1892 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void) 1893 { 1894 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); 1895 } 1896 1897 /** 1898 * @brief Disable D2 Domain debug during SLEEP mode 1899 * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode 1900 * @retval None 1901 */ 1902 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void) 1903 { 1904 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); 1905 } 1906 1907 /** 1908 * @brief Enable D2 Domain debug during STOP mode 1909 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode 1910 * @retval None 1911 */ 1912 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void) 1913 { 1914 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); 1915 } 1916 1917 /** 1918 * @brief Disable D2 Domain debug during STOP mode 1919 * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode 1920 * @retval None 1921 */ 1922 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void) 1923 { 1924 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); 1925 } 1926 1927 /** 1928 * @brief Enable D2 Domain debug during STANDBY mode 1929 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode 1930 * @retval None 1931 */ 1932 __STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void) 1933 { 1934 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); 1935 } 1936 1937 /** 1938 * @brief Disable D2 Domain debug during STANDBY mode 1939 * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode 1940 * @retval None 1941 */ 1942 __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) 1943 { 1944 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); 1945 } 1946 #endif /* DUAL_CORE */ 1947 1948 1949 #if defined(DBGMCU_CR_DBG_STOPD3) 1950 /** 1951 * @brief Enable D3 Domain/SRDomain debug during STOP mode 1952 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode 1953 * @retval None 1954 */ 1955 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void) 1956 { 1957 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); 1958 } 1959 1960 /** 1961 * @brief Disable D3 Domain/SRDomain debug during STOP mode 1962 * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode 1963 * @retval None 1964 */ 1965 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) 1966 { 1967 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); 1968 } 1969 #endif /*DBGMCU_CR_DBG_STOPD3*/ 1970 1971 #if defined(DBGMCU_CR_DBG_STANDBYD3) 1972 /** 1973 * @brief Enable D3 Domain/SRDomain debug during STANDBY mode 1974 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode 1975 * @retval None 1976 */ 1977 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void) 1978 { 1979 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); 1980 } 1981 1982 /** 1983 * @brief Disable D3 Domain/SRDomain debug during STANDBY mode 1984 * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode 1985 * @retval None 1986 */ 1987 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) 1988 { 1989 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); 1990 } 1991 #endif /*DBGMCU_CR_DBG_STANDBYD3*/ 1992 1993 /** 1994 * @brief Enable the trace port clock 1995 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock 1996 * @retval None 1997 */ 1998 __STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void) 1999 { 2000 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); 2001 } 2002 2003 /** 2004 * @brief Disable the trace port clock 2005 * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock 2006 * @retval None 2007 */ 2008 __STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void) 2009 { 2010 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); 2011 } 2012 2013 /** 2014 * @brief Enable the Domain1/CDomain debug clock enable 2015 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock 2016 * @retval None 2017 */ 2018 __STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void) 2019 { 2020 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); 2021 } 2022 2023 /** 2024 * @brief Disable the Domain1/CDomain debug clock enable 2025 * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock 2026 * @retval None 2027 */ 2028 __STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void) 2029 { 2030 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); 2031 } 2032 2033 /** 2034 * @brief Enable the Domain3/SRDomain debug clock enable 2035 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock 2036 * @retval None 2037 */ 2038 __STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void) 2039 { 2040 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); 2041 } 2042 2043 /** 2044 * @brief Disable the Domain3/SRDomain debug clock enable 2045 * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock 2046 * @retval None 2047 */ 2048 __STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void) 2049 { 2050 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); 2051 } 2052 2053 #define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U 2054 #define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN 2055 /** 2056 * @brief Set the direction of the bi-directional trigger pin TRGIO 2057 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n 2058 * @param PinDirection This parameter can be one of the following values: 2059 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION 2060 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION 2061 * @retval None 2062 */ 2063 __STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection) 2064 { 2065 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection); 2066 } 2067 2068 /** 2069 * @brief Get the direction of the bi-directional trigger pin TRGIO 2070 * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n 2071 * @retval Returned value can be one of the following values: 2072 * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION 2073 * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION 2074 */ 2075 __STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void) 2076 { 2077 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN)); 2078 } 2079 2080 /** 2081 * @brief Freeze APB1 group1 peripherals 2082 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2083 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2084 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2085 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2086 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2087 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2088 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2089 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2090 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2091 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2092 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2093 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2094 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2095 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*) 2096 * @param Periphs This parameter can be a combination of the following values: 2097 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 2098 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 2099 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 2100 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 2101 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 2102 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 2103 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 2104 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 2105 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 2106 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 2107 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 2108 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP 2109 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 2110 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) 2111 * 2112 * (*) value not defined in all devices 2113 * @retval None 2114 */ 2115 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) 2116 { 2117 SET_BIT(DBGMCU->APB1LFZ1, Periphs); 2118 } 2119 2120 /** 2121 * @brief Unfreeze APB1 peripherals (group1 peripherals) 2122 * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2123 * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2124 * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2125 * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2126 * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2127 * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2128 * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2129 * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2130 * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2131 * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2132 * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2133 * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2134 * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2135 * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n 2136 * @param Periphs This parameter can be a combination of the following values: 2137 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 2138 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 2139 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 2140 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 2141 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 2142 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 2143 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 2144 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 2145 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 2146 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP 2147 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 2148 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP 2149 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP 2150 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) 2151 * 2152 * (*) value not defined in all devices 2153 * @retval None 2154 */ 2155 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) 2156 { 2157 CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); 2158 } 2159 2160 #ifdef DBGMCU_APB1HFZ1_DBG_FDCAN 2161 /** 2162 * @brief Freeze APB1 group2 peripherals 2163 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n 2164 * @param Periphs This parameter can be a combination of the following values: 2165 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP 2166 * @retval None 2167 */ 2168 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) 2169 { 2170 SET_BIT(DBGMCU->APB1HFZ1, Periphs); 2171 } 2172 2173 /** 2174 * @brief Unfreeze APB1 group2 peripherals 2175 * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 2176 * @param Periphs This parameter can be a combination of the following values: 2177 * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP 2178 * @retval None 2179 */ 2180 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) 2181 { 2182 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); 2183 } 2184 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 2185 2186 #if defined(TIM23) || defined(TIM24) 2187 /** 2188 * @brief Freeze APB1 group2 peripherals 2189 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n 2190 * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n 2191 * @param Periphs This parameter can be a combination of the following values: 2192 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP 2193 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP 2194 * @retval None 2195 */ 2196 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) 2197 { 2198 SET_BIT(DBGMCU->APB1HFZ1, Periphs); 2199 } 2200 2201 /** 2202 * @brief Unfreeze APB1 group2 peripherals 2203 * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 2204 DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n 2205 * @param Periphs This parameter can be a combination of the following values: 2206 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP 2207 * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP 2208 * @retval None 2209 */ 2210 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) 2211 { 2212 CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); 2213 } 2214 #endif /* TIM23 || TIM24 */ 2215 2216 /** 2217 * @brief Freeze APB2 peripherals 2218 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2219 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2220 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2221 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2222 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph 2223 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph 2224 * @param Periphs This parameter can be a combination of the following values: 2225 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 2226 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP 2227 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 2228 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 2229 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP 2230 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) 2231 * 2232 * (*) value not defined in all devices 2233 * @retval None 2234 */ 2235 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) 2236 { 2237 SET_BIT(DBGMCU->APB2FZ1, Periphs); 2238 } 2239 2240 /** 2241 * @brief Unfreeze APB2 peripherals 2242 * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2243 * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2244 * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2245 * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n 2246 * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph 2247 * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph 2248 * @param Periphs This parameter can be a combination of the following values: 2249 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 2250 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP 2251 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP 2252 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP 2253 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP 2254 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) 2255 * 2256 * (*) value not defined in all devices 2257 * @retval None 2258 */ 2259 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) 2260 { 2261 CLEAR_BIT(DBGMCU->APB2FZ1, Periphs); 2262 } 2263 2264 /** 2265 * @brief Freeze APB3 peripherals 2266 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n 2267 * @param Periphs This parameter can be a combination of the following values: 2268 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP 2269 * @retval None 2270 */ 2271 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) 2272 { 2273 SET_BIT(DBGMCU->APB3FZ1, Periphs); 2274 } 2275 2276 /** 2277 * @brief Unfreeze APB3 peripherals 2278 * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n 2279 * @param Periphs This parameter can be a combination of the following values: 2280 * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP 2281 * @retval None 2282 */ 2283 __STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) 2284 { 2285 CLEAR_BIT(DBGMCU->APB3FZ1, Periphs); 2286 } 2287 2288 /** 2289 * @brief Freeze APB4 peripherals 2290 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2291 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2292 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2293 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2294 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2295 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2296 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2297 * @param Periphs This parameter can be a combination of the following values: 2298 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP 2299 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP 2300 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP 2301 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) 2302 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) 2303 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP 2304 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP 2305 * 2306 * (*) value not defined in all devices 2307 * @retval None 2308 */ 2309 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) 2310 { 2311 SET_BIT(DBGMCU->APB4FZ1, Periphs); 2312 } 2313 2314 /** 2315 * @brief Unfreeze APB4 peripherals 2316 * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2317 * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2318 * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2319 * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2320 * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2321 * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2322 * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n 2323 * @param Periphs This parameter can be a combination of the following values: 2324 * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP 2325 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP 2326 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP 2327 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) 2328 * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) 2329 * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP 2330 * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP 2331 * 2332 * (*) value not defined in all devices 2333 * @retval None 2334 */ 2335 __STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) 2336 { 2337 CLEAR_BIT(DBGMCU->APB4FZ1, Periphs); 2338 } 2339 /** 2340 * @} 2341 */ 2342 2343 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 2344 * @ingroup RTEMSBSPsARMSTM32H7 2345 * @{ 2346 */ 2347 2348 /** 2349 * @brief Set FLASH Latency 2350 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 2351 * @param Latency This parameter can be one of the following values: 2352 * @arg @ref LL_FLASH_LATENCY_0 2353 * @arg @ref LL_FLASH_LATENCY_1 2354 * @arg @ref LL_FLASH_LATENCY_2 2355 * @arg @ref LL_FLASH_LATENCY_3 2356 * @arg @ref LL_FLASH_LATENCY_4 2357 * @arg @ref LL_FLASH_LATENCY_5 2358 * @arg @ref LL_FLASH_LATENCY_6 2359 * @arg @ref LL_FLASH_LATENCY_7 2360 * @retval None 2361 */ 2362 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 2363 { 2364 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 2365 } 2366 2367 /** 2368 * @brief Get FLASH Latency 2369 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 2370 * @retval Returned value can be one of the following values: 2371 * @arg @ref LL_FLASH_LATENCY_0 2372 * @arg @ref LL_FLASH_LATENCY_1 2373 * @arg @ref LL_FLASH_LATENCY_2 2374 * @arg @ref LL_FLASH_LATENCY_3 2375 * @arg @ref LL_FLASH_LATENCY_4 2376 * @arg @ref LL_FLASH_LATENCY_5 2377 * @arg @ref LL_FLASH_LATENCY_6 2378 * @arg @ref LL_FLASH_LATENCY_7 2379 */ 2380 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 2381 { 2382 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 2383 } 2384 2385 /** 2386 * @} 2387 */ 2388 2389 #if defined(DUAL_CORE) 2390 /** @defgroup SYSTEM_LL_EF_ART ART 2391 * @ingroup RTEMSBSPsARMSTM32H7 2392 * @{ 2393 */ 2394 2395 /** 2396 * @brief Enable the Cortex-M4 ART cache. 2397 * @rmtoll ART_CTR EN LL_ART_Enable 2398 * @retval None 2399 */ 2400 __STATIC_INLINE void LL_ART_Enable(void) 2401 { 2402 SET_BIT(ART->CTR, ART_CTR_EN); 2403 } 2404 2405 /** 2406 * @brief Disable the Cortex-M4 ART cache. 2407 * @rmtoll ART_CTR EN LL_ART_Disable 2408 * @retval None 2409 */ 2410 __STATIC_INLINE void LL_ART_Disable(void) 2411 { 2412 CLEAR_BIT(ART->CTR, ART_CTR_EN); 2413 } 2414 2415 /** 2416 * @brief Check if the Cortex-M4 ART cache is enabled 2417 * @rmtoll ART_CTR EN LL_ART_IsEnabled 2418 * @retval State of bit (1 or 0). 2419 */ 2420 __STATIC_INLINE uint32_t LL_ART_IsEnabled(void) 2421 { 2422 return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); 2423 } 2424 2425 /** 2426 * @brief Set the Cortex-M4 ART cache Base Address. 2427 * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress 2428 * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) 2429 from which the ART accelerator loads code to the cache. 2430 * @retval None 2431 */ 2432 __STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) 2433 { 2434 MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); 2435 } 2436 2437 /** 2438 * @brief Get the Cortex-M4 ART cache Base Address. 2439 * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress 2440 * @retval the Base address of 1 Mbyte address page (cacheable page) 2441 from which the ART accelerator loads code to the cache 2442 */ 2443 __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) 2444 { 2445 return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); 2446 } 2447 #endif /* DUAL_CORE */ 2448 2449 /** 2450 * @} 2451 */ 2452 2453 /** 2454 * @} 2455 */ 2456 2457 /** 2458 * @} 2459 */ 2460 2461 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ 2462 2463 /** 2464 * @} 2465 */ 2466 2467 #ifdef __cplusplus 2468 } 2469 #endif 2470 2471 #endif /* __STM32H7xx_LL_SYSTEM_H */ 2472
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