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File indexing completed on 2025-05-11 08:23:38
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_swpmi.h 0004 * @author MCD Application Team 0005 * @brief Header file of SWPMI LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_SWPMI_H 0021 #define STM32H7xx_LL_SWPMI_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 0035 /** @defgroup SWPMI_LL SWPMI 0036 * @ingroup RTEMSBSPsARMSTM32H7 0037 * @{ 0038 */ 0039 0040 /* Private types -------------------------------------------------------------*/ 0041 /* Private variables ---------------------------------------------------------*/ 0042 /* Private constants ---------------------------------------------------------*/ 0043 /* Private macros ------------------------------------------------------------*/ 0044 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0045 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros 0046 * @ingroup RTEMSBSPsARMSTM32H7 0047 * @{ 0048 */ 0049 /** 0050 * @} 0051 */ 0052 #endif /*USE_FULL_LL_DRIVER*/ 0053 0054 /* Exported types ------------------------------------------------------------*/ 0055 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0056 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure 0057 * @ingroup RTEMSBSPsARMSTM32H7 0058 * @{ 0059 */ 0060 0061 /** 0062 * @brief SWPMI Init structures definition 0063 */ 0064 typedef struct 0065 { 0066 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. 0067 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS 0068 0069 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ 0070 0071 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. 0072 This parameter must be a number between Min_Data=0 and Max_Data=255U. 0073 0074 The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER 0075 0076 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ 0077 0078 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. 0079 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX 0080 0081 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ 0082 0083 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. 0084 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX 0085 0086 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ 0087 } LL_SWPMI_InitTypeDef; 0088 0089 /** 0090 * @} 0091 */ 0092 #endif /* USE_FULL_LL_DRIVER */ 0093 0094 /* Exported constants --------------------------------------------------------*/ 0095 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants 0096 * @ingroup RTEMSBSPsARMSTM32H7 0097 * @{ 0098 */ 0099 0100 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines 0101 * @ingroup RTEMSBSPsARMSTM32H7 0102 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function 0103 * @{ 0104 */ 0105 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */ 0106 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */ 0107 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */ 0108 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */ 0109 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */ 0110 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */ 0111 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */ 0112 /** 0113 * @} 0114 */ 0115 0116 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines 0117 * @ingroup RTEMSBSPsARMSTM32H7 0118 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function 0119 * @{ 0120 */ 0121 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */ 0122 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */ 0123 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */ 0124 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */ 0125 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */ 0126 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */ 0127 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */ 0128 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */ 0129 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */ 0130 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */ 0131 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */ 0132 /** 0133 * @} 0134 */ 0135 0136 /** @defgroup SWPMI_LL_EC_IT IT Defines 0137 * @ingroup RTEMSBSPsARMSTM32H7 0138 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions 0139 * @{ 0140 */ 0141 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */ 0142 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */ 0143 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */ 0144 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */ 0145 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */ 0146 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */ 0147 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */ 0148 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */ 0149 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */ 0150 /** 0151 * @} 0152 */ 0153 0154 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX 0155 * @ingroup RTEMSBSPsARMSTM32H7 0156 * @{ 0157 */ 0158 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */ 0159 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */ 0160 /** 0161 * @} 0162 */ 0163 0164 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX 0165 * @ingroup RTEMSBSPsARMSTM32H7 0166 * @{ 0167 */ 0168 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */ 0169 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */ 0170 /** 0171 * @} 0172 */ 0173 0174 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS 0175 * @ingroup RTEMSBSPsARMSTM32H7 0176 * @{ 0177 */ 0178 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */ 0179 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */ 0180 /** 0181 * @} 0182 */ 0183 0184 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data 0185 * @ingroup RTEMSBSPsARMSTM32H7 0186 * @{ 0187 */ 0188 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */ 0189 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */ 0190 /** 0191 * @} 0192 */ 0193 0194 /** 0195 * @} 0196 */ 0197 0198 /* Exported macro ------------------------------------------------------------*/ 0199 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros 0200 * @ingroup RTEMSBSPsARMSTM32H7 0201 * @{ 0202 */ 0203 0204 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros 0205 * @ingroup RTEMSBSPsARMSTM32H7 0206 * @{ 0207 */ 0208 0209 /** 0210 * @brief Write a value in SWPMI register 0211 * @param __INSTANCE__ SWPMI Instance 0212 * @param __REG__ Register to be written 0213 * @param __VALUE__ Value to be written in the register 0214 * @retval None 0215 */ 0216 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0217 0218 /** 0219 * @brief Read a value in SWPMI register 0220 * @param __INSTANCE__ SWPMI Instance 0221 * @param __REG__ Register to be read 0222 * @retval Register value 0223 */ 0224 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0225 /** 0226 * @} 0227 */ 0228 0229 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros 0230 * @ingroup RTEMSBSPsARMSTM32H7 0231 * @{ 0232 */ 0233 0234 /** 0235 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function) 0236 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000); 0237 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s) 0238 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz) 0239 * @retval Bitrate prescaler (BRR register) 0240 */ 0241 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1)) 0242 0243 /** 0244 * @} 0245 */ 0246 0247 /** 0248 * @} 0249 */ 0250 0251 /* Exported functions --------------------------------------------------------*/ 0252 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions 0253 * @ingroup RTEMSBSPsARMSTM32H7 0254 * @{ 0255 */ 0256 0257 /** @defgroup SWPMI_LL_EF_Configuration Configuration 0258 * @ingroup RTEMSBSPsARMSTM32H7 0259 * @{ 0260 */ 0261 0262 /** 0263 * @brief Set Reception buffering mode 0264 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set. 0265 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode 0266 * @param SWPMIx SWPMI Instance 0267 * @param RxBufferingMode This parameter can be one of the following values: 0268 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE 0269 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI 0270 * @retval None 0271 */ 0272 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode) 0273 { 0274 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode); 0275 } 0276 0277 /** 0278 * @brief Get Reception buffering mode 0279 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode 0280 * @param SWPMIx SWPMI Instance 0281 * @retval Returned value can be one of the following values: 0282 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE 0283 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI 0284 */ 0285 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) 0286 { 0287 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); 0288 } 0289 0290 /** 0291 * @brief Set Transmission buffering mode 0292 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set. 0293 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode 0294 * @param SWPMIx SWPMI Instance 0295 * @param TxBufferingMode This parameter can be one of the following values: 0296 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE 0297 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI 0298 * @retval None 0299 */ 0300 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode) 0301 { 0302 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode); 0303 } 0304 0305 /** 0306 * @brief Get Transmission buffering mode 0307 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode 0308 * @param SWPMIx SWPMI Instance 0309 * @retval Returned value can be one of the following values: 0310 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE 0311 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI 0312 */ 0313 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) 0314 { 0315 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); 0316 } 0317 0318 /** 0319 * @brief Enable loopback mode 0320 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback 0321 * @param SWPMIx SWPMI Instance 0322 * @retval None 0323 */ 0324 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx) 0325 { 0326 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK); 0327 } 0328 0329 /** 0330 * @brief Disable loopback mode 0331 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback 0332 * @param SWPMIx SWPMI Instance 0333 * @retval None 0334 */ 0335 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx) 0336 { 0337 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK); 0338 } 0339 0340 /** 0341 * @brief Enable SWPMI transceiver 0342 * @note SWPMI_IO pin is controlled by SWPMI 0343 * @rmtoll CR SWPEN LL_SWPMI_EnableTransceiver 0344 * @param SWPMIx SWPMI Instance 0345 * @retval None 0346 */ 0347 __STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx) 0348 { 0349 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN); 0350 } 0351 0352 /** 0353 * @brief Disable SWPMI transceiver 0354 * @note SWPMI_IO pin is controlled by GPIO controller 0355 * @rmtoll CR SWPEN LL_SWPMI_DisableTransceiver 0356 * @param SWPMIx SWPMI Instance 0357 * @retval None 0358 */ 0359 __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx) 0360 { 0361 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN); 0362 } 0363 0364 /** 0365 * @brief Check if SWPMI transceiver is enabled 0366 * @rmtoll CR SWPEN LL_SWPMI_IsEnabledTransceiver 0367 * @param SWPMIx SWPMI Instance 0368 * @retval State of bit (1 or 0). 0369 */ 0370 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx) 0371 { 0372 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL); 0373 } 0374 0375 /** 0376 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state) 0377 * @note SWP bus stays in the ACTIVATED state as long as there is a communication 0378 * with the slave, either in transmission or in reception. The SWP bus switches back 0379 * to the SUSPENDED state as soon as there is no more transmission or reception 0380 * activity, after 7 idle bits. 0381 * @rmtoll CR SWPACT LL_SWPMI_Activate 0382 * @param SWPMIx SWPMI Instance 0383 * @retval None 0384 */ 0385 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) 0386 { 0387 /* In order to activate SWP again, the software must clear DEACT bit*/ 0388 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT); 0389 0390 /* Set SWACT bit */ 0391 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); 0392 } 0393 0394 /** 0395 * @brief Check if Single wire protocol bus is in ACTIVATED state. 0396 * @rmtoll CR SWPACT LL_SWPMI_Activate 0397 * @param SWPMIx SWPMI Instance 0398 * @retval State of bit (1 or 0). 0399 */ 0400 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) 0401 { 0402 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); 0403 } 0404 0405 /** 0406 * @brief Deactivate immediately Single wire protocol bus (immediate transition to 0407 * DEACTIVATED state) 0408 * @rmtoll CR SWPACT LL_SWPMI_Deactivate 0409 * @param SWPMIx SWPMI Instance 0410 * @retval None 0411 */ 0412 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx) 0413 { 0414 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); 0415 } 0416 0417 /** 0418 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED 0419 * state if no resume from slave) 0420 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation 0421 * @param SWPMIx SWPMI Instance 0422 * @retval None 0423 */ 0424 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx) 0425 { 0426 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT); 0427 } 0428 0429 /** 0430 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) 0431 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler 0432 * @param SWPMIx SWPMI Instance 0433 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=255U 0434 * @retval None 0435 */ 0436 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler) 0437 { 0438 WRITE_REG(SWPMIx->BRR, BitRatePrescaler); 0439 } 0440 0441 /** 0442 * @brief Get Bitrate prescaler 0443 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler 0444 * @param SWPMIx SWPMI Instance 0445 * @retval A number between Min_Data=0 and Max_Data=255U 0446 */ 0447 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) 0448 { 0449 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); 0450 } 0451 0452 /** 0453 * @brief Set SWP Voltage Class 0454 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass 0455 * @param SWPMIx SWPMI Instance 0456 * @param VoltageClass This parameter can be one of the following values: 0457 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C 0458 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B 0459 * @retval None 0460 */ 0461 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass) 0462 { 0463 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass); 0464 } 0465 0466 /** 0467 * @brief Get SWP Voltage Class 0468 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass 0469 * @param SWPMIx SWPMI Instance 0470 * @retval Returned value can be one of the following values: 0471 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C 0472 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B 0473 */ 0474 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) 0475 { 0476 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); 0477 } 0478 0479 /** 0480 * @} 0481 */ 0482 0483 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management 0484 * @ingroup RTEMSBSPsARMSTM32H7 0485 * @{ 0486 */ 0487 0488 /** 0489 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR. 0490 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF 0491 * @param SWPMIx SWPMI Instance 0492 * @retval State of bit (1 or 0). 0493 */ 0494 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) 0495 { 0496 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); 0497 } 0498 0499 /** 0500 * @brief Check if Frame transmission buffer has been emptied 0501 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE 0502 * @param SWPMIx SWPMI Instance 0503 * @retval State of bit (1 or 0). 0504 */ 0505 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) 0506 { 0507 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); 0508 } 0509 0510 /** 0511 * @brief Check if CRC error in reception has been detected 0512 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER 0513 * @param SWPMIx SWPMI Instance 0514 * @retval State of bit (1 or 0). 0515 */ 0516 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) 0517 { 0518 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); 0519 } 0520 0521 /** 0522 * @brief Check if Overrun in reception has been detected 0523 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR 0524 * @param SWPMIx SWPMI Instance 0525 * @retval State of bit (1 or 0). 0526 */ 0527 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) 0528 { 0529 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); 0530 } 0531 0532 /** 0533 * @brief Check if underrun error in transmission has been detected 0534 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR 0535 * @param SWPMIx SWPMI Instance 0536 * @retval State of bit (1 or 0). 0537 */ 0538 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) 0539 { 0540 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); 0541 } 0542 0543 /** 0544 * @brief Check if Receive data register not empty (it means that Received data is ready 0545 * to be read in the SWPMI_RDR register) 0546 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE 0547 * @param SWPMIx SWPMI Instance 0548 * @retval State of bit (1 or 0). 0549 */ 0550 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) 0551 { 0552 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); 0553 } 0554 0555 /** 0556 * @brief Check if Transmit data register is empty (it means that Data written in transmit 0557 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again) 0558 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE 0559 * @param SWPMIx SWPMI Instance 0560 * @retval State of bit (1 or 0). 0561 */ 0562 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) 0563 { 0564 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); 0565 } 0566 0567 /** 0568 * @brief Check if Both transmission and reception are completed and SWP is switched to 0569 * the SUSPENDED state 0570 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC 0571 * @param SWPMIx SWPMI Instance 0572 * @retval State of bit (1 or 0). 0573 */ 0574 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) 0575 { 0576 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); 0577 } 0578 0579 /** 0580 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED 0581 * state 0582 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR 0583 * @param SWPMIx SWPMI Instance 0584 * @retval State of bit (1 or 0). 0585 */ 0586 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) 0587 { 0588 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); 0589 } 0590 0591 /** 0592 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state 0593 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP 0594 * @param SWPMIx SWPMI Instance 0595 * @retval State of bit (1 or 0). 0596 */ 0597 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) 0598 { 0599 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); 0600 } 0601 0602 /** 0603 * @brief Check if SWP bus is in DEACTIVATED state 0604 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT 0605 * @param SWPMIx SWPMI Instance 0606 * @retval State of bit (1 or 0). 0607 */ 0608 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) 0609 { 0610 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); 0611 } 0612 0613 /** 0614 * @brief Check if SWPMI transceiver is ready 0615 * @rmtoll ISR RDYF LL_SWPMI_IsActiveFlag_RDYF 0616 * @param SWPMIx SWPMI Instance 0617 * @retval State of bit (1 or 0). 0618 */ 0619 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx) 0620 { 0621 return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL); 0622 } 0623 0624 /** 0625 * @brief Clear receive buffer full flag 0626 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF 0627 * @param SWPMIx SWPMI Instance 0628 * @retval None 0629 */ 0630 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx) 0631 { 0632 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF); 0633 } 0634 0635 /** 0636 * @brief Clear transmit buffer empty flag 0637 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE 0638 * @param SWPMIx SWPMI Instance 0639 * @retval None 0640 */ 0641 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx) 0642 { 0643 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF); 0644 } 0645 0646 /** 0647 * @brief Clear receive CRC error flag 0648 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER 0649 * @param SWPMIx SWPMI Instance 0650 * @retval None 0651 */ 0652 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx) 0653 { 0654 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF); 0655 } 0656 0657 /** 0658 * @brief Clear receive overrun error flag 0659 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR 0660 * @param SWPMIx SWPMI Instance 0661 * @retval None 0662 */ 0663 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx) 0664 { 0665 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF); 0666 } 0667 0668 /** 0669 * @brief Clear transmit underrun error flag 0670 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR 0671 * @param SWPMIx SWPMI Instance 0672 * @retval None 0673 */ 0674 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx) 0675 { 0676 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF); 0677 } 0678 0679 /** 0680 * @brief Clear transfer complete flag 0681 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC 0682 * @param SWPMIx SWPMI Instance 0683 * @retval None 0684 */ 0685 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx) 0686 { 0687 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF); 0688 } 0689 0690 /** 0691 * @brief Clear slave resume flag 0692 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR 0693 * @param SWPMIx SWPMI Instance 0694 * @retval None 0695 */ 0696 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx) 0697 { 0698 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF); 0699 } 0700 0701 /** 0702 * @brief Clear SWPMI transceiver ready flag 0703 * @rmtoll ISR CRDYF LL_SWPMI_ClearFlag_RDY 0704 * @param SWPMIx SWPMI Instance 0705 * @retval None 0706 */ 0707 __STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx) 0708 { 0709 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF); 0710 } 0711 0712 /** 0713 * @} 0714 */ 0715 0716 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management 0717 * @ingroup RTEMSBSPsARMSTM32H7 0718 * @{ 0719 */ 0720 0721 /** 0722 * @brief Enable SWPMI transceiver ready interrupt 0723 * @rmtoll IER RDYIE LL_SWPMI_EnableIT_RDY 0724 * @param SWPMIx SWPMI Instance 0725 * @retval None 0726 */ 0727 __STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx) 0728 { 0729 SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE); 0730 } 0731 0732 /** 0733 * @brief Enable Slave resume interrupt 0734 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR 0735 * @param SWPMIx SWPMI Instance 0736 * @retval None 0737 */ 0738 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx) 0739 { 0740 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE); 0741 } 0742 0743 /** 0744 * @brief Enable Transmit complete interrupt 0745 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC 0746 * @param SWPMIx SWPMI Instance 0747 * @retval None 0748 */ 0749 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx) 0750 { 0751 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE); 0752 } 0753 0754 /** 0755 * @brief Enable Transmit interrupt 0756 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX 0757 * @param SWPMIx SWPMI Instance 0758 * @retval None 0759 */ 0760 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx) 0761 { 0762 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE); 0763 } 0764 0765 /** 0766 * @brief Enable Receive interrupt 0767 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX 0768 * @param SWPMIx SWPMI Instance 0769 * @retval None 0770 */ 0771 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx) 0772 { 0773 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE); 0774 } 0775 0776 /** 0777 * @brief Enable Transmit underrun error interrupt 0778 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR 0779 * @param SWPMIx SWPMI Instance 0780 * @retval None 0781 */ 0782 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx) 0783 { 0784 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); 0785 } 0786 0787 /** 0788 * @brief Enable Receive overrun error interrupt 0789 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR 0790 * @param SWPMIx SWPMI Instance 0791 * @retval None 0792 */ 0793 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx) 0794 { 0795 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); 0796 } 0797 0798 /** 0799 * @brief Enable Receive CRC error interrupt 0800 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER 0801 * @param SWPMIx SWPMI Instance 0802 * @retval None 0803 */ 0804 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx) 0805 { 0806 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); 0807 } 0808 0809 /** 0810 * @brief Enable Transmit buffer empty interrupt 0811 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE 0812 * @param SWPMIx SWPMI Instance 0813 * @retval None 0814 */ 0815 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx) 0816 { 0817 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); 0818 } 0819 0820 /** 0821 * @brief Enable Receive buffer full interrupt 0822 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF 0823 * @param SWPMIx SWPMI Instance 0824 * @retval None 0825 */ 0826 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx) 0827 { 0828 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); 0829 } 0830 0831 /** 0832 * @brief Disable SWPMI transceiver ready interrupt 0833 * @rmtoll IER RDYIE LL_SWPMI_DisableIT_RDY 0834 * @param SWPMIx SWPMI Instance 0835 * @retval None 0836 */ 0837 __STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx) 0838 { 0839 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE); 0840 } 0841 0842 /** 0843 * @brief Disable Slave resume interrupt 0844 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR 0845 * @param SWPMIx SWPMI Instance 0846 * @retval None 0847 */ 0848 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx) 0849 { 0850 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE); 0851 } 0852 0853 /** 0854 * @brief Disable Transmit complete interrupt 0855 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC 0856 * @param SWPMIx SWPMI Instance 0857 * @retval None 0858 */ 0859 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx) 0860 { 0861 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE); 0862 } 0863 0864 /** 0865 * @brief Disable Transmit interrupt 0866 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX 0867 * @param SWPMIx SWPMI Instance 0868 * @retval None 0869 */ 0870 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx) 0871 { 0872 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE); 0873 } 0874 0875 /** 0876 * @brief Disable Receive interrupt 0877 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX 0878 * @param SWPMIx SWPMI Instance 0879 * @retval None 0880 */ 0881 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx) 0882 { 0883 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE); 0884 } 0885 0886 /** 0887 * @brief Disable Transmit underrun error interrupt 0888 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR 0889 * @param SWPMIx SWPMI Instance 0890 * @retval None 0891 */ 0892 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx) 0893 { 0894 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); 0895 } 0896 0897 /** 0898 * @brief Disable Receive overrun error interrupt 0899 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR 0900 * @param SWPMIx SWPMI Instance 0901 * @retval None 0902 */ 0903 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx) 0904 { 0905 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); 0906 } 0907 0908 /** 0909 * @brief Disable Receive CRC error interrupt 0910 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER 0911 * @param SWPMIx SWPMI Instance 0912 * @retval None 0913 */ 0914 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx) 0915 { 0916 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); 0917 } 0918 0919 /** 0920 * @brief Disable Transmit buffer empty interrupt 0921 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE 0922 * @param SWPMIx SWPMI Instance 0923 * @retval None 0924 */ 0925 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx) 0926 { 0927 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); 0928 } 0929 0930 /** 0931 * @brief Disable Receive buffer full interrupt 0932 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF 0933 * @param SWPMIx SWPMI Instance 0934 * @retval None 0935 */ 0936 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) 0937 { 0938 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); 0939 } 0940 0941 /** 0942 * @brief Check if SWPMI transceiver ready interrupt is enabled 0943 * @rmtoll IER RDYIE LL_SWPMI_IsEnabledIT_RDY 0944 * @param SWPMIx SWPMI Instance 0945 * @retval State of bit (1 or 0). 0946 */ 0947 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) 0948 { 0949 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL); 0950 } 0951 0952 /** 0953 * @brief Check if Slave resume interrupt is enabled 0954 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR 0955 * @param SWPMIx SWPMI Instance 0956 * @retval State of bit (1 or 0). 0957 */ 0958 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) 0959 { 0960 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); 0961 } 0962 0963 /** 0964 * @brief Check if Transmit complete interrupt is enabled 0965 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC 0966 * @param SWPMIx SWPMI Instance 0967 * @retval State of bit (1 or 0). 0968 */ 0969 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) 0970 { 0971 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); 0972 } 0973 0974 /** 0975 * @brief Check if Transmit interrupt is enabled 0976 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX 0977 * @param SWPMIx SWPMI Instance 0978 * @retval State of bit (1 or 0). 0979 */ 0980 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) 0981 { 0982 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); 0983 } 0984 0985 /** 0986 * @brief Check if Receive interrupt is enabled 0987 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX 0988 * @param SWPMIx SWPMI Instance 0989 * @retval State of bit (1 or 0). 0990 */ 0991 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) 0992 { 0993 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); 0994 } 0995 0996 /** 0997 * @brief Check if Transmit underrun error interrupt is enabled 0998 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR 0999 * @param SWPMIx SWPMI Instance 1000 * @retval State of bit (1 or 0). 1001 */ 1002 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) 1003 { 1004 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); 1005 } 1006 1007 /** 1008 * @brief Check if Receive overrun error interrupt is enabled 1009 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR 1010 * @param SWPMIx SWPMI Instance 1011 * @retval State of bit (1 or 0). 1012 */ 1013 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) 1014 { 1015 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); 1016 } 1017 1018 /** 1019 * @brief Check if Receive CRC error interrupt is enabled 1020 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER 1021 * @param SWPMIx SWPMI Instance 1022 * @retval State of bit (1 or 0). 1023 */ 1024 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) 1025 { 1026 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); 1027 } 1028 1029 /** 1030 * @brief Check if Transmit buffer empty interrupt is enabled 1031 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE 1032 * @param SWPMIx SWPMI Instance 1033 * @retval State of bit (1 or 0). 1034 */ 1035 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) 1036 { 1037 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); 1038 } 1039 1040 /** 1041 * @brief Check if Receive buffer full interrupt is enabled 1042 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF 1043 * @param SWPMIx SWPMI Instance 1044 * @retval State of bit (1 or 0). 1045 */ 1046 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) 1047 { 1048 return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); 1049 } 1050 1051 /** 1052 * @} 1053 */ 1054 1055 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management 1056 * @ingroup RTEMSBSPsARMSTM32H7 1057 * @{ 1058 */ 1059 1060 /** 1061 * @brief Enable DMA mode for reception 1062 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX 1063 * @param SWPMIx SWPMI Instance 1064 * @retval None 1065 */ 1066 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx) 1067 { 1068 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); 1069 } 1070 1071 /** 1072 * @brief Disable DMA mode for reception 1073 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX 1074 * @param SWPMIx SWPMI Instance 1075 * @retval None 1076 */ 1077 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) 1078 { 1079 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); 1080 } 1081 1082 /** 1083 * @brief Check if DMA mode for reception is enabled 1084 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX 1085 * @param SWPMIx SWPMI Instance 1086 * @retval State of bit (1 or 0). 1087 */ 1088 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) 1089 { 1090 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); 1091 } 1092 1093 /** 1094 * @brief Enable DMA mode for transmission 1095 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX 1096 * @param SWPMIx SWPMI Instance 1097 * @retval None 1098 */ 1099 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx) 1100 { 1101 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); 1102 } 1103 1104 /** 1105 * @brief Disable DMA mode for transmission 1106 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX 1107 * @param SWPMIx SWPMI Instance 1108 * @retval None 1109 */ 1110 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) 1111 { 1112 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); 1113 } 1114 1115 /** 1116 * @brief Check if DMA mode for transmission is enabled 1117 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX 1118 * @param SWPMIx SWPMI Instance 1119 * @retval State of bit (1 or 0). 1120 */ 1121 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) 1122 { 1123 return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); 1124 } 1125 1126 /** 1127 * @brief Get the data register address used for DMA transfer 1128 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n 1129 * RDR RD LL_SWPMI_DMA_GetRegAddr 1130 * @param SWPMIx SWPMI Instance 1131 * @param Direction This parameter can be one of the following values: 1132 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT 1133 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE 1134 * @retval Address of data register 1135 */ 1136 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) 1137 { 1138 uint32_t data_reg_addr; 1139 1140 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) 1141 { 1142 /* return address of TDR register */ 1143 data_reg_addr = (uint32_t)&(SWPMIx->TDR); 1144 } 1145 else 1146 { 1147 /* return address of RDR register */ 1148 data_reg_addr = (uint32_t)&(SWPMIx->RDR); 1149 } 1150 1151 return data_reg_addr; 1152 } 1153 1154 /** 1155 * @} 1156 */ 1157 1158 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management 1159 * @ingroup RTEMSBSPsARMSTM32H7 1160 * @{ 1161 */ 1162 1163 /** 1164 * @brief Retrieve number of data bytes present in payload of received frame 1165 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength 1166 * @param SWPMIx SWPMI Instance 1167 * @retval Value between Min_Data=0x00 and Max_Data=0x1F 1168 */ 1169 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) 1170 { 1171 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); 1172 } 1173 1174 /** 1175 * @brief Transmit Data Register 1176 * @rmtoll TDR TD LL_SWPMI_TransmitData32 1177 * @param SWPMIx SWPMI Instance 1178 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 1179 * @retval None 1180 */ 1181 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData) 1182 { 1183 WRITE_REG(SWPMIx->TDR, TxData); 1184 } 1185 1186 /** 1187 * @brief Receive Data Register 1188 * @rmtoll RDR RD LL_SWPMI_ReceiveData32 1189 * @param SWPMIx SWPMI Instance 1190 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 1191 */ 1192 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx) 1193 { 1194 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD)); 1195 } 1196 1197 /** 1198 * @brief Enable SWP Transceiver Bypass 1199 * @note The external interface for SWPMI is SWPMI_IO 1200 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs) 1201 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass 1202 * @param SWPMIx SWPMI Instance 1203 * @retval None 1204 */ 1205 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx) 1206 { 1207 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP); 1208 } 1209 1210 /** 1211 * @brief Disable SWP Transceiver Bypass 1212 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate 1213 * function on GPIOs. This configuration is selected to connect an external transceiver 1214 * @note In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared 1215 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass 1216 * @param SWPMIx SWPMI Instance 1217 * @retval None 1218 */ 1219 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) 1220 { 1221 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP); 1222 } 1223 1224 /** 1225 * @} 1226 */ 1227 1228 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 1229 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions 1230 * @ingroup RTEMSBSPsARMSTM32H7 1231 * @{ 1232 */ 1233 1234 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); 1235 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); 1236 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); 1237 1238 /** 1239 * @} 1240 */ 1241 #endif /*USE_FULL_LL_DRIVER*/ 1242 1243 /** 1244 * @} 1245 */ 1246 1247 /** 1248 * @} 1249 */ 1250 1251 1252 /** 1253 * @} 1254 */ 1255 1256 #ifdef __cplusplus 1257 } 1258 #endif 1259 1260 #endif /* STM32H7xx_LL_SWPMI_H */
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