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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_rng.h 0004 * @author MCD Application Team 0005 * @brief Header file of RNG LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_RNG_H 0021 #define STM32H7xx_LL_RNG_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (RNG) 0035 0036 /** @defgroup RNG_LL RNG 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private defines -----------------------------------------------------------*/ 0043 /** @defgroup RNG_LL_Private_Defines RNG Private Defines 0044 * @ingroup RTEMSBSPsARMSTM32H7 0045 * @{ 0046 */ 0047 /* Health test control register information to use in CCM algorithm */ 0048 #define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */ 0049 /** 0050 * @} 0051 */ 0052 /* Private variables ---------------------------------------------------------*/ 0053 /* Private constants ---------------------------------------------------------*/ 0054 /* Private macros ------------------------------------------------------------*/ 0055 0056 /* Exported types ------------------------------------------------------------*/ 0057 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0058 /** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures 0059 * @ingroup RTEMSBSPsARMSTM32H7 0060 * @{ 0061 */ 0062 0063 0064 /** 0065 * @brief LL RNG Init Structure Definition 0066 */ 0067 typedef struct 0068 { 0069 uint32_t ClockErrorDetection; /*!< Clock error detection. 0070 This parameter can be one value of @ref RNG_LL_CED. 0071 This parameter can be modified using unitary 0072 functions @ref LL_RNG_EnableClkErrorDetect(). */ 0073 } LL_RNG_InitTypeDef; 0074 0075 /** 0076 * @} 0077 */ 0078 #endif /* USE_FULL_LL_DRIVER */ 0079 /* Exported constants --------------------------------------------------------*/ 0080 /** @defgroup RNG_LL_Exported_Constants RNG Exported Constants 0081 * @ingroup RTEMSBSPsARMSTM32H7 0082 * @{ 0083 */ 0084 0085 /** @defgroup RNG_LL_CED Clock Error Detection 0086 * @ingroup RTEMSBSPsARMSTM32H7 0087 * @{ 0088 */ 0089 #define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ 0090 #define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ 0091 /** 0092 * @} 0093 */ 0094 0095 #if defined(RNG_CR_CONDRST) 0096 /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal 0097 * @ingroup RTEMSBSPsARMSTM32H7 0098 * programmable divider acting on the incoming RNG clock 0099 * @{ 0100 */ 0101 #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ 0102 #define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */ 0103 #define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */ 0104 #define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */ 0105 #define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */ 0106 #define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */ 0107 #define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */ 0108 #define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */ 0109 #define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */ 0110 #define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */ 0111 #define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */ 0112 #define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */ 0113 #define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */ 0114 #define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */ 0115 #define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */ 0116 #define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */ 0117 /** 0118 * @} 0119 */ 0120 0121 /** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration 0122 * @ingroup RTEMSBSPsARMSTM32H7 0123 * @{ 0124 */ 0125 #define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ 0126 #define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ 0127 0128 /** 0129 * @} 0130 */ 0131 0132 #endif /* RNG_CR_CONDRST */ 0133 /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines 0134 * @ingroup RTEMSBSPsARMSTM32H7 0135 * @brief Flags defines which can be used with LL_RNG_ReadReg function 0136 * @{ 0137 */ 0138 #define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ 0139 #define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ 0140 #define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ 0141 #define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ 0142 #define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ 0143 /** 0144 * @} 0145 */ 0146 0147 /** @defgroup RNG_LL_EC_IT IT Defines 0148 * @ingroup RTEMSBSPsARMSTM32H7 0149 * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros 0150 * @{ 0151 */ 0152 #define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ 0153 /** 0154 * @} 0155 */ 0156 0157 /** 0158 * @} 0159 */ 0160 0161 /* Exported macro ------------------------------------------------------------*/ 0162 /** @defgroup RNG_LL_Exported_Macros RNG Exported Macros 0163 * @ingroup RTEMSBSPsARMSTM32H7 0164 * @{ 0165 */ 0166 0167 /** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros 0168 * @ingroup RTEMSBSPsARMSTM32H7 0169 * @{ 0170 */ 0171 0172 /** 0173 * @brief Write a value in RNG register 0174 * @param __INSTANCE__ RNG Instance 0175 * @param __REG__ Register to be written 0176 * @param __VALUE__ Value to be written in the register 0177 * @retval None 0178 */ 0179 #define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0180 0181 /** 0182 * @brief Read a value in RNG register 0183 * @param __INSTANCE__ RNG Instance 0184 * @param __REG__ Register to be read 0185 * @retval Register value 0186 */ 0187 #define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0188 /** 0189 * @} 0190 */ 0191 0192 /** 0193 * @} 0194 */ 0195 0196 0197 /* Exported functions --------------------------------------------------------*/ 0198 /** @defgroup RNG_LL_Exported_Functions RNG Exported Functions 0199 * @ingroup RTEMSBSPsARMSTM32H7 0200 * @{ 0201 */ 0202 /** @defgroup RNG_LL_EF_Configuration RNG Configuration functions 0203 * @ingroup RTEMSBSPsARMSTM32H7 0204 * @{ 0205 */ 0206 0207 /** 0208 * @brief Enable Random Number Generation 0209 * @rmtoll CR RNGEN LL_RNG_Enable 0210 * @param RNGx RNG Instance 0211 * @retval None 0212 */ 0213 __STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) 0214 { 0215 SET_BIT(RNGx->CR, RNG_CR_RNGEN); 0216 } 0217 0218 /** 0219 * @brief Disable Random Number Generation 0220 * @rmtoll CR RNGEN LL_RNG_Disable 0221 * @param RNGx RNG Instance 0222 * @retval None 0223 */ 0224 __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) 0225 { 0226 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); 0227 } 0228 0229 /** 0230 * @brief Check if Random Number Generator is enabled 0231 * @rmtoll CR RNGEN LL_RNG_IsEnabled 0232 * @param RNGx RNG Instance 0233 * @retval State of bit (1 or 0). 0234 */ 0235 __STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) 0236 { 0237 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); 0238 } 0239 0240 /** 0241 * @brief Enable Clock Error Detection 0242 * @rmtoll CR CED LL_RNG_EnableClkErrorDetect 0243 * @param RNGx RNG Instance 0244 * @retval None 0245 */ 0246 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) 0247 { 0248 #if defined(RNG_CR_CONDRST) 0249 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); 0250 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0251 #else 0252 CLEAR_BIT(RNGx->CR, RNG_CR_CED); 0253 #endif /* RNG_CR_CONDRST*/ 0254 } 0255 0256 /** 0257 * @brief Disable RNG Clock Error Detection 0258 * @rmtoll CR CED LL_RNG_DisableClkErrorDetect 0259 * @param RNGx RNG Instance 0260 * @retval None 0261 */ 0262 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) 0263 { 0264 #if defined(RNG_CR_CONDRST) 0265 MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); 0266 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0267 #else 0268 SET_BIT(RNGx->CR, RNG_CR_CED); 0269 #endif /* RNG_CR_CONDRST*/ 0270 } 0271 0272 /** 0273 * @brief Check if RNG Clock Error Detection is enabled 0274 * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect 0275 * @param RNGx RNG Instance 0276 * @retval State of bit (1 or 0). 0277 */ 0278 __STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) 0279 { 0280 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); 0281 } 0282 0283 #if defined(RNG_CR_CONDRST) 0284 /** 0285 * @brief Set RNG Conditioning Soft Reset bit 0286 * @rmtoll CR CONDRST LL_RNG_EnableCondReset 0287 * @param RNGx RNG Instance 0288 * @retval None 0289 */ 0290 __STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx) 0291 { 0292 SET_BIT(RNGx->CR, RNG_CR_CONDRST); 0293 } 0294 0295 /** 0296 * @brief Reset RNG Conditioning Soft Reset bit 0297 * @rmtoll CR CONDRST LL_RNG_DisableCondReset 0298 * @param RNGx RNG Instance 0299 * @retval None 0300 */ 0301 __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) 0302 { 0303 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0304 } 0305 0306 /** 0307 * @brief Check if RNG Conditioning Soft Reset bit is set 0308 * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset 0309 * @param RNGx RNG Instance 0310 * @retval State of bit (1 or 0). 0311 */ 0312 __STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) 0313 { 0314 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); 0315 } 0316 0317 /** 0318 * @brief Enable RNG Config Lock 0319 * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock 0320 * @param RNGx RNG Instance 0321 * @retval None 0322 */ 0323 __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) 0324 { 0325 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK); 0326 } 0327 0328 /** 0329 * @brief Check if RNG Config Lock is enabled 0330 * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked 0331 * @param RNGx RNG Instance 0332 * @retval State of bit (1 or 0). 0333 */ 0334 __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) 0335 { 0336 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); 0337 } 0338 0339 /** 0340 * @brief Enable NIST Compliance 0341 * @rmtoll CR NISTC LL_RNG_EnableNistCompliance 0342 * @param RNGx RNG Instance 0343 * @retval None 0344 */ 0345 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) 0346 { 0347 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); 0348 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0349 } 0350 0351 /** 0352 * @brief Disable NIST Compliance 0353 * @rmtoll CR NISTC LL_RNG_DisableNistCompliance 0354 * @param RNGx RNG Instance 0355 * @retval None 0356 */ 0357 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) 0358 { 0359 MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); 0360 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0361 } 0362 0363 /** 0364 * @brief Check if NIST Compliance is enabled 0365 * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance 0366 * @param RNGx RNG Instance 0367 * @retval State of bit (1 or 0). 0368 */ 0369 __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) 0370 { 0371 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); 0372 } 0373 0374 /** 0375 * @brief Set RNG Config1 Configuration field value 0376 * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1 0377 * @param RNGx RNG Instance 0378 * @param Config1 Value between 0 and 0x3F 0379 * @retval None 0380 */ 0381 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) 0382 { 0383 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); 0384 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0385 } 0386 0387 /** 0388 * @brief Get RNG Config1 Configuration field value 0389 * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1 0390 * @param RNGx RNG Instance 0391 * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F 0392 */ 0393 __STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) 0394 { 0395 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); 0396 } 0397 0398 /** 0399 * @brief Set RNG Config2 Configuration field value 0400 * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2 0401 * @param RNGx RNG Instance 0402 * @param Config2 Value between 0 and 0x7 0403 * @retval None 0404 */ 0405 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) 0406 { 0407 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); 0408 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0409 } 0410 0411 /** 0412 * @brief Get RNG Config2 Configuration field value 0413 * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2 0414 * @param RNGx RNG Instance 0415 * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 0416 */ 0417 __STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) 0418 { 0419 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); 0420 } 0421 0422 /** 0423 * @brief Set RNG Config3 Configuration field value 0424 * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3 0425 * @param RNGx RNG Instance 0426 * @param Config3 Value between 0 and 0xF 0427 * @retval None 0428 */ 0429 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) 0430 { 0431 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); 0432 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0433 } 0434 0435 /** 0436 * @brief Get RNG Config3 Configuration field value 0437 * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3 0438 * @param RNGx RNG Instance 0439 * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF 0440 */ 0441 __STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) 0442 { 0443 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); 0444 } 0445 0446 /** 0447 * @brief Set RNG Clock divider factor 0448 * @rmtoll CR CLKDIV LL_RNG_SetClockDivider 0449 * @param RNGx RNG Instance 0450 * @param Divider can be one of the following values: 0451 * @arg @ref LL_RNG_CLKDIV_BY_1 0452 * @arg @ref LL_RNG_CLKDIV_BY_2 0453 * @arg @ref LL_RNG_CLKDIV_BY_4 0454 * @arg @ref LL_RNG_CLKDIV_BY_8 0455 * @arg @ref LL_RNG_CLKDIV_BY_16 0456 * @arg @ref LL_RNG_CLKDIV_BY_32 0457 * @arg @ref LL_RNG_CLKDIV_BY_64 0458 * @arg @ref LL_RNG_CLKDIV_BY_128 0459 * @arg @ref LL_RNG_CLKDIV_BY_256 0460 * @arg @ref LL_RNG_CLKDIV_BY_512 0461 * @arg @ref LL_RNG_CLKDIV_BY_1024 0462 * @arg @ref LL_RNG_CLKDIV_BY_2048 0463 * @arg @ref LL_RNG_CLKDIV_BY_4096 0464 * @arg @ref LL_RNG_CLKDIV_BY_8192 0465 * @arg @ref LL_RNG_CLKDIV_BY_16384 0466 * @arg @ref LL_RNG_CLKDIV_BY_32768 0467 * @retval None 0468 */ 0469 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) 0470 { 0471 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); 0472 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); 0473 } 0474 0475 /** 0476 * @brief Get RNG Clock divider factor 0477 * @rmtoll CR CLKDIV LL_RNG_GetClockDivider 0478 * @param RNGx RNG Instance 0479 * @retval Returned value can be one of the following values: 0480 * @arg @ref LL_RNG_CLKDIV_BY_1 0481 * @arg @ref LL_RNG_CLKDIV_BY_2 0482 * @arg @ref LL_RNG_CLKDIV_BY_4 0483 * @arg @ref LL_RNG_CLKDIV_BY_8 0484 * @arg @ref LL_RNG_CLKDIV_BY_16 0485 * @arg @ref LL_RNG_CLKDIV_BY_32 0486 * @arg @ref LL_RNG_CLKDIV_BY_64 0487 * @arg @ref LL_RNG_CLKDIV_BY_128 0488 * @arg @ref LL_RNG_CLKDIV_BY_256 0489 * @arg @ref LL_RNG_CLKDIV_BY_512 0490 * @arg @ref LL_RNG_CLKDIV_BY_1024 0491 * @arg @ref LL_RNG_CLKDIV_BY_2048 0492 * @arg @ref LL_RNG_CLKDIV_BY_4096 0493 * @arg @ref LL_RNG_CLKDIV_BY_8192 0494 * @arg @ref LL_RNG_CLKDIV_BY_16384 0495 * @arg @ref LL_RNG_CLKDIV_BY_32768 0496 */ 0497 __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) 0498 { 0499 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); 0500 } 0501 #endif /* RNG_CR_CONDRST */ 0502 /** 0503 * @} 0504 */ 0505 0506 /** @defgroup RNG_LL_EF_FLAG_Management FLAG Management 0507 * @ingroup RTEMSBSPsARMSTM32H7 0508 * @{ 0509 */ 0510 0511 /** 0512 * @brief Indicate if the RNG Data ready Flag is set or not 0513 * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY 0514 * @param RNGx RNG Instance 0515 * @retval State of bit (1 or 0). 0516 */ 0517 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) 0518 { 0519 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); 0520 } 0521 0522 /** 0523 * @brief Indicate if the Clock Error Current Status Flag is set or not 0524 * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS 0525 * @param RNGx RNG Instance 0526 * @retval State of bit (1 or 0). 0527 */ 0528 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) 0529 { 0530 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); 0531 } 0532 0533 /** 0534 * @brief Indicate if the Seed Error Current Status Flag is set or not 0535 * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS 0536 * @param RNGx RNG Instance 0537 * @retval State of bit (1 or 0). 0538 */ 0539 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) 0540 { 0541 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); 0542 } 0543 0544 /** 0545 * @brief Indicate if the Clock Error Interrupt Status Flag is set or not 0546 * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS 0547 * @param RNGx RNG Instance 0548 * @retval State of bit (1 or 0). 0549 */ 0550 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) 0551 { 0552 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); 0553 } 0554 0555 /** 0556 * @brief Indicate if the Seed Error Interrupt Status Flag is set or not 0557 * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS 0558 * @param RNGx RNG Instance 0559 * @retval State of bit (1 or 0). 0560 */ 0561 __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) 0562 { 0563 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); 0564 } 0565 0566 /** 0567 * @brief Clear Clock Error interrupt Status (CEIS) Flag 0568 * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS 0569 * @param RNGx RNG Instance 0570 * @retval None 0571 */ 0572 __STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) 0573 { 0574 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); 0575 } 0576 0577 /** 0578 * @brief Clear Seed Error interrupt Status (SEIS) Flag 0579 * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS 0580 * @param RNGx RNG Instance 0581 * @retval None 0582 */ 0583 __STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) 0584 { 0585 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); 0586 } 0587 0588 /** 0589 * @} 0590 */ 0591 0592 /** @defgroup RNG_LL_EF_IT_Management IT Management 0593 * @ingroup RTEMSBSPsARMSTM32H7 0594 * @{ 0595 */ 0596 0597 /** 0598 * @brief Enable Random Number Generator Interrupt 0599 * (applies for either Seed error, Clock Error or Data ready interrupts) 0600 * @rmtoll CR IE LL_RNG_EnableIT 0601 * @param RNGx RNG Instance 0602 * @retval None 0603 */ 0604 __STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) 0605 { 0606 SET_BIT(RNGx->CR, RNG_CR_IE); 0607 } 0608 0609 /** 0610 * @brief Disable Random Number Generator Interrupt 0611 * (applies for either Seed error, Clock Error or Data ready interrupts) 0612 * @rmtoll CR IE LL_RNG_DisableIT 0613 * @param RNGx RNG Instance 0614 * @retval None 0615 */ 0616 __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) 0617 { 0618 CLEAR_BIT(RNGx->CR, RNG_CR_IE); 0619 } 0620 0621 /** 0622 * @brief Check if Random Number Generator Interrupt is enabled 0623 * (applies for either Seed error, Clock Error or Data ready interrupts) 0624 * @rmtoll CR IE LL_RNG_IsEnabledIT 0625 * @param RNGx RNG Instance 0626 * @retval State of bit (1 or 0). 0627 */ 0628 __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) 0629 { 0630 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); 0631 } 0632 0633 /** 0634 * @} 0635 */ 0636 0637 /** @defgroup RNG_LL_EF_Data_Management Data Management 0638 * @ingroup RTEMSBSPsARMSTM32H7 0639 * @{ 0640 */ 0641 0642 /** 0643 * @brief Return32-bit Random Number value 0644 * @rmtoll DR RNDATA LL_RNG_ReadRandData32 0645 * @param RNGx RNG Instance 0646 * @retval Generated 32-bit random value 0647 */ 0648 __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) 0649 { 0650 return (uint32_t)(READ_REG(RNGx->DR)); 0651 } 0652 0653 /** 0654 * @} 0655 */ 0656 0657 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) 0658 /** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control 0659 * @ingroup RTEMSBSPsARMSTM32H7 0660 * @{ 0661 */ 0662 0663 /** 0664 * @brief Set RNG Health Test Control 0665 * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig 0666 * @param RNGx RNG Instance 0667 * @param HTCFG can be values of 32 bits 0668 * @retval None 0669 */ 0670 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) 0671 { 0672 /*!< magic number must be written immediately before to RNG_HTCRG */ 0673 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); 0674 0675 WRITE_REG(RNGx->HTCR, HTCFG); 0676 } 0677 0678 /** 0679 * @brief Get RNG Health Test Control 0680 * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig 0681 * @param RNGx RNG Instance 0682 * @retval Return 32-bit RNG Health Test configuration 0683 */ 0684 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) 0685 { 0686 /*!< magic number must be written immediately before reading RNG_HTCRG */ 0687 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); 0688 0689 return (uint32_t)READ_REG(RNGx->HTCR); 0690 } 0691 0692 /** 0693 * @} 0694 */ 0695 #endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */ 0696 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0697 /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions 0698 * @ingroup RTEMSBSPsARMSTM32H7 0699 * @{ 0700 */ 0701 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); 0702 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); 0703 ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); 0704 0705 /** 0706 * @} 0707 */ 0708 #endif /* USE_FULL_LL_DRIVER */ 0709 0710 /** 0711 * @} 0712 */ 0713 0714 /** 0715 * @} 0716 */ 0717 0718 #endif /* RNG */ 0719 0720 /** 0721 * @} 0722 */ 0723 0724 #ifdef __cplusplus 0725 } 0726 #endif 0727 0728 #endif /* __STM32H7xx_LL_RNG_H */ 0729
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