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File indexing completed on 2025-05-11 08:23:37 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_rcc.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of RCC LL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file in
0013   * the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   ******************************************************************************
0016   */
0017 
0018 /* Define to prevent recursive inclusion -------------------------------------*/
0019 #ifndef STM32H7xx_LL_RCC_H
0020 #define STM32H7xx_LL_RCC_H
0021 
0022 #ifdef __cplusplus
0023 extern "C" {
0024 #endif
0025 
0026 /* Includes ------------------------------------------------------------------*/
0027 #include "stm32h7xx.h"
0028 #include <math.h>
0029 
0030 /** @addtogroup STM32H7xx_LL_Driver
0031   * @{
0032   */
0033 
0034 #if defined(RCC)
0035 
0036 /** @defgroup RCC_LL RCC
0037   * @ingroup RTEMSBSPsARMSTM32H7
0038   * @{
0039   */
0040 
0041 /* Private types -------------------------------------------------------------*/
0042 /* Private variables ---------------------------------------------------------*/
0043 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
0044   * @ingroup RTEMSBSPsARMSTM32H7
0045   * @{
0046   */
0047 extern const uint8_t LL_RCC_PrescTable[16];
0048 
0049 /**
0050   * @}
0051   */
0052 /* Private constants ---------------------------------------------------------*/
0053 /* Private macros ------------------------------------------------------------*/
0054 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
0055   * @ingroup RTEMSBSPsARMSTM32H7
0056   * @{
0057   */
0058 #if !defined(UNUSED)
0059 #define UNUSED(x) ((void)(x))
0060 #endif
0061 
0062 /* 32            24           16            8             0
0063    --------------------------------------------------------
0064    | Mask        | ClkSource   |  Bit       | Register    |
0065    |             |  Config     | Position   | Offset      |
0066    --------------------------------------------------------*/
0067 
0068 #if defined(RCC_VER_2_0)
0069 /* Clock source register offset Vs CDCCIPR register */
0070 #define CDCCIP    0x0UL
0071 #define CDCCIP1   0x4UL
0072 #define CDCCIP2   0x8UL
0073 #define SRDCCIP   0xCUL
0074 #else
0075 /* Clock source register offset Vs D1CCIPR register */
0076 #define D1CCIP    0x0UL
0077 #define D2CCIP1   0x4UL
0078 #define D2CCIP2   0x8UL
0079 #define D3CCIP    0xCUL
0080 #endif /* RCC_VER_2_0 */
0081 
0082 #define LL_RCC_REG_SHIFT     0U
0083 #define LL_RCC_POS_SHIFT     8U
0084 #define LL_RCC_CONFIG_SHIFT  16U
0085 #define LL_RCC_MASK_SHIFT    24U
0086 
0087 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)
0088 
0089 #define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
0090 
0091 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
0092 
0093 #define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)
0094 
0095 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
0096                                                                      (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
0097                                                                      (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
0098                                                                      (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
0099 /**
0100   * @}
0101   */
0102 /* Exported types ------------------------------------------------------------*/
0103 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0104 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
0105   * @ingroup RTEMSBSPsARMSTM32H7
0106   * @{
0107   */
0108 
0109 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
0110   * @ingroup RTEMSBSPsARMSTM32H7
0111   * @{
0112   */
0113 
0114 /**
0115   * @brief  RCC Clocks Frequency Structure
0116   */
0117 typedef struct
0118 {
0119   uint32_t SYSCLK_Frequency;
0120   uint32_t CPUCLK_Frequency;
0121   uint32_t HCLK_Frequency;
0122   uint32_t PCLK1_Frequency;
0123   uint32_t PCLK2_Frequency;
0124   uint32_t PCLK3_Frequency;
0125   uint32_t PCLK4_Frequency;
0126 } LL_RCC_ClocksTypeDef;
0127 
0128 /**
0129   * @}
0130   */
0131 
0132 /**
0133   * @brief  PLL Clocks Frequency Structure
0134   */
0135 typedef struct
0136 {
0137   uint32_t PLL_P_Frequency;
0138   uint32_t PLL_Q_Frequency;
0139   uint32_t PLL_R_Frequency;
0140 } LL_PLL_ClocksTypeDef;
0141 
0142 /**
0143   * @}
0144   */
0145 
0146 #endif /* USE_FULL_LL_DRIVER */
0147 
0148 /* Exported constants --------------------------------------------------------*/
0149 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
0150   * @ingroup RTEMSBSPsARMSTM32H7
0151   * @{
0152   */
0153 
0154 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
0155   * @ingroup RTEMSBSPsARMSTM32H7
0156   * @brief    Defines used to adapt values of different oscillators
0157   * @note     These values could be modified in the user environment according to
0158   *           HW set-up.
0159   * @{
0160   */
0161 #if !defined  (HSE_VALUE)
0162 #if defined(RCC_VER_X) || defined(RCC_VER_3_0)
0163 #define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
0164 #else
0165 #define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */
0166 #endif /* RCC_VER_X || RCC_VER_3_0 */
0167 #endif /* HSE_VALUE */
0168 
0169 #if !defined  (HSI_VALUE)
0170 #define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */
0171 #endif /* HSI_VALUE */
0172 
0173 #if !defined  (CSI_VALUE)
0174 #define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */
0175 #endif /* CSI_VALUE */
0176 
0177 #if !defined  (LSE_VALUE)
0178 #define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
0179 #endif /* LSE_VALUE */
0180 
0181 #if !defined  (LSI_VALUE)
0182 #define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
0183 #endif /* LSI_VALUE */
0184 
0185 #if !defined  (EXTERNAL_CLOCK_VALUE)
0186 #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
0187 #endif /* EXTERNAL_CLOCK_VALUE */
0188 
0189 #if !defined  (HSI48_VALUE)
0190 #define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */
0191 #endif /* HSI48_VALUE */
0192 
0193 /**
0194   * @}
0195   */
0196 
0197 /** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
0198   * @ingroup RTEMSBSPsARMSTM32H7
0199   * @{
0200   */
0201 #define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1
0202 #define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2
0203 #define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4
0204 #define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8
0205 /**
0206   * @}
0207   */
0208 
0209 /** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability
0210   * @ingroup RTEMSBSPsARMSTM32H7
0211   * @{
0212   */
0213 #define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)
0214 #define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)
0215 #define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)
0216 #define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)
0217 /**
0218   * @}
0219   */
0220 
0221 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
0222   * @ingroup RTEMSBSPsARMSTM32H7
0223   * @{
0224   */
0225 #define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI
0226 #define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI
0227 #define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE
0228 #define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1
0229 /**
0230   * @}
0231   */
0232 
0233 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
0234   * @ingroup RTEMSBSPsARMSTM32H7
0235   * @{
0236   */
0237 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
0238 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */
0239 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
0240 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */
0241 /**
0242   * @}
0243   */
0244 
0245 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source
0246   * @ingroup RTEMSBSPsARMSTM32H7
0247   * @{
0248   */
0249 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
0250 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)
0251 /**
0252   * @}
0253   */
0254 
0255 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source
0256   * @ingroup RTEMSBSPsARMSTM32H7
0257   * @{
0258   */
0259 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)
0260 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)
0261 /**
0262   * @}
0263   */
0264 
0265 /** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler
0266   * @ingroup RTEMSBSPsARMSTM32H7
0267   * @{
0268   */
0269 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
0270 #define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1
0271 #define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2
0272 #define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4
0273 #define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8
0274 #define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16
0275 #define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64
0276 #define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128
0277 #define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256
0278 #define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512
0279 #else
0280 #define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1
0281 #define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2
0282 #define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4
0283 #define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8
0284 #define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16
0285 #define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64
0286 #define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128
0287 #define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256
0288 #define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512
0289 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */
0290 /**
0291   * @}
0292   */
0293 
0294 /** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler
0295   * @ingroup RTEMSBSPsARMSTM32H7
0296   * @{
0297   */
0298 #if defined(RCC_D1CFGR_HPRE_DIV1)
0299 #define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1
0300 #define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2
0301 #define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4
0302 #define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8
0303 #define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16
0304 #define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64
0305 #define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128
0306 #define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256
0307 #define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512
0308 #else
0309 #define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1
0310 #define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2
0311 #define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4
0312 #define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8
0313 #define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16
0314 #define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64
0315 #define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128
0316 #define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256
0317 #define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512
0318 #endif /* RCC_D1CFGR_HPRE_DIV1 */
0319 /**
0320   * @}
0321   */
0322 
0323 /** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
0324   * @ingroup RTEMSBSPsARMSTM32H7
0325   * @{
0326   */
0327 #if defined(RCC_D2CFGR_D2PPRE1_DIV1)
0328 #define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1
0329 #define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2
0330 #define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4
0331 #define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8
0332 #define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16
0333 #else
0334 #define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1
0335 #define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2
0336 #define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4
0337 #define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8
0338 #define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16
0339 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
0340 /**
0341   * @}
0342   */
0343 
0344 /** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)
0345   * @ingroup RTEMSBSPsARMSTM32H7
0346   * @{
0347   */
0348 #if defined(RCC_D2CFGR_D2PPRE2_DIV1)
0349 #define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1
0350 #define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2
0351 #define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4
0352 #define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8
0353 #define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16
0354 #else
0355 #define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1
0356 #define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2
0357 #define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4
0358 #define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8
0359 #define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16
0360 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
0361 /**
0362   * @}
0363   */
0364 
0365 /** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)
0366   * @ingroup RTEMSBSPsARMSTM32H7
0367   * @{
0368   */
0369 #if defined(RCC_D1CFGR_D1PPRE_DIV1)
0370 #define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1
0371 #define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2
0372 #define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4
0373 #define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8
0374 #define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16
0375 #else
0376 #define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1
0377 #define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2
0378 #define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4
0379 #define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8
0380 #define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16
0381 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */
0382 /**
0383   * @}
0384   */
0385 
0386 /** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)
0387   * @ingroup RTEMSBSPsARMSTM32H7
0388   * @{
0389   */
0390 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
0391 #define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1
0392 #define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2
0393 #define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4
0394 #define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8
0395 #define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16
0396 #else
0397 #define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1
0398 #define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2
0399 #define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4
0400 #define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8
0401 #define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16
0402 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */
0403 /**
0404   * @}
0405   */
0406 
0407 /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
0408   * @ingroup RTEMSBSPsARMSTM32H7
0409   * @{
0410   */
0411 #define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
0412 #define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
0413 #define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
0414 #define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
0415 #define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
0416 #define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
0417 #define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
0418 #define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
0419 #define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
0420 #define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
0421 #define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
0422 /**
0423   * @}
0424   */
0425 
0426 /** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
0427   * @ingroup RTEMSBSPsARMSTM32H7
0428   * @{
0429   */
0430 #define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
0431 #define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
0432 #define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
0433 #define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
0434 #define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
0435 #define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
0436 #define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
0437 #define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
0438 #define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
0439 #define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
0440 #define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
0441 #define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
0442 #define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
0443 #define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
0444 #define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
0445 #define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
0446 #define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
0447 #define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
0448 #define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
0449 #define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
0450 #define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
0451 #define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
0452 #define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
0453 #define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
0454 #define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
0455 #define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
0456 #define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
0457 #define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
0458 #define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
0459 #define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
0460 
0461 /**
0462   * @}
0463   */
0464 
0465 /** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
0466   * @ingroup RTEMSBSPsARMSTM32H7
0467   * @{
0468   */
0469 #define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)
0470 #define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)
0471 #define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0472 #define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)
0473 #define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0474 #define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0475 #define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0476 #define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)
0477 #define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
0478 #define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
0479 #define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0480 #define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
0481 #define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0482 #define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0483 #define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0484 #define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)
0485 #define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
0486 #define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
0487 #define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0488 #define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
0489 #define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0490 #define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0491 #define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0492 #define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
0493 #define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
0494 #define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
0495 #define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0496 #define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
0497 #define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0498 #define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0499 #define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0500 #define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)
0501 #define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
0502 #define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
0503 #define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0504 #define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
0505 #define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0506 #define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0507 #define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0508 #define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
0509 #define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
0510 #define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
0511 #define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0512 #define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
0513 #define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0514 #define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0515 #define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0516 #define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
0517 #define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
0518 #define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
0519 #define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0520 #define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
0521 #define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0522 #define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0523 #define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0524 #define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
0525 #define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
0526 #define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
0527 #define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0528 #define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
0529 #define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
0530 #define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
0531 #define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
0532 /**
0533   * @}
0534   */
0535 
0536 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
0537   * @ingroup RTEMSBSPsARMSTM32H7
0538   * @{
0539   */
0540 #if defined(RCC_D2CCIP2R_USART16SEL)
0541 #define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
0542 #define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
0543 #define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
0544 #define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
0545 #define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
0546 #define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
0547 /*  Aliases */
0548 #define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_RCC_USART16_CLKSOURCE_PCLK2
0549 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_RCC_USART16_CLKSOURCE_PLL2Q
0550 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_RCC_USART16_CLKSOURCE_PLL3Q
0551 #define LL_RCC_USART16910_CLKSOURCE_HSI        LL_RCC_USART16_CLKSOURCE_HSI
0552 #define LL_RCC_USART16910_CLKSOURCE_CSI        LL_RCC_USART16_CLKSOURCE_CSI
0553 #define LL_RCC_USART16910_CLKSOURCE_LSE        LL_RCC_USART16_CLKSOURCE_LSE
0554 
0555 #elif defined(RCC_D2CCIP2R_USART16910SEL)
0556 #define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
0557 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
0558 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
0559 #define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
0560 #define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
0561 #define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
0562 /*  Aliases */
0563 #define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
0564 #define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
0565 #define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
0566 #define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
0567 #define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
0568 #define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
0569 
0570 #else
0571 #define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
0572 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
0573 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
0574 #define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
0575 #define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
0576 #define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
0577 /*  Aliases */
0578 #define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2
0579 #define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q
0580 #define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q
0581 #define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI
0582 #define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI
0583 #define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE
0584 #endif  /* RCC_D2CCIP2R_USART16SEL */
0585 #if defined(RCC_D2CCIP2R_USART28SEL)
0586 #define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
0587 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
0588 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
0589 #define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
0590 #define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
0591 #define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
0592 #else
0593 #define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
0594 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
0595 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
0596 #define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
0597 #define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
0598 #define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
0599 #endif /* RCC_D2CCIP2R_USART28SEL */
0600 /**
0601   * @}
0602   */
0603 
0604 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection
0605   * @ingroup RTEMSBSPsARMSTM32H7
0606   * @{
0607   */
0608 #if defined(RCC_D3CCIPR_LPUART1SEL)
0609 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
0610 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)
0611 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)
0612 #define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
0613 #define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)
0614 #define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
0615 #else
0616 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)
0617 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)
0618 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)
0619 #define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
0620 #define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)
0621 #define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
0622 #endif /* RCC_D3CCIPR_LPUART1SEL */
0623 /**
0624   * @}
0625   */
0626 
0627 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
0628   * @ingroup RTEMSBSPsARMSTM32H7
0629   * @{
0630   */
0631 #if defined (RCC_D2CCIP2R_I2C123SEL)
0632 #define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
0633 #define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
0634 #define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
0635 #define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
0636 /*  Aliases */
0637 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_RCC_I2C123_CLKSOURCE_PCLK1
0638 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_RCC_I2C123_CLKSOURCE_PLL3R
0639 #define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_RCC_I2C123_CLKSOURCE_HSI
0640 #define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_RCC_I2C123_CLKSOURCE_CSI
0641 
0642 #elif defined (RCC_D2CCIP2R_I2C1235SEL)
0643 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
0644 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
0645 #define LL_RCC_I2C1235_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
0646 #define LL_RCC_I2C1235_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
0647 /*  Aliases */
0648 #define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_RCC_I2C1235_CLKSOURCE_PCLK1
0649 #define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_RCC_I2C1235_CLKSOURCE_PLL3R
0650 #define LL_RCC_I2C123_CLKSOURCE_HSI            LL_RCC_I2C1235_CLKSOURCE_HSI
0651 #define LL_RCC_I2C123_CLKSOURCE_CSI            LL_RCC_I2C1235_CLKSOURCE_CSI
0652 
0653 #else
0654 #define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
0655 #define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
0656 #define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
0657 #define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
0658 #endif /* RCC_D2CCIP2R_I2C123SEL */
0659 #if defined (RCC_D3CCIPR_I2C4SEL)
0660 #define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
0661 #define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)
0662 #define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)
0663 #define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
0664 #else
0665 #define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)
0666 #define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)
0667 #define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)
0668 #define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
0669 #endif /* RCC_D3CCIPR_I2C4SEL */
0670 /**
0671   * @}
0672   */
0673 
0674 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
0675   * @ingroup RTEMSBSPsARMSTM32H7
0676   * @{
0677   */
0678 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
0679 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)
0680 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)
0681 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)
0682 #define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
0683 #define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)
0684 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
0685 #else
0686 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)
0687 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)
0688 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)
0689 #define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
0690 #define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)
0691 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
0692 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
0693 #if defined(RCC_D3CCIPR_LPTIM2SEL)
0694 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)
0695 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)
0696 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)
0697 #define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
0698 #define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)
0699 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
0700 #else
0701 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)
0702 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)
0703 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)
0704 #define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
0705 #define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)
0706 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
0707 #endif /* RCC_D3CCIPR_LPTIM2SEL */
0708 #if defined(RCC_D3CCIPR_LPTIM345SEL)
0709 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
0710 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
0711 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
0712 #define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
0713 #define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
0714 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
0715 #else
0716 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
0717 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
0718 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
0719 #define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
0720 #define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
0721 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
0722 /* aliases*/
0723 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4
0724 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P
0725 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R
0726 #define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE
0727 #define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI
0728 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP
0729 #endif /* RCC_D3CCIPR_LPTIM345SEL */
0730 /**
0731   * @}
0732   */
0733 
0734 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
0735   * @ingroup RTEMSBSPsARMSTM32H7
0736   * @{
0737   */
0738 #if defined(RCC_D2CCIP1R_SAI1SEL)
0739 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
0740 #define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)
0741 #define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)
0742 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
0743 #define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)
0744 #else
0745 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
0746 #define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)
0747 #define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)
0748 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
0749 #define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)
0750 #endif
0751 #if defined(SAI3)
0752 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
0753 #define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
0754 #define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
0755 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
0756 #define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
0757 #endif /* SAI3 */
0758 #if defined(RCC_CDCCIP1R_SAI2ASEL)
0759 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
0760 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)
0761 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)
0762 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
0763 #define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)
0764 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
0765 #endif /* RCC_CDCCIP1R_SAI2ASEL */
0766 #if defined(RCC_CDCCIP1R_SAI2BSEL)
0767 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
0768 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)
0769 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)
0770 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
0771 #define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)
0772 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
0773 #endif /* RCC_CDCCIP1R_SAI2BSEL */
0774 #if defined(SAI4_Block_A)
0775 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
0776 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)
0777 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)
0778 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
0779 #define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)
0780 #if defined(RCC_VER_3_0)
0781 #define LL_RCC_SAI4A_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
0782 #endif /* RCC_VER_3_0 */
0783 #endif /* SAI4_Block_A */
0784 #if defined(SAI4_Block_B)
0785 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
0786 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)
0787 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)
0788 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
0789 #define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)
0790 #if defined(RCC_VER_3_0)
0791 #define LL_RCC_SAI4B_CLKSOURCE_SPDIF           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
0792 #endif /* RCC_VER_3_0 */
0793 #endif /* SAI4_Block_B */
0794 /**
0795   * @}
0796   */
0797 
0798 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection
0799   * @ingroup RTEMSBSPsARMSTM32H7
0800   * @{
0801   */
0802 #if defined(RCC_D1CCIPR_SDMMCSEL)
0803 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
0804 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)
0805 #else
0806 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)
0807 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)
0808 #endif /* RCC_D1CCIPR_SDMMCSEL */
0809 /**
0810   * @}
0811   */
0812 
0813 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
0814   * @ingroup RTEMSBSPsARMSTM32H7
0815   * @{
0816   */
0817 #if defined(RCC_D2CCIP2R_RNGSEL)
0818 #define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
0819 #define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)
0820 #define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)
0821 #define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
0822 #else
0823 #define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)
0824 #define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)
0825 #define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)
0826 #define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
0827 #endif /* RCC_D2CCIP2R_RNGSEL */
0828 /**
0829   * @}
0830   */
0831 
0832 /** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
0833   * @ingroup RTEMSBSPsARMSTM32H7
0834   * @{
0835   */
0836 #if defined(RCC_D2CCIP2R_USBSEL)
0837 #define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
0838 #define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)
0839 #define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)
0840 #define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
0841 #else
0842 #define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)
0843 #define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)
0844 #define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)
0845 #define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
0846 #endif /* RCC_D2CCIP2R_USBSEL */
0847 /**
0848   * @}
0849   */
0850 
0851 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
0852   * @ingroup RTEMSBSPsARMSTM32H7
0853   * @{
0854   */
0855 #if defined(RCC_D2CCIP2R_CECSEL)
0856 #define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
0857 #define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)
0858 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)
0859 #else
0860 #define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)
0861 #define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)
0862 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)
0863 #endif
0864 /**
0865   * @}
0866   */
0867 
0868 #if defined(DSI)
0869 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
0870   * @ingroup RTEMSBSPsARMSTM32H7
0871   * @{
0872   */
0873 #define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)
0874 #define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)
0875 /**
0876   * @}
0877   */
0878 #endif /* DSI */
0879 
0880 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection
0881   * @ingroup RTEMSBSPsARMSTM32H7
0882   * @{
0883   */
0884 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
0885 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
0886 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)
0887 #else
0888 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)
0889 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)
0890 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
0891 /**
0892   * @}
0893   */
0894 
0895 #if defined(DFSDM2_BASE)
0896 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection
0897   * @ingroup RTEMSBSPsARMSTM32H7
0898   * @{
0899   */
0900 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)
0901 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)
0902 /**
0903   * @}
0904   */
0905 #endif /* DFSDM2_BASE */
0906 
0907 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
0908   * @ingroup RTEMSBSPsARMSTM32H7
0909   * @{
0910   */
0911 #if defined(RCC_D1CCIPR_FMCSEL)
0912 #define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
0913 #define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)
0914 #define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)
0915 #define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
0916 #else
0917 #define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)
0918 #define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)
0919 #define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)
0920 #define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
0921 #endif /* RCC_D1CCIPR_FMCSEL */
0922 /**
0923   * @}
0924   */
0925 
0926 #if defined(QUADSPI)
0927 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
0928   * @ingroup RTEMSBSPsARMSTM32H7
0929   * @{
0930   */
0931 #define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)
0932 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)
0933 #define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)
0934 #define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
0935 /**
0936   * @}
0937   */
0938 #endif /* QUADSPI */
0939 
0940 
0941 #if defined(OCTOSPI1) || defined(OCTOSPI2)
0942 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection
0943   * @ingroup RTEMSBSPsARMSTM32H7
0944   * @{
0945   */
0946 #if defined(RCC_D1CCIPR_OCTOSPISEL)
0947 #define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
0948 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_OCTOSPISEL_0)
0949 #define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_OCTOSPISEL_1)
0950 #define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
0951 #else
0952 #define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)
0953 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)
0954 #define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)
0955 #define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
0956 #endif /* RCC_D1CCIPR_OCTOSPISEL */
0957 /**
0958   * @}
0959   */
0960 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
0961 
0962 
0963 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection
0964   * @ingroup RTEMSBSPsARMSTM32H7
0965   * @{
0966   */
0967 #if defined(RCC_D1CCIPR_CKPERSEL)
0968 #define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
0969 #define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)
0970 #define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)
0971 #else
0972 #define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)
0973 #define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)
0974 #define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)
0975 #endif /* RCC_D1CCIPR_CKPERSEL */
0976 /**
0977   * @}
0978   */
0979 
0980 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection
0981   * @ingroup RTEMSBSPsARMSTM32H7
0982   * @{
0983   */
0984 #if defined(RCC_D2CCIP1R_SPI123SEL)
0985 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
0986 #define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
0987 #define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
0988 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
0989 #define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
0990 #else
0991 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
0992 #define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
0993 #define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
0994 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
0995 #define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
0996 #endif /* RCC_D2CCIP1R_SPI123SEL */
0997 #if defined(RCC_D2CCIP1R_SPI45SEL)
0998 #define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
0999 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)
1000 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)
1001 #define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
1002 #define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)
1003 #define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
1004 #else
1005 #define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
1006 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)
1007 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)
1008 #define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
1009 #define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)
1010 #define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
1011 #endif /* (RCC_D2CCIP1R_SPI45SEL */
1012 #if defined(RCC_D3CCIPR_SPI6SEL)
1013 #define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
1014 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)
1015 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)
1016 #define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
1017 #define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)
1018 #define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
1019 #else
1020 #define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)
1021 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)
1022 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)
1023 #define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
1024 #define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)
1025 #define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
1026 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
1027 #endif /* RCC_D3CCIPR_SPI6SEL */
1028 /**
1029   * @}
1030   */
1031 
1032 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection
1033   * @ingroup RTEMSBSPsARMSTM32H7
1034   * @{
1035   */
1036 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1037 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
1038 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)
1039 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)
1040 #define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
1041 #else
1042 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)
1043 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)
1044 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)
1045 #define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
1046 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1047 /**
1048   * @}
1049   */
1050 
1051 #if defined(FDCAN1) || defined(FDCAN2)
1052 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
1053   * @ingroup RTEMSBSPsARMSTM32H7
1054   * @{
1055   */
1056 #if defined(RCC_D2CCIP1R_FDCANSEL)
1057 #define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
1058 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)
1059 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)
1060 #else
1061 #define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)
1062 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)
1063 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)
1064 #endif /* RCC_D2CCIP1R_FDCANSEL */
1065 /**
1066   * @}
1067   */
1068 #endif /*FDCAN1 || FDCAN2*/
1069 
1070 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection
1071   * @ingroup RTEMSBSPsARMSTM32H7
1072   * @{
1073   */
1074 #if defined(RCC_D2CCIP1R_SWPSEL)
1075 #define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
1076 #define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)
1077 #else
1078 #define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)
1079 #define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)
1080 #endif /* RCC_D2CCIP1R_SWPSEL */
1081 /**
1082   * @}
1083   */
1084 
1085 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
1086   * @ingroup RTEMSBSPsARMSTM32H7
1087   * @{
1088   */
1089 #if defined(RCC_D3CCIPR_ADCSEL)
1090 #define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
1091 #define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)
1092 #define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)
1093 #else
1094 #define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)
1095 #define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)
1096 #define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)
1097 #endif /* RCC_D3CCIPR_ADCSEL */
1098 /**
1099   * @}
1100   */
1101 
1102 /** @defgroup RCC_LL_EC_USARTx  Peripheral USART get clock source
1103   * @ingroup RTEMSBSPsARMSTM32H7
1104   * @{
1105   */
1106 #if defined (RCC_D2CCIP2R_USART16SEL)
1107 #define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
1108 #elif defined (RCC_D2CCIP2R_USART16910SEL)
1109 #define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
1110 /* alias*/
1111 #define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
1112 #else
1113 #define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
1114 /* alias*/
1115 #define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE
1116 #endif /* RCC_D2CCIP2R_USART16SEL */
1117 #if defined (RCC_D2CCIP2R_USART28SEL)
1118 #define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
1119 #else
1120 #define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
1121 #endif /* RCC_D2CCIP2R_USART28SEL */
1122 /**
1123   * @}
1124   */
1125 
1126 /** @defgroup RCC_LL_EC_LPUARTx  Peripheral LPUART get clock source
1127   * @ingroup RTEMSBSPsARMSTM32H7
1128   * @{
1129   */
1130 #if defined(RCC_D3CCIPR_LPUART1SEL)
1131 #define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL
1132 #else
1133 #define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL
1134 #endif /* RCC_D3CCIPR_LPUART1SEL */
1135 /**
1136   * @}
1137   */
1138 
1139 /** @defgroup RCC_LL_EC_I2Cx  Peripheral I2C get clock source
1140   * @ingroup RTEMSBSPsARMSTM32H7
1141   * @{
1142   */
1143 #if defined(RCC_D2CCIP2R_I2C123SEL)
1144 #define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
1145 /* alias */
1146 #define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
1147 #elif defined(RCC_D2CCIP2R_I2C1235SEL)
1148 #define LL_RCC_I2C1235_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
1149 /* alias */
1150 #define LL_RCC_I2C123_CLKSOURCE          LL_RCC_I2C1235_CLKSOURCE
1151 #else
1152 #define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
1153 /* alias */
1154 #define LL_RCC_I2C1235_CLKSOURCE         LL_RCC_I2C123_CLKSOURCE
1155 #endif /* RCC_D2CCIP2R_I2C123SEL */
1156 #if defined(RCC_D3CCIPR_I2C4SEL)
1157 #define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)
1158 #else
1159 #define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)
1160 #endif /* RCC_D3CCIPR_I2C4SEL */
1161 /**
1162   * @}
1163   */
1164 
1165 /** @defgroup RCC_LL_EC_LPTIMx  Peripheral LPTIM get clock source
1166   * @ingroup RTEMSBSPsARMSTM32H7
1167   * @{
1168   */
1169 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1170 #define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,      0x00000000U)
1171 #else
1172 #define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,      0x00000000U)
1173 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */
1174 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1175 #define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,       0x00000000U)
1176 #else
1177 #define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,      0x00000000U)
1178 #endif /* RCC_D3CCIPR_LPTIM2SEL */
1179 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1180 #define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,     0x00000000U)
1181 #else
1182 #define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,      0x00000000U)
1183 #define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */
1184 #endif /* RCC_D3CCIPR_LPTIM345SEL */
1185 /**
1186   * @}
1187   */
1188 
1189 /** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
1190   * @ingroup RTEMSBSPsARMSTM32H7
1191   * @{
1192   */
1193 #if defined(RCC_D2CCIP1R_SAI1SEL)
1194 #define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)
1195 #else
1196 #define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)
1197 #endif /* RCC_D2CCIP1R_SAI1SEL */
1198 #if defined(RCC_D2CCIP1R_SAI23SEL)
1199 #define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
1200 #endif /* RCC_D2CCIP1R_SAI23SEL */
1201 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1202 #define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)
1203 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1204 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1205 #define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)
1206 #endif /*  RCC_CDCCIP1R_SAI2BSEL */
1207 #if defined(RCC_D3CCIPR_SAI4ASEL)
1208 #define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)
1209 #endif /* RCC_D3CCIPR_SAI4ASEL */
1210 #if defined(RCC_D3CCIPR_SAI4BSEL)
1211 #define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)
1212 #endif /*  RCC_D3CCIPR_SAI4BSEL */
1213 /**
1214   * @}
1215   */
1216 
1217 /** @defgroup RCC_LL_EC_SDMMC  Peripheral SDMMC get clock source
1218   * @ingroup RTEMSBSPsARMSTM32H7
1219   * @{
1220   */
1221 #if defined(RCC_D1CCIPR_SDMMCSEL)
1222 #define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL
1223 #else
1224 #define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL
1225 #endif /* RCC_D1CCIPR_SDMMCSEL */
1226 /**
1227   * @}
1228   */
1229 
1230 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
1231   * @ingroup RTEMSBSPsARMSTM32H7
1232   * @{
1233   */
1234 #if (RCC_D2CCIP2R_RNGSEL)
1235 #define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL
1236 #else
1237 #define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL
1238 #endif /* RCC_D2CCIP2R_RNGSEL */
1239 /**
1240   * @}
1241   */
1242 
1243 /** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
1244   * @ingroup RTEMSBSPsARMSTM32H7
1245   * @{
1246   */
1247 #if (RCC_D2CCIP2R_USBSEL)
1248 #define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL
1249 #else
1250 #define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL
1251 #endif  /* RCC_D2CCIP2R_USBSEL */
1252 /**
1253   * @}
1254   */
1255 
1256 /** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
1257   * @ingroup RTEMSBSPsARMSTM32H7
1258   * @{
1259   */
1260 #if (RCC_D2CCIP2R_CECSEL)
1261 #define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL
1262 #else
1263 #define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL
1264 #endif /* RCC_D2CCIP2R_CECSEL */
1265 /**
1266   * @}
1267   */
1268 
1269 #if defined(DSI)
1270 /** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
1271   * @ingroup RTEMSBSPsARMSTM32H7
1272   * @{
1273   */
1274 #define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL
1275 /**
1276   * @}
1277   */
1278 #endif /* DSI */
1279 
1280 /** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
1281   * @ingroup RTEMSBSPsARMSTM32H7
1282   * @{
1283   */
1284 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1285 #define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL
1286 #else
1287 #define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL
1288 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
1289 /**
1290   * @}
1291   */
1292 
1293 #if defined(DFSDM2_BASE)
1294 /** @defgroup RCC_LL_EC_DFSDM2  Peripheral DFSDM2 get clock source
1295   * @ingroup RTEMSBSPsARMSTM32H7
1296   * @{
1297   */
1298 #define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL
1299 /**
1300   * @}
1301   */
1302 #endif /* DFSDM2_BASE */
1303 
1304 
1305 
1306 /** @defgroup RCC_LL_EC_FMC  Peripheral FMC get clock source
1307   * @ingroup RTEMSBSPsARMSTM32H7
1308   * @{
1309   */
1310 #if defined(RCC_D1CCIPR_FMCSEL)
1311 #define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL
1312 #else
1313 #define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL
1314 #endif
1315 /**
1316   * @}
1317   */
1318 
1319 #if defined(QUADSPI)
1320 /** @defgroup RCC_LL_EC_QSPI  Peripheral QSPI get clock source
1321   * @ingroup RTEMSBSPsARMSTM32H7
1322   * @{
1323   */
1324 #define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL
1325 /**
1326   * @}
1327   */
1328 #endif /* QUADSPI */
1329 
1330 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1331 /** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
1332   * @ingroup RTEMSBSPsARMSTM32H7
1333   * @{
1334   */
1335 #if defined(RCC_CDCCIPR_OCTOSPISEL)
1336 #define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL
1337 #else
1338 #define LL_RCC_OSPI_CLKSOURCE            RCC_D1CCIPR_OCTOSPISEL
1339 #endif /* RCC_CDCCIPR_OCTOSPISEL */
1340 /**
1341   * @}
1342   */
1343 #endif /* OCTOSPI1 || OCTOSPI2 */
1344 
1345 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1346   * @ingroup RTEMSBSPsARMSTM32H7
1347   * @{
1348   */
1349 #if defined(RCC_D1CCIPR_CKPERSEL)
1350 #define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL
1351 #else
1352 #define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL
1353 #endif /* RCC_D1CCIPR_CKPERSEL */
1354 /**
1355   * @}
1356   */
1357 
1358 /** @defgroup RCC_LL_EC_SPIx  Peripheral SPI get clock source
1359   * @ingroup RTEMSBSPsARMSTM32H7
1360   * @{
1361   */
1362 #if defined(RCC_D2CCIP1R_SPI123SEL)
1363 #define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
1364 #else
1365 #define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
1366 #endif /* RCC_D2CCIP1R_SPI123SEL */
1367 #if defined(RCC_D2CCIP1R_SPI45SEL)
1368 #define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)
1369 #else
1370 #define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)
1371 #endif /* RCC_D2CCIP1R_SPI45SEL */
1372 #if defined(RCC_D3CCIPR_SPI6SEL)
1373 #define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)
1374 #else
1375 #define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)
1376 #endif /* RCC_D3CCIPR_SPI6SEL */
1377 /**
1378   * @}
1379   */
1380 
1381 /** @defgroup RCC_LL_EC_SPDIF  Peripheral SPDIF get clock source
1382   * @ingroup RTEMSBSPsARMSTM32H7
1383   * @{
1384   */
1385 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1386 #define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL
1387 #else
1388 #define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL
1389 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1390 /**
1391   * @}
1392   */
1393 
1394 #if defined(FDCAN1) || defined(FDCAN2)
1395 /** @defgroup RCC_LL_EC_FDCAN  Peripheral FDCAN get clock source
1396   * @ingroup RTEMSBSPsARMSTM32H7
1397   * @{
1398   */
1399 #if defined(RCC_D2CCIP1R_FDCANSEL)
1400 #define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL
1401 #else
1402 #define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL
1403 #endif
1404 /**
1405   * @}
1406   */
1407 #endif /*FDCAN1 || FDCAN2*/
1408 
1409 /** @defgroup RCC_LL_EC_SWP  Peripheral SWP get clock source
1410   * @ingroup RTEMSBSPsARMSTM32H7
1411   * @{
1412   */
1413 #if defined(RCC_D2CCIP1R_SWPSEL)
1414 #define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL
1415 #else
1416 #define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL
1417 #endif /* RCC_D2CCIP1R_SWPSEL */
1418 /**
1419   * @}
1420   */
1421 
1422 /** @defgroup RCC_LL_EC_ADC  Peripheral ADC get clock source
1423   * @ingroup RTEMSBSPsARMSTM32H7
1424   * @{
1425   */
1426 #if defined(RCC_D3CCIPR_ADCSEL)
1427 #define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL
1428 #else
1429 #define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL
1430 #endif /* RCC_D3CCIPR_ADCSEL */
1431 /**
1432   * @}
1433   */
1434 
1435 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
1436   * @ingroup RTEMSBSPsARMSTM32H7
1437   * @{
1438   */
1439 #define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)
1440 #define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)
1441 #define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)
1442 #define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
1443 /**
1444   * @}
1445   */
1446 
1447 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
1448   * @ingroup RTEMSBSPsARMSTM32H7
1449   * @{
1450   */
1451 #define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)
1452 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)
1453 /**
1454   * @}
1455   */
1456 
1457 #if defined(HRTIM1)
1458 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection
1459   * @ingroup RTEMSBSPsARMSTM32H7
1460   * @{
1461   */
1462 #define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */
1463 #define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */
1464 /**
1465   * @}
1466   */
1467 #endif /* HRTIM1 */
1468 
1469 /** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source
1470   * @ingroup RTEMSBSPsARMSTM32H7
1471   * @{
1472   */
1473 #define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI
1474 #define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI
1475 #define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE
1476 #define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE
1477 /**
1478   * @}
1479   */
1480 
1481 /** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range
1482   * @ingroup RTEMSBSPsARMSTM32H7
1483   * @{
1484   */
1485 #define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)
1486 #define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)
1487 #define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)
1488 #define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)
1489 /**
1490   * @}
1491   */
1492 
1493 /** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range
1494   * @ingroup RTEMSBSPsARMSTM32H7
1495   * @{
1496   */
1497 #define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */
1498 #define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */
1499 /**
1500   * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
1501   * @}
1502   */
1503 
1504 /**
1505   * @}
1506   */
1507 
1508 /* Exported macro ------------------------------------------------------------*/
1509 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1510   * @ingroup RTEMSBSPsARMSTM32H7
1511   * @{
1512   */
1513 
1514 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1515   * @ingroup RTEMSBSPsARMSTM32H7
1516   * @{
1517   */
1518 
1519 /**
1520   * @brief  Write a value in RCC register
1521   * @param  __REG__ Register to be written
1522   * @param  __VALUE__ Value to be written in the register
1523   * @retval None
1524   */
1525 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1526 
1527 /**
1528   * @brief  Read a value in RCC register
1529   * @param  __REG__ Register to be read
1530   * @retval Register value
1531   */
1532 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1533 /**
1534   * @}
1535   */
1536 
1537 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1538   * @ingroup RTEMSBSPsARMSTM32H7
1539   * @{
1540   */
1541 
1542 /**
1543   * @brief  Helper macro to calculate the SYSCLK frequency
1544   * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
1545   * @param  __SYSPRESCALER__ This parameter can be one of the following values:
1546   *         @arg @ref LL_RCC_SYSCLK_DIV_1
1547   *         @arg @ref LL_RCC_SYSCLK_DIV_2
1548   *         @arg @ref LL_RCC_SYSCLK_DIV_4
1549   *         @arg @ref LL_RCC_SYSCLK_DIV_8
1550   *         @arg @ref LL_RCC_SYSCLK_DIV_16
1551   *         @arg @ref LL_RCC_SYSCLK_DIV_64
1552   *         @arg @ref LL_RCC_SYSCLK_DIV_128
1553   *         @arg @ref LL_RCC_SYSCLK_DIV_256
1554   *         @arg @ref LL_RCC_SYSCLK_DIV_512
1555   * @retval SYSCLK clock frequency (in Hz)
1556   */
1557 #if defined(RCC_D1CFGR_D1CPRE)
1558 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
1559 #else
1560 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
1561 #endif /* RCC_D1CFGR_D1CPRE */
1562 
1563 /**
1564   * @brief  Helper macro to calculate the HCLK frequency
1565   * @param  __SYSCLKFREQ__ SYSCLK frequency.
1566   * @param  __HPRESCALER__ This parameter can be one of the following values:
1567   *         @arg @ref LL_RCC_AHB_DIV_1
1568   *         @arg @ref LL_RCC_AHB_DIV_2
1569   *         @arg @ref LL_RCC_AHB_DIV_4
1570   *         @arg @ref LL_RCC_AHB_DIV_8
1571   *         @arg @ref LL_RCC_AHB_DIV_16
1572   *         @arg @ref LL_RCC_AHB_DIV_64
1573   *         @arg @ref LL_RCC_AHB_DIV_128
1574   *         @arg @ref LL_RCC_AHB_DIV_256
1575   *         @arg @ref LL_RCC_AHB_DIV_512
1576   * @retval HCLK clock frequency (in Hz)
1577   */
1578 #if defined(RCC_D1CFGR_HPRE)
1579 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
1580 #else
1581 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
1582 #endif  /* RCC_D1CFGR_HPRE */
1583 
1584 /**
1585   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
1586   * @param  __HCLKFREQ__ HCLK frequency
1587   * @param  __APB1PRESCALER__ This parameter can be one of the following values:
1588   *         @arg @ref LL_RCC_APB1_DIV_1
1589   *         @arg @ref LL_RCC_APB1_DIV_2
1590   *         @arg @ref LL_RCC_APB1_DIV_4
1591   *         @arg @ref LL_RCC_APB1_DIV_8
1592   *         @arg @ref LL_RCC_APB1_DIV_16
1593   * @retval PCLK1 clock frequency (in Hz)
1594   */
1595 #if defined(RCC_D2CFGR_D2PPRE1)
1596 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
1597 #else
1598 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
1599 #endif /* RCC_D2CFGR_D2PPRE1 */
1600 
1601 /**
1602   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
1603   * @param  __HCLKFREQ__ HCLK frequency
1604   * @param  __APB2PRESCALER__ This parameter can be one of the following values:
1605   *         @arg @ref LL_RCC_APB2_DIV_1
1606   *         @arg @ref LL_RCC_APB2_DIV_2
1607   *         @arg @ref LL_RCC_APB2_DIV_4
1608   *         @arg @ref LL_RCC_APB2_DIV_8
1609   *         @arg @ref LL_RCC_APB2_DIV_16
1610   * @retval PCLK2 clock frequency (in Hz)
1611   */
1612 #if defined(RCC_D2CFGR_D2PPRE2)
1613 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
1614 #else
1615 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
1616 #endif /* RCC_D2CFGR_D2PPRE2 */
1617 
1618 /**
1619   * @brief  Helper macro to calculate the PCLK3 frequency (APB3)
1620   * @param  __HCLKFREQ__ HCLK frequency
1621   * @param  __APB3PRESCALER__ This parameter can be one of the following values:
1622   *         @arg @ref LL_RCC_APB3_DIV_1
1623   *         @arg @ref LL_RCC_APB3_DIV_2
1624   *         @arg @ref LL_RCC_APB3_DIV_4
1625   *         @arg @ref LL_RCC_APB3_DIV_8
1626   *         @arg @ref LL_RCC_APB3_DIV_16
1627   * @retval PCLK1 clock frequency (in Hz)
1628   */
1629 #if defined(RCC_D1CFGR_D1PPRE)
1630 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
1631 #else
1632 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
1633 #endif /* RCC_D1CFGR_D1PPRE */
1634 
1635 /**
1636   * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)
1637   * @param  __HCLKFREQ__ HCLK frequency
1638   * @param  __APB4PRESCALER__ This parameter can be one of the following values:
1639   *         @arg @ref LL_RCC_APB4_DIV_1
1640   *         @arg @ref LL_RCC_APB4_DIV_2
1641   *         @arg @ref LL_RCC_APB4_DIV_4
1642   *         @arg @ref LL_RCC_APB4_DIV_8
1643   *         @arg @ref LL_RCC_APB4_DIV_16
1644   * @retval PCLK1 clock frequency (in Hz)
1645   */
1646 #if defined(RCC_D3CFGR_D3PPRE)
1647 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
1648 #else
1649 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
1650 #endif /* RCC_D3CFGR_D3PPRE */
1651 
1652 /**
1653   * @}
1654   */
1655 
1656 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
1657 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1658   * @ingroup RTEMSBSPsARMSTM32H7
1659   * @{
1660   */
1661 #define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
1662 #define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
1663 /**
1664   * @}
1665   */
1666 #endif /* USE_FULL_LL_DRIVER */
1667 
1668 /**
1669   * @}
1670   */
1671 
1672 /* Exported functions --------------------------------------------------------*/
1673 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1674   * @ingroup RTEMSBSPsARMSTM32H7
1675   * @{
1676   */
1677 
1678 /** @defgroup RCC_LL_EF_HSE HSE
1679   * @ingroup RTEMSBSPsARMSTM32H7
1680   * @{
1681   */
1682 
1683 /**
1684   * @brief  Enable the Clock Security System.
1685   * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1686   *       a reset occurs or system enter in standby mode.
1687   * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS
1688   * @retval None
1689   */
1690 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1691 {
1692   SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
1693 }
1694 
1695 /**
1696   * @brief  Enable HSE external oscillator (HSE Bypass)
1697   * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
1698   * @retval None
1699   */
1700 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1701 {
1702   SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1703 }
1704 
1705 /**
1706   * @brief  Disable HSE external oscillator (HSE Bypass)
1707   * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
1708   * @retval None
1709   */
1710 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1711 {
1712   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1713 }
1714 
1715 #if defined(RCC_CR_HSEEXT)
1716 /**
1717   * @brief  Select the Analog HSE external clock type in Bypass mode
1718   * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock
1719   * @retval None
1720   */
1721 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1722 {
1723   CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
1724 }
1725 
1726 /**
1727   * @brief  Select the Digital HSE external clock type in Bypass mode
1728   * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock
1729   * @retval None
1730   */
1731 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1732 {
1733   SET_BIT(RCC->CR, RCC_CR_HSEEXT);
1734 }
1735 #endif /* RCC_CR_HSEEXT */
1736 
1737 /**
1738   * @brief  Enable HSE crystal oscillator (HSE ON)
1739   * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
1740   * @retval None
1741   */
1742 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1743 {
1744   SET_BIT(RCC->CR, RCC_CR_HSEON);
1745 }
1746 
1747 /**
1748   * @brief  Disable HSE crystal oscillator (HSE ON)
1749   * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
1750   * @retval None
1751   */
1752 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1753 {
1754   CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1755 }
1756 
1757 /**
1758   * @brief  Check if HSE oscillator Ready
1759   * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
1760   * @retval State of bit (1 or 0).
1761   */
1762 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1763 {
1764   return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1765 }
1766 
1767 /**
1768   * @}
1769   */
1770 
1771 /** @defgroup RCC_LL_EF_HSI HSI
1772   * @ingroup RTEMSBSPsARMSTM32H7
1773   * @{
1774   */
1775 
1776 /**
1777   * @brief  Enable HSI oscillator
1778   * @rmtoll CR           HSION         LL_RCC_HSI_Enable
1779   * @retval None
1780   */
1781 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1782 {
1783   SET_BIT(RCC->CR, RCC_CR_HSION);
1784 }
1785 
1786 /**
1787   * @brief  Disable HSI oscillator
1788   * @rmtoll CR           HSION         LL_RCC_HSI_Disable
1789   * @retval None
1790   */
1791 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1792 {
1793   CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1794 }
1795 
1796 /**
1797   * @brief  Check if HSI clock is ready
1798   * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
1799   * @retval State of bit (1 or 0).
1800   */
1801 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1802 {
1803   return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1804 }
1805 
1806 /**
1807   * @brief  Check if HSI new divider applied and ready
1808   * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady
1809   * @retval State of bit (1 or 0).
1810   */
1811 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1812 {
1813   return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);
1814 }
1815 
1816 /**
1817   * @brief  Set HSI divider
1818   * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider
1819   * @param  Divider This parameter can be one of the following values:
1820   *         @arg @ref LL_RCC_HSI_DIV1
1821   *         @arg @ref LL_RCC_HSI_DIV2
1822   *         @arg @ref LL_RCC_HSI_DIV4
1823   *         @arg @ref LL_RCC_HSI_DIV8
1824   * @retval None.
1825   */
1826 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1827 {
1828   MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1829 }
1830 
1831 /**
1832   * @brief  Get HSI divider
1833   * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider
1834   * @retval can be one of the following values:
1835   *         @arg @ref LL_RCC_HSI_DIV1
1836   *         @arg @ref LL_RCC_HSI_DIV2
1837   *         @arg @ref LL_RCC_HSI_DIV4
1838   *         @arg @ref LL_RCC_HSI_DIV8
1839   */
1840 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1841 {
1842   return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1843 }
1844 
1845 /**
1846   * @brief  Enable HSI oscillator in Stop mode
1847   * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode
1848   * @retval None
1849   */
1850 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
1851 {
1852   SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1853 }
1854 
1855 /**
1856   * @brief  Disable HSI oscillator in Stop mode
1857   * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode
1858   * @retval None
1859   */
1860 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
1861 {
1862   CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1863 }
1864 
1865 /**
1866   * @brief  Get HSI Calibration value
1867   * @note When HSITRIM is written, HSICAL is updated with the sum of
1868   *       HSITRIM and the factory trim value
1869   * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration
1870   * @retval A value between 0 and 4095 (0xFFF)
1871   */
1872 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1873 {
1874   return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1875 }
1876 
1877 /**
1878   * @brief  Set HSI Calibration trimming
1879   * @note user-programmable trimming value that is added to the HSICAL
1880   * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
1881   *       should trim the HSI to 64 MHz +/- 1 %
1882   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
1883   * @param  Value can be a value between 0 and 127 (63 for Cut1.x)
1884   * @retval None
1885   */
1886 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1887 {
1888 #if defined(RCC_VER_X)
1889   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1890   {
1891     /* STM32H7 Rev.Y */
1892     MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
1893   }
1894   else
1895   {
1896     /* STM32H7 Rev.V */
1897     MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1898   }
1899 #else
1900   MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1901 #endif /* RCC_VER_X */
1902 }
1903 
1904 /**
1905   * @brief  Get HSI Calibration trimming
1906   * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
1907   * @retval A value between 0 and 127 (63 for Cut1.x)
1908   */
1909 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1910 {
1911 #if defined(RCC_VER_X)
1912   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1913   {
1914     /* STM32H7 Rev.Y */
1915     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
1916   }
1917   else
1918   {
1919     /* STM32H7 Rev.V */
1920     return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1921   }
1922 #else
1923   return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1924 #endif /* RCC_VER_X */
1925 }
1926 
1927 /**
1928   * @}
1929   */
1930 
1931 /** @defgroup RCC_LL_EF_CSI CSI
1932   * @ingroup RTEMSBSPsARMSTM32H7
1933   * @{
1934   */
1935 
1936 /**
1937   * @brief  Enable CSI oscillator
1938   * @rmtoll CR           CSION         LL_RCC_CSI_Enable
1939   * @retval None
1940   */
1941 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1942 {
1943   SET_BIT(RCC->CR, RCC_CR_CSION);
1944 }
1945 
1946 /**
1947   * @brief  Disable CSI oscillator
1948   * @rmtoll CR           CSION         LL_RCC_CSI_Disable
1949   * @retval None
1950   */
1951 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1952 {
1953   CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1954 }
1955 
1956 /**
1957   * @brief  Check if CSI clock is ready
1958   * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady
1959   * @retval State of bit (1 or 0).
1960   */
1961 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1962 {
1963   return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);
1964 }
1965 
1966 /**
1967   * @brief  Enable CSI oscillator in Stop mode
1968   * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode
1969   * @retval None
1970   */
1971 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
1972 {
1973   SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1974 }
1975 
1976 /**
1977   * @brief  Disable CSI oscillator in Stop mode
1978   * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode
1979   * @retval None
1980   */
1981 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
1982 {
1983   CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1984 }
1985 
1986 /**
1987   * @brief  Get CSI Calibration value
1988   * @note When CSITRIM is written, CSICAL is updated with the sum of
1989   *       CSITRIM and the factory trim value
1990   * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration
1991   * @retval A value between 0 and 255 (0xFF)
1992   */
1993 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1994 {
1995 #if defined(RCC_VER_X)
1996   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1997   {
1998     /* STM32H7 Rev.Y */
1999     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
2000   }
2001   else
2002   {
2003     /* STM32H7 Rev.V */
2004     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
2005   }
2006 #else
2007   return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
2008 #endif /* RCC_VER_X */
2009 }
2010 
2011 /**
2012   * @brief  Set CSI Calibration trimming
2013   * @note user-programmable trimming value that is added to the CSICAL
2014   * @note Default value is 16, which, when added to the CSICAL value,
2015   *       should trim the CSI to 4 MHz +/- 1 %
2016   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming
2017   * @param  Value can be a value between 0 and 31
2018   * @retval None
2019   */
2020 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
2021 {
2022 #if defined(RCC_VER_X)
2023   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
2024   {
2025     /* STM32H7 Rev.Y */
2026     MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
2027   }
2028   else
2029   {
2030     /* STM32H7 Rev.V */
2031     MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
2032   }
2033 #else
2034   MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
2035 #endif /* RCC_VER_X */
2036 }
2037 
2038 /**
2039   * @brief  Get CSI Calibration trimming
2040   * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming
2041   * @retval A value between 0 and 31
2042   */
2043 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
2044 {
2045 #if defined(RCC_VER_X)
2046   if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
2047   {
2048     /* STM32H7 Rev.Y */
2049     return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
2050   }
2051   else
2052   {
2053     /* STM32H7 Rev.V */
2054     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
2055   }
2056 #else
2057   return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
2058 #endif /* RCC_VER_X */
2059 }
2060 
2061 /**
2062   * @}
2063   */
2064 
2065 /** @defgroup RCC_LL_EF_HSI48 HSI48
2066   * @ingroup RTEMSBSPsARMSTM32H7
2067   * @{
2068   */
2069 
2070 /**
2071   * @brief  Enable HSI48 oscillator
2072   * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable
2073   * @retval None
2074   */
2075 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
2076 {
2077   SET_BIT(RCC->CR, RCC_CR_HSI48ON);
2078 }
2079 
2080 /**
2081   * @brief  Disable HSI48 oscillator
2082   * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable
2083   * @retval None
2084   */
2085 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2086 {
2087   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
2088 }
2089 
2090 /**
2091   * @brief  Check if HSI48 clock is ready
2092   * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady
2093   * @retval State of bit (1 or 0).
2094   */
2095 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2096 {
2097   return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL);
2098 }
2099 
2100 /**
2101   * @brief  Get HSI48 Calibration value
2102   * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
2103   *       HSI48TRIM and the factory trim value
2104   * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration
2105   * @retval A value between 0 and 1023 (0x3FF)
2106   */
2107 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2108 {
2109   return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2110 }
2111 /**
2112   * @}
2113   */
2114 
2115 #if defined(RCC_CR_D1CKRDY)
2116 
2117 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY
2118   * @ingroup RTEMSBSPsARMSTM32H7
2119   * @{
2120   */
2121 
2122 /**
2123   * @brief  Check if D1 clock is ready
2124   * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady
2125   * @retval State of bit (1 or 0).
2126   */
2127 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
2128 {
2129   return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL);
2130 }
2131 
2132 /**
2133   * @}
2134   */
2135 #else
2136 
2137 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
2138   * @ingroup RTEMSBSPsARMSTM32H7
2139   * @{
2140   */
2141 
2142 /**
2143   * @brief  Check if CPU clock is ready
2144   * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady
2145   * @retval State of bit (1 or 0).
2146   */
2147 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
2148 {
2149   return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL);
2150 }
2151 /* alias */
2152 #define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
2153 /**
2154   * @}
2155   */
2156 #endif /* RCC_CR_D1CKRDY */
2157 
2158 #if defined(RCC_CR_D2CKRDY)
2159 
2160 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY
2161   * @ingroup RTEMSBSPsARMSTM32H7
2162   * @{
2163   */
2164 
2165 /**
2166   * @brief  Check if D2 clock is ready
2167   * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady
2168   * @retval State of bit (1 or 0).
2169   */
2170 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
2171 {
2172   return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL);
2173 }
2174 /**
2175   * @}
2176   */
2177 #else
2178 
2179 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY
2180   * @ingroup RTEMSBSPsARMSTM32H7
2181   * @{
2182   */
2183 
2184 /**
2185   * @brief  Check if CD clock is ready
2186   * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady
2187   * @retval State of bit (1 or 0).
2188   */
2189 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
2190 {
2191   return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL);
2192 }
2193 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
2194 /**
2195   * @}
2196   */
2197 #endif /* RCC_CR_D2CKRDY */
2198 
2199 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
2200   * @ingroup RTEMSBSPsARMSTM32H7
2201   * @{
2202   */
2203 #if defined(RCC_GCR_WW1RSC)
2204 
2205 /**
2206   * @brief  Enable system wide reset for Window Watch Dog 1
2207   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset
2208   * @retval None.
2209   */
2210 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
2211 {
2212   SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
2213 }
2214 
2215 /**
2216   * @brief  Check if Window Watch Dog 1 reset is system wide
2217   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset
2218   * @retval State of bit (1 or 0).
2219   */
2220 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
2221 {
2222   return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL);
2223 }
2224 #endif  /* RCC_GCR_WW1RSC */
2225 
2226 #if defined(DUAL_CORE)
2227 /**
2228   * @brief  Enable system wide reset for Window Watch Dog 2
2229   * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset
2230   * @retval None.
2231   */
2232 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
2233 {
2234   SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
2235 }
2236 
2237 /**
2238   * @brief  Check if Window Watch Dog 2 reset is system wide
2239   * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset
2240   * @retval State of bit (1 or 0).
2241   */
2242 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
2243 {
2244   return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL);
2245 }
2246 #endif  /*DUAL_CORE*/
2247 /**
2248   * @}
2249   */
2250 
2251 #if defined(DUAL_CORE)
2252 /** @defgroup RCC_LL_EF_BOOT_CPU CPU
2253   * @ingroup RTEMSBSPsARMSTM32H7
2254   * @{
2255   */
2256 
2257 /**
2258   * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)
2259   * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot
2260   * @retval None.
2261   */
2262 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
2263 {
2264   SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
2265 }
2266 
2267 /**
2268   * @brief  Check if CM4 boot is forced
2269   * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced
2270   * @retval State of bit (1 or 0).
2271   */
2272 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
2273 {
2274   return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL);
2275 }
2276 
2277 /**
2278   * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)
2279   * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot
2280   * @retval None.
2281   */
2282 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
2283 {
2284   SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
2285 }
2286 
2287 /**
2288   * @brief  Check if CM7 boot is forced
2289   * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced
2290   * @retval State of bit (1 or 0).
2291   */
2292 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
2293 {
2294   return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL);
2295 }
2296 
2297 /**
2298   * @}
2299   */
2300 #endif  /*DUAL_CORE*/
2301 
2302 /** @defgroup RCC_LL_EF_LSE LSE
2303   * @ingroup RTEMSBSPsARMSTM32H7
2304   * @{
2305   */
2306 
2307 /**
2308   * @brief  Enable the Clock Security System on LSE.
2309   * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2310   *       a clock failure is detected.
2311   * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS
2312   * @retval None
2313   */
2314 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2315 {
2316   SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2317 }
2318 
2319 /**
2320   * @brief  Check if LSE failure is detected by Clock Security System
2321   * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected
2322   * @retval State of bit (1 or 0).
2323   */
2324 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
2325 {
2326   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
2327 }
2328 
2329 /**
2330   * @brief  Enable  Low Speed External (LSE) crystal.
2331   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
2332   * @retval None
2333   */
2334 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2335 {
2336   SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2337 }
2338 
2339 /**
2340   * @brief  Disable  Low Speed External (LSE) crystal.
2341   * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
2342   * @retval None
2343   */
2344 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2345 {
2346   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2347 }
2348 
2349 /**
2350   * @brief  Enable external clock source (LSE bypass).
2351   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
2352   * @retval None
2353   */
2354 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2355 {
2356   SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2357 }
2358 
2359 /**
2360   * @brief  Disable external clock source (LSE bypass).
2361   * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
2362   * @retval None
2363   */
2364 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2365 {
2366   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2367 }
2368 
2369 #if defined(RCC_BDCR_LSEEXT)
2370 /**
2371   * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
2372   * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
2373   *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
2374   * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock
2375   * @retval None
2376   */
2377 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
2378 {
2379   SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2380 }
2381 
2382 /**
2383   * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
2384   * @note   The external clock must be enabled with the LSEON bit, to be used by the device.
2385   *         The LSEEXT bit can be written only if the LSE oscillator is disabled.
2386   * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock
2387   * @retval None
2388   */
2389 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
2390 {
2391   CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2392 }
2393 #endif /* RCC_BDCR_LSEEXT */
2394 
2395 /**
2396   * @brief  Set LSE oscillator drive capability
2397   * @note The oscillator is in Xtal mode when it is not in bypass mode.
2398   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability
2399   * @param  LSEDrive This parameter can be one of the following values:
2400   *         @arg @ref LL_RCC_LSEDRIVE_LOW
2401   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2402   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2403   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
2404   * @retval None
2405   */
2406 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2407 {
2408   MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2409 }
2410 
2411 /**
2412   * @brief  Get LSE oscillator drive capability
2413   * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability
2414   * @retval Returned value can be one of the following values:
2415   *         @arg @ref LL_RCC_LSEDRIVE_LOW
2416   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2417   *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2418   *         @arg @ref LL_RCC_LSEDRIVE_HIGH
2419   */
2420 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2421 {
2422   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2423 }
2424 
2425 /**
2426   * @brief  Check if LSE oscillator Ready
2427   * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
2428   * @retval State of bit (1 or 0).
2429   */
2430 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2431 {
2432   return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
2433 }
2434 
2435 /**
2436   * @}
2437   */
2438 
2439 /** @defgroup RCC_LL_EF_LSI LSI
2440   * @ingroup RTEMSBSPsARMSTM32H7
2441   * @{
2442   */
2443 
2444 /**
2445   * @brief  Enable LSI Oscillator
2446   * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
2447   * @retval None
2448   */
2449 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2450 {
2451   SET_BIT(RCC->CSR, RCC_CSR_LSION);
2452 }
2453 
2454 /**
2455   * @brief  Disable LSI Oscillator
2456   * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
2457   * @retval None
2458   */
2459 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2460 {
2461   CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2462 }
2463 
2464 /**
2465   * @brief  Check if LSI is Ready
2466   * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
2467   * @retval State of bit (1 or 0).
2468   */
2469 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2470 {
2471   return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
2472 }
2473 
2474 /**
2475   * @}
2476   */
2477 
2478 /** @defgroup RCC_LL_EF_System System
2479   * @ingroup RTEMSBSPsARMSTM32H7
2480   * @{
2481   */
2482 
2483 /**
2484   * @brief  Configure the system clock source
2485   * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
2486   * @param  Source This parameter can be one of the following values:
2487   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2488   *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2489   *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2490   *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2491   * @retval None
2492   */
2493 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2494 {
2495   MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2496 }
2497 
2498 /**
2499   * @brief  Get the system clock source
2500   * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
2501   * @retval Returned value can be one of the following values:
2502   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2503   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2504   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2505   *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2506   */
2507 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2508 {
2509   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2510 }
2511 
2512 /**
2513   * @brief  Configure the system wakeup clock source
2514   * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource
2515   * @param  Source This parameter can be one of the following values:
2516   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2517   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2518   * @retval None
2519   */
2520 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2521 {
2522   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
2523 }
2524 
2525 /**
2526   * @brief  Get the system wakeup clock source
2527   * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource
2528   * @retval Returned value can be one of the following values:
2529   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2530   *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2531   */
2532 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2533 {
2534   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2535 }
2536 
2537 /**
2538   * @brief  Configure the kernel wakeup clock source
2539   * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource
2540   * @param  Source This parameter can be one of the following values:
2541   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2542   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2543   * @retval None
2544   */
2545 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
2546 {
2547   MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
2548 }
2549 
2550 /**
2551   * @brief  Get the kernel wakeup clock source
2552   * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource
2553   * @retval Returned value can be one of the following values:
2554   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2555   *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2556   */
2557 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
2558 {
2559   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
2560 }
2561 
2562 /**
2563   * @brief  Set System prescaler
2564   * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler
2565   * @param  Prescaler This parameter can be one of the following values:
2566   *         @arg @ref LL_RCC_SYSCLK_DIV_1
2567   *         @arg @ref LL_RCC_SYSCLK_DIV_2
2568   *         @arg @ref LL_RCC_SYSCLK_DIV_4
2569   *         @arg @ref LL_RCC_SYSCLK_DIV_8
2570   *         @arg @ref LL_RCC_SYSCLK_DIV_16
2571   *         @arg @ref LL_RCC_SYSCLK_DIV_64
2572   *         @arg @ref LL_RCC_SYSCLK_DIV_128
2573   *         @arg @ref LL_RCC_SYSCLK_DIV_256
2574   *         @arg @ref LL_RCC_SYSCLK_DIV_512
2575   * @retval None
2576   */
2577 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
2578 {
2579 #if defined(RCC_D1CFGR_D1CPRE)
2580   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
2581 #else
2582   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
2583 #endif /* RCC_D1CFGR_D1CPRE */
2584 }
2585 
2586 /**
2587   * @brief  Set AHB prescaler
2588   * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler
2589   * @param  Prescaler This parameter can be one of the following values:
2590   *         @arg @ref LL_RCC_AHB_DIV_1
2591   *         @arg @ref LL_RCC_AHB_DIV_2
2592   *         @arg @ref LL_RCC_AHB_DIV_4
2593   *         @arg @ref LL_RCC_AHB_DIV_8
2594   *         @arg @ref LL_RCC_AHB_DIV_16
2595   *         @arg @ref LL_RCC_AHB_DIV_64
2596   *         @arg @ref LL_RCC_AHB_DIV_128
2597   *         @arg @ref LL_RCC_AHB_DIV_256
2598   *         @arg @ref LL_RCC_AHB_DIV_512
2599   * @retval None
2600   */
2601 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2602 {
2603 #if defined(RCC_D1CFGR_HPRE)
2604   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
2605 #else
2606   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
2607 #endif /* RCC_D1CFGR_HPRE */
2608 }
2609 
2610 /**
2611   * @brief  Set APB1 prescaler
2612   * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler
2613   * @param  Prescaler This parameter can be one of the following values:
2614   *         @arg @ref LL_RCC_APB1_DIV_1
2615   *         @arg @ref LL_RCC_APB1_DIV_2
2616   *         @arg @ref LL_RCC_APB1_DIV_4
2617   *         @arg @ref LL_RCC_APB1_DIV_8
2618   *         @arg @ref LL_RCC_APB1_DIV_16
2619   * @retval None
2620   */
2621 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2622 {
2623 #if defined(RCC_D2CFGR_D2PPRE1)
2624   MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
2625 #else
2626   MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
2627 #endif /* RCC_D2CFGR_D2PPRE1 */
2628 }
2629 
2630 /**
2631   * @brief  Set APB2 prescaler
2632   * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler
2633   * @param  Prescaler This parameter can be one of the following values:
2634   *         @arg @ref LL_RCC_APB2_DIV_1
2635   *         @arg @ref LL_RCC_APB2_DIV_2
2636   *         @arg @ref LL_RCC_APB2_DIV_4
2637   *         @arg @ref LL_RCC_APB2_DIV_8
2638   *         @arg @ref LL_RCC_APB2_DIV_16
2639   * @retval None
2640   */
2641 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2642 {
2643 #if defined(RCC_D2CFGR_D2PPRE2)
2644   MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
2645 #else
2646   MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
2647 #endif /* RCC_D2CFGR_D2PPRE2 */
2648 }
2649 
2650 /**
2651   * @brief  Set APB3 prescaler
2652   * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler
2653   * @param  Prescaler This parameter can be one of the following values:
2654   *         @arg @ref LL_RCC_APB3_DIV_1
2655   *         @arg @ref LL_RCC_APB3_DIV_2
2656   *         @arg @ref LL_RCC_APB3_DIV_4
2657   *         @arg @ref LL_RCC_APB3_DIV_8
2658   *         @arg @ref LL_RCC_APB3_DIV_16
2659   * @retval None
2660   */
2661 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2662 {
2663 #if defined(RCC_D1CFGR_D1PPRE)
2664   MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
2665 #else
2666   MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
2667 #endif /* RCC_D1CFGR_D1PPRE */
2668 }
2669 
2670 /**
2671   * @brief  Set APB4 prescaler
2672   * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler
2673   * @param  Prescaler This parameter can be one of the following values:
2674   *         @arg @ref LL_RCC_APB4_DIV_1
2675   *         @arg @ref LL_RCC_APB4_DIV_2
2676   *         @arg @ref LL_RCC_APB4_DIV_4
2677   *         @arg @ref LL_RCC_APB4_DIV_8
2678   *         @arg @ref LL_RCC_APB4_DIV_16
2679   * @retval None
2680   */
2681 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2682 {
2683 #if defined(RCC_D3CFGR_D3PPRE)
2684   MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
2685 #else
2686   MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
2687 #endif /* RCC_D3CFGR_D3PPRE */
2688 }
2689 
2690 /**
2691   * @brief  Get System prescaler
2692   * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler
2693   * @retval Returned value can be one of the following values:
2694   *         @arg @ref LL_RCC_SYSCLK_DIV_1
2695   *         @arg @ref LL_RCC_SYSCLK_DIV_2
2696   *         @arg @ref LL_RCC_SYSCLK_DIV_4
2697   *         @arg @ref LL_RCC_SYSCLK_DIV_8
2698   *         @arg @ref LL_RCC_SYSCLK_DIV_16
2699   *         @arg @ref LL_RCC_SYSCLK_DIV_64
2700   *         @arg @ref LL_RCC_SYSCLK_DIV_128
2701   *         @arg @ref LL_RCC_SYSCLK_DIV_256
2702   *         @arg @ref LL_RCC_SYSCLK_DIV_512
2703   */
2704 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
2705 {
2706 #if defined(RCC_D1CFGR_D1CPRE)
2707   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
2708 #else
2709   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
2710 #endif /* RCC_D1CFGR_D1CPRE */
2711 }
2712 
2713 /**
2714   * @brief  Get AHB prescaler
2715   * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler
2716   * @retval Returned value can be one of the following values:
2717   *         @arg @ref LL_RCC_AHB_DIV_1
2718   *         @arg @ref LL_RCC_AHB_DIV_2
2719   *         @arg @ref LL_RCC_AHB_DIV_4
2720   *         @arg @ref LL_RCC_AHB_DIV_8
2721   *         @arg @ref LL_RCC_AHB_DIV_16
2722   *         @arg @ref LL_RCC_AHB_DIV_64
2723   *         @arg @ref LL_RCC_AHB_DIV_128
2724   *         @arg @ref LL_RCC_AHB_DIV_256
2725   *         @arg @ref LL_RCC_AHB_DIV_512
2726   */
2727 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2728 {
2729 #if defined(RCC_D1CFGR_HPRE)
2730   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
2731 #else
2732   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
2733 #endif /* RCC_D1CFGR_HPRE */
2734 }
2735 
2736 /**
2737   * @brief  Get APB1 prescaler
2738   * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler
2739   * @retval Returned value can be one of the following values:
2740   *         @arg @ref LL_RCC_APB1_DIV_1
2741   *         @arg @ref LL_RCC_APB1_DIV_2
2742   *         @arg @ref LL_RCC_APB1_DIV_4
2743   *         @arg @ref LL_RCC_APB1_DIV_8
2744   *         @arg @ref LL_RCC_APB1_DIV_16
2745   */
2746 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2747 {
2748 #if defined(RCC_D2CFGR_D2PPRE1)
2749   return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
2750 #else
2751   return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
2752 #endif /* RCC_D2CFGR_D2PPRE1 */
2753 }
2754 
2755 /**
2756   * @brief  Get APB2 prescaler
2757   * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler
2758   * @retval Returned value can be one of the following values:
2759   *         @arg @ref LL_RCC_APB2_DIV_1
2760   *         @arg @ref LL_RCC_APB2_DIV_2
2761   *         @arg @ref LL_RCC_APB2_DIV_4
2762   *         @arg @ref LL_RCC_APB2_DIV_8
2763   *         @arg @ref LL_RCC_APB2_DIV_16
2764   */
2765 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2766 {
2767 #if defined(RCC_D2CFGR_D2PPRE2)
2768   return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
2769 #else
2770   return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
2771 #endif /* RCC_D2CFGR_D2PPRE2 */
2772 }
2773 
2774 /**
2775   * @brief  Get APB3 prescaler
2776   * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler
2777   * @retval Returned value can be one of the following values:
2778   *         @arg @ref LL_RCC_APB3_DIV_1
2779   *         @arg @ref LL_RCC_APB3_DIV_2
2780   *         @arg @ref LL_RCC_APB3_DIV_4
2781   *         @arg @ref LL_RCC_APB3_DIV_8
2782   *         @arg @ref LL_RCC_APB3_DIV_16
2783   */
2784 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2785 {
2786 #if defined(RCC_D1CFGR_D1PPRE)
2787   return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
2788 #else
2789   return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
2790 #endif /* RCC_D1CFGR_D1PPRE */
2791 }
2792 
2793 /**
2794   * @brief  Get APB4 prescaler
2795   * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler
2796   * @retval Returned value can be one of the following values:
2797   *         @arg @ref LL_RCC_APB4_DIV_1
2798   *         @arg @ref LL_RCC_APB4_DIV_2
2799   *         @arg @ref LL_RCC_APB4_DIV_4
2800   *         @arg @ref LL_RCC_APB4_DIV_8
2801   *         @arg @ref LL_RCC_APB4_DIV_16
2802   */
2803 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2804 {
2805 #if defined(RCC_D3CFGR_D3PPRE)
2806   return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
2807 #else
2808   return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
2809 #endif /* RCC_D3CFGR_D3PPRE */
2810 }
2811 
2812 /**
2813   * @}
2814   */
2815 
2816 /** @defgroup RCC_LL_EF_MCO MCO
2817   * @ingroup RTEMSBSPsARMSTM32H7
2818   * @{
2819   */
2820 
2821 /**
2822   * @brief  Configure MCOx
2823   * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
2824   *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
2825   *         CFGR         MCO2          LL_RCC_ConfigMCO\n
2826   *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
2827   * @param  MCOxSource This parameter can be one of the following values:
2828   *         @arg @ref LL_RCC_MCO1SOURCE_HSI
2829   *         @arg @ref LL_RCC_MCO1SOURCE_LSE
2830   *         @arg @ref LL_RCC_MCO1SOURCE_HSE
2831   *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
2832   *         @arg @ref LL_RCC_MCO1SOURCE_HSI48
2833   *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2834   *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
2835   *         @arg @ref LL_RCC_MCO2SOURCE_HSE
2836   *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
2837   *         @arg @ref LL_RCC_MCO2SOURCE_CSI
2838   *         @arg @ref LL_RCC_MCO2SOURCE_LSI
2839   * @param  MCOxPrescaler This parameter can be one of the following values:
2840   *         @arg @ref LL_RCC_MCO1_DIV_1
2841   *         @arg @ref LL_RCC_MCO1_DIV_2
2842   *         @arg @ref LL_RCC_MCO1_DIV_3
2843   *         @arg @ref LL_RCC_MCO1_DIV_4
2844   *         @arg @ref LL_RCC_MCO1_DIV_5
2845   *         @arg @ref LL_RCC_MCO1_DIV_6
2846   *         @arg @ref LL_RCC_MCO1_DIV_7
2847   *         @arg @ref LL_RCC_MCO1_DIV_8
2848   *         @arg @ref LL_RCC_MCO1_DIV_9
2849   *         @arg @ref LL_RCC_MCO1_DIV_10
2850   *         @arg @ref LL_RCC_MCO1_DIV_11
2851   *         @arg @ref LL_RCC_MCO1_DIV_12
2852   *         @arg @ref LL_RCC_MCO1_DIV_13
2853   *         @arg @ref LL_RCC_MCO1_DIV_14
2854   *         @arg @ref LL_RCC_MCO1_DIV_15
2855   *         @arg @ref LL_RCC_MCO2_DIV_1
2856   *         @arg @ref LL_RCC_MCO2_DIV_2
2857   *         @arg @ref LL_RCC_MCO2_DIV_3
2858   *         @arg @ref LL_RCC_MCO2_DIV_4
2859   *         @arg @ref LL_RCC_MCO2_DIV_5
2860   *         @arg @ref LL_RCC_MCO2_DIV_6
2861   *         @arg @ref LL_RCC_MCO2_DIV_7
2862   *         @arg @ref LL_RCC_MCO2_DIV_8
2863   *         @arg @ref LL_RCC_MCO2_DIV_9
2864   *         @arg @ref LL_RCC_MCO2_DIV_10
2865   *         @arg @ref LL_RCC_MCO2_DIV_11
2866   *         @arg @ref LL_RCC_MCO2_DIV_12
2867   *         @arg @ref LL_RCC_MCO2_DIV_13
2868   *         @arg @ref LL_RCC_MCO2_DIV_14
2869   *         @arg @ref LL_RCC_MCO2_DIV_15
2870   * @retval None
2871   */
2872 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2873 {
2874   MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2875 }
2876 
2877 /**
2878   * @}
2879   */
2880 
2881 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2882   * @ingroup RTEMSBSPsARMSTM32H7
2883   * @{
2884   */
2885 
2886 /**
2887   * @brief  Configure periph clock source
2888   * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n
2889   *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n
2890   *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource
2891   * @param  ClkSource This parameter can be one of the following values:
2892   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2893   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2894   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2895   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2896   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2897   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2898   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2899   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2900   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2901   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2902   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2903   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2904   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2905   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2906   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2907   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2908   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2909   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2910   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2911   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2912   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2913   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2914   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2915   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2916   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2917   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2918   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2919   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2920   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2921   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2922   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2923   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2924   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2925   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2926   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2927   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2928   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2929   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2930   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2931   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2932   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2933   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2934   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2935   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
2936   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
2937   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
2938   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
2939   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
2940   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
2941   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
2942   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
2943   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
2944   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
2945   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
2946   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
2947   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
2948   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
2949   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
2950   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
2951   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
2952   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
2953   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
2954   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
2955   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
2956   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
2957   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
2958   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
2959   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
2960   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
2961   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
2962   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
2963   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
2964   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
2965   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
2966   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
2967   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
2968   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2969   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2970   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2971   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2972   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2973   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2974   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2975   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2976   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2977   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2978   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2979   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2980   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
2981   *
2982   *         (*) value not defined in all devices.
2983   * @retval None
2984   */
2985 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2986 {
2987 #if defined(RCC_D1CCIPR_FMCSEL)
2988   uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
2989 #else
2990   uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
2991 #endif /*  */
2992   MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2993 }
2994 
2995 /**
2996   * @brief  Configure USARTx clock source
2997   * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n
2998   *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource
2999   * @param  ClkSource This parameter can be one of the following values:
3000   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3001   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3002   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3003   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3004   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3005   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3006   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3007   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3008   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3009   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3010   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3011   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3012   * @retval None
3013   */
3014 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
3015 {
3016   LL_RCC_SetClockSource(ClkSource);
3017 }
3018 
3019 /**
3020   * @brief  Configure LPUARTx clock source
3021   * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource
3022   * @param  ClkSource This parameter can be one of the following values:
3023   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3024   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3025   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3026   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3027   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3028   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3029   * @retval None
3030   */
3031 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
3032 {
3033 #if defined(RCC_D3CCIPR_LPUART1SEL)
3034   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
3035 #else
3036   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
3037 #endif /* RCC_D3CCIPR_LPUART1SEL */
3038 }
3039 
3040 /**
3041   * @brief  Configure I2Cx clock source
3042   * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n
3043   *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource
3044   * @param  ClkSource This parameter can be one of the following values:
3045   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3046   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3047   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3048   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3049   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3050   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3051   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3052   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3053   * @retval None
3054   */
3055 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
3056 {
3057   LL_RCC_SetClockSource(ClkSource);
3058 }
3059 
3060 /**
3061   * @brief  Configure LPTIMx clock source
3062   * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource
3063   *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n
3064   *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource
3065   * @param  ClkSource This parameter can be one of the following values:
3066   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3067   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3068   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3069   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3070   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3071   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3072   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3073   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3074   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3075   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3076   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3077   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3078   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3079   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3080   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3081   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3082   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3083   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3084   * @retval None
3085   */
3086 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
3087 {
3088   LL_RCC_SetClockSource(ClkSource);
3089 }
3090 
3091 /**
3092   * @brief  Configure SAIx clock source
3093   * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n
3094   *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource
3095   *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n
3096   *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource
3097   * @param  ClkSource This parameter can be one of the following values:
3098   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3099   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3100   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3101   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3102   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3103   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3104   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3105   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3106   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3107   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3108   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3109   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
3110   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)
3111   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)
3112   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF  (*)
3113   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)
3114   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)
3115   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)
3116   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)
3117   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)
3118   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)
3119   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)
3120   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3121   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3122   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3123   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3124   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF  (*)
3125   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3126   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3127   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3128   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3129   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3130   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)
3131   *
3132   *         (*) value not defined in all devices.
3133   * @retval None
3134   */
3135 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
3136 {
3137   LL_RCC_SetClockSource(ClkSource);
3138 }
3139 
3140 /**
3141   * @brief  Configure SDMMCx clock source
3142   * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource
3143   * @param  ClkSource This parameter can be one of the following values:
3144   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3145   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3146   * @retval None
3147   */
3148 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
3149 {
3150 #if defined(RCC_D1CCIPR_SDMMCSEL)
3151   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
3152 #else
3153   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
3154 #endif /* RCC_D1CCIPR_SDMMCSEL */
3155 }
3156 
3157 /**
3158   * @brief  Configure RNGx clock source
3159   * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource
3160   * @param  ClkSource This parameter can be one of the following values:
3161   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3162   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3163   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3164   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3165   * @retval None
3166   */
3167 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
3168 {
3169 #if defined(RCC_D2CCIP2R_RNGSEL)
3170   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
3171 #else
3172   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
3173 #endif /* RCC_D2CCIP2R_RNGSEL */
3174 }
3175 
3176 /**
3177   * @brief  Configure USBx clock source
3178   * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource
3179   * @param  ClkSource This parameter can be one of the following values:
3180   *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3181   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3182   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3183   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3184   * @retval None
3185   */
3186 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
3187 {
3188 #if defined(RCC_D2CCIP2R_USBSEL)
3189   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
3190 #else
3191   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
3192 #endif /* RCC_D2CCIP2R_USBSEL */
3193 }
3194 
3195 /**
3196   * @brief  Configure CECx clock source
3197   * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource
3198   * @param  ClkSource This parameter can be one of the following values:
3199   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3200   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3201   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3202   * @retval None
3203   */
3204 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
3205 {
3206 #if defined(RCC_D2CCIP2R_CECSEL)
3207   MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
3208 #else
3209   MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
3210 #endif /* RCC_D2CCIP2R_CECSEL */
3211 }
3212 
3213 #if defined(DSI)
3214 /**
3215   * @brief  Configure DSIx clock source
3216   * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource
3217   * @param  ClkSource This parameter can be one of the following values:
3218   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3219   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3220   * @retval None
3221   */
3222 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
3223 {
3224   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
3225 }
3226 #endif /* DSI */
3227 
3228 /**
3229   * @brief  Configure DFSDMx Kernel clock source
3230   * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource
3231   * @param  ClkSource This parameter can be one of the following values:
3232   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3233   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3234   * @retval None
3235   */
3236 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
3237 {
3238 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3239   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
3240 #else
3241   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
3242 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3243 }
3244 
3245 #if defined(DFSDM2_BASE)
3246 /**
3247   * @brief  Configure DFSDMx Kernel clock source
3248   * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource
3249   * @param  ClkSource This parameter can be one of the following values:
3250   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3251   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3252   * @retval None
3253   */
3254 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
3255 {
3256   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
3257 }
3258 #endif /* DFSDM2_BASE */
3259 
3260 /**
3261   * @brief  Configure FMCx Kernel clock source
3262   * @rmtoll D1CCIPR /  CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource
3263   * @param  ClkSource This parameter can be one of the following values:
3264   *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3265   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3266   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3267   *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3268   * @retval None
3269   */
3270 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
3271 {
3272 #if defined(RCC_D1CCIPR_FMCSEL)
3273   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
3274 #else
3275   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
3276 #endif /* RCC_D1CCIPR_FMCSEL */
3277 }
3278 
3279 #if defined(QUADSPI)
3280 /**
3281   * @brief  Configure QSPIx Kernel clock source
3282   * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource
3283   * @param  ClkSource This parameter can be one of the following values:
3284   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3285   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3286   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3287   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3288   * @retval None
3289   */
3290 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
3291 {
3292   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
3293 }
3294 #endif /* QUADSPI */
3295 
3296 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3297 /**
3298   * @brief  Configure OSPIx Kernel clock source
3299   * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource
3300   * @param  ClkSource This parameter can be one of the following values:
3301   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3302   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3303   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3304   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3305   * @retval None
3306   */
3307 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
3308 {
3309 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3310   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
3311 #else
3312   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
3313 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3314 }
3315 #endif /* OCTOSPI1 || OCTOSPI2 */
3316 
3317 /**
3318   * @brief  Configure CLKP Kernel clock source
3319   * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource
3320   * @param  ClkSource This parameter can be one of the following values:
3321   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3322   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3323   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3324   * @retval None
3325   */
3326 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3327 {
3328 #if defined(RCC_D1CCIPR_CKPERSEL)
3329   MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
3330 #else
3331   MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
3332 #endif /* RCC_D1CCIPR_CKPERSEL */
3333 }
3334 
3335 /**
3336   * @brief  Configure SPIx Kernel clock source
3337   * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n
3338   *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n
3339   *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource
3340   * @param  ClkSource This parameter can be one of the following values:
3341   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3342   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3343   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3344   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3345   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3346   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3347   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3348   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3349   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3350   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3351   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3352   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3353   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3354   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3355   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3356   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3357   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3358   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3359   *
3360   *         (*) value not defined in all devices.
3361   * @retval None
3362   */
3363 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
3364 {
3365   LL_RCC_SetClockSource(ClkSource);
3366 }
3367 
3368 /**
3369   * @brief  Configure SPDIFx Kernel clock source
3370   * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource
3371   * @param  ClkSource This parameter can be one of the following values:
3372   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3373   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3374   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3375   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3376   * @retval None
3377   */
3378 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
3379 {
3380 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3381   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
3382 #else
3383   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
3384 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3385 }
3386 
3387 /**
3388   * @brief  Configure FDCANx Kernel clock source
3389   * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource
3390   * @param  ClkSource This parameter can be one of the following values:
3391   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3392   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3393   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3394   * @retval None
3395   */
3396 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
3397 {
3398 #if defined(RCC_D2CCIP1R_FDCANSEL)
3399   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
3400 #else
3401   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
3402 #endif /* RCC_D2CCIP1R_FDCANSEL */
3403 }
3404 
3405 /**
3406   * @brief  Configure SWPx Kernel clock source
3407   * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource
3408   * @param  ClkSource This parameter can be one of the following values:
3409   *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3410   *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3411   * @retval None
3412   */
3413 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
3414 {
3415 #if defined(RCC_D2CCIP1R_SWPSEL)
3416   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
3417 #else
3418   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
3419 #endif /* RCC_D2CCIP1R_SWPSEL */
3420 }
3421 
3422 /**
3423   * @brief  Configure ADCx Kernel clock source
3424   * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource
3425   * @param  ClkSource This parameter can be one of the following values:
3426   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3427   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3428   *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3429   * @retval None
3430   */
3431 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
3432 {
3433 #if defined(RCC_D3CCIPR_ADCSEL)
3434   MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
3435 #else
3436   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
3437 #endif /* RCC_D3CCIPR_ADCSEL */
3438 }
3439 
3440 /**
3441   * @brief  Get periph clock source
3442   * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n
3443   *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n
3444   *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n
3445   *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource
3446   * @param  Periph This parameter can be one of the following values:
3447   *         @arg @ref LL_RCC_USART16_CLKSOURCE
3448   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
3449   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
3450   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
3451   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3452   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3453   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3454   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
3455   *         @arg @ref LL_RCC_SAI23_CLKSOURCE
3456   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3457   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3458   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3459   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3460   *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
3461   *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
3462   *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3463   * @retval Returned value can be one of the following values:
3464   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3465   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3466   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3467   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3468   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3469   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3470   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3471   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3472   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3473   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3474   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3475   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3476   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3477   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3478   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3479   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3480   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3481   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3482   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3483   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3484   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3485   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3486   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3487   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3488   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3489   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3490   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3491   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3492   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3493   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3494   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3495   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3496   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3497   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3498   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3499   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3500   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3501   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3502   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3503   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3504   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3505   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3506   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3507   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3508   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3509   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3510   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3511   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3512   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3513   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3514   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3515   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3516   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3517   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3518   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3519   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3520   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3521   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3522   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3523   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3524   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3525   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3526   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3527   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3528   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3529   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3530   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3531   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3532   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3533   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3534   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3535   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3536   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3537   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3538   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3539   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3540   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3541   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3542   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3543   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3544   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3545   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3546   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3547   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3548   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3549   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3550   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3551   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3552   *
3553   *         (*) value not defined in all devices.
3554   * @retval None
3555   */
3556 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3557 {
3558 #if defined(RCC_D1CCIPR_FMCSEL)
3559   const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
3560 #else
3561   const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
3562 #endif /* RCC_D1CCIPR_FMCSEL */
3563   return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
3564 }
3565 
3566 /**
3567   * @brief  Get USARTx clock source
3568   * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n
3569   *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource
3570   * @param  Periph This parameter can be one of the following values:
3571   *         @arg @ref LL_RCC_USART16_CLKSOURCE
3572   *         @arg @ref LL_RCC_USART234578_CLKSOURCE
3573   * @retval Returned value can be one of the following values:
3574   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3575   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3576   *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3577   *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3578   *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3579   *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3580   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3581   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3582   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3583   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3584   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3585   *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3586   */
3587 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
3588 {
3589   return LL_RCC_GetClockSource(Periph);
3590 }
3591 
3592 /**
3593   * @brief  Get LPUART clock source
3594   * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource
3595   * @param  Periph This parameter can be one of the following values:
3596   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
3597   * @retval Returned value can be one of the following values:
3598   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3599   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3600   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3601   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3602   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3603   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3604   */
3605 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
3606 {
3607   UNUSED(Periph);
3608 #if defined(RCC_D3CCIPR_LPUART1SEL)
3609   return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
3610 #else
3611   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
3612 #endif  /* RCC_D3CCIPR_LPUART1SEL */
3613 }
3614 
3615 /**
3616   * @brief  Get I2Cx clock source
3617   * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n
3618   *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource
3619   * @param  Periph This parameter can be one of the following values:
3620   *         @arg @ref LL_RCC_I2C123_CLKSOURCE
3621   *         @arg @ref LL_RCC_I2C4_CLKSOURCE
3622   * @retval Returned value can be one of the following values:
3623   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3624   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3625   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3626   *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3627   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3628   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3629   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3630   *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3631   */
3632 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3633 {
3634   return LL_RCC_GetClockSource(Periph);
3635 }
3636 
3637 /**
3638   * @brief  Get LPTIM clock source
3639   * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n
3640   *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n
3641   *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource
3642   * @param  Periph This parameter can be one of the following values:
3643   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3644   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3645   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3646   * @retval Returned value can be one of the following values:
3647   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3648   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3649   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3650   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3651   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3652   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3653   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3654   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3655   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3656   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3657   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3658   *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3659   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3660   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3661   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3662   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3663   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3664   *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3665   * @retval None
3666   */
3667 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3668 {
3669   return LL_RCC_GetClockSource(Periph);
3670 }
3671 
3672 /**
3673   * @brief  Get SAIx clock source
3674   * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n
3675   *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource
3676   *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n
3677   *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource
3678   * @param  Periph This parameter can be one of the following values:
3679   *         @arg @ref LL_RCC_SAI1_CLKSOURCE    (*)
3680   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE  (*)
3681    *         @arg @ref LL_RCC_SAI2B_CLKSOURCE  (*)
3682   *         @arg @ref LL_RCC_SAI23_CLKSOURCE   (*)
3683   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE   (*)
3684   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE   (*)
3685   * @retval Returned value can be one of the following values:
3686   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3687   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3688   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3689   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3690   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3691   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3692   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3693   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3694   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3695   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3696   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3697   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3698   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3699   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3700   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3701   *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3702   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3703   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3704   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3705   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3706   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3707   *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3708   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3709   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3710   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3711   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3712   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3713   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3714   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3715   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3716   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3717   *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3718   *
3719   *  (*) value not defined in all devices.
3720   */
3721 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3722 {
3723   return LL_RCC_GetClockSource(Periph);
3724 }
3725 
3726 /**
3727   * @brief  Get SDMMC clock source
3728   * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource
3729   * @param  Periph This parameter can be one of the following values:
3730   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE
3731   * @retval Returned value can be one of the following values:
3732   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3733   *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3734   */
3735 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3736 {
3737   UNUSED(Periph);
3738 #if defined(RCC_D1CCIPR_SDMMCSEL)
3739   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
3740 #else
3741   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
3742 #endif /* RCC_D1CCIPR_SDMMCSEL */
3743 }
3744 
3745 /**
3746   * @brief  Get RNG clock source
3747   * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource
3748   * @param  Periph This parameter can be one of the following values:
3749   *         @arg @ref LL_RCC_RNG_CLKSOURCE
3750   * @retval Returned value can be one of the following values:
3751   *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3752   *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3753   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3754   *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3755   */
3756 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
3757 {
3758   UNUSED(Periph);
3759 #if defined(RCC_D2CCIP2R_RNGSEL)
3760   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
3761 #else
3762   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
3763 #endif /* RCC_D2CCIP2R_RNGSEL */
3764 }
3765 
3766 /**
3767   * @brief  Get USB clock source
3768   * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource
3769   * @param  Periph This parameter can be one of the following values:
3770   *         @arg @ref LL_RCC_USB_CLKSOURCE
3771   * @retval Returned value can be one of the following values:
3772   *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3773   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3774   *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3775   *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3776   */
3777 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
3778 {
3779   UNUSED(Periph);
3780 #if defined(RCC_D2CCIP2R_USBSEL)
3781   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
3782 #else
3783   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
3784 #endif /* RCC_D2CCIP2R_USBSEL */
3785 }
3786 
3787 /**
3788   * @brief  Get CEC clock source
3789   * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource
3790   * @param  Periph This parameter can be one of the following values:
3791   *         @arg @ref LL_RCC_CEC_CLKSOURCE
3792   * @retval Returned value can be one of the following values:
3793   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3794   *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3795   *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3796   */
3797 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
3798 {
3799   UNUSED(Periph);
3800 #if defined(RCC_D2CCIP2R_CECSEL)
3801   return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
3802 #else
3803   return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
3804 #endif  /* RCC_D2CCIP2R_CECSEL */
3805 }
3806 
3807 #if defined(DSI)
3808 /**
3809   * @brief  Get DSI clock source
3810   * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource
3811   * @param  Periph This parameter can be one of the following values:
3812   *         @arg @ref LL_RCC_DSI_CLKSOURCE
3813   * @retval Returned value can be one of the following values:
3814   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3815   *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3816   */
3817 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
3818 {
3819   UNUSED(Periph);
3820   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
3821 }
3822 #endif /* DSI */
3823 
3824 /**
3825   * @brief  Get DFSDM Kernel clock source
3826   * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource
3827   * @param  Periph This parameter can be one of the following values:
3828   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3829   * @retval Returned value can be one of the following values:
3830   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3831   *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3832   */
3833 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
3834 {
3835   UNUSED(Periph);
3836 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3837   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
3838 #else
3839   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
3840 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3841 }
3842 
3843 #if defined(DFSDM2_BASE)
3844 /**
3845   * @brief  Get DFSDM2 Kernel clock source
3846   * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource
3847   * @param  Periph This parameter can be one of the following values:
3848   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE
3849   * @retval Returned value can be one of the following values:
3850   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3851   *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3852   */
3853 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
3854 {
3855   UNUSED(Periph);
3856   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
3857 }
3858 #endif /* DFSDM2_BASE */
3859 
3860 /**
3861   * @brief  Get FMC Kernel clock source
3862   * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource
3863   * @param  Periph This parameter can be one of the following values:
3864   *         @arg @ref LL_RCC_FMC_CLKSOURCE
3865   * @retval Returned value can be one of the following values:
3866   *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3867   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3868   *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3869   *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3870   */
3871 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3872 {
3873   UNUSED(Periph);
3874 #if defined(RCC_D1CCIPR_FMCSEL)
3875   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
3876 #else
3877   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
3878 #endif /* RCC_D1CCIPR_FMCSEL */
3879 }
3880 
3881 #if defined(QUADSPI)
3882 /**
3883   * @brief  Get QSPI Kernel clock source
3884   * @rmtoll D1CCIPR  /  CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource
3885   * @param  Periph This parameter can be one of the following values:
3886   *         @arg @ref LL_RCC_QSPI_CLKSOURCE
3887   * @retval Returned value can be one of the following values:
3888   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3889   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3890   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3891   *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3892   */
3893 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
3894 {
3895   UNUSED(Periph);
3896   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
3897 }
3898 #endif /* QUADSPI */
3899 
3900 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3901 /**
3902   * @brief  Get OSPI Kernel clock source
3903   * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource
3904   * @param  Periph This parameter can be one of the following values:
3905   *         @arg @ref LL_RCC_OSPI_CLKSOURCE
3906   * @retval Returned value can be one of the following values:
3907   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3908   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3909   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3910   *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3911   */
3912 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
3913 {
3914   UNUSED(Periph);
3915 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3916   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
3917 #else
3918   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
3919 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3920 }
3921 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3922 
3923 /**
3924   * @brief  Get CLKP Kernel clock source
3925   * @rmtoll D1CCIPR /  CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource
3926   * @param  Periph This parameter can be one of the following values:
3927   *         @arg @ref LL_RCC_CLKP_CLKSOURCE
3928   * @retval Returned value can be one of the following values:
3929   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3930   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3931   *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3932   */
3933 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
3934 {
3935   UNUSED(Periph);
3936 #if defined(RCC_D1CCIPR_CKPERSEL)
3937   return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
3938 #else
3939   return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
3940 #endif /* RCC_D1CCIPR_CKPERSEL */
3941 }
3942 
3943 /**
3944   * @brief  Get SPIx Kernel clock source
3945   * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n
3946   *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n
3947   *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource
3948   * @param  Periph This parameter can be one of the following values:
3949   *         @arg @ref LL_RCC_SPI123_CLKSOURCE
3950   *         @arg @ref LL_RCC_SPI45_CLKSOURCE
3951   *         @arg @ref LL_RCC_SPI6_CLKSOURCE
3952   * @retval Returned value can be one of the following values:
3953   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3954   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3955   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3956   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3957   *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3958   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3959   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3960   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3961   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3962   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3963   *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3964   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3965   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3966   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3967   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3968   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3969   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3970   *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3971   *
3972   *         (*) value not defined in all stm32h7xx lines.
3973   */
3974 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3975 {
3976   return LL_RCC_GetClockSource(Periph);
3977 }
3978 
3979 /**
3980   * @brief  Get SPDIF Kernel clock source
3981   * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource
3982   * @param  Periph This parameter can be one of the following values:
3983   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE
3984   * @retval Returned value can be one of the following values:
3985   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3986   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3987   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3988   *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3989   */
3990 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
3991 {
3992   UNUSED(Periph);
3993 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3994   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
3995 #else
3996   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
3997 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3998 }
3999 
4000 /**
4001   * @brief  Get FDCAN Kernel clock source
4002   * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource
4003   * @param  Periph This parameter can be one of the following values:
4004   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
4005   * @retval Returned value can be one of the following values:
4006   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
4007   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
4008   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
4009   */
4010 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
4011 {
4012   UNUSED(Periph);
4013 #if defined(RCC_D2CCIP1R_FDCANSEL)
4014   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
4015 #else
4016   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
4017 #endif /* RCC_D2CCIP1R_FDCANSEL */
4018 }
4019 
4020 /**
4021   * @brief  Get SWP Kernel clock source
4022   * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource
4023   * @param  Periph This parameter can be one of the following values:
4024   *         @arg @ref LL_RCC_SWP_CLKSOURCE
4025   * @retval Returned value can be one of the following values:
4026   *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
4027   *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
4028   */
4029 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
4030 {
4031   UNUSED(Periph);
4032 #if defined(RCC_D2CCIP1R_SWPSEL)
4033   return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
4034 #else
4035   return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
4036 #endif /* RCC_D2CCIP1R_SWPSEL */
4037 }
4038 
4039 /**
4040   * @brief  Get ADC Kernel clock source
4041   * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource
4042   * @param  Periph This parameter can be one of the following values:
4043   *         @arg @ref LL_RCC_ADC_CLKSOURCE
4044   * @retval Returned value can be one of the following values:
4045   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
4046   *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
4047   *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
4048   */
4049 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
4050 {
4051   UNUSED(Periph);
4052 #if defined (RCC_D3CCIPR_ADCSEL)
4053   return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
4054 #else
4055   return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
4056 #endif /* RCC_D3CCIPR_ADCSEL */
4057 }
4058 
4059 /**
4060   * @}
4061   */
4062 
4063 /** @defgroup RCC_LL_EF_RTC RTC
4064   * @ingroup RTEMSBSPsARMSTM32H7
4065   * @{
4066   */
4067 
4068 /**
4069   * @brief  Set RTC Clock Source
4070   * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless
4071   *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
4072   *         set). The BDRST bit can be used to reset them.
4073   * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
4074   * @param  Source This parameter can be one of the following values:
4075   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4076   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4077   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4078   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4079   * @retval None
4080   */
4081 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
4082 {
4083   MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
4084 }
4085 
4086 /**
4087   * @brief  Get RTC Clock Source
4088   * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
4089   * @retval Returned value can be one of the following values:
4090   *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4091   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4092   *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4093   *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4094   */
4095 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4096 {
4097   return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4098 }
4099 
4100 /**
4101   * @brief  Enable RTC
4102   * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
4103   * @retval None
4104   */
4105 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4106 {
4107   SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4108 }
4109 
4110 /**
4111   * @brief  Disable RTC
4112   * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
4113   * @retval None
4114   */
4115 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4116 {
4117   CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4118 }
4119 
4120 /**
4121   * @brief  Check if RTC has been enabled or not
4122   * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
4123   * @retval State of bit (1 or 0).
4124   */
4125 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4126 {
4127   return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
4128 }
4129 
4130 /**
4131   * @brief  Force the Backup domain reset
4132   * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset
4133   * @retval None
4134   */
4135 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4136 {
4137   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4138 }
4139 
4140 /**
4141   * @brief  Release the Backup domain reset
4142   * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset
4143   * @retval None
4144   */
4145 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4146 {
4147 #if defined(RCC_BDCR_BDRST)
4148   CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4149 #else
4150   CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
4151 #endif /* RCC_BDCR_BDRST */
4152 }
4153 
4154 /**
4155   * @brief  Set HSE Prescalers for RTC Clock
4156   * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
4157   * @param  Prescaler This parameter can be one of the following values:
4158   *         @arg @ref LL_RCC_RTC_NOCLOCK
4159   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
4160   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
4161   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
4162   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
4163   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
4164   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
4165   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
4166   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
4167   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
4168   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
4169   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
4170   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
4171   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
4172   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
4173   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
4174   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
4175   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
4176   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
4177   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
4178   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
4179   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
4180   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
4181   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
4182   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
4183   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
4184   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
4185   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
4186   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
4187   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
4188   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
4189   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
4190   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
4191   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
4192   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
4193   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
4194   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
4195   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
4196   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
4197   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
4198   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
4199   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
4200   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
4201   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
4202   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
4203   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
4204   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
4205   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
4206   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
4207   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
4208   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
4209   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
4210   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
4211   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
4212   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
4213   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
4214   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
4215   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
4216   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
4217   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
4218   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
4219   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
4220   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
4221   * @retval None
4222   */
4223 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4224 {
4225   MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4226 }
4227 
4228 /**
4229   * @brief  Get HSE Prescalers for RTC Clock
4230   * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
4231   * @retval Returned value can be one of the following values:
4232   *         @arg @ref LL_RCC_RTC_NOCLOCK
4233   *         @arg @ref LL_RCC_RTC_HSE_DIV_2
4234   *         @arg @ref LL_RCC_RTC_HSE_DIV_3
4235   *         @arg @ref LL_RCC_RTC_HSE_DIV_4
4236   *         @arg @ref LL_RCC_RTC_HSE_DIV_5
4237   *         @arg @ref LL_RCC_RTC_HSE_DIV_6
4238   *         @arg @ref LL_RCC_RTC_HSE_DIV_7
4239   *         @arg @ref LL_RCC_RTC_HSE_DIV_8
4240   *         @arg @ref LL_RCC_RTC_HSE_DIV_9
4241   *         @arg @ref LL_RCC_RTC_HSE_DIV_10
4242   *         @arg @ref LL_RCC_RTC_HSE_DIV_11
4243   *         @arg @ref LL_RCC_RTC_HSE_DIV_12
4244   *         @arg @ref LL_RCC_RTC_HSE_DIV_13
4245   *         @arg @ref LL_RCC_RTC_HSE_DIV_14
4246   *         @arg @ref LL_RCC_RTC_HSE_DIV_15
4247   *         @arg @ref LL_RCC_RTC_HSE_DIV_16
4248   *         @arg @ref LL_RCC_RTC_HSE_DIV_17
4249   *         @arg @ref LL_RCC_RTC_HSE_DIV_18
4250   *         @arg @ref LL_RCC_RTC_HSE_DIV_19
4251   *         @arg @ref LL_RCC_RTC_HSE_DIV_20
4252   *         @arg @ref LL_RCC_RTC_HSE_DIV_21
4253   *         @arg @ref LL_RCC_RTC_HSE_DIV_22
4254   *         @arg @ref LL_RCC_RTC_HSE_DIV_23
4255   *         @arg @ref LL_RCC_RTC_HSE_DIV_24
4256   *         @arg @ref LL_RCC_RTC_HSE_DIV_25
4257   *         @arg @ref LL_RCC_RTC_HSE_DIV_26
4258   *         @arg @ref LL_RCC_RTC_HSE_DIV_27
4259   *         @arg @ref LL_RCC_RTC_HSE_DIV_28
4260   *         @arg @ref LL_RCC_RTC_HSE_DIV_29
4261   *         @arg @ref LL_RCC_RTC_HSE_DIV_30
4262   *         @arg @ref LL_RCC_RTC_HSE_DIV_31
4263   *         @arg @ref LL_RCC_RTC_HSE_DIV_32
4264   *         @arg @ref LL_RCC_RTC_HSE_DIV_33
4265   *         @arg @ref LL_RCC_RTC_HSE_DIV_34
4266   *         @arg @ref LL_RCC_RTC_HSE_DIV_35
4267   *         @arg @ref LL_RCC_RTC_HSE_DIV_36
4268   *         @arg @ref LL_RCC_RTC_HSE_DIV_37
4269   *         @arg @ref LL_RCC_RTC_HSE_DIV_38
4270   *         @arg @ref LL_RCC_RTC_HSE_DIV_39
4271   *         @arg @ref LL_RCC_RTC_HSE_DIV_40
4272   *         @arg @ref LL_RCC_RTC_HSE_DIV_41
4273   *         @arg @ref LL_RCC_RTC_HSE_DIV_42
4274   *         @arg @ref LL_RCC_RTC_HSE_DIV_43
4275   *         @arg @ref LL_RCC_RTC_HSE_DIV_44
4276   *         @arg @ref LL_RCC_RTC_HSE_DIV_45
4277   *         @arg @ref LL_RCC_RTC_HSE_DIV_46
4278   *         @arg @ref LL_RCC_RTC_HSE_DIV_47
4279   *         @arg @ref LL_RCC_RTC_HSE_DIV_48
4280   *         @arg @ref LL_RCC_RTC_HSE_DIV_49
4281   *         @arg @ref LL_RCC_RTC_HSE_DIV_50
4282   *         @arg @ref LL_RCC_RTC_HSE_DIV_51
4283   *         @arg @ref LL_RCC_RTC_HSE_DIV_52
4284   *         @arg @ref LL_RCC_RTC_HSE_DIV_53
4285   *         @arg @ref LL_RCC_RTC_HSE_DIV_54
4286   *         @arg @ref LL_RCC_RTC_HSE_DIV_55
4287   *         @arg @ref LL_RCC_RTC_HSE_DIV_56
4288   *         @arg @ref LL_RCC_RTC_HSE_DIV_57
4289   *         @arg @ref LL_RCC_RTC_HSE_DIV_58
4290   *         @arg @ref LL_RCC_RTC_HSE_DIV_59
4291   *         @arg @ref LL_RCC_RTC_HSE_DIV_60
4292   *         @arg @ref LL_RCC_RTC_HSE_DIV_61
4293   *         @arg @ref LL_RCC_RTC_HSE_DIV_62
4294   *         @arg @ref LL_RCC_RTC_HSE_DIV_63
4295   */
4296 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4297 {
4298   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4299 }
4300 
4301 /**
4302   * @}
4303   */
4304 
4305 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4306   * @ingroup RTEMSBSPsARMSTM32H7
4307   * @{
4308   */
4309 
4310 /**
4311   * @brief  Set Timers Clock Prescalers
4312   * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler
4313   * @param  Prescaler This parameter can be one of the following values:
4314   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4315   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4316   * @retval None
4317   */
4318 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4319 {
4320   MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
4321 }
4322 
4323 /**
4324   * @brief  Get Timers Clock Prescalers
4325   * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler
4326   * @retval Returned value can be one of the following values:
4327   *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4328   *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4329   */
4330 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4331 {
4332   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
4333 }
4334 
4335 /**
4336   * @}
4337   */
4338 
4339 #if defined(HRTIM1)
4340 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
4341   * @ingroup RTEMSBSPsARMSTM32H7
4342   * @{
4343   */
4344 
4345 /**
4346   * @brief  Set High Resolution Timers Clock Source
4347   * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource
4348   * @param  Prescaler This parameter can be one of the following values:
4349   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4350   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4351   * @retval None
4352   */
4353 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
4354 {
4355   MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
4356 }
4357 #endif /* HRTIM1 */
4358 
4359 #if defined(HRTIM1)
4360 /**
4361   * @brief  Get High Resolution Timers Clock Source
4362   * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource
4363   * @retval Returned value can be one of the following values:
4364   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4365   *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4366   */
4367 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
4368 {
4369   return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
4370 }
4371 /**
4372   * @}
4373   */
4374 #endif /* HRTIM1 */
4375 
4376 /** @defgroup RCC_LL_EF_PLL PLL
4377   * @ingroup RTEMSBSPsARMSTM32H7
4378   * @{
4379   */
4380 
4381 /**
4382   * @brief  Set the oscillator used as PLL clock source.
4383   * @note   PLLSRC can be written only when All PLLs are disabled.
4384   * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource
4385   * @param  PLLSource parameter can be one of the following values:
4386   *         @arg @ref LL_RCC_PLLSOURCE_HSI
4387   *         @arg @ref LL_RCC_PLLSOURCE_CSI
4388   *         @arg @ref LL_RCC_PLLSOURCE_HSE
4389   *         @arg @ref LL_RCC_PLLSOURCE_NONE
4390   * @retval None
4391   */
4392 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
4393 {
4394   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
4395 }
4396 
4397 /**
4398   * @brief  Get the oscillator used as PLL clock source.
4399   * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource
4400   * @retval Returned value can be one of the following values:
4401   *         @arg @ref LL_RCC_PLLSOURCE_HSI
4402   *         @arg @ref LL_RCC_PLLSOURCE_CSI
4403   *         @arg @ref LL_RCC_PLLSOURCE_HSE
4404   *         @arg @ref LL_RCC_PLLSOURCE_NONE
4405   */
4406 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
4407 {
4408   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
4409 }
4410 
4411 /**
4412   * @brief  Enable PLL1
4413   * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable
4414   * @retval None
4415   */
4416 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4417 {
4418   SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4419 }
4420 
4421 /**
4422   * @brief  Disable PLL1
4423   * @note Cannot be disabled if the PLL1 clock is used as the system clock
4424   * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable
4425   * @retval None
4426   */
4427 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4428 {
4429   CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4430 }
4431 
4432 /**
4433   * @brief  Check if PLL1 Ready
4434   * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady
4435   * @retval State of bit (1 or 0).
4436   */
4437 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4438 {
4439   return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL);
4440 }
4441 
4442 /**
4443   * @brief  Enable PLL1P
4444   * @note   This API shall be called only when PLL1 is disabled.
4445   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable
4446   * @retval None
4447   */
4448 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4449 {
4450   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4451 }
4452 
4453 /**
4454   * @brief  Enable PLL1Q
4455   * @note   This API shall be called only when PLL1 is disabled.
4456   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable
4457   * @retval None
4458   */
4459 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4460 {
4461   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4462 }
4463 
4464 /**
4465   * @brief  Enable PLL1R
4466   * @note   This API shall be called only when PLL1 is disabled.
4467   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable
4468   * @retval None
4469   */
4470 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4471 {
4472   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4473 }
4474 
4475 /**
4476   * @brief  Enable PLL1 FRACN
4477   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
4478   * @retval None
4479   */
4480 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4481 {
4482   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4483 }
4484 
4485 /**
4486   * @brief  Check if PLL1 P is enabled
4487   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled
4488   * @retval State of bit (1 or 0).
4489   */
4490 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4491 {
4492   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL);
4493 }
4494 
4495 /**
4496   * @brief  Check if PLL1 Q is enabled
4497   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled
4498   * @retval State of bit (1 or 0).
4499   */
4500 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4501 {
4502   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL);
4503 }
4504 
4505 /**
4506   * @brief  Check if PLL1 R is enabled
4507   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled
4508   * @retval State of bit (1 or 0).
4509   */
4510 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4511 {
4512   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL);
4513 }
4514 
4515 /**
4516   * @brief  Check if PLL1 FRACN is enabled
4517   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled
4518   * @retval State of bit (1 or 0).
4519   */
4520 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4521 {
4522   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL);
4523 }
4524 
4525 /**
4526   * @brief  Disable PLL1P
4527   * @note   This API shall be called only when PLL1 is disabled.
4528   * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable
4529   * @retval None
4530   */
4531 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4532 {
4533   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4534 }
4535 
4536 /**
4537   * @brief  Disable PLL1Q
4538   * @note   This API shall be called only when PLL1 is disabled.
4539   * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable
4540   * @retval None
4541   */
4542 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4543 {
4544   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4545 }
4546 
4547 /**
4548   * @brief  Disable PLL1R
4549   * @note   This API shall be called only when PLL1 is disabled.
4550   * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable
4551   * @retval None
4552   */
4553 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4554 {
4555   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4556 }
4557 
4558 /**
4559   * @brief  Disable PLL1 FRACN
4560   * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable
4561   * @retval None
4562   */
4563 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4564 {
4565   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4566 }
4567 
4568 /**
4569   * @brief  Set PLL1 VCO OutputRange
4570   * @note   This API shall be called only when PLL1 is disabled.
4571   * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
4572   * @param  VCORange This parameter can be one of the following values:
4573   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
4574   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4575   * @retval None
4576   */
4577 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4578 {
4579   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
4580 }
4581 
4582 /**
4583   * @brief  Set PLL1 VCO Input Range
4584   * @note   This API shall be called only when PLL1 is disabled.
4585   * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange
4586   * @param  InputRange This parameter can be one of the following values:
4587   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4588   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4589   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4590   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4591   * @retval None
4592   */
4593 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4594 {
4595   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
4596 }
4597 
4598 /**
4599   * @brief  Get PLL1 N Coefficient
4600   * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN
4601   * @retval A value between 4 and 512
4602   */
4603 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4604 {
4605   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);
4606 }
4607 
4608 /**
4609   * @brief  Get PLL1 M Coefficient
4610   * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM
4611   * @retval A value between 0 and 63
4612   */
4613 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4614 {
4615   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);
4616 }
4617 
4618 /**
4619   * @brief  Get PLL1 P Coefficient
4620   * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP
4621   * @retval A value between 2 and 128
4622   */
4623 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4624 {
4625   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);
4626 }
4627 
4628 /**
4629   * @brief  Get PLL1 Q Coefficient
4630   * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ
4631   * @retval A value between 1 and 128
4632   */
4633 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4634 {
4635   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);
4636 }
4637 
4638 /**
4639   * @brief  Get PLL1 R Coefficient
4640   * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR
4641   * @retval A value between 1 and 128
4642   */
4643 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4644 {
4645   return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);
4646 }
4647 
4648 /**
4649   * @brief  Get PLL1 FRACN Coefficient
4650   * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN
4651   * @retval A value between 0 and 8191 (0x1FFF)
4652   */
4653 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4654 {
4655   return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);
4656 }
4657 
4658 /**
4659   * @brief  Set PLL1 N Coefficient
4660   * @note   This API shall be called only when PLL1 is disabled.
4661   * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN
4662   * @param  N parameter can be a value between 4 and 512
4663   */
4664 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
4665 {
4666   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos);
4667 }
4668 
4669 /**
4670   * @brief  Set PLL1 M Coefficient
4671   * @note   This API shall be called only when PLL1 is disabled.
4672   * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM
4673   * @param  M parameter can be a value between 0 and 63
4674   */
4675 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
4676 {
4677   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
4678 }
4679 
4680 /**
4681   * @brief  Set PLL1 P Coefficient
4682   * @note   This API shall be called only when PLL1 is disabled.
4683   * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP
4684   * @param  P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
4685   *
4686   * (*) : For stm32h72xxx and stm32h73xxx family lines.
4687   */
4688 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
4689 {
4690   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos);
4691 }
4692 
4693 /**
4694   * @brief  Set PLL1 Q Coefficient
4695   * @note   This API shall be called only when PLL1 is disabled.
4696   * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ
4697   * @param  Q parameter can be a value between 1 and 128
4698   */
4699 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
4700 {
4701   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos);
4702 }
4703 
4704 /**
4705   * @brief  Set PLL1 R Coefficient
4706   * @note   This API shall be called only when PLL1 is disabled.
4707   * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR
4708   * @param  R parameter can be a value between 1 and 128
4709   */
4710 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
4711 {
4712   MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos);
4713 }
4714 
4715 /**
4716   * @brief  Set PLL1 FRACN Coefficient
4717   * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN
4718   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4719   */
4720 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4721 {
4722   MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
4723 }
4724 
4725 /**
4726   * @brief  Enable PLL2
4727   * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable
4728   * @retval None
4729   */
4730 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4731 {
4732   SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4733 }
4734 
4735 /**
4736   * @brief  Disable PLL2
4737   * @note Cannot be disabled if the PLL2 clock is used as the system clock
4738   * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable
4739   * @retval None
4740   */
4741 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4742 {
4743   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4744 }
4745 
4746 /**
4747   * @brief  Check if PLL2 Ready
4748   * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady
4749   * @retval State of bit (1 or 0).
4750   */
4751 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4752 {
4753   return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL);
4754 }
4755 
4756 /**
4757   * @brief  Enable PLL2P
4758   * @note   This API shall be called only when PLL2 is disabled.
4759   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable
4760   * @retval None
4761   */
4762 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4763 {
4764   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4765 }
4766 
4767 /**
4768   * @brief  Enable PLL2Q
4769   * @note   This API shall be called only when PLL2 is disabled.
4770   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable
4771   * @retval None
4772   */
4773 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4774 {
4775   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4776 }
4777 
4778 /**
4779   * @brief  Enable PLL2R
4780   * @note   This API shall be called only when PLL2 is disabled.
4781   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable
4782   * @retval None
4783   */
4784 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4785 {
4786   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4787 }
4788 
4789 /**
4790   * @brief  Enable PLL2 FRACN
4791   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
4792   * @retval None
4793   */
4794 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4795 {
4796   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4797 }
4798 
4799 /**
4800   * @brief  Check if PLL2 P is enabled
4801   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled
4802   * @retval State of bit (1 or 0).
4803   */
4804 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4805 {
4806   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL);
4807 }
4808 
4809 /**
4810   * @brief  Check if PLL2 Q is enabled
4811   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled
4812   * @retval State of bit (1 or 0).
4813   */
4814 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4815 {
4816   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL);
4817 }
4818 
4819 /**
4820   * @brief  Check if PLL2 R is enabled
4821   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled
4822   * @retval State of bit (1 or 0).
4823   */
4824 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4825 {
4826   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL);
4827 }
4828 
4829 /**
4830   * @brief  Check if PLL2 FRACN is enabled
4831   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled
4832   * @retval State of bit (1 or 0).
4833   */
4834 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4835 {
4836   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL);
4837 }
4838 
4839 /**
4840   * @brief  Disable PLL2P
4841   * @note   This API shall be called only when PLL2 is disabled.
4842   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable
4843   * @retval None
4844   */
4845 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4846 {
4847   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4848 }
4849 
4850 /**
4851   * @brief  Disable PLL2Q
4852   * @note   This API shall be called only when PLL2 is disabled.
4853   * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable
4854   * @retval None
4855   */
4856 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4857 {
4858   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4859 }
4860 
4861 /**
4862   * @brief  Disable PLL2R
4863   * @note   This API shall be called only when PLL2 is disabled.
4864   * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable
4865   * @retval None
4866   */
4867 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4868 {
4869   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4870 }
4871 
4872 /**
4873   * @brief  Disable PLL2 FRACN
4874   * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable
4875   * @retval None
4876   */
4877 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4878 {
4879   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4880 }
4881 
4882 /**
4883   * @brief  Set PLL2 VCO OutputRange
4884   * @note   This API shall be called only when PLL2 is disabled.
4885   * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange
4886   * @param  VCORange This parameter can be one of the following values:
4887   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
4888   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4889   * @retval None
4890   */
4891 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4892 {
4893   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
4894 }
4895 
4896 /**
4897   * @brief  Set PLL2 VCO Input Range
4898   * @note   This API shall be called only when PLL2 is disabled.
4899   * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange
4900   * @param  InputRange This parameter can be one of the following values:
4901   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4902   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4903   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4904   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4905   * @retval None
4906   */
4907 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4908 {
4909   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
4910 }
4911 
4912 /**
4913   * @brief  Get PLL2 N Coefficient
4914   * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN
4915   * @retval A value between 4 and 512
4916   */
4917 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4918 {
4919   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);
4920 }
4921 
4922 /**
4923   * @brief  Get PLL2 M Coefficient
4924   * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM
4925   * @retval A value between 0 and 63
4926   */
4927 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4928 {
4929   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);
4930 }
4931 
4932 /**
4933   * @brief  Get PLL2 P Coefficient
4934   * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP
4935   * @retval A value between 1 and 128
4936   */
4937 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4938 {
4939   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);
4940 }
4941 
4942 /**
4943   * @brief  Get PLL2 Q Coefficient
4944   * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ
4945   * @retval A value between 1 and 128
4946   */
4947 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4948 {
4949   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);
4950 }
4951 
4952 /**
4953   * @brief  Get PLL2 R Coefficient
4954   * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR
4955   * @retval A value between 1 and 128
4956   */
4957 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4958 {
4959   return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);
4960 }
4961 
4962 /**
4963   * @brief  Get PLL2 FRACN Coefficient
4964   * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN
4965   * @retval A value between 0 and 8191 (0x1FFF)
4966   */
4967 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4968 {
4969   return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);
4970 }
4971 
4972 /**
4973   * @brief  Set PLL2 N Coefficient
4974   * @note   This API shall be called only when PLL2 is disabled.
4975   * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN
4976   * @param  N parameter can be a value between 4 and 512
4977   */
4978 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
4979 {
4980   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos);
4981 }
4982 
4983 /**
4984   * @brief  Set PLL2 M Coefficient
4985   * @note   This API shall be called only when PLL2 is disabled.
4986   * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM
4987   * @param  M parameter can be a value between 0 and 63
4988   */
4989 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
4990 {
4991   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
4992 }
4993 
4994 /**
4995   * @brief  Set PLL2 P Coefficient
4996   * @note   This API shall be called only when PLL2 is disabled.
4997   * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP
4998   * @param  P parameter can be a value between 1 and 128
4999   */
5000 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
5001 {
5002   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos);
5003 }
5004 
5005 /**
5006   * @brief  Set PLL2 Q Coefficient
5007   * @note   This API shall be called only when PLL2 is disabled.
5008   * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ
5009   * @param  Q parameter can be a value between 1 and 128
5010   */
5011 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
5012 {
5013   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos);
5014 }
5015 
5016 /**
5017   * @brief  Set PLL2 R Coefficient
5018   * @note   This API shall be called only when PLL2 is disabled.
5019   * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR
5020   * @param  R parameter can be a value between 1 and 128
5021   */
5022 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
5023 {
5024   MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos);
5025 }
5026 
5027 /**
5028   * @brief  Set PLL2 FRACN Coefficient
5029   * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN
5030   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5031   */
5032 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
5033 {
5034   MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
5035 }
5036 
5037 /**
5038   * @brief  Enable PLL3
5039   * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable
5040   * @retval None
5041   */
5042 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
5043 {
5044   SET_BIT(RCC->CR, RCC_CR_PLL3ON);
5045 }
5046 
5047 /**
5048   * @brief  Disable PLL3
5049   * @note Cannot be disabled if the PLL3 clock is used as the system clock
5050   * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable
5051   * @retval None
5052   */
5053 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
5054 {
5055   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
5056 }
5057 
5058 /**
5059   * @brief  Check if PLL3 Ready
5060   * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady
5061   * @retval State of bit (1 or 0).
5062   */
5063 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
5064 {
5065   return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL);
5066 }
5067 
5068 /**
5069   * @brief  Enable PLL3P
5070   * @note   This API shall be called only when PLL3 is disabled.
5071   * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable
5072   * @retval None
5073   */
5074 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
5075 {
5076   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
5077 }
5078 
5079 /**
5080   * @brief  Enable PLL3Q
5081   * @note   This API shall be called only when PLL3 is disabled.
5082   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable
5083   * @retval None
5084   */
5085 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
5086 {
5087   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
5088 }
5089 
5090 /**
5091   * @brief  Enable PLL3R
5092   * @note   This API shall be called only when PLL3 is disabled.
5093   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable
5094   * @retval None
5095   */
5096 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
5097 {
5098   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5099 }
5100 
5101 /**
5102   * @brief  Enable PLL3 FRACN
5103   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
5104   * @retval None
5105   */
5106 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
5107 {
5108   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5109 }
5110 
5111 /**
5112   * @brief  Check if PLL3 P is enabled
5113   * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled
5114   * @retval State of bit (1 or 0).
5115   */
5116 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5117 {
5118   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL);
5119 }
5120 
5121 /**
5122   * @brief  Check if PLL3 Q is enabled
5123   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled
5124   * @retval State of bit (1 or 0).
5125   */
5126 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
5127 {
5128   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL);
5129 }
5130 
5131 /**
5132   * @brief  Check if PLL3 R is enabled
5133   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled
5134   * @retval State of bit (1 or 0).
5135   */
5136 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
5137 {
5138   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL);
5139 }
5140 
5141 /**
5142   * @brief  Check if PLL3 FRACN is enabled
5143   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled
5144   * @retval State of bit (1 or 0).
5145   */
5146 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
5147 {
5148   return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL);
5149 }
5150 
5151 /**
5152   * @brief  Disable PLL3P
5153   * @note   This API shall be called only when PLL3 is disabled.
5154   * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable
5155   * @retval None
5156   */
5157 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5158 {
5159   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
5160 }
5161 
5162 /**
5163   * @brief  Disable PLL3Q
5164   * @note   This API shall be called only when PLL3 is disabled.
5165   * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable
5166   * @retval None
5167   */
5168 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
5169 {
5170   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
5171 }
5172 
5173 /**
5174   * @brief  Disable PLL3R
5175   * @note   This API shall be called only when PLL3 is disabled.
5176   * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable
5177   * @retval None
5178   */
5179 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5180 {
5181   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5182 }
5183 
5184 /**
5185   * @brief  Disable PLL3 FRACN
5186   * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable
5187   * @retval None
5188   */
5189 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5190 {
5191   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5192 }
5193 
5194 /**
5195   * @brief  Set PLL3 VCO OutputRange
5196   * @note   This API shall be called only when PLL3 is disabled.
5197   * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange
5198   * @param  VCORange This parameter can be one of the following values:
5199   *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
5200   *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5201   * @retval None
5202   */
5203 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5204 {
5205   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
5206 }
5207 
5208 /**
5209   * @brief  Set PLL3 VCO Input Range
5210   * @note   This API shall be called only when PLL3 is disabled.
5211   * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange
5212   * @param  InputRange This parameter can be one of the following values:
5213   *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5214   *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5215   *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5216   *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5217   * @retval None
5218   */
5219 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5220 {
5221   MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
5222 }
5223 
5224 /**
5225   * @brief  Get PLL3 N Coefficient
5226   * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN
5227   * @retval A value between 4 and 512
5228   */
5229 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
5230 {
5231   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);
5232 }
5233 
5234 /**
5235   * @brief  Get PLL3 M Coefficient
5236   * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM
5237   * @retval A value between 0 and 63
5238   */
5239 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5240 {
5241   return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);
5242 }
5243 
5244 /**
5245   * @brief  Get PLL3 P Coefficient
5246   * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP
5247   * @retval A value between 1 and 128
5248   */
5249 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5250 {
5251   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);
5252 }
5253 
5254 /**
5255   * @brief  Get PLL3 Q Coefficient
5256   * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ
5257   * @retval A value between 1 and 128
5258   */
5259 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5260 {
5261   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);
5262 }
5263 
5264 /**
5265   * @brief  Get PLL3 R Coefficient
5266   * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR
5267   * @retval A value between 1 and 128
5268   */
5269 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5270 {
5271   return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);
5272 }
5273 
5274 /**
5275   * @brief  Get PLL3 FRACN Coefficient
5276   * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN
5277   * @retval A value between 0 and 8191 (0x1FFF)
5278   */
5279 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5280 {
5281   return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);
5282 }
5283 
5284 /**
5285   * @brief  Set PLL3 N Coefficient
5286   * @note   This API shall be called only when PLL3 is disabled.
5287   * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN
5288   * @param  N parameter can be a value between 4 and 512
5289   */
5290 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5291 {
5292   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos);
5293 }
5294 
5295 /**
5296   * @brief  Set PLL3 M Coefficient
5297   * @note   This API shall be called only when PLL3 is disabled.
5298   * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM
5299   * @param  M parameter can be a value between 0 and 63
5300   */
5301 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5302 {
5303   MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
5304 }
5305 
5306 /**
5307   * @brief  Set PLL3 P Coefficient
5308   * @note   This API shall be called only when PLL3 is disabled.
5309   * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP
5310   * @param  P parameter can be a value between 1 and 128
5311   */
5312 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
5313 {
5314   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos);
5315 }
5316 
5317 /**
5318   * @brief  Set PLL3 Q Coefficient
5319   * @note   This API shall be called only when PLL3 is disabled.
5320   * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ
5321   * @param  Q parameter can be a value between 1 and 128
5322   */
5323 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
5324 {
5325   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos);
5326 }
5327 
5328 /**
5329   * @brief  Set PLL3 R Coefficient
5330   * @note   This API shall be called only when PLL3 is disabled.
5331   * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR
5332   * @param  R parameter can be a value between 1 and 128
5333   */
5334 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
5335 {
5336   MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos);
5337 }
5338 
5339 /**
5340   * @brief  Set PLL3 FRACN Coefficient
5341   * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN
5342   * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5343   */
5344 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5345 {
5346   MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
5347 }
5348 
5349 
5350 /**
5351   * @}
5352   */
5353 
5354 
5355 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5356   * @ingroup RTEMSBSPsARMSTM32H7
5357   * @{
5358   */
5359 
5360 /**
5361   * @brief  Clear LSI ready interrupt flag
5362   * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
5363   * @retval None
5364   */
5365 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5366 {
5367   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5368 }
5369 
5370 /**
5371   * @brief  Clear LSE ready interrupt flag
5372   * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY
5373   * @retval None
5374   */
5375 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5376 {
5377   SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5378 }
5379 
5380 /**
5381   * @brief  Clear HSI ready interrupt flag
5382   * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
5383   * @retval None
5384   */
5385 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5386 {
5387   SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5388 }
5389 
5390 /**
5391   * @brief  Clear HSE ready interrupt flag
5392   * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY
5393   * @retval None
5394   */
5395 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5396 {
5397   SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5398 }
5399 
5400 /**
5401   * @brief  Clear CSI ready interrupt flag
5402   * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY
5403   * @retval None
5404   */
5405 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5406 {
5407   SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5408 }
5409 
5410 /**
5411   * @brief  Clear HSI48 ready interrupt flag
5412   * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY
5413   * @retval None
5414   */
5415 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5416 {
5417   SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5418 }
5419 
5420 /**
5421   * @brief  Clear PLL1 ready interrupt flag
5422   * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY
5423   * @retval None
5424   */
5425 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5426 {
5427   SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5428 }
5429 
5430 /**
5431   * @brief  Clear PLL2 ready interrupt flag
5432   * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY
5433   * @retval None
5434   */
5435 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5436 {
5437   SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5438 }
5439 
5440 /**
5441   * @brief  Clear PLL3 ready interrupt flag
5442   * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY
5443   * @retval None
5444   */
5445 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5446 {
5447   SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5448 }
5449 
5450 /**
5451   * @brief  Clear LSE Clock security system interrupt flag
5452   * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS
5453   * @retval None
5454   */
5455 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5456 {
5457   SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5458 }
5459 
5460 /**
5461   * @brief  Clear HSE Clock security system interrupt flag
5462   * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS
5463   * @retval None
5464   */
5465 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5466 {
5467   SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5468 }
5469 
5470 /**
5471   * @brief  Check if LSI ready interrupt occurred or not
5472   * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
5473   * @retval State of bit (1 or 0).
5474   */
5475 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5476 {
5477   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
5478 }
5479 
5480 /**
5481   * @brief  Check if LSE ready interrupt occurred or not
5482   * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
5483   * @retval State of bit (1 or 0).
5484   */
5485 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5486 {
5487   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
5488 }
5489 
5490 /**
5491   * @brief  Check if HSI ready interrupt occurred or not
5492   * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
5493   * @retval State of bit (1 or 0).
5494   */
5495 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5496 {
5497   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
5498 }
5499 
5500 /**
5501   * @brief  Check if HSE ready interrupt occurred or not
5502   * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
5503   * @retval State of bit (1 or 0).
5504   */
5505 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5506 {
5507   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
5508 }
5509 
5510 /**
5511   * @brief  Check if CSI ready interrupt occurred or not
5512   * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY
5513   * @retval State of bit (1 or 0).
5514   */
5515 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5516 {
5517   return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL);
5518 }
5519 
5520 /**
5521   * @brief  Check if HSI48 ready interrupt occurred or not
5522   * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY
5523   * @retval State of bit (1 or 0).
5524   */
5525 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5526 {
5527   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
5528 }
5529 
5530 /**
5531   * @brief  Check if PLL1 ready interrupt occurred or not
5532   * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY
5533   * @retval State of bit (1 or 0).
5534   */
5535 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5536 {
5537   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
5538 }
5539 
5540 /**
5541   * @brief  Check if PLL2 ready interrupt occurred or not
5542   * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY
5543   * @retval State of bit (1 or 0).
5544   */
5545 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5546 {
5547   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL);
5548 }
5549 
5550 /**
5551   * @brief  Check if PLL3 ready interrupt occurred or not
5552   * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY
5553   * @retval State of bit (1 or 0).
5554   */
5555 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5556 {
5557   return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL);
5558 }
5559 
5560 /**
5561   * @brief  Check if LSE Clock security system interrupt occurred or not
5562   * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS
5563   * @retval State of bit (1 or 0).
5564   */
5565 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5566 {
5567   return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
5568 }
5569 
5570 /**
5571   * @brief  Check if HSE Clock security system interrupt occurred or not
5572   * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS
5573   * @retval State of bit (1 or 0).
5574   */
5575 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5576 {
5577   return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL);
5578 }
5579 
5580 /**
5581   * @brief  Check if RCC flag Low Power D1 reset is set or not.
5582   * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n
5583   *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)
5584   *
5585   * (*) Only available for single core devices
5586   * (**) Only available for Dual core devices
5587   * @retval State of bit (1 or 0).
5588   */
5589 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5590 {
5591 #if defined(DUAL_CORE)
5592   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5593 #else
5594   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL);
5595 #endif /*DUAL_CORE*/
5596 }
5597 
5598 #if defined(DUAL_CORE)
5599 /**
5600   * @brief  Check if RCC flag Low Power D2 reset is set or not.
5601   * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST
5602   * @retval State of bit (1 or 0).
5603   */
5604 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
5605 {
5606   return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5607 }
5608 #endif  /*DUAL_CORE*/
5609 
5610 /**
5611   * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.
5612   * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST
5613   * @retval State of bit (1 or 0).
5614   */
5615 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
5616 {
5617   return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5618 }
5619 
5620 #if defined(DUAL_CORE)
5621 /**
5622   * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.
5623   * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST
5624   * @retval State of bit (1 or 0).
5625   */
5626 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
5627 {
5628   return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5629 }
5630 #endif  /*DUAL_CORE*/
5631 
5632 /**
5633   * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.
5634   * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST
5635   * @retval State of bit (1 or 0).
5636   */
5637 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
5638 {
5639   return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
5640 }
5641 
5642 #if defined(DUAL_CORE)
5643 /**
5644   * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.
5645   * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST
5646   * @retval State of bit (1 or 0).
5647   */
5648 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
5649 {
5650   return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
5651 }
5652 #endif  /*DUAL_CORE*/
5653 
5654 /**
5655   * @brief  Check if RCC flag Software reset is set or not.
5656   * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n
5657   *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)
5658   *
5659   * (*) Only available for single core devices
5660   * (**) Only available for Dual core devices
5661   * @retval State of bit (1 or 0).
5662   */
5663 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5664 {
5665 #if defined(DUAL_CORE)
5666   return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
5667 #else
5668   return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL);
5669 #endif  /*DUAL_CORE*/
5670 }
5671 
5672 #if defined(DUAL_CORE)
5673 /**
5674   * @brief  Check if RCC flag Software reset is set or not.
5675   * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST
5676   * @retval State of bit (1 or 0).
5677   */
5678 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
5679 {
5680   return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
5681 }
5682 #endif  /*DUAL_CORE*/
5683 
5684 /**
5685   * @brief  Check if RCC flag POR/PDR reset is set or not.
5686   * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
5687   * @retval State of bit (1 or 0).
5688   */
5689 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5690 {
5691   return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
5692 }
5693 
5694 /**
5695   * @brief  Check if RCC flag Pin reset is set or not.
5696   * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
5697   * @retval State of bit (1 or 0).
5698   */
5699 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5700 {
5701   return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
5702 }
5703 
5704 /**
5705   * @brief  Check if RCC flag BOR reset is set or not.
5706   * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
5707   * @retval State of bit (1 or 0).
5708   */
5709 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5710 {
5711   return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5712 }
5713 
5714 #if defined(RCC_RSR_D1RSTF)
5715 /**
5716   * @brief  Check if RCC flag D1 reset is set or not.
5717   * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST
5718   * @retval State of bit (1 or 0).
5719   */
5720 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
5721 {
5722   return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
5723 }
5724 #endif /* RCC_RSR_D1RSTF */
5725 
5726 #if defined(RCC_RSR_CDRSTF)
5727 /**
5728   * @brief  Check if RCC flag CD reset is set or not.
5729   * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST
5730   * @retval State of bit (1 or 0).
5731   */
5732 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
5733 {
5734   return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL);
5735 }
5736 #endif /* RCC_RSR_CDRSTF */
5737 
5738 #if defined(RCC_RSR_D2RSTF)
5739 /**
5740   * @brief  Check if RCC flag D2 reset is set or not.
5741   * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST
5742   * @retval State of bit (1 or 0).
5743   */
5744 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
5745 {
5746   return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
5747 }
5748 #endif /* RCC_RSR_D2RSTF */
5749 
5750 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
5751 /**
5752   * @brief  Check if RCC flag CPU reset is set or not.
5753   * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n
5754   *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)
5755   *
5756   * (*) Only available for single core devices
5757   * (**) Only available for Dual core devices
5758   * @retval State of bit (1 or 0).
5759   */
5760 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
5761 {
5762 #if defined(DUAL_CORE)
5763   return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
5764 #else
5765   return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL);
5766 #endif/*DUAL_CORE*/
5767 }
5768 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
5769 
5770 #if defined(DUAL_CORE)
5771 /**
5772   * @brief  Check if RCC flag CPU2 reset is set or not.
5773   * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST
5774   * @retval State of bit (1 or 0).
5775   */
5776 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
5777 {
5778   return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
5779 }
5780 #endif  /*DUAL_CORE*/
5781 
5782 /**
5783   * @brief  Set RMVF bit to clear all reset flags.
5784   * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags
5785   * @retval None
5786   */
5787 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5788 {
5789   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5790 }
5791 
5792 #if defined(DUAL_CORE)
5793 /**
5794   * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.
5795   * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST
5796   * @retval State of bit (1 or 0).
5797   */
5798 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
5799 {
5800   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5801 }
5802 
5803 /**
5804   * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.
5805   * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST
5806   * @retval State of bit (1 or 0).
5807   */
5808 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
5809 {
5810   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5811 }
5812 
5813 /**
5814   * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
5815   * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST
5816   * @retval State of bit (1 or 0).
5817   */
5818 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
5819 {
5820   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5821 }
5822 
5823 /**
5824   * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
5825   * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST
5826   * @retval State of bit (1 or 0).
5827   */
5828 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
5829 {
5830   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5831 }
5832 
5833 /**
5834   * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
5835   * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST
5836   * @retval State of bit (1 or 0).
5837   */
5838 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
5839 {
5840   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
5841 }
5842 
5843 /**
5844   * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
5845   * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST
5846   * @retval State of bit (1 or 0).
5847   */
5848 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
5849 {
5850   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
5851 }
5852 
5853 /**
5854   * @brief  Check if RCC_C1 flag Software reset is set or not.
5855   * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST
5856   * @retval State of bit (1 or 0).
5857   */
5858 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
5859 {
5860   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
5861 }
5862 
5863 /**
5864   * @brief  Check if RCC_C1 flag Software reset is set or not.
5865   * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST
5866   * @retval State of bit (1 or 0).
5867   */
5868 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
5869 {
5870   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
5871 }
5872 
5873 /**
5874   * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.
5875   * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST
5876   * @retval State of bit (1 or 0).
5877   */
5878 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
5879 {
5880   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
5881 }
5882 
5883 /**
5884   * @brief  Check if RCC_C1 flag Pin reset is set or not.
5885   * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST
5886   * @retval State of bit (1 or 0).
5887   */
5888 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
5889 {
5890   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
5891 }
5892 
5893 /**
5894   * @brief  Check if RCC_C1 flag BOR reset is set or not.
5895   * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST
5896   * @retval State of bit (1 or 0).
5897   */
5898 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
5899 {
5900   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5901 }
5902 
5903 /**
5904   * @brief  Check if RCC_C1 flag D1 reset is set or not.
5905   * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST
5906   * @retval State of bit (1 or 0).
5907   */
5908 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
5909 {
5910   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
5911 }
5912 
5913 /**
5914   * @brief  Check if RCC_C1 flag D2 reset is set or not.
5915   * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST
5916   * @retval State of bit (1 or 0).
5917   */
5918 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
5919 {
5920   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
5921 }
5922 
5923 /**
5924   * @brief  Check if RCC_C1 flag CPU reset is set or not.
5925   * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST
5926   * @retval State of bit (1 or 0).
5927   */
5928 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
5929 {
5930   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
5931 }
5932 
5933 /**
5934   * @brief  Check if RCC_C1 flag CPU2 reset is set or not.
5935   * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST
5936   * @retval State of bit (1 or 0).
5937   */
5938 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
5939 {
5940   return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
5941 }
5942 
5943 /**
5944   * @brief  Set RMVF bit to clear the reset flags.
5945   * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags
5946   * @retval None
5947   */
5948 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
5949 {
5950   SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
5951 }
5952 
5953 /**
5954   * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.
5955   * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST
5956   * @retval State of bit (1 or 0).
5957   */
5958 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
5959 {
5960   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5961 }
5962 
5963 /**
5964   * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.
5965   * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST
5966   * @retval State of bit (1 or 0).
5967   */
5968 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
5969 {
5970   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5971 }
5972 
5973 /**
5974   * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
5975   * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST
5976   * @retval State of bit (1 or 0).
5977   */
5978 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
5979 {
5980   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5981 }
5982 
5983 /**
5984   * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
5985   * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST
5986   * @retval State of bit (1 or 0).
5987   */
5988 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
5989 {
5990   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5991 }
5992 
5993 /**
5994   * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
5995   * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST
5996   * @retval State of bit (1 or 0).
5997   */
5998 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
5999 {
6000   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
6001 }
6002 
6003 /**
6004   * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
6005   * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST
6006   * @retval State of bit (1 or 0).
6007   */
6008 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
6009 {
6010   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
6011 }
6012 
6013 /**
6014   * @brief  Check if RCC_C2 flag Software reset is set or not.
6015   * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST
6016   * @retval State of bit (1 or 0).
6017   */
6018 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
6019 {
6020   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
6021 }
6022 
6023 /**
6024   * @brief  Check if RCC_C2 flag Software reset is set or not.
6025   * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST
6026   * @retval State of bit (1 or 0).
6027   */
6028 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
6029 {
6030   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
6031 }
6032 
6033 /**
6034   * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.
6035   * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST
6036   * @retval State of bit (1 or 0).
6037   */
6038 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
6039 {
6040   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
6041 }
6042 
6043 /**
6044   * @brief  Check if RCC_C2 flag Pin reset is set or not.
6045   * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST
6046   * @retval State of bit (1 or 0).
6047   */
6048 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
6049 {
6050   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
6051 }
6052 
6053 /**
6054   * @brief  Check if RCC_C2 flag BOR reset is set or not.
6055   * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST
6056   * @retval State of bit (1 or 0).
6057   */
6058 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
6059 {
6060   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
6061 }
6062 
6063 /**
6064   * @brief  Check if RCC_C2 flag D1 reset is set or not.
6065   * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST
6066   * @retval State of bit (1 or 0).
6067   */
6068 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
6069 {
6070   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
6071 }
6072 
6073 /**
6074   * @brief  Check if RCC_C2 flag D2 reset is set or not.
6075   * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST
6076   * @retval State of bit (1 or 0).
6077   */
6078 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
6079 {
6080   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
6081 }
6082 
6083 /**
6084   * @brief  Check if RCC_C2 flag CPU reset is set or not.
6085   * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST
6086   * @retval State of bit (1 or 0).
6087   */
6088 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
6089 {
6090   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
6091 }
6092 
6093 /**
6094   * @brief  Check if RCC_C2 flag CPU2 reset is set or not.
6095   * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST
6096   * @retval State of bit (1 or 0).
6097   */
6098 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
6099 {
6100   return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
6101 }
6102 
6103 /**
6104   * @brief  Set RMVF bit to clear the reset flags.
6105   * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags
6106   * @retval None
6107   */
6108 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
6109 {
6110   SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
6111 }
6112 #endif /*DUAL_CORE*/
6113 
6114 /**
6115   * @}
6116   */
6117 
6118 /** @defgroup RCC_LL_EF_IT_Management IT Management
6119   * @ingroup RTEMSBSPsARMSTM32H7
6120   * @{
6121   */
6122 
6123 /**
6124   * @brief  Enable LSI ready interrupt
6125   * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
6126   * @retval None
6127   */
6128 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6129 {
6130   SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6131 }
6132 
6133 /**
6134   * @brief  Enable LSE ready interrupt
6135   * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY
6136   * @retval None
6137   */
6138 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6139 {
6140   SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6141 }
6142 
6143 /**
6144   * @brief  Enable HSI ready interrupt
6145   * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
6146   * @retval None
6147   */
6148 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6149 {
6150   SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6151 }
6152 
6153 /**
6154   * @brief  Enable HSE ready interrupt
6155   * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY
6156   * @retval None
6157   */
6158 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6159 {
6160   SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6161 }
6162 
6163 /**
6164   * @brief  Enable CSI ready interrupt
6165   * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY
6166   * @retval None
6167   */
6168 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
6169 {
6170   SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6171 }
6172 
6173 /**
6174   * @brief  Enable HSI48 ready interrupt
6175   * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY
6176   * @retval None
6177   */
6178 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
6179 {
6180   SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6181 }
6182 
6183 /**
6184   * @brief  Enable PLL1 ready interrupt
6185   * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY
6186   * @retval None
6187   */
6188 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
6189 {
6190   SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6191 }
6192 
6193 /**
6194   * @brief  Enable PLL2 ready interrupt
6195   * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY
6196   * @retval None
6197   */
6198 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
6199 {
6200   SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6201 }
6202 
6203 /**
6204   * @brief  Enable PLL3 ready interrupt
6205   * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY
6206   * @retval None
6207   */
6208 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
6209 {
6210   SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6211 }
6212 
6213 /**
6214   * @brief  Enable LSECSS interrupt
6215   * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS
6216   * @retval None
6217   */
6218 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
6219 {
6220   SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6221 }
6222 
6223 /**
6224   * @brief  Disable LSI ready interrupt
6225   * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
6226   * @retval None
6227   */
6228 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6229 {
6230   CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6231 }
6232 
6233 /**
6234   * @brief  Disable LSE ready interrupt
6235   * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY
6236   * @retval None
6237   */
6238 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6239 {
6240   CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6241 }
6242 
6243 /**
6244   * @brief  Disable HSI ready interrupt
6245   * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
6246   * @retval None
6247   */
6248 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6249 {
6250   CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6251 }
6252 
6253 /**
6254   * @brief  Disable HSE ready interrupt
6255   * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY
6256   * @retval None
6257   */
6258 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6259 {
6260   CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6261 }
6262 
6263 /**
6264   * @brief  Disable CSI ready interrupt
6265   * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY
6266   * @retval None
6267   */
6268 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
6269 {
6270   CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6271 }
6272 
6273 /**
6274   * @brief  Disable HSI48 ready interrupt
6275   * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY
6276   * @retval None
6277   */
6278 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
6279 {
6280   CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6281 }
6282 
6283 /**
6284   * @brief  Disable PLL1 ready interrupt
6285   * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY
6286   * @retval None
6287   */
6288 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
6289 {
6290   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6291 }
6292 
6293 /**
6294   * @brief  Disable PLL2 ready interrupt
6295   * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY
6296   * @retval None
6297   */
6298 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
6299 {
6300   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6301 }
6302 
6303 /**
6304   * @brief  Disable PLL3 ready interrupt
6305   * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY
6306   * @retval None
6307   */
6308 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
6309 {
6310   CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6311 }
6312 
6313 /**
6314   * @brief  Disable LSECSS interrupt
6315   * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS
6316   * @retval None
6317   */
6318 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
6319 {
6320   CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6321 }
6322 
6323 /**
6324   * @brief  Checks if LSI ready interrupt source is enabled or disabled.
6325   * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY
6326   * @retval State of bit (1 or 0).
6327   */
6328 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
6329 {
6330   return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
6331 }
6332 
6333 /**
6334   * @brief  Checks if LSE ready interrupt source is enabled or disabled.
6335   * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY
6336   * @retval State of bit (1 or 0).
6337   */
6338 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
6339 {
6340   return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
6341 }
6342 
6343 /**
6344   * @brief  Checks if HSI ready interrupt source is enabled or disabled.
6345   * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY
6346   * @retval State of bit (1 or 0).
6347   */
6348 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
6349 {
6350   return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
6351 }
6352 
6353 /**
6354   * @brief  Checks if HSE ready interrupt source is enabled or disabled.
6355   * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY
6356   * @retval State of bit (1 or 0).
6357   */
6358 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
6359 {
6360   return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
6361 }
6362 
6363 /**
6364   * @brief  Checks if CSI ready interrupt source is enabled or disabled.
6365   * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY
6366   * @retval State of bit (1 or 0).
6367   */
6368 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
6369 {
6370   return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
6371 }
6372 
6373 /**
6374   * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.
6375   * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY
6376   * @retval State of bit (1 or 0).
6377   */
6378 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
6379 {
6380   return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
6381 }
6382 
6383 /**
6384   * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.
6385   * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY
6386   * @retval State of bit (1 or 0).
6387   */
6388 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
6389 {
6390   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
6391 }
6392 
6393 /**
6394   * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.
6395   * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY
6396   * @retval State of bit (1 or 0).
6397   */
6398 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
6399 {
6400   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
6401 }
6402 
6403 /**
6404   * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.
6405   * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY
6406   * @retval State of bit (1 or 0).
6407   */
6408 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
6409 {
6410   return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
6411 }
6412 
6413 /**
6414   * @brief  Checks if LSECSS interrupt source is enabled or disabled.
6415   * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS
6416   * @retval State of bit (1 or 0).
6417   */
6418 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
6419 {
6420   return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
6421 }
6422 /**
6423   * @}
6424   */
6425 
6426 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
6427 /** @defgroup RCC_LL_EF_Init De-initialization function
6428   * @ingroup RTEMSBSPsARMSTM32H7
6429   * @{
6430   */
6431 void LL_RCC_DeInit(void);
6432 /**
6433   * @}
6434   */
6435 
6436 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6437   * @ingroup RTEMSBSPsARMSTM32H7
6438   * @{
6439   */
6440 uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6441 
6442 void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6443 void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6444 void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6445 void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6446 
6447 uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6448 uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6449 uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6450 uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6451 uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6452 uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6453 uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6454 uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6455 uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6456 uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6457 uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6458 #if defined(DFSDM2_BASE)
6459 uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
6460 #endif /* DFSDM2_BASE */
6461 #if defined(DSI)
6462 uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6463 #endif /* DSI */
6464 uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
6465 uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6466 uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
6467 uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6468 uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
6469 #if defined(QUADSPI)
6470 uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
6471 #endif /* QUADSPI */
6472 #if defined(OCTOSPI1) || defined(OCTOSPI2)
6473 uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
6474 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
6475 uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6476 
6477 
6478 /**
6479   * @}
6480   */
6481 #endif /* USE_FULL_LL_DRIVER */
6482 
6483 /**
6484   * @}
6485   */
6486 
6487 
6488 /**
6489   * @}
6490   */
6491 #endif /* defined(RCC) */
6492 
6493 /**
6494   * @}
6495   */
6496 
6497 #ifdef __cplusplus
6498 }
6499 #endif
6500 
6501 #endif /* STM32H7xx_LL_RCC_H */
6502
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