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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_pwr.h 0004 * @author MCD Application Team 0005 * @brief Header file of PWR LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_PWR_H 0021 #define STM32H7xx_LL_PWR_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (PWR) 0035 0036 /** @defgroup PWR_LL PWR 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /* Private constants ---------------------------------------------------------*/ 0044 /** @defgroup PWR_LL_Private_Constants PWR Private Constants 0045 * @ingroup RTEMSBSPsARMSTM32H7 0046 * @{ 0047 */ 0048 0049 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines 0050 * @ingroup RTEMSBSPsARMSTM32H7 0051 * @brief Flags defines which can be used with LL_PWR_WriteReg function 0052 * @{ 0053 */ 0054 /* Wake-Up Pins PWR register offsets */ 0055 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL 0056 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU 0057 /** 0058 * @} 0059 */ 0060 /** 0061 * @} 0062 */ 0063 /* Private macros ------------------------------------------------------------*/ 0064 /* Exported types ------------------------------------------------------------*/ 0065 /* Exported constants --------------------------------------------------------*/ 0066 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 0067 * @ingroup RTEMSBSPsARMSTM32H7 0068 * @{ 0069 */ 0070 0071 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 0072 * @ingroup RTEMSBSPsARMSTM32H7 0073 * @brief Flags defines which can be used with LL_PWR_WriteReg function 0074 * @{ 0075 */ 0076 #define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */ 0077 #if defined (DUAL_CORE) 0078 #define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */ 0079 #endif /* DUAL_CORE */ 0080 #define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */ 0081 #if defined (PWR_WKUPCR_WKUPC5) 0082 #define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */ 0083 #endif /* defined (PWR_WKUPCR_WKUPC5) */ 0084 #define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */ 0085 #if defined (PWR_WKUPCR_WKUPC3) 0086 #define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */ 0087 #endif /* defined (PWR_WKUPCR_WKUPC3) */ 0088 #define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */ 0089 #define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */ 0090 /** 0091 * @} 0092 */ 0093 0094 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 0095 * @ingroup RTEMSBSPsARMSTM32H7 0096 * @brief Flags defines which can be used with LL_PWR_ReadReg function 0097 * @{ 0098 */ 0099 #define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */ 0100 #define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */ 0101 #define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */ 0102 #define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */ 0103 #if defined (PWR_CSR1_MMCVDO) 0104 #define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */ 0105 #endif /* PWR_CSR1_MMCVDO */ 0106 0107 #define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */ 0108 #define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */ 0109 #define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */ 0110 #define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */ 0111 #define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */ 0112 0113 #define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */ 0114 #define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */ 0115 0116 #if defined (PWR_CPUCR_SBF_D2) 0117 #define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ 0118 #endif /* PWR_CPUCR_SBF_D2 */ 0119 #if defined (PWR_CPUCR_SBF_D1) 0120 #define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ 0121 #endif /* PWR_CPUCR_SBF_D1 */ 0122 #define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */ 0123 #define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */ 0124 #if defined (DUAL_CORE) 0125 #define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */ 0126 #endif /* DUAL_CORE */ 0127 0128 #if defined (DUAL_CORE) 0129 #define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ 0130 #define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ 0131 #define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */ 0132 #define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */ 0133 #define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */ 0134 #endif /* DUAL_CORE */ 0135 0136 #if defined (PWR_CPUCR_PDDS_D2) 0137 #define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */ 0138 #else 0139 #define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */ 0140 #endif /* PWR_CPUCR_PDDS_D2 */ 0141 0142 #define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ 0143 #if defined (PWR_WKUPFR_WKUPF5) 0144 #define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ 0145 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 0146 #define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ 0147 #if defined (PWR_WKUPFR_WKUPF3) 0148 #define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ 0149 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 0150 #define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ 0151 #define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ 0152 /** 0153 * @} 0154 */ 0155 0156 /** @defgroup PWR_LL_EC_MODE_PWR Power mode 0157 * @ingroup RTEMSBSPsARMSTM32H7 0158 * @{ 0159 */ 0160 #if defined (PWR_CPUCR_PDDS_D2) 0161 #define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */ 0162 #define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */ 0163 #else 0164 #define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */ 0165 #define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */ 0166 #endif /* PWR_CPUCR_PDDS_D2 */ 0167 0168 #if defined (PWR_CPUCR_PDDS_D2) 0169 #define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */ 0170 #define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */ 0171 #endif /* PWR_CPUCR_PDDS_D2 */ 0172 0173 #if defined (PWR_CPUCR_PDDS_D2) 0174 #define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */ 0175 #define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */ 0176 #define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */ 0177 #else 0178 #define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */ 0179 #define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */ 0180 #define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */ 0181 #endif /* PWR_CPUCR_PDDS_D2 */ 0182 0183 #if defined (DUAL_CORE) 0184 #define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */ 0185 #define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */ 0186 #define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */ 0187 #define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */ 0188 #define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */ 0189 #define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */ 0190 #define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */ 0191 #endif /* DUAL_CORE */ 0192 /** 0193 * @} 0194 */ 0195 0196 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling 0197 * @ingroup RTEMSBSPsARMSTM32H7 0198 * @{ 0199 */ 0200 #if defined (PWR_CPUCR_PDDS_D2) 0201 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */ 0202 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */ 0203 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */ 0204 #if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ 0205 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ 0206 #else 0207 #define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */ 0208 #endif /* defined (SYSCFG_PWRCR_ODEN) */ 0209 #else 0210 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */ 0211 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */ 0212 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */ 0213 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ 0214 #endif /* PWR_CPUCR_PDDS_D2 */ 0215 /** 0216 * @} 0217 */ 0218 0219 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling 0220 * @ingroup RTEMSBSPsARMSTM32H7 0221 * @{ 0222 */ 0223 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ 0224 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ 0225 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ 0226 /** 0227 * @} 0228 */ 0229 0230 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode 0231 * @ingroup RTEMSBSPsARMSTM32H7 0232 * @{ 0233 */ 0234 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ 0235 #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ 0236 /** 0237 * @} 0238 */ 0239 0240 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector 0241 * @ingroup RTEMSBSPsARMSTM32H7 0242 * @{ 0243 */ 0244 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */ 0245 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ 0246 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */ 0247 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */ 0248 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */ 0249 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ 0250 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */ 0251 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */ 0252 /** 0253 * @} 0254 */ 0255 0256 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector 0257 * @ingroup RTEMSBSPsARMSTM32H7 0258 * @{ 0259 */ 0260 #define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */ 0261 #define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */ 0262 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */ 0263 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */ 0264 0265 /** 0266 * @} 0267 */ 0268 0269 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor 0270 * @ingroup RTEMSBSPsARMSTM32H7 0271 * @{ 0272 */ 0273 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */ 0274 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ 0275 /** 0276 * @} 0277 */ 0278 0279 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins 0280 * @ingroup RTEMSBSPsARMSTM32H7 0281 * @{ 0282 */ 0283 #define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ 0284 #define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ 0285 #if defined (PWR_WKUPEPR_WKUPEN3) 0286 #define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */ 0287 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 0288 #define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */ 0289 #if defined (PWR_WKUPEPR_WKUPEN5) 0290 #define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */ 0291 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 0292 #define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */ 0293 /** 0294 * @} 0295 */ 0296 0297 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration 0298 * @ingroup RTEMSBSPsARMSTM32H7 0299 * @{ 0300 */ 0301 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ 0302 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ 0303 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ 0304 /** 0305 * @} 0306 */ 0307 0308 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration 0309 * @ingroup RTEMSBSPsARMSTM32H7 0310 * @{ 0311 */ 0312 #define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ 0313 #if defined (SMPS) 0314 #define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ 0315 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ 0316 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ 0317 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 0318 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 0319 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ 0320 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ 0321 #endif /* SMPS */ 0322 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ 0323 /** 0324 * @} 0325 */ 0326 0327 /** 0328 * @} 0329 */ 0330 /* Exported macro ------------------------------------------------------------*/ 0331 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 0332 * @ingroup RTEMSBSPsARMSTM32H7 0333 * @{ 0334 */ 0335 0336 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros 0337 * @ingroup RTEMSBSPsARMSTM32H7 0338 * @{ 0339 */ 0340 0341 /** 0342 * @brief Write a value in PWR register 0343 * @param __REG__ Register to be written 0344 * @param __VALUE__ Value to be written in the register 0345 * @retval None 0346 */ 0347 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 0348 0349 /** 0350 * @brief Read a value in PWR register 0351 * @param __REG__ Register to be read 0352 * @retval Register value 0353 */ 0354 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 0355 /** 0356 * @} 0357 */ 0358 0359 /** 0360 * @} 0361 */ 0362 /* Exported functions --------------------------------------------------------*/ 0363 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 0364 * @ingroup RTEMSBSPsARMSTM32H7 0365 * @{ 0366 */ 0367 0368 /** @defgroup PWR_LL_EF_Configuration Configuration 0369 * @ingroup RTEMSBSPsARMSTM32H7 0370 * @{ 0371 */ 0372 0373 /** 0374 * @brief Set the voltage Regulator mode during deep sleep mode 0375 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS 0376 * @param RegulMode This parameter can be one of the following values: 0377 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 0378 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 0379 * @retval None 0380 */ 0381 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) 0382 { 0383 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); 0384 } 0385 0386 /** 0387 * @brief Get the voltage Regulator mode during deep sleep mode 0388 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS 0389 * @retval Returned value can be one of the following values: 0390 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 0391 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 0392 */ 0393 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) 0394 { 0395 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); 0396 } 0397 0398 /** 0399 * @brief Enable Power Voltage Detector 0400 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD 0401 * @retval None 0402 */ 0403 __STATIC_INLINE void LL_PWR_EnablePVD(void) 0404 { 0405 SET_BIT(PWR->CR1, PWR_CR1_PVDEN); 0406 } 0407 0408 /** 0409 * @brief Disable Power Voltage Detector 0410 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD 0411 * @retval None 0412 */ 0413 __STATIC_INLINE void LL_PWR_DisablePVD(void) 0414 { 0415 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); 0416 } 0417 0418 /** 0419 * @brief Check if Power Voltage Detector is enabled 0420 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD 0421 * @retval State of bit (1 or 0). 0422 */ 0423 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 0424 { 0425 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); 0426 } 0427 0428 /** 0429 * @brief Configure the voltage threshold detected by the Power Voltage Detector 0430 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel 0431 * @param PVDLevel This parameter can be one of the following values: 0432 * @arg @ref LL_PWR_PVDLEVEL_0 0433 * @arg @ref LL_PWR_PVDLEVEL_1 0434 * @arg @ref LL_PWR_PVDLEVEL_2 0435 * @arg @ref LL_PWR_PVDLEVEL_3 0436 * @arg @ref LL_PWR_PVDLEVEL_4 0437 * @arg @ref LL_PWR_PVDLEVEL_5 0438 * @arg @ref LL_PWR_PVDLEVEL_6 0439 * @arg @ref LL_PWR_PVDLEVEL_7 0440 * @retval None 0441 */ 0442 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 0443 { 0444 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); 0445 } 0446 0447 /** 0448 * @brief Get the voltage threshold detection 0449 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel 0450 * @retval Returned value can be one of the following values: 0451 * @arg @ref LL_PWR_PVDLEVEL_0 0452 * @arg @ref LL_PWR_PVDLEVEL_1 0453 * @arg @ref LL_PWR_PVDLEVEL_2 0454 * @arg @ref LL_PWR_PVDLEVEL_3 0455 * @arg @ref LL_PWR_PVDLEVEL_4 0456 * @arg @ref LL_PWR_PVDLEVEL_5 0457 * @arg @ref LL_PWR_PVDLEVEL_6 0458 * @arg @ref LL_PWR_PVDLEVEL_7 0459 */ 0460 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 0461 { 0462 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); 0463 } 0464 0465 /** 0466 * @brief Enable access to the backup domain 0467 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 0468 * @retval None 0469 */ 0470 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 0471 { 0472 SET_BIT(PWR->CR1, PWR_CR1_DBP); 0473 } 0474 0475 /** 0476 * @brief Disable access to the backup domain 0477 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 0478 * @retval None 0479 */ 0480 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 0481 { 0482 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 0483 } 0484 0485 /** 0486 * @brief Check if the backup domain is enabled 0487 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 0488 * @retval State of bit (1 or 0). 0489 */ 0490 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 0491 { 0492 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); 0493 } 0494 0495 /** 0496 * @brief Enable the Flash Power Down in Stop Mode 0497 * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown 0498 * @retval None 0499 */ 0500 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) 0501 { 0502 SET_BIT(PWR->CR1, PWR_CR1_FLPS); 0503 } 0504 0505 /** 0506 * @brief Disable the Flash Power Down in Stop Mode 0507 * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown 0508 * @retval None 0509 */ 0510 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) 0511 { 0512 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); 0513 } 0514 0515 /** 0516 * @brief Check if the Flash Power Down in Stop Mode is enabled 0517 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown 0518 * @retval State of bit (1 or 0). 0519 */ 0520 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) 0521 { 0522 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); 0523 } 0524 0525 #if defined (PWR_CR1_BOOSTE) 0526 /** 0527 * @brief Enable the Analog Voltage Booster (VDDA) 0528 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster 0529 * @retval None 0530 */ 0531 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) 0532 { 0533 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); 0534 } 0535 0536 /** 0537 * @brief Disable the Analog Voltage Booster (VDDA) 0538 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster 0539 * @retval None 0540 */ 0541 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) 0542 { 0543 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); 0544 } 0545 0546 /** 0547 * @brief Check if the Analog Voltage Booster (VDDA) is enabled 0548 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster 0549 * @retval State of bit (1 or 0). 0550 */ 0551 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) 0552 { 0553 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); 0554 } 0555 #endif /* PWR_CR1_BOOSTE */ 0556 0557 #if defined (PWR_CR1_AVD_READY) 0558 /** 0559 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready 0560 * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady 0561 * @retval None 0562 */ 0563 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) 0564 { 0565 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); 0566 } 0567 0568 /** 0569 * @brief Disable the Analog Voltage Ready (VDDA) 0570 * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady 0571 * @retval None 0572 */ 0573 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) 0574 { 0575 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); 0576 } 0577 0578 /** 0579 * @brief Check if the Analog Voltage Booster (VDDA) is enabled 0580 * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady 0581 * @retval State of bit (1 or 0). 0582 */ 0583 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) 0584 { 0585 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); 0586 } 0587 #endif /* PWR_CR1_AVD_READY */ 0588 0589 /** 0590 * @brief Set the internal Regulator output voltage in STOP mode 0591 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling 0592 * @param VoltageScaling This parameter can be one of the following values: 0593 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 0594 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 0595 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 0596 * @retval None 0597 */ 0598 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) 0599 { 0600 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); 0601 } 0602 0603 /** 0604 * @brief Get the internal Regulator output voltage in STOP mode 0605 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling 0606 * @retval Returned value can be one of the following values: 0607 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 0608 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 0609 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 0610 */ 0611 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) 0612 { 0613 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); 0614 } 0615 0616 /** 0617 * @brief Enable Analog Power Voltage Detector 0618 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD 0619 * @retval None 0620 */ 0621 __STATIC_INLINE void LL_PWR_EnableAVD(void) 0622 { 0623 SET_BIT(PWR->CR1, PWR_CR1_AVDEN); 0624 } 0625 0626 /** 0627 * @brief Disable Analog Power Voltage Detector 0628 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD 0629 * @retval None 0630 */ 0631 __STATIC_INLINE void LL_PWR_DisableAVD(void) 0632 { 0633 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); 0634 } 0635 0636 /** 0637 * @brief Check if Analog Power Voltage Detector is enabled 0638 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD 0639 * @retval State of bit (1 or 0). 0640 */ 0641 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) 0642 { 0643 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); 0644 } 0645 0646 /** 0647 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector 0648 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel 0649 * @param AVDLevel This parameter can be one of the following values: 0650 * @arg @ref LL_PWR_AVDLEVEL_0 0651 * @arg @ref LL_PWR_AVDLEVEL_1 0652 * @arg @ref LL_PWR_AVDLEVEL_2 0653 * @arg @ref LL_PWR_AVDLEVEL_3 0654 * @retval None 0655 */ 0656 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) 0657 { 0658 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); 0659 } 0660 0661 /** 0662 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector 0663 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel 0664 * @retval Returned value can be one of the following values: 0665 * @arg @ref LL_PWR_AVDLEVEL_0 0666 * @arg @ref LL_PWR_AVDLEVEL_1 0667 * @arg @ref LL_PWR_AVDLEVEL_2 0668 * @arg @ref LL_PWR_AVDLEVEL_3 0669 */ 0670 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) 0671 { 0672 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); 0673 } 0674 0675 #if defined (PWR_CR1_AXIRAM1SO) 0676 /** 0677 * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode 0678 * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff 0679 * @retval None 0680 */ 0681 __STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void) 0682 { 0683 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); 0684 } 0685 0686 /** 0687 * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode 0688 * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff 0689 * @retval None 0690 */ 0691 __STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void) 0692 { 0693 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); 0694 } 0695 0696 /** 0697 * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled 0698 * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff 0699 * @retval State of bit (1 or 0). 0700 */ 0701 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void) 0702 { 0703 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); 0704 } 0705 #endif /* PWR_CR1_AXIRAM1SO */ 0706 0707 #if defined (PWR_CR1_AXIRAM2SO) 0708 /** 0709 * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode 0710 * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff 0711 * @retval None 0712 */ 0713 __STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void) 0714 { 0715 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); 0716 } 0717 0718 /** 0719 * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode 0720 * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff 0721 * @retval None 0722 */ 0723 __STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void) 0724 { 0725 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); 0726 } 0727 0728 /** 0729 * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled 0730 * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff 0731 * @retval State of bit (1 or 0). 0732 */ 0733 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void) 0734 { 0735 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); 0736 } 0737 #endif /* PWR_CR1_AXIRAM2SO */ 0738 0739 #if defined (PWR_CR1_AXIRAM3SO) 0740 /** 0741 * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode 0742 * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff 0743 * @retval None 0744 */ 0745 __STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void) 0746 { 0747 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); 0748 } 0749 0750 /** 0751 * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode 0752 * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff 0753 * @retval None 0754 */ 0755 __STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void) 0756 { 0757 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); 0758 } 0759 0760 /** 0761 * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled 0762 * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff 0763 * @retval State of bit (1 or 0). 0764 */ 0765 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void) 0766 { 0767 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); 0768 } 0769 #endif /* PWR_CR1_AXIRAM3SO */ 0770 0771 #if defined (PWR_CR1_AHBRAM1SO) 0772 /** 0773 * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode 0774 * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff 0775 * @retval None 0776 */ 0777 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) 0778 { 0779 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); 0780 } 0781 0782 /** 0783 * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode 0784 * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff 0785 * @retval None 0786 */ 0787 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) 0788 { 0789 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); 0790 } 0791 0792 /** 0793 * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled 0794 * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff 0795 * @retval State of bit (1 or 0). 0796 */ 0797 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) 0798 { 0799 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); 0800 } 0801 #endif /* PWR_CR1_AHBRAM1SO */ 0802 0803 #if defined (PWR_CR1_AHBRAM2SO) 0804 /** 0805 * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode 0806 * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff 0807 * @retval None 0808 */ 0809 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) 0810 { 0811 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); 0812 } 0813 0814 /** 0815 * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode 0816 * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff 0817 * @retval None 0818 */ 0819 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) 0820 { 0821 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); 0822 } 0823 0824 /** 0825 * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled 0826 * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff 0827 * @retval State of bit (1 or 0). 0828 */ 0829 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) 0830 { 0831 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); 0832 } 0833 #endif /* PWR_CR1_AHBRAM2SO */ 0834 0835 #if defined (PWR_CR1_ITCMSO) 0836 /** 0837 * @brief Enable the ITCM shut-off in DStop/DStop2 mode 0838 * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff 0839 * @retval None 0840 */ 0841 __STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void) 0842 { 0843 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); 0844 } 0845 0846 /** 0847 * @brief Disable the ITCM shut-off in DStop/DStop2 mode 0848 * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff 0849 * @retval None 0850 */ 0851 __STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void) 0852 { 0853 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); 0854 } 0855 0856 /** 0857 * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled 0858 * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff 0859 * @retval State of bit (1 or 0). 0860 */ 0861 __STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void) 0862 { 0863 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); 0864 } 0865 #endif /* PWR_CR1_ITCMSO */ 0866 0867 #if defined (PWR_CR1_HSITFSO) 0868 /** 0869 * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode 0870 * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff 0871 * @retval None 0872 */ 0873 __STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void) 0874 { 0875 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); 0876 } 0877 0878 /** 0879 * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode 0880 * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff 0881 * @retval None 0882 */ 0883 __STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void) 0884 { 0885 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); 0886 } 0887 0888 /** 0889 * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled 0890 * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff 0891 * @retval State of bit (1 or 0). 0892 */ 0893 __STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void) 0894 { 0895 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); 0896 } 0897 #endif /* PWR_CR1_HSITFSO */ 0898 0899 #if defined (PWR_CR1_SRDRAMSO) 0900 /** 0901 * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode 0902 * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff 0903 * @retval None 0904 */ 0905 __STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void) 0906 { 0907 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); 0908 } 0909 0910 /** 0911 * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode 0912 * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff 0913 * @retval None 0914 */ 0915 __STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void) 0916 { 0917 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); 0918 } 0919 0920 /** 0921 * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled 0922 * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff 0923 * @retval State of bit (1 or 0). 0924 */ 0925 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void) 0926 { 0927 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); 0928 } 0929 #endif /* PWR_CR1_SRDRAMSO */ 0930 0931 /** 0932 * @brief Enable Backup Regulator 0933 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator 0934 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and 0935 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup 0936 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, 0937 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that 0938 * the data written into the RAM will be maintained in the Standby and VBAT modes. 0939 * @retval None 0940 */ 0941 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) 0942 { 0943 SET_BIT(PWR->CR2, PWR_CR2_BREN); 0944 } 0945 0946 /** 0947 * @brief Disable Backup Regulator 0948 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator 0949 * @retval None 0950 */ 0951 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) 0952 { 0953 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); 0954 } 0955 0956 /** 0957 * @brief Check if the backup Regulator is enabled 0958 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator 0959 * @retval State of bit (1 or 0). 0960 */ 0961 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) 0962 { 0963 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); 0964 } 0965 0966 /** 0967 * @brief Enable VBAT and Temperature monitoring 0968 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring 0969 * @retval None 0970 */ 0971 __STATIC_INLINE void LL_PWR_EnableMonitoring(void) 0972 { 0973 SET_BIT(PWR->CR2, PWR_CR2_MONEN); 0974 } 0975 0976 /** 0977 * @brief Disable VBAT and Temperature monitoring 0978 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring 0979 * @retval None 0980 */ 0981 __STATIC_INLINE void LL_PWR_DisableMonitoring(void) 0982 { 0983 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); 0984 } 0985 0986 /** 0987 * @brief Check if the VBAT and Temperature monitoring is enabled 0988 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring 0989 * @retval State of bit (1 or 0). 0990 */ 0991 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) 0992 { 0993 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); 0994 } 0995 0996 #if defined (SMPS) 0997 /** 0998 * @brief Configure the PWR supply 0999 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply 1000 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply 1001 * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply 1002 * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply 1003 * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply 1004 * @param SupplySource This parameter can be one of the following values: 1005 * @arg @ref LL_PWR_LDO_SUPPLY 1006 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY 1007 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO 1008 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO 1009 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO 1010 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO 1011 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT 1012 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT 1013 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 1014 * @retval None 1015 */ 1016 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) 1017 { 1018 /* Set the power supply configuration */ 1019 MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); 1020 } 1021 #else 1022 /** 1023 * @brief Configure the PWR supply 1024 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply 1025 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply 1026 * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply 1027 * @param SupplySource This parameter can be one of the following values: 1028 * @arg @ref LL_PWR_LDO_SUPPLY 1029 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 1030 * @retval None 1031 */ 1032 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) 1033 { 1034 /* Set the power supply configuration */ 1035 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); 1036 } 1037 #endif /* defined (SMPS) */ 1038 1039 #if defined (SMPS) 1040 /** 1041 * @brief Get the PWR supply 1042 * @rmtoll CR3 BYPASS LL_PWR_GetSupply 1043 * @rmtoll CR3 LDOEN LL_PWR_GetSupply 1044 * @rmtoll CR3 SMPSEN LL_PWR_GetSupply 1045 * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply 1046 * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply 1047 * @retval Returned value can be one of the following values: 1048 * @arg @ref LL_PWR_LDO_SUPPLY 1049 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY 1050 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO 1051 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO 1052 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO 1053 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO 1054 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT 1055 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT 1056 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 1057 */ 1058 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void) 1059 { 1060 /* Get the power supply configuration */ 1061 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); 1062 } 1063 #else 1064 /** 1065 * @brief Get the PWR supply 1066 * @rmtoll CR3 BYPASS LL_PWR_GetSupply 1067 * @rmtoll CR3 LDOEN LL_PWR_GetSupply 1068 * @rmtoll CR3 SCUEN LL_PWR_GetSupply 1069 * @retval Returned value can be one of the following values: 1070 * @arg @ref LL_PWR_LDO_SUPPLY 1071 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 1072 */ 1073 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void) 1074 { 1075 /* Get the power supply configuration */ 1076 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); 1077 } 1078 #endif /* defined (SMPS) */ 1079 1080 /** 1081 * @brief Enable battery charging 1082 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging 1083 * @retval None 1084 */ 1085 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 1086 { 1087 SET_BIT(PWR->CR3, PWR_CR3_VBE); 1088 } 1089 1090 /** 1091 * @brief Disable battery charging 1092 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging 1093 * @retval None 1094 */ 1095 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 1096 { 1097 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); 1098 } 1099 1100 /** 1101 * @brief Check if battery charging is enabled 1102 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging 1103 * @retval State of bit (1 or 0). 1104 */ 1105 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 1106 { 1107 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); 1108 } 1109 1110 /** 1111 * @brief Set the Battery charge resistor impedance 1112 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor 1113 * @param Resistor This parameter can be one of the following values: 1114 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 1115 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 1116 * @retval None 1117 */ 1118 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 1119 { 1120 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); 1121 } 1122 1123 /** 1124 * @brief Get the Battery charge resistor impedance 1125 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor 1126 * @retval Returned value can be one of the following values: 1127 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 1128 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 1129 */ 1130 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 1131 { 1132 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); 1133 } 1134 1135 /** 1136 * @brief Enable the USB regulator 1137 * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg 1138 * @retval None 1139 */ 1140 __STATIC_INLINE void LL_PWR_EnableUSBReg(void) 1141 { 1142 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); 1143 } 1144 1145 /** 1146 * @brief Disable the USB regulator 1147 * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg 1148 * @retval None 1149 */ 1150 __STATIC_INLINE void LL_PWR_DisableUSBReg(void) 1151 { 1152 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); 1153 } 1154 1155 /** 1156 * @brief Check if the USB regulator is enabled 1157 * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg 1158 * @retval State of bit (1 or 0). 1159 */ 1160 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) 1161 { 1162 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); 1163 } 1164 1165 /** 1166 * @brief Enable the USB voltage detector 1167 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector 1168 * @retval None 1169 */ 1170 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) 1171 { 1172 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); 1173 } 1174 1175 /** 1176 * @brief Disable the USB voltage detector 1177 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector 1178 * @retval None 1179 */ 1180 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) 1181 { 1182 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); 1183 } 1184 1185 /** 1186 * @brief Check if the USB voltage detector is enabled 1187 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector 1188 * @retval State of bit (1 or 0). 1189 */ 1190 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) 1191 { 1192 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); 1193 } 1194 1195 #if defined (PWR_CPUCR_PDDS_D2) 1196 /** 1197 * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep 1198 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode 1199 * @param PDMode This parameter can be one of the following values: 1200 * @arg @ref LL_PWR_CPU_MODE_D1STOP 1201 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY 1202 * @retval None 1203 */ 1204 __STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode) 1205 { 1206 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); 1207 } 1208 #else 1209 /** 1210 * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep 1211 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode 1212 * @param PDMode This parameter can be one of the following values: 1213 * @arg @ref LL_PWR_CPU_MODE_CDSTOP 1214 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 1215 * @retval None 1216 */ 1217 __STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode) 1218 { 1219 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); 1220 } 1221 #endif /* PWR_CPUCR_PDDS_D2 */ 1222 1223 #if defined (DUAL_CORE) 1224 /** 1225 * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep 1226 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode 1227 * @param PDMode This parameter can be one of the following values: 1228 * @arg @ref LL_PWR_CPU2_MODE_D1STOP 1229 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY 1230 * @retval None 1231 */ 1232 __STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode) 1233 { 1234 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); 1235 } 1236 #endif /* DUAL_CORE */ 1237 1238 #if defined (PWR_CPUCR_PDDS_D2) 1239 /** 1240 * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep 1241 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode 1242 * @retval Returned value can be one of the following values: 1243 * @arg @ref LL_PWR_CPU_MODE_D1STOP 1244 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY 1245 */ 1246 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void) 1247 { 1248 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); 1249 } 1250 #else 1251 /** 1252 * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep 1253 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode 1254 * @retval Returned value can be one of the following values: 1255 * @arg @ref LL_PWR_CPU_MODE_CDSTOP 1256 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 1257 */ 1258 __STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void) 1259 { 1260 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); 1261 } 1262 #endif /* PWR_CPUCR_PDDS_D2 */ 1263 1264 #if defined (DUAL_CORE) 1265 /** 1266 * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep 1267 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode 1268 * @retval Returned value can be one of the following values: 1269 * @arg @ref LL_PWR_CPU2_MODE_D1STOP 1270 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY 1271 */ 1272 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void) 1273 { 1274 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); 1275 } 1276 #endif /* DUAL_CORE */ 1277 1278 #if defined (PWR_CPUCR_PDDS_D2) 1279 /** 1280 * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep 1281 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode 1282 * @param PDMode This parameter can be one of the following values: 1283 * @arg @ref LL_PWR_CPU_MODE_D2STOP 1284 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY 1285 * @retval None 1286 */ 1287 __STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode) 1288 { 1289 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); 1290 } 1291 #endif /* PWR_CPUCR_PDDS_D2 */ 1292 1293 #if defined (DUAL_CORE) 1294 /** 1295 * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep 1296 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode 1297 * @param PDMode This parameter can be one of the following values: 1298 * @arg @ref LL_PWR_CPU2_MODE_D2STOP 1299 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY 1300 * @retval None 1301 */ 1302 __STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode) 1303 { 1304 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); 1305 } 1306 #endif /* DUAL_CORE */ 1307 1308 #if defined (PWR_CPUCR_PDDS_D2) 1309 /** 1310 * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep 1311 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode 1312 * @retval Returned value can be one of the following values: 1313 * @arg @ref LL_PWR_CPU_MODE_D2STOP 1314 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY 1315 */ 1316 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void) 1317 { 1318 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); 1319 } 1320 #endif /* PWR_CPUCR_PDDS_D2 */ 1321 1322 #if defined (DUAL_CORE) 1323 /** 1324 * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep 1325 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode 1326 * @retval Returned value can be one of the following values: 1327 * @arg @ref LL_PWR_CPU2_MODE_D2STOP 1328 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY 1329 */ 1330 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void) 1331 { 1332 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); 1333 } 1334 #endif /* DUAL_CORE */ 1335 1336 #if defined (PWR_CPUCR_PDDS_D2) 1337 /** 1338 * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep 1339 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode 1340 * @param PDMode This parameter can be one of the following values: 1341 * @arg @ref LL_PWR_CPU_MODE_D3STOP 1342 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY 1343 * @retval None 1344 */ 1345 __STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode) 1346 { 1347 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); 1348 } 1349 #else 1350 /** 1351 * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep 1352 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode 1353 * @param PDMode This parameter can be one of the following values: 1354 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP 1355 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY 1356 * @retval None 1357 */ 1358 __STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode) 1359 { 1360 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); 1361 } 1362 #endif /* PWR_CPUCR_PDDS_D2 */ 1363 1364 #if defined (DUAL_CORE) 1365 /** 1366 * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep 1367 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode 1368 * @param PDMode This parameter can be one of the following values: 1369 * @arg @ref LL_PWR_CPU2_MODE_D3STOP 1370 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY 1371 * @retval None 1372 */ 1373 __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode) 1374 { 1375 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); 1376 } 1377 #endif /* DUAL_CORE */ 1378 1379 #if defined (PWR_CPUCR_PDDS_D2) 1380 /** 1381 * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep 1382 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode 1383 * @retval Returned value can be one of the following values: 1384 * @arg @ref LL_PWR_CPU_MODE_D3STOP 1385 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY 1386 */ 1387 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void) 1388 { 1389 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); 1390 } 1391 #else 1392 /** 1393 * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep 1394 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode 1395 * @retval Returned value can be one of the following values: 1396 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP 1397 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY 1398 */ 1399 __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void) 1400 { 1401 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); 1402 } 1403 #endif /* PWR_CPUCR_PDDS_D2 */ 1404 1405 #if defined (DUAL_CORE) 1406 /** 1407 * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep 1408 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode 1409 * @retval Returned value can be one of the following values: 1410 * @arg @ref LL_PWR_CPU2_MODE_D3STOP 1411 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY 1412 */ 1413 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void) 1414 { 1415 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); 1416 } 1417 #endif /* DUAL_CORE */ 1418 1419 #if defined (DUAL_CORE) 1420 /** 1421 * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode 1422 * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1 1423 * @retval None 1424 */ 1425 __STATIC_INLINE void LL_PWR_HoldCPU1(void) 1426 { 1427 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); 1428 } 1429 1430 /** 1431 * @brief Release the CPU1 and allocated peripherals 1432 * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1 1433 * @retval None 1434 */ 1435 __STATIC_INLINE void LL_PWR_ReleaseCPU1(void) 1436 { 1437 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); 1438 } 1439 1440 /** 1441 * @brief Ckeck if the CPU1 and allocated peripherals are held 1442 * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held 1443 * @retval State of bit (1 or 0). 1444 */ 1445 __STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void) 1446 { 1447 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); 1448 } 1449 1450 /** 1451 * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode 1452 * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2 1453 * @retval None 1454 */ 1455 __STATIC_INLINE void LL_PWR_HoldCPU2(void) 1456 { 1457 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); 1458 } 1459 1460 /** 1461 * @brief Release the CPU2 and allocated peripherals 1462 * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2 1463 * @retval None 1464 */ 1465 __STATIC_INLINE void LL_PWR_ReleaseCPU2(void) 1466 { 1467 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); 1468 } 1469 1470 /** 1471 * @brief Ckeck if the CPU2 and allocated peripherals are held 1472 * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held 1473 * @retval State of bit (1 or 0). 1474 */ 1475 __STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void) 1476 { 1477 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); 1478 } 1479 #endif /* DUAL_CORE */ 1480 1481 #if defined (PWR_CPUCR_PDDS_D2) 1482 /** 1483 * @brief D3 domain remains in Run mode regardless of CPU subsystem modes 1484 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode 1485 * @retval None 1486 */ 1487 __STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void) 1488 { 1489 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); 1490 } 1491 #else 1492 /** 1493 * @brief SRD domain remains in Run mode regardless of CPU subsystem modes 1494 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode 1495 * @retval None 1496 */ 1497 __STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void) 1498 { 1499 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); 1500 } 1501 #endif /* PWR_CPUCR_PDDS_D2 */ 1502 1503 #if defined (DUAL_CORE) 1504 /** 1505 * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes 1506 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode 1507 * @retval None 1508 */ 1509 __STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void) 1510 { 1511 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); 1512 } 1513 #endif /* DUAL_CORE */ 1514 1515 #if defined (PWR_CPUCR_PDDS_D2) 1516 /** 1517 * @brief D3 domain follows CPU subsystem modes 1518 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode 1519 * @retval None 1520 */ 1521 __STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void) 1522 { 1523 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); 1524 } 1525 #else 1526 /** 1527 * @brief SRD domain follows CPU subsystem modes 1528 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode 1529 * @retval None 1530 */ 1531 __STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void) 1532 { 1533 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); 1534 } 1535 #endif /* PWR_CPUCR_PDDS_D2 */ 1536 1537 #if defined (DUAL_CORE) 1538 /** 1539 * @brief D3 domain follows CPU2 subsystem modes 1540 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode 1541 * @retval None 1542 */ 1543 __STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void) 1544 { 1545 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); 1546 } 1547 #endif /* DUAL_CORE */ 1548 1549 #if defined (PWR_CPUCR_PDDS_D2) 1550 /** 1551 * @brief Check if D3 is kept in Run mode when CPU enters low power mode 1552 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode 1553 * @retval State of bit (1 or 0). 1554 */ 1555 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void) 1556 { 1557 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); 1558 } 1559 #else 1560 /** 1561 * @brief Check if SRD is kept in Run mode when CPU enters low power mode 1562 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode 1563 * @retval State of bit (1 or 0). 1564 */ 1565 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void) 1566 { 1567 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); 1568 } 1569 #endif /* PWR_CPUCR_PDDS_D2 */ 1570 1571 #if defined (DUAL_CORE) 1572 /** 1573 * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode 1574 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode 1575 * @retval State of bit (1 or 0). 1576 */ 1577 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void) 1578 { 1579 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); 1580 } 1581 #endif /* DUAL_CORE */ 1582 1583 /** 1584 * @brief Set the main internal Regulator output voltage 1585 * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling 1586 * @param VoltageScaling This parameter can be one of the following values: 1587 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 1588 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 1589 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 1590 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 1591 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 1592 * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1. 1593 * @retval None 1594 */ 1595 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 1596 { 1597 #if defined (PWR_CPUCR_PDDS_D2) 1598 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); 1599 #else 1600 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); 1601 #endif /* PWR_CPUCR_PDDS_D2 */ 1602 } 1603 1604 /** 1605 * @brief Get the main internal Regulator output voltage 1606 * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling 1607 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 1608 * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit. 1609 * @retval Returned value can be one of the following values: 1610 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 1611 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 1612 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 1613 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 1614 */ 1615 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 1616 { 1617 #if defined (PWR_CPUCR_PDDS_D2) 1618 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); 1619 #else 1620 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); 1621 #endif /* PWR_CPUCR_PDDS_D2 */ 1622 } 1623 1624 /** 1625 * @brief Enable the WakeUp PINx functionality 1626 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n 1627 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n 1628 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n 1629 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n 1630 * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n 1631 * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin 1632 * @param WakeUpPin This parameter can be one of the following values: 1633 * @arg @ref LL_PWR_WAKEUP_PIN1 1634 * @arg @ref LL_PWR_WAKEUP_PIN2 1635 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1636 * @arg @ref LL_PWR_WAKEUP_PIN4 1637 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1638 * @arg @ref LL_PWR_WAKEUP_PIN6 1639 * 1640 * (*) value not defined in all devices. 1641 * 1642 * @retval None 1643 */ 1644 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 1645 { 1646 SET_BIT(PWR->WKUPEPR, WakeUpPin); 1647 } 1648 1649 /** 1650 * @brief Disable the WakeUp PINx functionality 1651 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n 1652 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n 1653 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n 1654 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n 1655 * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n 1656 * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin 1657 * @param WakeUpPin This parameter can be one of the following values: 1658 * @arg @ref LL_PWR_WAKEUP_PIN1 1659 * @arg @ref LL_PWR_WAKEUP_PIN2 1660 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1661 * @arg @ref LL_PWR_WAKEUP_PIN4 1662 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1663 * @arg @ref LL_PWR_WAKEUP_PIN6 1664 * 1665 * (*) value not defined in all devices. 1666 * 1667 * @retval None 1668 */ 1669 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 1670 { 1671 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); 1672 } 1673 1674 /** 1675 * @brief Check if the WakeUp PINx functionality is enabled 1676 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n 1677 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n 1678 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n 1679 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n 1680 * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n 1681 * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin 1682 * @param WakeUpPin This parameter can be one of the following values: 1683 * @arg @ref LL_PWR_WAKEUP_PIN1 1684 * @arg @ref LL_PWR_WAKEUP_PIN2 1685 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1686 * @arg @ref LL_PWR_WAKEUP_PIN4 1687 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1688 * @arg @ref LL_PWR_WAKEUP_PIN6 1689 * 1690 * (*) value not defined in all devices. 1691 * 1692 * @retval State of bit (1 or 0). 1693 */ 1694 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 1695 { 1696 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); 1697 } 1698 1699 /** 1700 * @brief Set the Wake-Up pin polarity low for the event detection 1701 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n 1702 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n 1703 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n 1704 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n 1705 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n 1706 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow 1707 * @param WakeUpPin This parameter can be one of the following values: 1708 * @arg @ref LL_PWR_WAKEUP_PIN1 1709 * @arg @ref LL_PWR_WAKEUP_PIN2 1710 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1711 * @arg @ref LL_PWR_WAKEUP_PIN4 1712 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1713 * @arg @ref LL_PWR_WAKEUP_PIN6 1714 * 1715 * (*) value not defined in all devices. 1716 * 1717 * @retval None 1718 */ 1719 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 1720 { 1721 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); 1722 } 1723 1724 /** 1725 * @brief Set the Wake-Up pin polarity high for the event detection 1726 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n 1727 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n 1728 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n 1729 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n 1730 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n 1731 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh 1732 * @param WakeUpPin This parameter can be one of the following values: 1733 * @arg @ref LL_PWR_WAKEUP_PIN1 1734 * @arg @ref LL_PWR_WAKEUP_PIN2 1735 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1736 * @arg @ref LL_PWR_WAKEUP_PIN4 1737 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1738 * @arg @ref LL_PWR_WAKEUP_PIN6 1739 * 1740 * (*) value not defined in all devices. 1741 * 1742 * @retval None 1743 */ 1744 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 1745 { 1746 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); 1747 } 1748 1749 /** 1750 * @brief Get the Wake-Up pin polarity for the event detection 1751 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n 1752 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n 1753 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n 1754 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n 1755 * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n 1756 * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow 1757 * @param WakeUpPin This parameter can be one of the following values: 1758 * @arg @ref LL_PWR_WAKEUP_PIN1 1759 * @arg @ref LL_PWR_WAKEUP_PIN2 1760 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1761 * @arg @ref LL_PWR_WAKEUP_PIN4 1762 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1763 * @arg @ref LL_PWR_WAKEUP_PIN6 1764 * 1765 * (*) value not defined in all devices. 1766 * 1767 * @retval State of bit (1 or 0). 1768 */ 1769 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 1770 { 1771 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); 1772 } 1773 1774 /** 1775 * @brief Set the Wake-Up pin Pull None 1776 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n 1777 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n 1778 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n 1779 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n 1780 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n 1781 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone 1782 * @param WakeUpPin This parameter can be one of the following values: 1783 * @arg @ref LL_PWR_WAKEUP_PIN1 1784 * @arg @ref LL_PWR_WAKEUP_PIN2 1785 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1786 * @arg @ref LL_PWR_WAKEUP_PIN4 1787 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1788 * @arg @ref LL_PWR_WAKEUP_PIN6 1789 * 1790 * (*) value not defined in all devices. 1791 * 1792 * @retval None 1793 */ 1794 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) 1795 { 1796 MODIFY_REG(PWR->WKUPEPR, \ 1797 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 1798 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 1799 } 1800 1801 /** 1802 * @brief Set the Wake-Up pin Pull Up 1803 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n 1804 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n 1805 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n 1806 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n 1807 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n 1808 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp 1809 * @param WakeUpPin This parameter can be one of the following values: 1810 * @arg @ref LL_PWR_WAKEUP_PIN1 1811 * @arg @ref LL_PWR_WAKEUP_PIN2 1812 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1813 * @arg @ref LL_PWR_WAKEUP_PIN4 1814 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1815 * @arg @ref LL_PWR_WAKEUP_PIN6 1816 * 1817 * (*) value not defined in all devices. 1818 * 1819 * @retval None 1820 */ 1821 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) 1822 { 1823 MODIFY_REG(PWR->WKUPEPR, \ 1824 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 1825 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 1826 } 1827 1828 /** 1829 * @brief Set the Wake-Up pin Pull Down 1830 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n 1831 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n 1832 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n 1833 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n 1834 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n 1835 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown 1836 * @param WakeUpPin This parameter can be one of the following values: 1837 * @arg @ref LL_PWR_WAKEUP_PIN1 1838 * @arg @ref LL_PWR_WAKEUP_PIN2 1839 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1840 * @arg @ref LL_PWR_WAKEUP_PIN4 1841 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1842 * @arg @ref LL_PWR_WAKEUP_PIN6 1843 * 1844 * (*) value not defined in all devices. 1845 * 1846 * @retval None 1847 */ 1848 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) 1849 { 1850 MODIFY_REG(PWR->WKUPEPR, \ 1851 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 1852 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 1853 } 1854 1855 /** 1856 * @brief Get the Wake-Up pin pull 1857 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n 1858 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n 1859 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n 1860 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n 1861 * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n 1862 * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull 1863 * @param WakeUpPin This parameter can be one of the following values: 1864 * @arg @ref LL_PWR_WAKEUP_PIN1 1865 * @arg @ref LL_PWR_WAKEUP_PIN2 1866 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 1867 * @arg @ref LL_PWR_WAKEUP_PIN4 1868 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 1869 * @arg @ref LL_PWR_WAKEUP_PIN6 1870 * 1871 * (*) value not defined in all devices. 1872 * 1873 * @retval Returned value can be one of the following values: 1874 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL 1875 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP 1876 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN 1877 */ 1878 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) 1879 { 1880 uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 1881 1882 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); 1883 } 1884 1885 /** 1886 * @} 1887 */ 1888 1889 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 1890 * @ingroup RTEMSBSPsARMSTM32H7 1891 * @{ 1892 */ 1893 1894 /** 1895 * @brief Indicate whether VDD voltage is below the selected PVD threshold 1896 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO 1897 * @retval State of bit (1 or 0). 1898 */ 1899 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 1900 { 1901 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); 1902 } 1903 1904 /** 1905 * @brief Indicate whether the voltage level is ready for current actual used VOS 1906 * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS 1907 * @retval State of bit (1 or 0). 1908 */ 1909 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) 1910 { 1911 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); 1912 } 1913 1914 /** 1915 * @brief Indicate whether VDDA voltage is below the selected AVD threshold 1916 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO 1917 * @retval State of bit (1 or 0). 1918 */ 1919 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) 1920 { 1921 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); 1922 } 1923 1924 #if defined (PWR_CSR1_MMCVDO) 1925 /** 1926 * @brief Indicate whether VDDMMC voltage is below 1V2 1927 * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO 1928 * @retval State of bit (1 or 0). 1929 */ 1930 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void) 1931 { 1932 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); 1933 } 1934 #endif /* PWR_CSR1_MMCVDO */ 1935 1936 /** 1937 * @brief Get Backup Regulator ready Flag 1938 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR 1939 * @retval State of bit (1 or 0). 1940 */ 1941 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) 1942 { 1943 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); 1944 } 1945 1946 /** 1947 * @brief Indicate whether the VBAT level is above or below low threshold 1948 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL 1949 * @retval State of bit (1 or 0). 1950 */ 1951 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) 1952 { 1953 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); 1954 } 1955 1956 /** 1957 * @brief Indicate whether the VBAT level is above or below high threshold 1958 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH 1959 * @retval State of bit (1 or 0). 1960 */ 1961 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) 1962 { 1963 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); 1964 } 1965 1966 /** 1967 * @brief Indicate whether the CPU temperature level is above or below low threshold 1968 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL 1969 * @retval State of bit (1 or 0). 1970 */ 1971 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) 1972 { 1973 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); 1974 } 1975 1976 /** 1977 * @brief Indicate whether the CPU temperature level is above or below high threshold 1978 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH 1979 * @retval State of bit (1 or 0). 1980 */ 1981 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) 1982 { 1983 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); 1984 } 1985 1986 #if defined (SMPS) 1987 /** 1988 * @brief Indicate whether the SMPS external supply is ready or not 1989 * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT 1990 * @retval State of bit (1 or 0). 1991 */ 1992 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void) 1993 { 1994 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); 1995 } 1996 #endif /* SMPS */ 1997 1998 /** 1999 * @brief Indicate whether the USB supply is ready or not 2000 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB 2001 * @retval State of bit (1 or 0). 2002 */ 2003 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void) 2004 { 2005 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); 2006 } 2007 2008 #if defined (DUAL_CORE) 2009 /** 2010 * @brief Get HOLD2 Flag 2011 * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2 2012 * @retval State of bit (1 or 0). 2013 */ 2014 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void) 2015 { 2016 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); 2017 } 2018 2019 /** 2020 * @brief Get HOLD1 Flag 2021 * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1 2022 * @retval State of bit (1 or 0). 2023 */ 2024 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void) 2025 { 2026 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); 2027 } 2028 #endif /* DUAL_CORE */ 2029 2030 /** 2031 * @brief Get CPU System Stop Flag 2032 * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP 2033 * @retval State of bit (1 or 0). 2034 */ 2035 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void) 2036 { 2037 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); 2038 } 2039 2040 #if defined (DUAL_CORE) 2041 /** 2042 * @brief Get CPU2 System Stop Flag 2043 * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP 2044 * @retval State of bit (1 or 0). 2045 */ 2046 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void) 2047 { 2048 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); 2049 } 2050 #endif /* DUAL_CORE */ 2051 2052 /** 2053 * @brief Get CPU System Standby Flag 2054 * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB 2055 * @retval State of bit (1 or 0). 2056 */ 2057 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void) 2058 { 2059 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); 2060 } 2061 2062 #if defined (DUAL_CORE) 2063 /** 2064 * @brief Get CPU2 System Standby Flag 2065 * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB 2066 * @retval State of bit (1 or 0). 2067 */ 2068 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void) 2069 { 2070 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); 2071 } 2072 #endif /* DUAL_CORE */ 2073 2074 #if defined (PWR_CPUCR_SBF_D1) 2075 /** 2076 * @brief Get CPU D1 Domain Standby Flag 2077 * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1 2078 * @retval State of bit (1 or 0). 2079 */ 2080 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void) 2081 { 2082 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); 2083 } 2084 #endif /* PWR_CPUCR_SBF_D1 */ 2085 2086 #if defined (DUAL_CORE) 2087 /** 2088 * @brief Get CPU2 D1 Domain Standby Flag 2089 * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1 2090 * @retval State of bit (1 or 0). 2091 */ 2092 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void) 2093 { 2094 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); 2095 } 2096 #endif /* DUAL_CORE */ 2097 2098 #if defined (PWR_CPUCR_SBF_D2) 2099 /** 2100 * @brief Get CPU D2 Domain Standby Flag 2101 * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2 2102 * @retval State of bit (1 or 0). 2103 */ 2104 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void) 2105 { 2106 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); 2107 } 2108 #endif /* PWR_CPUCR_SBF_D2 */ 2109 2110 #if defined (DUAL_CORE) 2111 /** 2112 * @brief Get CPU2 D2 Domain Standby Flag 2113 * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2 2114 * @retval State of bit (1 or 0). 2115 */ 2116 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void) 2117 { 2118 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); 2119 } 2120 #endif /* DUAL_CORE */ 2121 2122 2123 /** 2124 * @brief Indicate whether the Regulator is ready in the selected voltage range 2125 * or if its output voltage is still changing to the required voltage level 2126 * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS 2127 * @retval State of bit (1 or 0). 2128 */ 2129 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) 2130 { 2131 #if defined (PWR_CPUCR_PDDS_D2) 2132 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); 2133 #else 2134 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); 2135 #endif /* PWR_CPUCR_PDDS_D2 */ 2136 } 2137 2138 /** 2139 * @brief Get Wake-up Flag 6 2140 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6 2141 * @retval State of bit (1 or 0). 2142 */ 2143 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) 2144 { 2145 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); 2146 } 2147 2148 #if defined (PWR_WKUPFR_WKUPF5) 2149 /** 2150 * @brief Get Wake-up Flag 5 2151 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5 2152 * @retval State of bit (1 or 0). 2153 */ 2154 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 2155 { 2156 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); 2157 } 2158 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 2159 2160 /** 2161 * @brief Get Wake-up Flag 4 2162 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 2163 * @retval State of bit (1 or 0). 2164 */ 2165 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 2166 { 2167 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); 2168 } 2169 2170 #if defined (PWR_WKUPFR_WKUPF3) 2171 /** 2172 * @brief Get Wake-up Flag 3 2173 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 2174 * @retval State of bit (1 or 0). 2175 */ 2176 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 2177 { 2178 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); 2179 } 2180 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 2181 2182 /** 2183 * @brief Get Wake-up Flag 2 2184 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 2185 * @retval State of bit (1 or 0). 2186 */ 2187 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 2188 { 2189 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); 2190 } 2191 2192 /** 2193 * @brief Get Wake-up Flag 1 2194 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 2195 * @retval State of bit (1 or 0). 2196 */ 2197 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 2198 { 2199 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); 2200 } 2201 2202 /** 2203 * @brief Clear CPU STANDBY, STOP and HOLD flags 2204 * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU 2205 * @retval None 2206 */ 2207 __STATIC_INLINE void LL_PWR_ClearFlag_CPU(void) 2208 { 2209 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); 2210 } 2211 2212 #if defined (DUAL_CORE) 2213 /** 2214 * @brief Clear CPU2 STANDBY, STOP and HOLD flags 2215 * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2 2216 * @retval None 2217 */ 2218 __STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void) 2219 { 2220 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); 2221 } 2222 #endif /* DUAL_CORE */ 2223 2224 /** 2225 * @brief Clear Wake-up Flag 6 2226 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6 2227 * @retval None 2228 */ 2229 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) 2230 { 2231 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); 2232 } 2233 2234 #if defined (PWR_WKUPCR_WKUPC5) 2235 /** 2236 * @brief Clear Wake-up Flag 5 2237 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5 2238 * @retval None 2239 */ 2240 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 2241 { 2242 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); 2243 } 2244 #endif /* defined (PWR_WKUPCR_WKUPC5) */ 2245 2246 /** 2247 * @brief Clear Wake-up Flag 4 2248 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 2249 * @retval None 2250 */ 2251 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 2252 { 2253 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); 2254 } 2255 2256 #if defined (PWR_WKUPCR_WKUPC3) 2257 /** 2258 * @brief Clear Wake-up Flag 3 2259 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 2260 * @retval None 2261 */ 2262 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 2263 { 2264 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); 2265 } 2266 #endif /* defined (PWR_WKUPCR_WKUPC3) */ 2267 2268 /** 2269 * @brief Clear Wake-up Flag 2 2270 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 2271 * @retval None 2272 */ 2273 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 2274 { 2275 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); 2276 } 2277 2278 /** 2279 * @brief Clear Wake-up Flag 1 2280 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 2281 * @retval None 2282 */ 2283 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 2284 { 2285 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); 2286 } 2287 2288 #if defined (USE_FULL_LL_DRIVER) 2289 /** @defgroup PWR_LL_EF_Init De-initialization function 2290 * @ingroup RTEMSBSPsARMSTM32H7 2291 * @{ 2292 */ 2293 ErrorStatus LL_PWR_DeInit(void); 2294 /** 2295 * @} 2296 */ 2297 #endif /* defined (USE_FULL_LL_DRIVER) */ 2298 2299 2300 /** 2301 * @} 2302 */ 2303 2304 /** 2305 * @} 2306 */ 2307 2308 /** 2309 * @} 2310 */ 2311 2312 #endif /* defined (PWR) */ 2313 2314 /** 2315 * @} 2316 */ 2317 2318 #ifdef __cplusplus 2319 } 2320 #endif 2321 2322 #endif /* STM32H7xx_LL_PWR_H */ 2323
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