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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_lpuart.h 0004 * @author MCD Application Team 0005 * @brief Header file of LPUART LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_LPUART_H 0021 #define STM32H7xx_LL_LPUART_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (LPUART1) 0035 0036 /** @defgroup LPUART_LL LPUART 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables 0044 * @ingroup RTEMSBSPsARMSTM32H7 0045 * @{ 0046 */ 0047 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ 0048 static const uint16_t LPUART_PRESCALER_TAB[] = 0049 { 0050 (uint16_t)1, 0051 (uint16_t)2, 0052 (uint16_t)4, 0053 (uint16_t)6, 0054 (uint16_t)8, 0055 (uint16_t)10, 0056 (uint16_t)12, 0057 (uint16_t)16, 0058 (uint16_t)32, 0059 (uint16_t)64, 0060 (uint16_t)128, 0061 (uint16_t)256 0062 }; 0063 /** 0064 * @} 0065 */ 0066 0067 /* Private constants ---------------------------------------------------------*/ 0068 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants 0069 * @ingroup RTEMSBSPsARMSTM32H7 0070 * @{ 0071 */ 0072 /* Defines used in Baud Rate related macros and corresponding register setting computation */ 0073 #define LPUART_LPUARTDIV_FREQ_MUL 256U 0074 #define LPUART_BRR_MASK 0x000FFFFFU 0075 #define LPUART_BRR_MIN_VALUE 0x00000300U 0076 /** 0077 * @} 0078 */ 0079 0080 0081 /* Private macros ------------------------------------------------------------*/ 0082 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0083 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros 0084 * @ingroup RTEMSBSPsARMSTM32H7 0085 * @{ 0086 */ 0087 /** 0088 * @} 0089 */ 0090 #endif /*USE_FULL_LL_DRIVER*/ 0091 0092 /* Exported types ------------------------------------------------------------*/ 0093 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0094 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures 0095 * @ingroup RTEMSBSPsARMSTM32H7 0096 * @{ 0097 */ 0098 0099 /** 0100 * @brief LL LPUART Init Structure definition 0101 */ 0102 typedef struct 0103 { 0104 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. 0105 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. 0106 0107 This feature can be modified afterwards using unitary 0108 function @ref LL_LPUART_SetPrescaler().*/ 0109 0110 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. 0111 0112 This feature can be modified afterwards using unitary 0113 function @ref LL_LPUART_SetBaudRate().*/ 0114 0115 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. 0116 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. 0117 0118 This feature can be modified afterwards using unitary 0119 function @ref LL_LPUART_SetDataWidth().*/ 0120 0121 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 0122 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. 0123 0124 This feature can be modified afterwards using unitary 0125 function @ref LL_LPUART_SetStopBitsLength().*/ 0126 0127 uint32_t Parity; /*!< Specifies the parity mode. 0128 This parameter can be a value of @ref LPUART_LL_EC_PARITY. 0129 0130 This feature can be modified afterwards using unitary 0131 function @ref LL_LPUART_SetParity().*/ 0132 0133 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. 0134 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. 0135 0136 This feature can be modified afterwards using unitary 0137 function @ref LL_LPUART_SetTransferDirection().*/ 0138 0139 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. 0140 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. 0141 0142 This feature can be modified afterwards using unitary 0143 function @ref LL_LPUART_SetHWFlowCtrl().*/ 0144 0145 } LL_LPUART_InitTypeDef; 0146 0147 /** 0148 * @} 0149 */ 0150 #endif /* USE_FULL_LL_DRIVER */ 0151 0152 /* Exported constants --------------------------------------------------------*/ 0153 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants 0154 * @ingroup RTEMSBSPsARMSTM32H7 0155 * @{ 0156 */ 0157 0158 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines 0159 * @ingroup RTEMSBSPsARMSTM32H7 0160 * @brief Flags defines which can be used with LL_LPUART_WriteReg function 0161 * @{ 0162 */ 0163 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ 0164 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ 0165 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ 0166 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ 0167 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ 0168 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ 0169 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ 0170 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ 0171 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ 0172 /** 0173 * @} 0174 */ 0175 0176 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines 0177 * @ingroup RTEMSBSPsARMSTM32H7 0178 * @brief Flags defines which can be used with LL_LPUART_ReadReg function 0179 * @{ 0180 */ 0181 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ 0182 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ 0183 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ 0184 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ 0185 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ 0186 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ 0187 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ 0188 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ 0189 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ 0190 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 0191 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ 0192 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ 0193 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ 0194 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ 0195 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ 0196 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ 0197 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ 0198 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ 0199 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ 0200 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ 0201 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ 0202 /** 0203 * @} 0204 */ 0205 0206 /** @defgroup LPUART_LL_EC_IT IT Defines 0207 * @ingroup RTEMSBSPsARMSTM32H7 0208 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions 0209 * @{ 0210 */ 0211 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ 0212 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty 0213 interrupt enable */ 0214 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ 0215 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO 0216 not full interrupt enable */ 0217 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 0218 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ 0219 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ 0220 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ 0221 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ 0222 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ 0223 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ 0224 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ 0225 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ 0226 /** 0227 * @} 0228 */ 0229 0230 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold 0231 * @ingroup RTEMSBSPsARMSTM32H7 0232 * @{ 0233 */ 0234 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ 0235 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ 0236 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ 0237 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ 0238 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ 0239 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ 0240 /** 0241 * @} 0242 */ 0243 0244 /** @defgroup LPUART_LL_EC_DIRECTION Direction 0245 * @ingroup RTEMSBSPsARMSTM32H7 0246 * @{ 0247 */ 0248 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ 0249 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ 0250 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ 0251 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ 0252 /** 0253 * @} 0254 */ 0255 0256 /** @defgroup LPUART_LL_EC_PARITY Parity Control 0257 * @ingroup RTEMSBSPsARMSTM32H7 0258 * @{ 0259 */ 0260 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ 0261 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ 0262 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ 0263 /** 0264 * @} 0265 */ 0266 0267 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup 0268 * @ingroup RTEMSBSPsARMSTM32H7 0269 * @{ 0270 */ 0271 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ 0272 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ 0273 /** 0274 * @} 0275 */ 0276 0277 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth 0278 * @ingroup RTEMSBSPsARMSTM32H7 0279 * @{ 0280 */ 0281 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ 0282 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ 0283 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ 0284 /** 0285 * @} 0286 */ 0287 0288 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler 0289 * @ingroup RTEMSBSPsARMSTM32H7 0290 * @{ 0291 */ 0292 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ 0293 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ 0294 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ 0295 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ 0296 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ 0297 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ 0298 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ 0299 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ 0300 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ 0301 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ 0302 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ 0303 USART_PRESC_PRESCALER_1 |\ 0304 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ 0305 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ 0306 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ 0307 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ 0308 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ 0309 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ 0310 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ 0311 USART_PRESC_PRESCALER_1 |\ 0312 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ 0313 /** 0314 * @} 0315 */ 0316 0317 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits 0318 * @ingroup RTEMSBSPsARMSTM32H7 0319 * @{ 0320 */ 0321 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ 0322 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ 0323 /** 0324 * @} 0325 */ 0326 0327 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap 0328 * @ingroup RTEMSBSPsARMSTM32H7 0329 * @{ 0330 */ 0331 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ 0332 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ 0333 /** 0334 * @} 0335 */ 0336 0337 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 0338 * @ingroup RTEMSBSPsARMSTM32H7 0339 * @{ 0340 */ 0341 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ 0342 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ 0343 /** 0344 * @} 0345 */ 0346 0347 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion 0348 * @ingroup RTEMSBSPsARMSTM32H7 0349 * @{ 0350 */ 0351 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ 0352 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ 0353 /** 0354 * @} 0355 */ 0356 0357 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion 0358 * @ingroup RTEMSBSPsARMSTM32H7 0359 * @{ 0360 */ 0361 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received 0362 in positive/direct logic. (1=H, 0=L) */ 0363 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received 0364 in negative/inverse logic. (1=L, 0=H). 0365 The parity bit is also inverted. */ 0366 /** 0367 * @} 0368 */ 0369 0370 /** @defgroup LPUART_LL_EC_BITORDER Bit Order 0371 * @ingroup RTEMSBSPsARMSTM32H7 0372 * @{ 0373 */ 0374 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, 0375 following the start bit */ 0376 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, 0377 following the start bit */ 0378 /** 0379 * @} 0380 */ 0381 0382 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection 0383 * @ingroup RTEMSBSPsARMSTM32H7 0384 * @{ 0385 */ 0386 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ 0387 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ 0388 /** 0389 * @} 0390 */ 0391 0392 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control 0393 * @ingroup RTEMSBSPsARMSTM32H7 0394 * @{ 0395 */ 0396 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ 0397 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested 0398 when there is space in the receive buffer */ 0399 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted 0400 when the nCTS input is asserted (tied to 0)*/ 0401 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ 0402 /** 0403 * @} 0404 */ 0405 0406 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation 0407 * @ingroup RTEMSBSPsARMSTM32H7 0408 * @{ 0409 */ 0410 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ 0411 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ 0412 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ 0413 /** 0414 * @} 0415 */ 0416 0417 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity 0418 * @ingroup RTEMSBSPsARMSTM32H7 0419 * @{ 0420 */ 0421 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ 0422 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ 0423 /** 0424 * @} 0425 */ 0426 0427 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data 0428 * @ingroup RTEMSBSPsARMSTM32H7 0429 * @{ 0430 */ 0431 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ 0432 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ 0433 /** 0434 * @} 0435 */ 0436 0437 /** 0438 * @} 0439 */ 0440 0441 /* Exported macro ------------------------------------------------------------*/ 0442 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros 0443 * @ingroup RTEMSBSPsARMSTM32H7 0444 * @{ 0445 */ 0446 0447 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros 0448 * @ingroup RTEMSBSPsARMSTM32H7 0449 * @{ 0450 */ 0451 0452 /** 0453 * @brief Write a value in LPUART register 0454 * @param __INSTANCE__ LPUART Instance 0455 * @param __REG__ Register to be written 0456 * @param __VALUE__ Value to be written in the register 0457 * @retval None 0458 */ 0459 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0460 0461 /** 0462 * @brief Read a value in LPUART register 0463 * @param __INSTANCE__ LPUART Instance 0464 * @param __REG__ Register to be read 0465 * @retval Register value 0466 */ 0467 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0468 /** 0469 * @} 0470 */ 0471 0472 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros 0473 * @ingroup RTEMSBSPsARMSTM32H7 0474 * @{ 0475 */ 0476 0477 /** 0478 * @brief Compute LPUARTDIV value according to Peripheral Clock and 0479 * expected Baud Rate (20-bit value of LPUARTDIV is returned) 0480 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance 0481 * @param __PRESCALER__ This parameter can be one of the following values: 0482 * @arg @ref LL_LPUART_PRESCALER_DIV1 0483 * @arg @ref LL_LPUART_PRESCALER_DIV2 0484 * @arg @ref LL_LPUART_PRESCALER_DIV4 0485 * @arg @ref LL_LPUART_PRESCALER_DIV6 0486 * @arg @ref LL_LPUART_PRESCALER_DIV8 0487 * @arg @ref LL_LPUART_PRESCALER_DIV10 0488 * @arg @ref LL_LPUART_PRESCALER_DIV12 0489 * @arg @ref LL_LPUART_PRESCALER_DIV16 0490 * @arg @ref LL_LPUART_PRESCALER_DIV32 0491 * @arg @ref LL_LPUART_PRESCALER_DIV64 0492 * @arg @ref LL_LPUART_PRESCALER_DIV128 0493 * @arg @ref LL_LPUART_PRESCALER_DIV256 0494 * @param __BAUDRATE__ Baud Rate value to achieve 0495 * @retval LPUARTDIV value to be used for BRR register filling 0496 */ 0497 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ 0498 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ 0499 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) 0500 0501 /** 0502 * @} 0503 */ 0504 0505 /** 0506 * @} 0507 */ 0508 0509 /* Exported functions --------------------------------------------------------*/ 0510 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions 0511 * @ingroup RTEMSBSPsARMSTM32H7 0512 * @{ 0513 */ 0514 0515 /** @defgroup LPUART_LL_EF_Configuration Configuration functions 0516 * @ingroup RTEMSBSPsARMSTM32H7 0517 * @{ 0518 */ 0519 0520 /** 0521 * @brief LPUART Enable 0522 * @rmtoll CR1 UE LL_LPUART_Enable 0523 * @param LPUARTx LPUART Instance 0524 * @retval None 0525 */ 0526 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) 0527 { 0528 SET_BIT(LPUARTx->CR1, USART_CR1_UE); 0529 } 0530 0531 /** 0532 * @brief LPUART Disable 0533 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, 0534 * and current operations are discarded. The configuration of the LPUART is kept, but all the status 0535 * flags, in the LPUARTx_ISR are set to their default values. 0536 * @note In order to go into low-power mode without generating errors on the line, 0537 * the TE bit must be reset before and the software must wait 0538 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. 0539 * The DMA requests are also reset when UE = 0 so the DMA channel must 0540 * be disabled before resetting the UE bit. 0541 * @rmtoll CR1 UE LL_LPUART_Disable 0542 * @param LPUARTx LPUART Instance 0543 * @retval None 0544 */ 0545 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) 0546 { 0547 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); 0548 } 0549 0550 /** 0551 * @brief Indicate if LPUART is enabled 0552 * @rmtoll CR1 UE LL_LPUART_IsEnabled 0553 * @param LPUARTx LPUART Instance 0554 * @retval State of bit (1 or 0). 0555 */ 0556 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) 0557 { 0558 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); 0559 } 0560 0561 /** 0562 * @brief FIFO Mode Enable 0563 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO 0564 * @param LPUARTx LPUART Instance 0565 * @retval None 0566 */ 0567 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) 0568 { 0569 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); 0570 } 0571 0572 /** 0573 * @brief FIFO Mode Disable 0574 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO 0575 * @param LPUARTx LPUART Instance 0576 * @retval None 0577 */ 0578 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) 0579 { 0580 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); 0581 } 0582 0583 /** 0584 * @brief Indicate if FIFO Mode is enabled 0585 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO 0586 * @param LPUARTx LPUART Instance 0587 * @retval State of bit (1 or 0). 0588 */ 0589 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) 0590 { 0591 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); 0592 } 0593 0594 /** 0595 * @brief Configure TX FIFO Threshold 0596 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold 0597 * @param LPUARTx LPUART Instance 0598 * @param Threshold This parameter can be one of the following values: 0599 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0600 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0601 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0602 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0605 * @retval None 0606 */ 0607 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) 0608 { 0609 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); 0610 } 0611 0612 /** 0613 * @brief Return TX FIFO Threshold Configuration 0614 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold 0615 * @param LPUARTx LPUART Instance 0616 * @retval Returned value can be one of the following values: 0617 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0618 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0623 */ 0624 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) 0625 { 0626 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 0627 } 0628 0629 /** 0630 * @brief Configure RX FIFO Threshold 0631 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold 0632 * @param LPUARTx LPUART Instance 0633 * @param Threshold This parameter can be one of the following values: 0634 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0635 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0636 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0637 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0638 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0640 * @retval None 0641 */ 0642 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) 0643 { 0644 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); 0645 } 0646 0647 /** 0648 * @brief Return RX FIFO Threshold Configuration 0649 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold 0650 * @param LPUARTx LPUART Instance 0651 * @retval Returned value can be one of the following values: 0652 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0653 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0654 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0657 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0658 */ 0659 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) 0660 { 0661 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 0662 } 0663 0664 /** 0665 * @brief Configure TX and RX FIFOs Threshold 0666 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n 0667 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold 0668 * @param LPUARTx LPUART Instance 0669 * @param TXThreshold This parameter can be one of the following values: 0670 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0671 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0672 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0673 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0674 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0675 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0676 * @param RXThreshold This parameter can be one of the following values: 0677 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 0678 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 0679 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 0680 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 0681 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 0682 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 0683 * @retval None 0684 */ 0685 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) 0686 { 0687 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ 0688 (RXThreshold << USART_CR3_RXFTCFG_Pos)); 0689 } 0690 0691 /** 0692 * @brief LPUART enabled in STOP Mode 0693 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that 0694 * LPUART clock selection is HSI or LSE in RCC. 0695 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode 0696 * @param LPUARTx LPUART Instance 0697 * @retval None 0698 */ 0699 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) 0700 { 0701 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); 0702 } 0703 0704 /** 0705 * @brief LPUART disabled in STOP Mode 0706 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode 0707 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode 0708 * @param LPUARTx LPUART Instance 0709 * @retval None 0710 */ 0711 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) 0712 { 0713 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); 0714 } 0715 0716 /** 0717 * @brief Indicate if LPUART is enabled in STOP Mode 0718 * (able to wake up MCU from Stop mode or not) 0719 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode 0720 * @param LPUARTx LPUART Instance 0721 * @retval State of bit (1 or 0). 0722 */ 0723 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) 0724 { 0725 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); 0726 } 0727 0728 /** 0729 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 0730 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx 0731 * @param LPUARTx LPUART Instance 0732 * @retval None 0733 */ 0734 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) 0735 { 0736 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); 0737 } 0738 0739 /** 0740 * @brief Receiver Disable 0741 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx 0742 * @param LPUARTx LPUART Instance 0743 * @retval None 0744 */ 0745 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) 0746 { 0747 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); 0748 } 0749 0750 /** 0751 * @brief Transmitter Enable 0752 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx 0753 * @param LPUARTx LPUART Instance 0754 * @retval None 0755 */ 0756 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) 0757 { 0758 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); 0759 } 0760 0761 /** 0762 * @brief Transmitter Disable 0763 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx 0764 * @param LPUARTx LPUART Instance 0765 * @retval None 0766 */ 0767 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) 0768 { 0769 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); 0770 } 0771 0772 /** 0773 * @brief Configure simultaneously enabled/disabled states 0774 * of Transmitter and Receiver 0775 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n 0776 * CR1 TE LL_LPUART_SetTransferDirection 0777 * @param LPUARTx LPUART Instance 0778 * @param TransferDirection This parameter can be one of the following values: 0779 * @arg @ref LL_LPUART_DIRECTION_NONE 0780 * @arg @ref LL_LPUART_DIRECTION_RX 0781 * @arg @ref LL_LPUART_DIRECTION_TX 0782 * @arg @ref LL_LPUART_DIRECTION_TX_RX 0783 * @retval None 0784 */ 0785 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) 0786 { 0787 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 0788 } 0789 0790 /** 0791 * @brief Return enabled/disabled states of Transmitter and Receiver 0792 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n 0793 * CR1 TE LL_LPUART_GetTransferDirection 0794 * @param LPUARTx LPUART Instance 0795 * @retval Returned value can be one of the following values: 0796 * @arg @ref LL_LPUART_DIRECTION_NONE 0797 * @arg @ref LL_LPUART_DIRECTION_RX 0798 * @arg @ref LL_LPUART_DIRECTION_TX 0799 * @arg @ref LL_LPUART_DIRECTION_TX_RX 0800 */ 0801 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) 0802 { 0803 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 0804 } 0805 0806 /** 0807 * @brief Configure Parity (enabled/disabled and parity mode if enabled) 0808 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. 0809 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position 0810 * (depending on data width) and parity is checked on the received data. 0811 * @rmtoll CR1 PS LL_LPUART_SetParity\n 0812 * CR1 PCE LL_LPUART_SetParity 0813 * @param LPUARTx LPUART Instance 0814 * @param Parity This parameter can be one of the following values: 0815 * @arg @ref LL_LPUART_PARITY_NONE 0816 * @arg @ref LL_LPUART_PARITY_EVEN 0817 * @arg @ref LL_LPUART_PARITY_ODD 0818 * @retval None 0819 */ 0820 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) 0821 { 0822 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 0823 } 0824 0825 /** 0826 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 0827 * @rmtoll CR1 PS LL_LPUART_GetParity\n 0828 * CR1 PCE LL_LPUART_GetParity 0829 * @param LPUARTx LPUART Instance 0830 * @retval Returned value can be one of the following values: 0831 * @arg @ref LL_LPUART_PARITY_NONE 0832 * @arg @ref LL_LPUART_PARITY_EVEN 0833 * @arg @ref LL_LPUART_PARITY_ODD 0834 */ 0835 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) 0836 { 0837 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 0838 } 0839 0840 /** 0841 * @brief Set Receiver Wake Up method from Mute mode. 0842 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod 0843 * @param LPUARTx LPUART Instance 0844 * @param Method This parameter can be one of the following values: 0845 * @arg @ref LL_LPUART_WAKEUP_IDLELINE 0846 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK 0847 * @retval None 0848 */ 0849 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) 0850 { 0851 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); 0852 } 0853 0854 /** 0855 * @brief Return Receiver Wake Up method from Mute mode 0856 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod 0857 * @param LPUARTx LPUART Instance 0858 * @retval Returned value can be one of the following values: 0859 * @arg @ref LL_LPUART_WAKEUP_IDLELINE 0860 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK 0861 */ 0862 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) 0863 { 0864 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); 0865 } 0866 0867 /** 0868 * @brief Set Word length (nb of data bits, excluding start and stop bits) 0869 * @rmtoll CR1 M LL_LPUART_SetDataWidth 0870 * @param LPUARTx LPUART Instance 0871 * @param DataWidth This parameter can be one of the following values: 0872 * @arg @ref LL_LPUART_DATAWIDTH_7B 0873 * @arg @ref LL_LPUART_DATAWIDTH_8B 0874 * @arg @ref LL_LPUART_DATAWIDTH_9B 0875 * @retval None 0876 */ 0877 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) 0878 { 0879 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); 0880 } 0881 0882 /** 0883 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 0884 * @rmtoll CR1 M LL_LPUART_GetDataWidth 0885 * @param LPUARTx LPUART Instance 0886 * @retval Returned value can be one of the following values: 0887 * @arg @ref LL_LPUART_DATAWIDTH_7B 0888 * @arg @ref LL_LPUART_DATAWIDTH_8B 0889 * @arg @ref LL_LPUART_DATAWIDTH_9B 0890 */ 0891 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) 0892 { 0893 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); 0894 } 0895 0896 /** 0897 * @brief Allow switch between Mute Mode and Active mode 0898 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode 0899 * @param LPUARTx LPUART Instance 0900 * @retval None 0901 */ 0902 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) 0903 { 0904 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); 0905 } 0906 0907 /** 0908 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 0909 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode 0910 * @param LPUARTx LPUART Instance 0911 * @retval None 0912 */ 0913 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) 0914 { 0915 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); 0916 } 0917 0918 /** 0919 * @brief Indicate if switch between Mute Mode and Active mode is allowed 0920 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode 0921 * @param LPUARTx LPUART Instance 0922 * @retval State of bit (1 or 0). 0923 */ 0924 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) 0925 { 0926 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); 0927 } 0928 0929 /** 0930 * @brief Configure Clock source prescaler for baudrate generator and oversampling 0931 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler 0932 * @param LPUARTx LPUART Instance 0933 * @param PrescalerValue This parameter can be one of the following values: 0934 * @arg @ref LL_LPUART_PRESCALER_DIV1 0935 * @arg @ref LL_LPUART_PRESCALER_DIV2 0936 * @arg @ref LL_LPUART_PRESCALER_DIV4 0937 * @arg @ref LL_LPUART_PRESCALER_DIV6 0938 * @arg @ref LL_LPUART_PRESCALER_DIV8 0939 * @arg @ref LL_LPUART_PRESCALER_DIV10 0940 * @arg @ref LL_LPUART_PRESCALER_DIV12 0941 * @arg @ref LL_LPUART_PRESCALER_DIV16 0942 * @arg @ref LL_LPUART_PRESCALER_DIV32 0943 * @arg @ref LL_LPUART_PRESCALER_DIV64 0944 * @arg @ref LL_LPUART_PRESCALER_DIV128 0945 * @arg @ref LL_LPUART_PRESCALER_DIV256 0946 * @retval None 0947 */ 0948 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) 0949 { 0950 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); 0951 } 0952 0953 /** 0954 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling 0955 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler 0956 * @param LPUARTx LPUART Instance 0957 * @retval Returned value can be one of the following values: 0958 * @arg @ref LL_LPUART_PRESCALER_DIV1 0959 * @arg @ref LL_LPUART_PRESCALER_DIV2 0960 * @arg @ref LL_LPUART_PRESCALER_DIV4 0961 * @arg @ref LL_LPUART_PRESCALER_DIV6 0962 * @arg @ref LL_LPUART_PRESCALER_DIV8 0963 * @arg @ref LL_LPUART_PRESCALER_DIV10 0964 * @arg @ref LL_LPUART_PRESCALER_DIV12 0965 * @arg @ref LL_LPUART_PRESCALER_DIV16 0966 * @arg @ref LL_LPUART_PRESCALER_DIV32 0967 * @arg @ref LL_LPUART_PRESCALER_DIV64 0968 * @arg @ref LL_LPUART_PRESCALER_DIV128 0969 * @arg @ref LL_LPUART_PRESCALER_DIV256 0970 */ 0971 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) 0972 { 0973 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); 0974 } 0975 0976 /** 0977 * @brief Set the length of the stop bits 0978 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength 0979 * @param LPUARTx LPUART Instance 0980 * @param StopBits This parameter can be one of the following values: 0981 * @arg @ref LL_LPUART_STOPBITS_1 0982 * @arg @ref LL_LPUART_STOPBITS_2 0983 * @retval None 0984 */ 0985 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) 0986 { 0987 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); 0988 } 0989 0990 /** 0991 * @brief Retrieve the length of the stop bits 0992 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength 0993 * @param LPUARTx LPUART Instance 0994 * @retval Returned value can be one of the following values: 0995 * @arg @ref LL_LPUART_STOPBITS_1 0996 * @arg @ref LL_LPUART_STOPBITS_2 0997 */ 0998 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) 0999 { 1000 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); 1001 } 1002 1003 /** 1004 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 1005 * @note Call of this function is equivalent to following function call sequence : 1006 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function 1007 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function 1008 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function 1009 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n 1010 * CR1 PCE LL_LPUART_ConfigCharacter\n 1011 * CR1 M LL_LPUART_ConfigCharacter\n 1012 * CR2 STOP LL_LPUART_ConfigCharacter 1013 * @param LPUARTx LPUART Instance 1014 * @param DataWidth This parameter can be one of the following values: 1015 * @arg @ref LL_LPUART_DATAWIDTH_7B 1016 * @arg @ref LL_LPUART_DATAWIDTH_8B 1017 * @arg @ref LL_LPUART_DATAWIDTH_9B 1018 * @param Parity This parameter can be one of the following values: 1019 * @arg @ref LL_LPUART_PARITY_NONE 1020 * @arg @ref LL_LPUART_PARITY_EVEN 1021 * @arg @ref LL_LPUART_PARITY_ODD 1022 * @param StopBits This parameter can be one of the following values: 1023 * @arg @ref LL_LPUART_STOPBITS_1 1024 * @arg @ref LL_LPUART_STOPBITS_2 1025 * @retval None 1026 */ 1027 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, 1028 uint32_t StopBits) 1029 { 1030 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 1031 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); 1032 } 1033 1034 /** 1035 * @brief Configure TX/RX pins swapping setting. 1036 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap 1037 * @param LPUARTx LPUART Instance 1038 * @param SwapConfig This parameter can be one of the following values: 1039 * @arg @ref LL_LPUART_TXRX_STANDARD 1040 * @arg @ref LL_LPUART_TXRX_SWAPPED 1041 * @retval None 1042 */ 1043 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) 1044 { 1045 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); 1046 } 1047 1048 /** 1049 * @brief Retrieve TX/RX pins swapping configuration. 1050 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap 1051 * @param LPUARTx LPUART Instance 1052 * @retval Returned value can be one of the following values: 1053 * @arg @ref LL_LPUART_TXRX_STANDARD 1054 * @arg @ref LL_LPUART_TXRX_SWAPPED 1055 */ 1056 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) 1057 { 1058 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); 1059 } 1060 1061 /** 1062 * @brief Configure RX pin active level logic 1063 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel 1064 * @param LPUARTx LPUART Instance 1065 * @param PinInvMethod This parameter can be one of the following values: 1066 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD 1067 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED 1068 * @retval None 1069 */ 1070 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) 1071 { 1072 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); 1073 } 1074 1075 /** 1076 * @brief Retrieve RX pin active level logic configuration 1077 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel 1078 * @param LPUARTx LPUART Instance 1079 * @retval Returned value can be one of the following values: 1080 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD 1081 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED 1082 */ 1083 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) 1084 { 1085 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); 1086 } 1087 1088 /** 1089 * @brief Configure TX pin active level logic 1090 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel 1091 * @param LPUARTx LPUART Instance 1092 * @param PinInvMethod This parameter can be one of the following values: 1093 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD 1094 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED 1095 * @retval None 1096 */ 1097 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) 1098 { 1099 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); 1100 } 1101 1102 /** 1103 * @brief Retrieve TX pin active level logic configuration 1104 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel 1105 * @param LPUARTx LPUART Instance 1106 * @retval Returned value can be one of the following values: 1107 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD 1108 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED 1109 */ 1110 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) 1111 { 1112 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); 1113 } 1114 1115 /** 1116 * @brief Configure Binary data logic. 1117 * 1118 * @note Allow to define how Logical data from the data register are send/received : 1119 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 1120 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic 1121 * @param LPUARTx LPUART Instance 1122 * @param DataLogic This parameter can be one of the following values: 1123 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE 1124 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE 1125 * @retval None 1126 */ 1127 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) 1128 { 1129 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); 1130 } 1131 1132 /** 1133 * @brief Retrieve Binary data configuration 1134 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic 1135 * @param LPUARTx LPUART Instance 1136 * @retval Returned value can be one of the following values: 1137 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE 1138 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE 1139 */ 1140 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) 1141 { 1142 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); 1143 } 1144 1145 /** 1146 * @brief Configure transfer bit order (either Less or Most Significant Bit First) 1147 * @note MSB First means data is transmitted/received with the MSB first, following the start bit. 1148 * LSB First means data is transmitted/received with data bit 0 first, following the start bit. 1149 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder 1150 * @param LPUARTx LPUART Instance 1151 * @param BitOrder This parameter can be one of the following values: 1152 * @arg @ref LL_LPUART_BITORDER_LSBFIRST 1153 * @arg @ref LL_LPUART_BITORDER_MSBFIRST 1154 * @retval None 1155 */ 1156 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) 1157 { 1158 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 1159 } 1160 1161 /** 1162 * @brief Return transfer bit order (either Less or Most Significant Bit First) 1163 * @note MSB First means data is transmitted/received with the MSB first, following the start bit. 1164 * LSB First means data is transmitted/received with data bit 0 first, following the start bit. 1165 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder 1166 * @param LPUARTx LPUART Instance 1167 * @retval Returned value can be one of the following values: 1168 * @arg @ref LL_LPUART_BITORDER_LSBFIRST 1169 * @arg @ref LL_LPUART_BITORDER_MSBFIRST 1170 */ 1171 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) 1172 { 1173 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); 1174 } 1175 1176 /** 1177 * @brief Set Address of the LPUART node. 1178 * @note This is used in multiprocessor communication during Mute mode or Stop mode, 1179 * for wake up with address mark detection. 1180 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 1181 * (b7-b4 should be set to 0) 1182 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 1183 * (This is used in multiprocessor communication during Mute mode or Stop mode, 1184 * for wake up with 7-bit address mark detection. 1185 * The MSB of the character sent by the transmitter should be equal to 1. 1186 * It may also be used for character detection during normal reception, 1187 * Mute mode inactive (for example, end of block detection in ModBus protocol). 1188 * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 1189 * value and CMF flag is set on match) 1190 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n 1191 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress 1192 * @param LPUARTx LPUART Instance 1193 * @param AddressLen This parameter can be one of the following values: 1194 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B 1195 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B 1196 * @param NodeAddress 4 or 7 bit Address of the LPUART node. 1197 * @retval None 1198 */ 1199 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) 1200 { 1201 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 1202 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 1203 } 1204 1205 /** 1206 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. 1207 * @note If 4-bit Address Detection is selected in ADDM7, 1208 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 1209 * If 7-bit Address Detection is selected in ADDM7, 1210 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 1211 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress 1212 * @param LPUARTx LPUART Instance 1213 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) 1214 */ 1215 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) 1216 { 1217 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 1218 } 1219 1220 /** 1221 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 1222 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen 1223 * @param LPUARTx LPUART Instance 1224 * @retval Returned value can be one of the following values: 1225 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B 1226 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B 1227 */ 1228 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) 1229 { 1230 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); 1231 } 1232 1233 /** 1234 * @brief Enable RTS HW Flow Control 1235 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl 1236 * @param LPUARTx LPUART Instance 1237 * @retval None 1238 */ 1239 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) 1240 { 1241 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); 1242 } 1243 1244 /** 1245 * @brief Disable RTS HW Flow Control 1246 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl 1247 * @param LPUARTx LPUART Instance 1248 * @retval None 1249 */ 1250 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) 1251 { 1252 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); 1253 } 1254 1255 /** 1256 * @brief Enable CTS HW Flow Control 1257 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl 1258 * @param LPUARTx LPUART Instance 1259 * @retval None 1260 */ 1261 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) 1262 { 1263 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); 1264 } 1265 1266 /** 1267 * @brief Disable CTS HW Flow Control 1268 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl 1269 * @param LPUARTx LPUART Instance 1270 * @retval None 1271 */ 1272 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) 1273 { 1274 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); 1275 } 1276 1277 /** 1278 * @brief Configure HW Flow Control mode (both CTS and RTS) 1279 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n 1280 * CR3 CTSE LL_LPUART_SetHWFlowCtrl 1281 * @param LPUARTx LPUART Instance 1282 * @param HardwareFlowControl This parameter can be one of the following values: 1283 * @arg @ref LL_LPUART_HWCONTROL_NONE 1284 * @arg @ref LL_LPUART_HWCONTROL_RTS 1285 * @arg @ref LL_LPUART_HWCONTROL_CTS 1286 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS 1287 * @retval None 1288 */ 1289 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) 1290 { 1291 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 1292 } 1293 1294 /** 1295 * @brief Return HW Flow Control configuration (both CTS and RTS) 1296 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n 1297 * CR3 CTSE LL_LPUART_GetHWFlowCtrl 1298 * @param LPUARTx LPUART Instance 1299 * @retval Returned value can be one of the following values: 1300 * @arg @ref LL_LPUART_HWCONTROL_NONE 1301 * @arg @ref LL_LPUART_HWCONTROL_RTS 1302 * @arg @ref LL_LPUART_HWCONTROL_CTS 1303 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS 1304 */ 1305 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) 1306 { 1307 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 1308 } 1309 1310 /** 1311 * @brief Enable Overrun detection 1312 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect 1313 * @param LPUARTx LPUART Instance 1314 * @retval None 1315 */ 1316 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) 1317 { 1318 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); 1319 } 1320 1321 /** 1322 * @brief Disable Overrun detection 1323 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect 1324 * @param LPUARTx LPUART Instance 1325 * @retval None 1326 */ 1327 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) 1328 { 1329 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); 1330 } 1331 1332 /** 1333 * @brief Indicate if Overrun detection is enabled 1334 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect 1335 * @param LPUARTx LPUART Instance 1336 * @retval State of bit (1 or 0). 1337 */ 1338 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) 1339 { 1340 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); 1341 } 1342 1343 /** 1344 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1345 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType 1346 * @param LPUARTx LPUART Instance 1347 * @param Type This parameter can be one of the following values: 1348 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS 1349 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT 1350 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE 1351 * @retval None 1352 */ 1353 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) 1354 { 1355 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); 1356 } 1357 1358 /** 1359 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 1360 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType 1361 * @param LPUARTx LPUART Instance 1362 * @retval Returned value can be one of the following values: 1363 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS 1364 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT 1365 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE 1366 */ 1367 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) 1368 { 1369 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); 1370 } 1371 1372 /** 1373 * @brief Configure LPUART BRR register for achieving expected Baud Rate value. 1374 * 1375 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) 1376 * according to used Peripheral Clock and expected Baud Rate values 1377 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid 1378 * (Baud rate value != 0). 1379 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, 1380 * a care should be taken when generating high baud rates using high PeriphClk 1381 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. 1382 * @rmtoll BRR BRR LL_LPUART_SetBaudRate 1383 * @param LPUARTx LPUART Instance 1384 * @param PeriphClk Peripheral Clock 1385 * @param PrescalerValue This parameter can be one of the following values: 1386 * @arg @ref LL_LPUART_PRESCALER_DIV1 1387 * @arg @ref LL_LPUART_PRESCALER_DIV2 1388 * @arg @ref LL_LPUART_PRESCALER_DIV4 1389 * @arg @ref LL_LPUART_PRESCALER_DIV6 1390 * @arg @ref LL_LPUART_PRESCALER_DIV8 1391 * @arg @ref LL_LPUART_PRESCALER_DIV10 1392 * @arg @ref LL_LPUART_PRESCALER_DIV12 1393 * @arg @ref LL_LPUART_PRESCALER_DIV16 1394 * @arg @ref LL_LPUART_PRESCALER_DIV32 1395 * @arg @ref LL_LPUART_PRESCALER_DIV64 1396 * @arg @ref LL_LPUART_PRESCALER_DIV128 1397 * @arg @ref LL_LPUART_PRESCALER_DIV256 1398 * @param BaudRate Baud Rate 1399 * @retval None 1400 */ 1401 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, 1402 uint32_t BaudRate) 1403 { 1404 if (BaudRate != 0U) 1405 { 1406 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); 1407 } 1408 } 1409 1410 /** 1411 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register 1412 * (full BRR content), and to used Peripheral Clock values 1413 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. 1414 * @rmtoll BRR BRR LL_LPUART_GetBaudRate 1415 * @param LPUARTx LPUART Instance 1416 * @param PeriphClk Peripheral Clock 1417 * @param PrescalerValue This parameter can be one of the following values: 1418 * @arg @ref LL_LPUART_PRESCALER_DIV1 1419 * @arg @ref LL_LPUART_PRESCALER_DIV2 1420 * @arg @ref LL_LPUART_PRESCALER_DIV4 1421 * @arg @ref LL_LPUART_PRESCALER_DIV6 1422 * @arg @ref LL_LPUART_PRESCALER_DIV8 1423 * @arg @ref LL_LPUART_PRESCALER_DIV10 1424 * @arg @ref LL_LPUART_PRESCALER_DIV12 1425 * @arg @ref LL_LPUART_PRESCALER_DIV16 1426 * @arg @ref LL_LPUART_PRESCALER_DIV32 1427 * @arg @ref LL_LPUART_PRESCALER_DIV64 1428 * @arg @ref LL_LPUART_PRESCALER_DIV128 1429 * @arg @ref LL_LPUART_PRESCALER_DIV256 1430 * @retval Baud Rate 1431 */ 1432 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, 1433 uint32_t PrescalerValue) 1434 { 1435 uint32_t lpuartdiv; 1436 uint32_t brrresult; 1437 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); 1438 1439 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; 1440 1441 if (lpuartdiv >= LPUART_BRR_MIN_VALUE) 1442 { 1443 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); 1444 } 1445 else 1446 { 1447 brrresult = 0x0UL; 1448 } 1449 1450 return (brrresult); 1451 } 1452 1453 /** 1454 * @} 1455 */ 1456 1457 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature 1458 * @ingroup RTEMSBSPsARMSTM32H7 1459 * @{ 1460 */ 1461 1462 /** 1463 * @brief Enable Single Wire Half-Duplex mode 1464 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex 1465 * @param LPUARTx LPUART Instance 1466 * @retval None 1467 */ 1468 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) 1469 { 1470 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); 1471 } 1472 1473 /** 1474 * @brief Disable Single Wire Half-Duplex mode 1475 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex 1476 * @param LPUARTx LPUART Instance 1477 * @retval None 1478 */ 1479 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) 1480 { 1481 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); 1482 } 1483 1484 /** 1485 * @brief Indicate if Single Wire Half-Duplex mode is enabled 1486 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex 1487 * @param LPUARTx LPUART Instance 1488 * @retval State of bit (1 or 0). 1489 */ 1490 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) 1491 { 1492 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); 1493 } 1494 1495 /** 1496 * @} 1497 */ 1498 1499 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 1500 * @ingroup RTEMSBSPsARMSTM32H7 1501 * @{ 1502 */ 1503 1504 /** 1505 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). 1506 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime 1507 * @param LPUARTx LPUART Instance 1508 * @param Time Value between Min_Data=0 and Max_Data=31 1509 * @retval None 1510 */ 1511 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) 1512 { 1513 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 1514 } 1515 1516 /** 1517 * @brief Return DEDT (Driver Enable De-Assertion Time) 1518 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime 1519 * @param LPUARTx LPUART Instance 1520 * @retval Time value expressed on 5 bits ([4:0] bits) : c 1521 */ 1522 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) 1523 { 1524 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 1525 } 1526 1527 /** 1528 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 1529 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime 1530 * @param LPUARTx LPUART Instance 1531 * @param Time Value between Min_Data=0 and Max_Data=31 1532 * @retval None 1533 */ 1534 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) 1535 { 1536 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 1537 } 1538 1539 /** 1540 * @brief Return DEAT (Driver Enable Assertion Time) 1541 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime 1542 * @param LPUARTx LPUART Instance 1543 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 1544 */ 1545 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) 1546 { 1547 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 1548 } 1549 1550 /** 1551 * @brief Enable Driver Enable (DE) Mode 1552 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode 1553 * @param LPUARTx LPUART Instance 1554 * @retval None 1555 */ 1556 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) 1557 { 1558 SET_BIT(LPUARTx->CR3, USART_CR3_DEM); 1559 } 1560 1561 /** 1562 * @brief Disable Driver Enable (DE) Mode 1563 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode 1564 * @param LPUARTx LPUART Instance 1565 * @retval None 1566 */ 1567 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) 1568 { 1569 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); 1570 } 1571 1572 /** 1573 * @brief Indicate if Driver Enable (DE) Mode is enabled 1574 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode 1575 * @param LPUARTx LPUART Instance 1576 * @retval State of bit (1 or 0). 1577 */ 1578 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) 1579 { 1580 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); 1581 } 1582 1583 /** 1584 * @brief Select Driver Enable Polarity 1585 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity 1586 * @param LPUARTx LPUART Instance 1587 * @param Polarity This parameter can be one of the following values: 1588 * @arg @ref LL_LPUART_DE_POLARITY_HIGH 1589 * @arg @ref LL_LPUART_DE_POLARITY_LOW 1590 * @retval None 1591 */ 1592 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) 1593 { 1594 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); 1595 } 1596 1597 /** 1598 * @brief Return Driver Enable Polarity 1599 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity 1600 * @param LPUARTx LPUART Instance 1601 * @retval Returned value can be one of the following values: 1602 * @arg @ref LL_LPUART_DE_POLARITY_HIGH 1603 * @arg @ref LL_LPUART_DE_POLARITY_LOW 1604 */ 1605 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) 1606 { 1607 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); 1608 } 1609 1610 /** 1611 * @} 1612 */ 1613 1614 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management 1615 * @ingroup RTEMSBSPsARMSTM32H7 1616 * @{ 1617 */ 1618 1619 /** 1620 * @brief Check if the LPUART Parity Error Flag is set or not 1621 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE 1622 * @param LPUARTx LPUART Instance 1623 * @retval State of bit (1 or 0). 1624 */ 1625 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) 1626 { 1627 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); 1628 } 1629 1630 /** 1631 * @brief Check if the LPUART Framing Error Flag is set or not 1632 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE 1633 * @param LPUARTx LPUART Instance 1634 * @retval State of bit (1 or 0). 1635 */ 1636 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) 1637 { 1638 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); 1639 } 1640 1641 /** 1642 * @brief Check if the LPUART Noise error detected Flag is set or not 1643 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE 1644 * @param LPUARTx LPUART Instance 1645 * @retval State of bit (1 or 0). 1646 */ 1647 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) 1648 { 1649 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); 1650 } 1651 1652 /** 1653 * @brief Check if the LPUART OverRun Error Flag is set or not 1654 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE 1655 * @param LPUARTx LPUART Instance 1656 * @retval State of bit (1 or 0). 1657 */ 1658 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) 1659 { 1660 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); 1661 } 1662 1663 /** 1664 * @brief Check if the LPUART IDLE line detected Flag is set or not 1665 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE 1666 * @param LPUARTx LPUART Instance 1667 * @retval State of bit (1 or 0). 1668 */ 1669 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) 1670 { 1671 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); 1672 } 1673 1674 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ 1675 1676 /** 1677 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not 1678 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE 1679 * @param LPUARTx LPUART Instance 1680 * @retval State of bit (1 or 0). 1681 */ 1682 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) 1683 { 1684 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); 1685 } 1686 1687 /** 1688 * @brief Check if the LPUART Transmission Complete Flag is set or not 1689 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC 1690 * @param LPUARTx LPUART Instance 1691 * @retval State of bit (1 or 0). 1692 */ 1693 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) 1694 { 1695 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); 1696 } 1697 1698 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ 1699 1700 /** 1701 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not 1702 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF 1703 * @param LPUARTx LPUART Instance 1704 * @retval State of bit (1 or 0). 1705 */ 1706 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) 1707 { 1708 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); 1709 } 1710 1711 /** 1712 * @brief Check if the LPUART CTS interrupt Flag is set or not 1713 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS 1714 * @param LPUARTx LPUART Instance 1715 * @retval State of bit (1 or 0). 1716 */ 1717 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) 1718 { 1719 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); 1720 } 1721 1722 /** 1723 * @brief Check if the LPUART CTS Flag is set or not 1724 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS 1725 * @param LPUARTx LPUART Instance 1726 * @retval State of bit (1 or 0). 1727 */ 1728 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) 1729 { 1730 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); 1731 } 1732 1733 /** 1734 * @brief Check if the LPUART Busy Flag is set or not 1735 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY 1736 * @param LPUARTx LPUART Instance 1737 * @retval State of bit (1 or 0). 1738 */ 1739 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) 1740 { 1741 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); 1742 } 1743 1744 /** 1745 * @brief Check if the LPUART Character Match Flag is set or not 1746 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM 1747 * @param LPUARTx LPUART Instance 1748 * @retval State of bit (1 or 0). 1749 */ 1750 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) 1751 { 1752 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); 1753 } 1754 1755 /** 1756 * @brief Check if the LPUART Send Break Flag is set or not 1757 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK 1758 * @param LPUARTx LPUART Instance 1759 * @retval State of bit (1 or 0). 1760 */ 1761 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) 1762 { 1763 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); 1764 } 1765 1766 /** 1767 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not 1768 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU 1769 * @param LPUARTx LPUART Instance 1770 * @retval State of bit (1 or 0). 1771 */ 1772 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) 1773 { 1774 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); 1775 } 1776 1777 /** 1778 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not 1779 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP 1780 * @param LPUARTx LPUART Instance 1781 * @retval State of bit (1 or 0). 1782 */ 1783 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) 1784 { 1785 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); 1786 } 1787 1788 /** 1789 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not 1790 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK 1791 * @param LPUARTx LPUART Instance 1792 * @retval State of bit (1 or 0). 1793 */ 1794 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) 1795 { 1796 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); 1797 } 1798 1799 /** 1800 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not 1801 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK 1802 * @param LPUARTx LPUART Instance 1803 * @retval State of bit (1 or 0). 1804 */ 1805 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) 1806 { 1807 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); 1808 } 1809 1810 /** 1811 * @brief Check if the LPUART TX FIFO Empty Flag is set or not 1812 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE 1813 * @param LPUARTx LPUART Instance 1814 * @retval State of bit (1 or 0). 1815 */ 1816 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) 1817 { 1818 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); 1819 } 1820 1821 /** 1822 * @brief Check if the LPUART RX FIFO Full Flag is set or not 1823 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF 1824 * @param LPUARTx LPUART Instance 1825 * @retval State of bit (1 or 0). 1826 */ 1827 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) 1828 { 1829 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); 1830 } 1831 1832 /** 1833 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not 1834 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT 1835 * @param LPUARTx LPUART Instance 1836 * @retval State of bit (1 or 0). 1837 */ 1838 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) 1839 { 1840 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); 1841 } 1842 1843 /** 1844 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not 1845 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT 1846 * @param LPUARTx LPUART Instance 1847 * @retval State of bit (1 or 0). 1848 */ 1849 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) 1850 { 1851 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); 1852 } 1853 1854 /** 1855 * @brief Clear Parity Error Flag 1856 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE 1857 * @param LPUARTx LPUART Instance 1858 * @retval None 1859 */ 1860 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) 1861 { 1862 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); 1863 } 1864 1865 /** 1866 * @brief Clear Framing Error Flag 1867 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE 1868 * @param LPUARTx LPUART Instance 1869 * @retval None 1870 */ 1871 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) 1872 { 1873 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); 1874 } 1875 1876 /** 1877 * @brief Clear Noise detected Flag 1878 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE 1879 * @param LPUARTx LPUART Instance 1880 * @retval None 1881 */ 1882 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) 1883 { 1884 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); 1885 } 1886 1887 /** 1888 * @brief Clear OverRun Error Flag 1889 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE 1890 * @param LPUARTx LPUART Instance 1891 * @retval None 1892 */ 1893 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) 1894 { 1895 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); 1896 } 1897 1898 /** 1899 * @brief Clear IDLE line detected Flag 1900 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE 1901 * @param LPUARTx LPUART Instance 1902 * @retval None 1903 */ 1904 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) 1905 { 1906 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); 1907 } 1908 1909 /** 1910 * @brief Clear Transmission Complete Flag 1911 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC 1912 * @param LPUARTx LPUART Instance 1913 * @retval None 1914 */ 1915 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) 1916 { 1917 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); 1918 } 1919 1920 /** 1921 * @brief Clear CTS Interrupt Flag 1922 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS 1923 * @param LPUARTx LPUART Instance 1924 * @retval None 1925 */ 1926 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) 1927 { 1928 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); 1929 } 1930 1931 /** 1932 * @brief Clear Character Match Flag 1933 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM 1934 * @param LPUARTx LPUART Instance 1935 * @retval None 1936 */ 1937 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) 1938 { 1939 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); 1940 } 1941 1942 /** 1943 * @brief Clear Wake Up from stop mode Flag 1944 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP 1945 * @param LPUARTx LPUART Instance 1946 * @retval None 1947 */ 1948 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) 1949 { 1950 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); 1951 } 1952 1953 /** 1954 * @} 1955 */ 1956 1957 /** @defgroup LPUART_LL_EF_IT_Management IT_Management 1958 * @ingroup RTEMSBSPsARMSTM32H7 1959 * @{ 1960 */ 1961 1962 /** 1963 * @brief Enable IDLE Interrupt 1964 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE 1965 * @param LPUARTx LPUART Instance 1966 * @retval None 1967 */ 1968 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) 1969 { 1970 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); 1971 } 1972 1973 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ 1974 1975 /** 1976 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt 1977 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE 1978 * @param LPUARTx LPUART Instance 1979 * @retval None 1980 */ 1981 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) 1982 { 1983 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); 1984 } 1985 1986 /** 1987 * @brief Enable Transmission Complete Interrupt 1988 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC 1989 * @param LPUARTx LPUART Instance 1990 * @retval None 1991 */ 1992 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) 1993 { 1994 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); 1995 } 1996 1997 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ 1998 1999 /** 2000 * @brief Enable TX Empty and TX FIFO Not Full Interrupt 2001 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF 2002 * @param LPUARTx LPUART Instance 2003 * @retval None 2004 */ 2005 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) 2006 { 2007 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); 2008 } 2009 2010 /** 2011 * @brief Enable Parity Error Interrupt 2012 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE 2013 * @param LPUARTx LPUART Instance 2014 * @retval None 2015 */ 2016 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) 2017 { 2018 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); 2019 } 2020 2021 /** 2022 * @brief Enable Character Match Interrupt 2023 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM 2024 * @param LPUARTx LPUART Instance 2025 * @retval None 2026 */ 2027 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) 2028 { 2029 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); 2030 } 2031 2032 /** 2033 * @brief Enable TX FIFO Empty Interrupt 2034 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE 2035 * @param LPUARTx LPUART Instance 2036 * @retval None 2037 */ 2038 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) 2039 { 2040 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); 2041 } 2042 2043 /** 2044 * @brief Enable RX FIFO Full Interrupt 2045 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF 2046 * @param LPUARTx LPUART Instance 2047 * @retval None 2048 */ 2049 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) 2050 { 2051 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); 2052 } 2053 2054 /** 2055 * @brief Enable Error Interrupt 2056 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing 2057 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). 2058 * - 0: Interrupt is inhibited 2059 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. 2060 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR 2061 * @param LPUARTx LPUART Instance 2062 * @retval None 2063 */ 2064 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) 2065 { 2066 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); 2067 } 2068 2069 /** 2070 * @brief Enable CTS Interrupt 2071 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS 2072 * @param LPUARTx LPUART Instance 2073 * @retval None 2074 */ 2075 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) 2076 { 2077 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); 2078 } 2079 2080 /** 2081 * @brief Enable Wake Up from Stop Mode Interrupt 2082 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP 2083 * @param LPUARTx LPUART Instance 2084 * @retval None 2085 */ 2086 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) 2087 { 2088 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); 2089 } 2090 2091 /** 2092 * @brief Enable TX FIFO Threshold Interrupt 2093 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT 2094 * @param LPUARTx LPUART Instance 2095 * @retval None 2096 */ 2097 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) 2098 { 2099 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); 2100 } 2101 2102 /** 2103 * @brief Enable RX FIFO Threshold Interrupt 2104 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT 2105 * @param LPUARTx LPUART Instance 2106 * @retval None 2107 */ 2108 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) 2109 { 2110 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); 2111 } 2112 2113 /** 2114 * @brief Disable IDLE Interrupt 2115 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE 2116 * @param LPUARTx LPUART Instance 2117 * @retval None 2118 */ 2119 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) 2120 { 2121 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); 2122 } 2123 2124 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ 2125 2126 /** 2127 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt 2128 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE 2129 * @param LPUARTx LPUART Instance 2130 * @retval None 2131 */ 2132 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) 2133 { 2134 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); 2135 } 2136 2137 /** 2138 * @brief Disable Transmission Complete Interrupt 2139 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC 2140 * @param LPUARTx LPUART Instance 2141 * @retval None 2142 */ 2143 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) 2144 { 2145 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); 2146 } 2147 2148 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ 2149 2150 /** 2151 * @brief Disable TX Empty and TX FIFO Not Full Interrupt 2152 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF 2153 * @param LPUARTx LPUART Instance 2154 * @retval None 2155 */ 2156 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) 2157 { 2158 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); 2159 } 2160 2161 /** 2162 * @brief Disable Parity Error Interrupt 2163 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE 2164 * @param LPUARTx LPUART Instance 2165 * @retval None 2166 */ 2167 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) 2168 { 2169 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); 2170 } 2171 2172 /** 2173 * @brief Disable Character Match Interrupt 2174 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM 2175 * @param LPUARTx LPUART Instance 2176 * @retval None 2177 */ 2178 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) 2179 { 2180 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); 2181 } 2182 2183 /** 2184 * @brief Disable TX FIFO Empty Interrupt 2185 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE 2186 * @param LPUARTx LPUART Instance 2187 * @retval None 2188 */ 2189 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) 2190 { 2191 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); 2192 } 2193 2194 /** 2195 * @brief Disable RX FIFO Full Interrupt 2196 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF 2197 * @param LPUARTx LPUART Instance 2198 * @retval None 2199 */ 2200 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) 2201 { 2202 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); 2203 } 2204 2205 /** 2206 * @brief Disable Error Interrupt 2207 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing 2208 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). 2209 * - 0: Interrupt is inhibited 2210 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. 2211 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR 2212 * @param LPUARTx LPUART Instance 2213 * @retval None 2214 */ 2215 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) 2216 { 2217 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); 2218 } 2219 2220 /** 2221 * @brief Disable CTS Interrupt 2222 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS 2223 * @param LPUARTx LPUART Instance 2224 * @retval None 2225 */ 2226 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) 2227 { 2228 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); 2229 } 2230 2231 /** 2232 * @brief Disable Wake Up from Stop Mode Interrupt 2233 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP 2234 * @param LPUARTx LPUART Instance 2235 * @retval None 2236 */ 2237 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) 2238 { 2239 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); 2240 } 2241 2242 /** 2243 * @brief Disable TX FIFO Threshold Interrupt 2244 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT 2245 * @param LPUARTx LPUART Instance 2246 * @retval None 2247 */ 2248 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) 2249 { 2250 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); 2251 } 2252 2253 /** 2254 * @brief Disable RX FIFO Threshold Interrupt 2255 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT 2256 * @param LPUARTx LPUART Instance 2257 * @retval None 2258 */ 2259 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) 2260 { 2261 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); 2262 } 2263 2264 /** 2265 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. 2266 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE 2267 * @param LPUARTx LPUART Instance 2268 * @retval State of bit (1 or 0). 2269 */ 2270 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) 2271 { 2272 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); 2273 } 2274 2275 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ 2276 2277 /** 2278 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. 2279 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE 2280 * @param LPUARTx LPUART Instance 2281 * @retval State of bit (1 or 0). 2282 */ 2283 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) 2284 { 2285 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); 2286 } 2287 2288 /** 2289 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. 2290 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC 2291 * @param LPUARTx LPUART Instance 2292 * @retval State of bit (1 or 0). 2293 */ 2294 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) 2295 { 2296 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); 2297 } 2298 2299 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ 2300 2301 /** 2302 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled 2303 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF 2304 * @param LPUARTx LPUART Instance 2305 * @retval State of bit (1 or 0). 2306 */ 2307 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) 2308 { 2309 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); 2310 } 2311 2312 /** 2313 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. 2314 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE 2315 * @param LPUARTx LPUART Instance 2316 * @retval State of bit (1 or 0). 2317 */ 2318 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) 2319 { 2320 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); 2321 } 2322 2323 /** 2324 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. 2325 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM 2326 * @param LPUARTx LPUART Instance 2327 * @retval State of bit (1 or 0). 2328 */ 2329 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) 2330 { 2331 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); 2332 } 2333 2334 /** 2335 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled 2336 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE 2337 * @param LPUARTx LPUART Instance 2338 * @retval State of bit (1 or 0). 2339 */ 2340 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) 2341 { 2342 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); 2343 } 2344 2345 /** 2346 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled 2347 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF 2348 * @param LPUARTx LPUART Instance 2349 * @retval State of bit (1 or 0). 2350 */ 2351 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) 2352 { 2353 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); 2354 } 2355 2356 /** 2357 * @brief Check if the LPUART Error Interrupt is enabled or disabled. 2358 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR 2359 * @param LPUARTx LPUART Instance 2360 * @retval State of bit (1 or 0). 2361 */ 2362 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) 2363 { 2364 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); 2365 } 2366 2367 /** 2368 * @brief Check if the LPUART CTS Interrupt is enabled or disabled. 2369 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS 2370 * @param LPUARTx LPUART Instance 2371 * @retval State of bit (1 or 0). 2372 */ 2373 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) 2374 { 2375 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); 2376 } 2377 2378 /** 2379 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. 2380 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP 2381 * @param LPUARTx LPUART Instance 2382 * @retval State of bit (1 or 0). 2383 */ 2384 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) 2385 { 2386 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); 2387 } 2388 2389 /** 2390 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled 2391 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT 2392 * @param LPUARTx LPUART Instance 2393 * @retval State of bit (1 or 0). 2394 */ 2395 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) 2396 { 2397 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); 2398 } 2399 2400 /** 2401 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled 2402 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT 2403 * @param LPUARTx LPUART Instance 2404 * @retval State of bit (1 or 0). 2405 */ 2406 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) 2407 { 2408 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); 2409 } 2410 2411 /** 2412 * @} 2413 */ 2414 2415 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management 2416 * @ingroup RTEMSBSPsARMSTM32H7 2417 * @{ 2418 */ 2419 2420 /** 2421 * @brief Enable DMA Mode for reception 2422 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX 2423 * @param LPUARTx LPUART Instance 2424 * @retval None 2425 */ 2426 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) 2427 { 2428 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); 2429 } 2430 2431 /** 2432 * @brief Disable DMA Mode for reception 2433 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX 2434 * @param LPUARTx LPUART Instance 2435 * @retval None 2436 */ 2437 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) 2438 { 2439 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); 2440 } 2441 2442 /** 2443 * @brief Check if DMA Mode is enabled for reception 2444 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX 2445 * @param LPUARTx LPUART Instance 2446 * @retval State of bit (1 or 0). 2447 */ 2448 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) 2449 { 2450 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); 2451 } 2452 2453 /** 2454 * @brief Enable DMA Mode for transmission 2455 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX 2456 * @param LPUARTx LPUART Instance 2457 * @retval None 2458 */ 2459 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) 2460 { 2461 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); 2462 } 2463 2464 /** 2465 * @brief Disable DMA Mode for transmission 2466 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX 2467 * @param LPUARTx LPUART Instance 2468 * @retval None 2469 */ 2470 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) 2471 { 2472 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); 2473 } 2474 2475 /** 2476 * @brief Check if DMA Mode is enabled for transmission 2477 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX 2478 * @param LPUARTx LPUART Instance 2479 * @retval State of bit (1 or 0). 2480 */ 2481 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) 2482 { 2483 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); 2484 } 2485 2486 /** 2487 * @brief Enable DMA Disabling on Reception Error 2488 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr 2489 * @param LPUARTx LPUART Instance 2490 * @retval None 2491 */ 2492 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) 2493 { 2494 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); 2495 } 2496 2497 /** 2498 * @brief Disable DMA Disabling on Reception Error 2499 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr 2500 * @param LPUARTx LPUART Instance 2501 * @retval None 2502 */ 2503 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) 2504 { 2505 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); 2506 } 2507 2508 /** 2509 * @brief Indicate if DMA Disabling on Reception Error is disabled 2510 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr 2511 * @param LPUARTx LPUART Instance 2512 * @retval State of bit (1 or 0). 2513 */ 2514 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) 2515 { 2516 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); 2517 } 2518 2519 /** 2520 * @brief Get the LPUART data register address used for DMA transfer 2521 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n 2522 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr 2523 * @param LPUARTx LPUART Instance 2524 * @param Direction This parameter can be one of the following values: 2525 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT 2526 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE 2527 * @retval Address of data register 2528 */ 2529 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) 2530 { 2531 uint32_t data_reg_addr; 2532 2533 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) 2534 { 2535 /* return address of TDR register */ 2536 data_reg_addr = (uint32_t) &(LPUARTx->TDR); 2537 } 2538 else 2539 { 2540 /* return address of RDR register */ 2541 data_reg_addr = (uint32_t) &(LPUARTx->RDR); 2542 } 2543 2544 return data_reg_addr; 2545 } 2546 2547 /** 2548 * @} 2549 */ 2550 2551 /** @defgroup LPUART_LL_EF_Data_Management Data_Management 2552 * @ingroup RTEMSBSPsARMSTM32H7 2553 * @{ 2554 */ 2555 2556 /** 2557 * @brief Read Receiver Data register (Receive Data value, 8 bits) 2558 * @rmtoll RDR RDR LL_LPUART_ReceiveData8 2559 * @param LPUARTx LPUART Instance 2560 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF 2561 */ 2562 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) 2563 { 2564 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); 2565 } 2566 2567 /** 2568 * @brief Read Receiver Data register (Receive Data value, 9 bits) 2569 * @rmtoll RDR RDR LL_LPUART_ReceiveData9 2570 * @param LPUARTx LPUART Instance 2571 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF 2572 */ 2573 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) 2574 { 2575 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); 2576 } 2577 2578 /** 2579 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 2580 * @rmtoll TDR TDR LL_LPUART_TransmitData8 2581 * @param LPUARTx LPUART Instance 2582 * @param Value between Min_Data=0x00 and Max_Data=0xFF 2583 * @retval None 2584 */ 2585 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) 2586 { 2587 LPUARTx->TDR = Value; 2588 } 2589 2590 /** 2591 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) 2592 * @rmtoll TDR TDR LL_LPUART_TransmitData9 2593 * @param LPUARTx LPUART Instance 2594 * @param Value between Min_Data=0x00 and Max_Data=0x1FF 2595 * @retval None 2596 */ 2597 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) 2598 { 2599 LPUARTx->TDR = Value & 0x1FFUL; 2600 } 2601 2602 /** 2603 * @} 2604 */ 2605 2606 /** @defgroup LPUART_LL_EF_Execution Execution 2607 * @ingroup RTEMSBSPsARMSTM32H7 2608 * @{ 2609 */ 2610 2611 /** 2612 * @brief Request Break sending 2613 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending 2614 * @param LPUARTx LPUART Instance 2615 * @retval None 2616 */ 2617 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) 2618 { 2619 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); 2620 } 2621 2622 /** 2623 * @brief Put LPUART in mute mode and set the RWU flag 2624 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode 2625 * @param LPUARTx LPUART Instance 2626 * @retval None 2627 */ 2628 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) 2629 { 2630 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); 2631 } 2632 2633 /** 2634 * @brief Request a Receive Data and FIFO flush 2635 * @note Allows to discard the received data without reading them, and avoid an overrun 2636 * condition. 2637 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush 2638 * @param LPUARTx LPUART Instance 2639 * @retval None 2640 */ 2641 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) 2642 { 2643 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); 2644 } 2645 2646 /** 2647 * @} 2648 */ 2649 2650 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 2651 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions 2652 * @ingroup RTEMSBSPsARMSTM32H7 2653 * @{ 2654 */ 2655 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); 2656 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); 2657 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); 2658 /** 2659 * @} 2660 */ 2661 #endif /* USE_FULL_LL_DRIVER */ 2662 2663 /** 2664 * @} 2665 */ 2666 2667 /** 2668 * @} 2669 */ 2670 2671 #endif /* LPUART1 */ 2672 2673 /** 2674 * @} 2675 */ 2676 2677 #ifdef __cplusplus 2678 } 2679 #endif 2680 2681 #endif /* STM32H7xx_LL_LPUART_H */ 2682
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