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0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_lptim.h 0004 * @author MCD Application Team 0005 * @brief Header file of LPTIM LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_LPTIM_H 0021 #define STM32H7xx_LL_LPTIM_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5) 0035 0036 /** @defgroup LPTIM_LL LPTIM 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 0044 /* Private constants ---------------------------------------------------------*/ 0045 0046 /* Private macros ------------------------------------------------------------*/ 0047 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0048 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros 0049 * @ingroup RTEMSBSPsARMSTM32H7 0050 * @{ 0051 */ 0052 /** 0053 * @} 0054 */ 0055 #endif /*USE_FULL_LL_DRIVER*/ 0056 0057 /* Exported types ------------------------------------------------------------*/ 0058 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0059 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure 0060 * @ingroup RTEMSBSPsARMSTM32H7 0061 * @{ 0062 */ 0063 0064 /** 0065 * @brief LPTIM Init structure definition 0066 */ 0067 typedef struct 0068 { 0069 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. 0070 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. 0071 0072 This feature can be modified afterwards using unitary 0073 function @ref LL_LPTIM_SetClockSource().*/ 0074 0075 uint32_t Prescaler; /*!< Specifies the prescaler division ratio. 0076 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. 0077 0078 This feature can be modified afterwards using using unitary 0079 function @ref LL_LPTIM_SetPrescaler().*/ 0080 0081 uint32_t Waveform; /*!< Specifies the waveform shape. 0082 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. 0083 0084 This feature can be modified afterwards using unitary 0085 function @ref LL_LPTIM_ConfigOutput().*/ 0086 0087 uint32_t Polarity; /*!< Specifies waveform polarity. 0088 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. 0089 0090 This feature can be modified afterwards using unitary 0091 function @ref LL_LPTIM_ConfigOutput().*/ 0092 } LL_LPTIM_InitTypeDef; 0093 0094 /** 0095 * @} 0096 */ 0097 #endif /* USE_FULL_LL_DRIVER */ 0098 0099 /* Exported constants --------------------------------------------------------*/ 0100 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants 0101 * @ingroup RTEMSBSPsARMSTM32H7 0102 * @{ 0103 */ 0104 0105 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines 0106 * @ingroup RTEMSBSPsARMSTM32H7 0107 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function 0108 * @{ 0109 */ 0110 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ 0111 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ 0112 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ 0113 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ 0114 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ 0115 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ 0116 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ 0117 /** 0118 * @} 0119 */ 0120 0121 /** @defgroup LPTIM_LL_EC_IT IT Defines 0122 * @ingroup RTEMSBSPsARMSTM32H7 0123 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions 0124 * @{ 0125 */ 0126 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ 0127 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ 0128 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ 0129 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ 0130 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ 0131 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ 0132 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ 0133 /** 0134 * @} 0135 */ 0136 0137 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode 0138 * @ingroup RTEMSBSPsARMSTM32H7 0139 * @{ 0140 */ 0141 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/ 0142 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/ 0143 /** 0144 * @} 0145 */ 0146 0147 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode 0148 * @ingroup RTEMSBSPsARMSTM32H7 0149 * @{ 0150 */ 0151 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/ 0152 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/ 0153 /** 0154 * @} 0155 */ 0156 0157 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode 0158 * @ingroup RTEMSBSPsARMSTM32H7 0159 * @{ 0160 */ 0161 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/ 0162 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/ 0163 /** 0164 * @} 0165 */ 0166 0167 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type 0168 * @ingroup RTEMSBSPsARMSTM32H7 0169 * @{ 0170 */ 0171 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/ 0172 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/ 0173 /** 0174 * @} 0175 */ 0176 0177 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity 0178 * @ingroup RTEMSBSPsARMSTM32H7 0179 * @{ 0180 */ 0181 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/ 0182 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/ 0183 /** 0184 * @} 0185 */ 0186 0187 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value 0188 * @ingroup RTEMSBSPsARMSTM32H7 0189 * @{ 0190 */ 0191 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/ 0192 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/ 0193 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/ 0194 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/ 0195 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/ 0196 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/ 0197 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/ 0198 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/ 0199 /** 0200 * @} 0201 */ 0202 0203 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source 0204 * @ingroup RTEMSBSPsARMSTM32H7 0205 * @{ 0206 */ 0207 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/ 0208 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/ 0209 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/ 0210 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/ 0211 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/ 0212 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/ 0213 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/ 0214 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/ 0215 #define LL_LPTIM_TRIG_SOURCE_LPTIM2 0x00000000U /*!<External input trigger is connected to LPTIM2 output*/ 0216 #define LL_LPTIM_TRIG_SOURCE_LPTIM3 LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to LPTIM3 output*/ 0217 #define LL_LPTIM_TRIG_SOURCE_LPTIM4 LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to LPTIM4 output*/ 0218 #define LL_LPTIM_TRIG_SOURCE_LPTIM5 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to LPTIM5 output*/ 0219 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI1 FS A output*/ 0220 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI1 FS B output*/ 0221 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI2 FS A output*/ 0222 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI2 FS B output*/ 0223 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to SAI4 FS A output*/ 0224 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to SAI4 FS B output*/ 0225 #define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to DFSDM2_BRK[0] */ 0226 /** 0227 * @} 0228 */ 0229 0230 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter 0231 * @ingroup RTEMSBSPsARMSTM32H7 0232 * @{ 0233 */ 0234 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/ 0235 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/ 0236 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/ 0237 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/ 0238 /** 0239 * @} 0240 */ 0241 0242 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity 0243 * @ingroup RTEMSBSPsARMSTM32H7 0244 * @{ 0245 */ 0246 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/ 0247 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/ 0248 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/ 0249 /** 0250 * @} 0251 */ 0252 0253 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source 0254 * @ingroup RTEMSBSPsARMSTM32H7 0255 * @{ 0256 */ 0257 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/ 0258 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/ 0259 /** 0260 * @} 0261 */ 0262 0263 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter 0264 * @ingroup RTEMSBSPsARMSTM32H7 0265 * @{ 0266 */ 0267 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/ 0268 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/ 0269 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/ 0270 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/ 0271 /** 0272 * @} 0273 */ 0274 0275 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity 0276 * @ingroup RTEMSBSPsARMSTM32H7 0277 * @{ 0278 */ 0279 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/ 0280 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/ 0281 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/ 0282 /** 0283 * @} 0284 */ 0285 0286 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode 0287 * @ingroup RTEMSBSPsARMSTM32H7 0288 * @{ 0289 */ 0290 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/ 0291 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/ 0292 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/ 0293 /** 0294 * @} 0295 */ 0296 0297 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source 0298 * @ingroup RTEMSBSPsARMSTM32H7 0299 * @{ 0300 */ 0301 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */ 0302 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */ 0303 #define LL_LPTIM_INPUT1_SRC_COMP2 LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM2 */ 0304 #define LL_LPTIM_INPUT1_SRC_COMP1_COMP2 (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */ 0305 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_A LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM3 */ 0306 #define LL_LPTIM_INPUT1_SRC_SAI4_FS_B LPTIM_CFGR2_IN1SEL_1 /*!< For LPTIM3 */ 0307 /** 0308 * @} 0309 */ 0310 0311 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source 0312 * @ingroup RTEMSBSPsARMSTM32H7 0313 * @{ 0314 */ 0315 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U /*!< For LPTIM1 */ 0316 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 */ 0317 /** 0318 * @} 0319 */ 0320 0321 /** 0322 * @} 0323 */ 0324 0325 /* Exported macro ------------------------------------------------------------*/ 0326 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros 0327 * @ingroup RTEMSBSPsARMSTM32H7 0328 * @{ 0329 */ 0330 0331 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros 0332 * @ingroup RTEMSBSPsARMSTM32H7 0333 * @{ 0334 */ 0335 0336 /** 0337 * @brief Write a value in LPTIM register 0338 * @param __INSTANCE__ LPTIM Instance 0339 * @param __REG__ Register to be written 0340 * @param __VALUE__ Value to be written in the register 0341 * @retval None 0342 */ 0343 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 0344 0345 /** 0346 * @brief Read a value in LPTIM register 0347 * @param __INSTANCE__ LPTIM Instance 0348 * @param __REG__ Register to be read 0349 * @retval Register value 0350 */ 0351 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 0352 /** 0353 * @} 0354 */ 0355 0356 /** 0357 * @} 0358 */ 0359 0360 /* Exported functions --------------------------------------------------------*/ 0361 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions 0362 * @ingroup RTEMSBSPsARMSTM32H7 0363 * @{ 0364 */ 0365 0366 /** Legacy definitions for compatibility purpose 0367 @cond 0 0368 */ 0369 #define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM 0370 #define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 0371 #define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 0372 #define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O 0373 #define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O 0374 #define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM 0375 /** 0376 @endcond 0377 */ 0378 0379 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0380 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions 0381 * @ingroup RTEMSBSPsARMSTM32H7 0382 * @{ 0383 */ 0384 0385 ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); 0386 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); 0387 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); 0388 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); 0389 /** 0390 * @} 0391 */ 0392 #endif /* USE_FULL_LL_DRIVER */ 0393 0394 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration 0395 * @ingroup RTEMSBSPsARMSTM32H7 0396 * @{ 0397 */ 0398 0399 /** 0400 * @brief Enable the LPTIM instance 0401 * @note After setting the ENABLE bit, a delay of two counter clock is needed 0402 * before the LPTIM instance is actually enabled. 0403 * @rmtoll CR ENABLE LL_LPTIM_Enable 0404 * @param LPTIMx Low-Power Timer instance 0405 * @retval None 0406 */ 0407 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) 0408 { 0409 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); 0410 } 0411 0412 /** 0413 * @brief Indicates whether the LPTIM instance is enabled. 0414 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled 0415 * @param LPTIMx Low-Power Timer instance 0416 * @retval State of bit (1 or 0). 0417 */ 0418 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) 0419 { 0420 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); 0421 } 0422 0423 /** 0424 * @brief Starts the LPTIM counter in the desired mode. 0425 * @note LPTIM instance must be enabled before starting the counter. 0426 * @note It is possible to change on the fly from One Shot mode to 0427 * Continuous mode. 0428 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n 0429 * CR SNGSTRT LL_LPTIM_StartCounter 0430 * @param LPTIMx Low-Power Timer instance 0431 * @param OperatingMode This parameter can be one of the following values: 0432 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS 0433 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT 0434 * @retval None 0435 */ 0436 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode) 0437 { 0438 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); 0439 } 0440 0441 /** 0442 * @brief Enable reset after read. 0443 * @note After calling this function any read access to LPTIM_CNT 0444 * register will asynchronously reset the LPTIM_CNT register content. 0445 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead 0446 * @param LPTIMx Low-Power Timer instance 0447 * @retval None 0448 */ 0449 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) 0450 { 0451 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); 0452 } 0453 0454 /** 0455 * @brief Disable reset after read. 0456 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead 0457 * @param LPTIMx Low-Power Timer instance 0458 * @retval None 0459 */ 0460 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) 0461 { 0462 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); 0463 } 0464 0465 /** 0466 * @brief Indicate whether the reset after read feature is enabled. 0467 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead 0468 * @param LPTIMx Low-Power Timer instance 0469 * @retval State of bit (1 or 0). 0470 */ 0471 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) 0472 { 0473 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); 0474 } 0475 0476 /** 0477 * @brief Reset of the LPTIM_CNT counter register (synchronous). 0478 * @note Due to the synchronous nature of this reset, it only takes 0479 * place after a synchronization delay of 3 LPTIM core clock cycles 0480 * (LPTIM core clock may be different from APB clock). 0481 * @note COUNTRST is automatically cleared by hardware 0482 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n 0483 * @param LPTIMx Low-Power Timer instance 0484 * @retval None 0485 */ 0486 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx) 0487 { 0488 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); 0489 } 0490 0491 /** 0492 * @brief Set the LPTIM registers update mode (enable/disable register preload) 0493 * @note This function must be called when the LPTIM instance is disabled. 0494 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode 0495 * @param LPTIMx Low-Power Timer instance 0496 * @param UpdateMode This parameter can be one of the following values: 0497 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE 0498 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD 0499 * @retval None 0500 */ 0501 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode) 0502 { 0503 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); 0504 } 0505 0506 /** 0507 * @brief Get the LPTIM registers update mode 0508 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode 0509 * @param LPTIMx Low-Power Timer instance 0510 * @retval Returned value can be one of the following values: 0511 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE 0512 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD 0513 */ 0514 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) 0515 { 0516 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); 0517 } 0518 0519 /** 0520 * @brief Set the auto reload value 0521 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled 0522 * @note After a write to the LPTIMx_ARR register a new write operation to the 0523 * same register can only be performed when the previous write operation 0524 * is completed. Any successive write before the ARROK flag is set, will 0525 * lead to unpredictable results. 0526 * @note autoreload value be strictly greater than the compare value. 0527 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload 0528 * @param LPTIMx Low-Power Timer instance 0529 * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF 0530 * @retval None 0531 */ 0532 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) 0533 { 0534 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); 0535 } 0536 0537 /** 0538 * @brief Get actual auto reload value 0539 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload 0540 * @param LPTIMx Low-Power Timer instance 0541 * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF 0542 */ 0543 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) 0544 { 0545 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); 0546 } 0547 0548 /** 0549 * @brief Set the compare value 0550 * @note After a write to the LPTIMx_CMP register a new write operation to the 0551 * same register can only be performed when the previous write operation 0552 * is completed. Any successive write before the CMPOK flag is set, will 0553 * lead to unpredictable results. 0554 * @rmtoll CMP CMP LL_LPTIM_SetCompare 0555 * @param LPTIMx Low-Power Timer instance 0556 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF 0557 * @retval None 0558 */ 0559 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) 0560 { 0561 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue); 0562 } 0563 0564 /** 0565 * @brief Get actual compare value 0566 * @rmtoll CMP CMP LL_LPTIM_GetCompare 0567 * @param LPTIMx Low-Power Timer instance 0568 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF 0569 */ 0570 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) 0571 { 0572 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); 0573 } 0574 0575 /** 0576 * @brief Get actual counter value 0577 * @note When the LPTIM instance is running with an asynchronous clock, reading 0578 * the LPTIMx_CNT register may return unreliable values. So in this case 0579 * it is necessary to perform two consecutive read accesses and verify 0580 * that the two returned values are identical. 0581 * @rmtoll CNT CNT LL_LPTIM_GetCounter 0582 * @param LPTIMx Low-Power Timer instance 0583 * @retval Counter value 0584 */ 0585 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) 0586 { 0587 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); 0588 } 0589 0590 /** 0591 * @brief Set the counter mode (selection of the LPTIM counter clock source). 0592 * @note The counter mode can be set only when the LPTIM instance is disabled. 0593 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode 0594 * @param LPTIMx Low-Power Timer instance 0595 * @param CounterMode This parameter can be one of the following values: 0596 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL 0597 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL 0598 * @retval None 0599 */ 0600 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode) 0601 { 0602 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); 0603 } 0604 0605 /** 0606 * @brief Get the counter mode 0607 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode 0608 * @param LPTIMx Low-Power Timer instance 0609 * @retval Returned value can be one of the following values: 0610 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL 0611 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL 0612 */ 0613 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) 0614 { 0615 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); 0616 } 0617 0618 /** 0619 * @brief Configure the LPTIM instance output (LPTIMx_OUT) 0620 * @note This function must be called when the LPTIM instance is disabled. 0621 * @note Regarding the LPTIM output polarity the change takes effect 0622 * immediately, so the output default value will change immediately after 0623 * the polarity is re-configured, even before the timer is enabled. 0624 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n 0625 * CFGR WAVPOL LL_LPTIM_ConfigOutput 0626 * @param LPTIMx Low-Power Timer instance 0627 * @param Waveform This parameter can be one of the following values: 0628 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM 0629 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE 0630 * @param Polarity This parameter can be one of the following values: 0631 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR 0632 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE 0633 * @retval None 0634 */ 0635 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity) 0636 { 0637 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); 0638 } 0639 0640 /** 0641 * @brief Set waveform shape 0642 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform 0643 * @param LPTIMx Low-Power Timer instance 0644 * @param Waveform This parameter can be one of the following values: 0645 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM 0646 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE 0647 * @retval None 0648 */ 0649 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform) 0650 { 0651 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); 0652 } 0653 0654 /** 0655 * @brief Get actual waveform shape 0656 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform 0657 * @param LPTIMx Low-Power Timer instance 0658 * @retval Returned value can be one of the following values: 0659 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM 0660 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE 0661 */ 0662 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) 0663 { 0664 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); 0665 } 0666 0667 /** 0668 * @brief Set output polarity 0669 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity 0670 * @param LPTIMx Low-Power Timer instance 0671 * @param Polarity This parameter can be one of the following values: 0672 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR 0673 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE 0674 * @retval None 0675 */ 0676 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity) 0677 { 0678 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); 0679 } 0680 0681 /** 0682 * @brief Get actual output polarity 0683 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity 0684 * @param LPTIMx Low-Power Timer instance 0685 * @retval Returned value can be one of the following values: 0686 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR 0687 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE 0688 */ 0689 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) 0690 { 0691 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); 0692 } 0693 0694 /** 0695 * @brief Set actual prescaler division ratio. 0696 * @note This function must be called when the LPTIM instance is disabled. 0697 * @note When the LPTIM is configured to be clocked by an internal clock source 0698 * and the LPTIM counter is configured to be updated by active edges 0699 * detected on the LPTIM external Input1, the internal clock provided to 0700 * the LPTIM must be not be prescaled. 0701 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler 0702 * @param LPTIMx Low-Power Timer instance 0703 * @param Prescaler This parameter can be one of the following values: 0704 * @arg @ref LL_LPTIM_PRESCALER_DIV1 0705 * @arg @ref LL_LPTIM_PRESCALER_DIV2 0706 * @arg @ref LL_LPTIM_PRESCALER_DIV4 0707 * @arg @ref LL_LPTIM_PRESCALER_DIV8 0708 * @arg @ref LL_LPTIM_PRESCALER_DIV16 0709 * @arg @ref LL_LPTIM_PRESCALER_DIV32 0710 * @arg @ref LL_LPTIM_PRESCALER_DIV64 0711 * @arg @ref LL_LPTIM_PRESCALER_DIV128 0712 * @retval None 0713 */ 0714 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler) 0715 { 0716 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); 0717 } 0718 0719 /** 0720 * @brief Get actual prescaler division ratio. 0721 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler 0722 * @param LPTIMx Low-Power Timer instance 0723 * @retval Returned value can be one of the following values: 0724 * @arg @ref LL_LPTIM_PRESCALER_DIV1 0725 * @arg @ref LL_LPTIM_PRESCALER_DIV2 0726 * @arg @ref LL_LPTIM_PRESCALER_DIV4 0727 * @arg @ref LL_LPTIM_PRESCALER_DIV8 0728 * @arg @ref LL_LPTIM_PRESCALER_DIV16 0729 * @arg @ref LL_LPTIM_PRESCALER_DIV32 0730 * @arg @ref LL_LPTIM_PRESCALER_DIV64 0731 * @arg @ref LL_LPTIM_PRESCALER_DIV128 0732 */ 0733 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) 0734 { 0735 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); 0736 } 0737 0738 /** 0739 * @brief Set LPTIM input 1 source (default GPIO). 0740 * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src 0741 * @param LPTIMx Low-Power Timer instance 0742 * @param Src This parameter can be one of the following values: 0743 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO 0744 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 0745 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP2 0746 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2 0747 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A 0748 * @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B 0749 * @retval None 0750 */ 0751 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) 0752 { 0753 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src); 0754 } 0755 0756 /** 0757 * @brief Set LPTIM input 2 source (default GPIO). 0758 * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src 0759 * @param LPTIMx Low-Power Timer instance 0760 * @param Src This parameter can be one of the following values: 0761 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO 0762 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 0763 * @retval None 0764 */ 0765 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) 0766 { 0767 MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src); 0768 } 0769 0770 /** 0771 * @} 0772 */ 0773 0774 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration 0775 * @ingroup RTEMSBSPsARMSTM32H7 0776 * @{ 0777 */ 0778 0779 /** 0780 * @brief Enable the timeout function 0781 * @note This function must be called when the LPTIM instance is disabled. 0782 * @note The first trigger event will start the timer, any successive trigger 0783 * event will reset the counter and the timer will restart. 0784 * @note The timeout value corresponds to the compare value; if no trigger 0785 * occurs within the expected time frame, the MCU is waked-up by the 0786 * compare match event. 0787 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout 0788 * @param LPTIMx Low-Power Timer instance 0789 * @retval None 0790 */ 0791 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx) 0792 { 0793 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); 0794 } 0795 0796 /** 0797 * @brief Disable the timeout function 0798 * @note This function must be called when the LPTIM instance is disabled. 0799 * @note A trigger event arriving when the timer is already started will be 0800 * ignored. 0801 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout 0802 * @param LPTIMx Low-Power Timer instance 0803 * @retval None 0804 */ 0805 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) 0806 { 0807 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); 0808 } 0809 0810 /** 0811 * @brief Indicate whether the timeout function is enabled. 0812 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout 0813 * @param LPTIMx Low-Power Timer instance 0814 * @retval State of bit (1 or 0). 0815 */ 0816 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) 0817 { 0818 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); 0819 } 0820 0821 /** 0822 * @brief Start the LPTIM counter 0823 * @note This function must be called when the LPTIM instance is disabled. 0824 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw 0825 * @param LPTIMx Low-Power Timer instance 0826 * @retval None 0827 */ 0828 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) 0829 { 0830 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN); 0831 } 0832 0833 /** 0834 * @brief Configure the external trigger used as a trigger event for the LPTIM. 0835 * @note This function must be called when the LPTIM instance is disabled. 0836 * @note An internal clock source must be present when a digital filter is 0837 * required for the trigger. 0838 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n 0839 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n 0840 * CFGR TRIGEN LL_LPTIM_ConfigTrigger 0841 * @param LPTIMx Low-Power Timer instance 0842 * @param Source This parameter can be one of the following values: 0843 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO 0844 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA 0845 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB 0846 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 0847 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 0848 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 0849 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 0850 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 0851 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*) 0852 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*) 0853 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*) 0854 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*) 0855 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*) 0856 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*) 0857 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*) 0858 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*) 0859 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*) 0860 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*) 0861 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*) 0862 * 0863 * (*) Value not defined in all devices. \n 0864 * 0865 * @param Filter This parameter can be one of the following values: 0866 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE 0867 * @arg @ref LL_LPTIM_TRIG_FILTER_2 0868 * @arg @ref LL_LPTIM_TRIG_FILTER_4 0869 * @arg @ref LL_LPTIM_TRIG_FILTER_8 0870 * @param Polarity This parameter can be one of the following values: 0871 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING 0872 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING 0873 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING 0874 * @retval None 0875 */ 0876 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) 0877 { 0878 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity); 0879 } 0880 0881 /** 0882 * @brief Get actual external trigger source. 0883 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource 0884 * @param LPTIMx Low-Power Timer instance 0885 * @retval Returned value can be one of the following values: 0886 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO 0887 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA 0888 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB 0889 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 0890 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 0891 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 0892 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 0893 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 0894 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2 (*) 0895 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3 (*) 0896 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4 (*) 0897 * @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5 (*) 0898 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A (*) 0899 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B (*) 0900 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A (*) 0901 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B (*) 0902 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A (*) 0903 * @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B (*) 0904 * @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*) 0905 * 0906 * (*) Value not defined in all devices. \n 0907 * 0908 */ 0909 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) 0910 { 0911 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); 0912 } 0913 0914 /** 0915 * @brief Get actual external trigger filter. 0916 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter 0917 * @param LPTIMx Low-Power Timer instance 0918 * @retval Returned value can be one of the following values: 0919 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE 0920 * @arg @ref LL_LPTIM_TRIG_FILTER_2 0921 * @arg @ref LL_LPTIM_TRIG_FILTER_4 0922 * @arg @ref LL_LPTIM_TRIG_FILTER_8 0923 */ 0924 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) 0925 { 0926 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); 0927 } 0928 0929 /** 0930 * @brief Get actual external trigger polarity. 0931 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity 0932 * @param LPTIMx Low-Power Timer instance 0933 * @retval Returned value can be one of the following values: 0934 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING 0935 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING 0936 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING 0937 */ 0938 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) 0939 { 0940 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); 0941 } 0942 0943 /** 0944 * @} 0945 */ 0946 0947 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration 0948 * @ingroup RTEMSBSPsARMSTM32H7 0949 * @{ 0950 */ 0951 0952 /** 0953 * @brief Set the source of the clock used by the LPTIM instance. 0954 * @note This function must be called when the LPTIM instance is disabled. 0955 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource 0956 * @param LPTIMx Low-Power Timer instance 0957 * @param ClockSource This parameter can be one of the following values: 0958 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL 0959 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL 0960 * @retval None 0961 */ 0962 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource) 0963 { 0964 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource); 0965 } 0966 0967 /** 0968 * @brief Get actual LPTIM instance clock source. 0969 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource 0970 * @param LPTIMx Low-Power Timer instance 0971 * @retval Returned value can be one of the following values: 0972 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL 0973 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL 0974 */ 0975 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) 0976 { 0977 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); 0978 } 0979 0980 /** 0981 * @brief Configure the active edge or edges used by the counter when 0982 the LPTIM is clocked by an external clock source. 0983 * @note This function must be called when the LPTIM instance is disabled. 0984 * @note When both external clock signal edges are considered active ones, 0985 * the LPTIM must also be clocked by an internal clock source with a 0986 * frequency equal to at least four times the external clock frequency. 0987 * @note An internal clock source must be present when a digital filter is 0988 * required for external clock. 0989 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n 0990 * CFGR CKPOL LL_LPTIM_ConfigClock 0991 * @param LPTIMx Low-Power Timer instance 0992 * @param ClockFilter This parameter can be one of the following values: 0993 * @arg @ref LL_LPTIM_CLK_FILTER_NONE 0994 * @arg @ref LL_LPTIM_CLK_FILTER_2 0995 * @arg @ref LL_LPTIM_CLK_FILTER_4 0996 * @arg @ref LL_LPTIM_CLK_FILTER_8 0997 * @param ClockPolarity This parameter can be one of the following values: 0998 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING 0999 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING 1000 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING 1001 * @retval None 1002 */ 1003 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) 1004 { 1005 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity); 1006 } 1007 1008 /** 1009 * @brief Get actual clock polarity 1010 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity 1011 * @param LPTIMx Low-Power Timer instance 1012 * @retval Returned value can be one of the following values: 1013 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING 1014 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING 1015 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING 1016 */ 1017 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) 1018 { 1019 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); 1020 } 1021 1022 /** 1023 * @brief Get actual clock digital filter 1024 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter 1025 * @param LPTIMx Low-Power Timer instance 1026 * @retval Returned value can be one of the following values: 1027 * @arg @ref LL_LPTIM_CLK_FILTER_NONE 1028 * @arg @ref LL_LPTIM_CLK_FILTER_2 1029 * @arg @ref LL_LPTIM_CLK_FILTER_4 1030 * @arg @ref LL_LPTIM_CLK_FILTER_8 1031 */ 1032 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) 1033 { 1034 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); 1035 } 1036 1037 /** 1038 * @} 1039 */ 1040 1041 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode 1042 * @ingroup RTEMSBSPsARMSTM32H7 1043 * @{ 1044 */ 1045 1046 /** 1047 * @brief Configure the encoder mode. 1048 * @note This function must be called when the LPTIM instance is disabled. 1049 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode 1050 * @param LPTIMx Low-Power Timer instance 1051 * @param EncoderMode This parameter can be one of the following values: 1052 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING 1053 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING 1054 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING 1055 * @retval None 1056 */ 1057 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode) 1058 { 1059 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode); 1060 } 1061 1062 /** 1063 * @brief Get actual encoder mode. 1064 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode 1065 * @param LPTIMx Low-Power Timer instance 1066 * @retval Returned value can be one of the following values: 1067 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING 1068 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING 1069 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING 1070 */ 1071 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) 1072 { 1073 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); 1074 } 1075 1076 /** 1077 * @brief Enable the encoder mode 1078 * @note This function must be called when the LPTIM instance is disabled. 1079 * @note In this mode the LPTIM instance must be clocked by an internal clock 1080 * source. Also, the prescaler division ratio must be equal to 1. 1081 * @note LPTIM instance must be configured in continuous mode prior enabling 1082 * the encoder mode. 1083 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode 1084 * @param LPTIMx Low-Power Timer instance 1085 * @retval None 1086 */ 1087 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx) 1088 { 1089 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); 1090 } 1091 1092 /** 1093 * @brief Disable the encoder mode 1094 * @note This function must be called when the LPTIM instance is disabled. 1095 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode 1096 * @param LPTIMx Low-Power Timer instance 1097 * @retval None 1098 */ 1099 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) 1100 { 1101 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); 1102 } 1103 1104 /** 1105 * @brief Indicates whether the LPTIM operates in encoder mode. 1106 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode 1107 * @param LPTIMx Low-Power Timer instance 1108 * @retval State of bit (1 or 0). 1109 */ 1110 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) 1111 { 1112 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); 1113 } 1114 1115 /** 1116 * @} 1117 */ 1118 1119 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management 1120 * @ingroup RTEMSBSPsARMSTM32H7 1121 * @{ 1122 */ 1123 1124 1125 /** 1126 * @brief Clear the compare match flag (CMPMCF) 1127 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM 1128 * @param LPTIMx Low-Power Timer instance 1129 * @retval None 1130 */ 1131 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) 1132 { 1133 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); 1134 } 1135 1136 /** 1137 * @brief Inform application whether a compare match interrupt has occurred. 1138 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM 1139 * @param LPTIMx Low-Power Timer instance 1140 * @retval State of bit (1 or 0). 1141 */ 1142 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) 1143 { 1144 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); 1145 } 1146 1147 /** 1148 * @brief Clear the autoreload match flag (ARRMCF) 1149 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM 1150 * @param LPTIMx Low-Power Timer instance 1151 * @retval None 1152 */ 1153 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) 1154 { 1155 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); 1156 } 1157 1158 /** 1159 * @brief Inform application whether a autoreload match interrupt has occurred. 1160 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM 1161 * @param LPTIMx Low-Power Timer instance 1162 * @retval State of bit (1 or 0). 1163 */ 1164 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) 1165 { 1166 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); 1167 } 1168 1169 /** 1170 * @brief Clear the external trigger valid edge flag(EXTTRIGCF). 1171 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG 1172 * @param LPTIMx Low-Power Timer instance 1173 * @retval None 1174 */ 1175 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) 1176 { 1177 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); 1178 } 1179 1180 /** 1181 * @brief Inform application whether a valid edge on the selected external trigger input has occurred. 1182 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG 1183 * @param LPTIMx Low-Power Timer instance 1184 * @retval State of bit (1 or 0). 1185 */ 1186 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) 1187 { 1188 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); 1189 } 1190 1191 /** 1192 * @brief Clear the compare register update interrupt flag (CMPOKCF). 1193 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK 1194 * @param LPTIMx Low-Power Timer instance 1195 * @retval None 1196 */ 1197 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) 1198 { 1199 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF); 1200 } 1201 1202 /** 1203 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully 1204 completed. If so, a new one can be initiated. 1205 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK 1206 * @param LPTIMx Low-Power Timer instance 1207 * @retval State of bit (1 or 0). 1208 */ 1209 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) 1210 { 1211 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); 1212 } 1213 1214 /** 1215 * @brief Clear the autoreload register update interrupt flag (ARROKCF). 1216 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK 1217 * @param LPTIMx Low-Power Timer instance 1218 * @retval None 1219 */ 1220 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) 1221 { 1222 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); 1223 } 1224 1225 /** 1226 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully 1227 completed. If so, a new one can be initiated. 1228 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK 1229 * @param LPTIMx Low-Power Timer instance 1230 * @retval State of bit (1 or 0). 1231 */ 1232 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) 1233 { 1234 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); 1235 } 1236 1237 /** 1238 * @brief Clear the counter direction change to up interrupt flag (UPCF). 1239 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP 1240 * @param LPTIMx Low-Power Timer instance 1241 * @retval None 1242 */ 1243 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) 1244 { 1245 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF); 1246 } 1247 1248 /** 1249 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance 1250 operates in encoder mode). 1251 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP 1252 * @param LPTIMx Low-Power Timer instance 1253 * @retval State of bit (1 or 0). 1254 */ 1255 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) 1256 { 1257 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); 1258 } 1259 1260 /** 1261 * @brief Clear the counter direction change to down interrupt flag (DOWNCF). 1262 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN 1263 * @param LPTIMx Low-Power Timer instance 1264 * @retval None 1265 */ 1266 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) 1267 { 1268 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF); 1269 } 1270 1271 /** 1272 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance 1273 operates in encoder mode). 1274 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN 1275 * @param LPTIMx Low-Power Timer instance 1276 * @retval State of bit (1 or 0). 1277 */ 1278 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) 1279 { 1280 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); 1281 } 1282 1283 /** 1284 * @} 1285 */ 1286 1287 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management 1288 * @ingroup RTEMSBSPsARMSTM32H7 1289 * @{ 1290 */ 1291 1292 /** 1293 * @brief Enable compare match interrupt (CMPMIE). 1294 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM 1295 * @param LPTIMx Low-Power Timer instance 1296 * @retval None 1297 */ 1298 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx) 1299 { 1300 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); 1301 } 1302 1303 /** 1304 * @brief Disable compare match interrupt (CMPMIE). 1305 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM 1306 * @param LPTIMx Low-Power Timer instance 1307 * @retval None 1308 */ 1309 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) 1310 { 1311 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); 1312 } 1313 1314 /** 1315 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. 1316 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM 1317 * @param LPTIMx Low-Power Timer instance 1318 * @retval State of bit (1 or 0). 1319 */ 1320 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) 1321 { 1322 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); 1323 } 1324 1325 /** 1326 * @brief Enable autoreload match interrupt (ARRMIE). 1327 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM 1328 * @param LPTIMx Low-Power Timer instance 1329 * @retval None 1330 */ 1331 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx) 1332 { 1333 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); 1334 } 1335 1336 /** 1337 * @brief Disable autoreload match interrupt (ARRMIE). 1338 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM 1339 * @param LPTIMx Low-Power Timer instance 1340 * @retval None 1341 */ 1342 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) 1343 { 1344 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); 1345 } 1346 1347 /** 1348 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. 1349 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM 1350 * @param LPTIMx Low-Power Timer instance 1351 * @retval State of bit (1 or 0). 1352 */ 1353 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) 1354 { 1355 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); 1356 } 1357 1358 /** 1359 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). 1360 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG 1361 * @param LPTIMx Low-Power Timer instance 1362 * @retval None 1363 */ 1364 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) 1365 { 1366 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); 1367 } 1368 1369 /** 1370 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). 1371 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG 1372 * @param LPTIMx Low-Power Timer instance 1373 * @retval None 1374 */ 1375 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) 1376 { 1377 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); 1378 } 1379 1380 /** 1381 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. 1382 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG 1383 * @param LPTIMx Low-Power Timer instance 1384 * @retval State of bit (1 or 0). 1385 */ 1386 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) 1387 { 1388 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); 1389 } 1390 1391 /** 1392 * @brief Enable compare register write completed interrupt (CMPOKIE). 1393 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK 1394 * @param LPTIMx Low-Power Timer instance 1395 * @retval None 1396 */ 1397 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx) 1398 { 1399 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); 1400 } 1401 1402 /** 1403 * @brief Disable compare register write completed interrupt (CMPOKIE). 1404 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK 1405 * @param LPTIMx Low-Power Timer instance 1406 * @retval None 1407 */ 1408 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) 1409 { 1410 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); 1411 } 1412 1413 /** 1414 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. 1415 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK 1416 * @param LPTIMx Low-Power Timer instance 1417 * @retval State of bit (1 or 0). 1418 */ 1419 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) 1420 { 1421 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); 1422 } 1423 1424 /** 1425 * @brief Enable autoreload register write completed interrupt (ARROKIE). 1426 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK 1427 * @param LPTIMx Low-Power Timer instance 1428 * @retval None 1429 */ 1430 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) 1431 { 1432 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); 1433 } 1434 1435 /** 1436 * @brief Disable autoreload register write completed interrupt (ARROKIE). 1437 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK 1438 * @param LPTIMx Low-Power Timer instance 1439 * @retval None 1440 */ 1441 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) 1442 { 1443 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); 1444 } 1445 1446 /** 1447 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. 1448 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK 1449 * @param LPTIMx Low-Power Timer instance 1450 * @retval State of bit(1 or 0). 1451 */ 1452 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) 1453 { 1454 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); 1455 } 1456 1457 /** 1458 * @brief Enable direction change to up interrupt (UPIE). 1459 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP 1460 * @param LPTIMx Low-Power Timer instance 1461 * @retval None 1462 */ 1463 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) 1464 { 1465 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE); 1466 } 1467 1468 /** 1469 * @brief Disable direction change to up interrupt (UPIE). 1470 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP 1471 * @param LPTIMx Low-Power Timer instance 1472 * @retval None 1473 */ 1474 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) 1475 { 1476 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE); 1477 } 1478 1479 /** 1480 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. 1481 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP 1482 * @param LPTIMx Low-Power Timer instance 1483 * @retval State of bit(1 or 0). 1484 */ 1485 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) 1486 { 1487 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); 1488 } 1489 1490 /** 1491 * @brief Enable direction change to down interrupt (DOWNIE). 1492 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN 1493 * @param LPTIMx Low-Power Timer instance 1494 * @retval None 1495 */ 1496 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) 1497 { 1498 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); 1499 } 1500 1501 /** 1502 * @brief Disable direction change to down interrupt (DOWNIE). 1503 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN 1504 * @param LPTIMx Low-Power Timer instance 1505 * @retval None 1506 */ 1507 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) 1508 { 1509 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); 1510 } 1511 1512 /** 1513 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. 1514 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN 1515 * @param LPTIMx Low-Power Timer instance 1516 * @retval State of bit(1 or 0). 1517 */ 1518 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) 1519 { 1520 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); 1521 } 1522 1523 /** 1524 * @} 1525 */ 1526 1527 /** 1528 * @} 1529 */ 1530 1531 /** 1532 * @} 1533 */ 1534 1535 #endif /* LPTIM1 || LPTIM2 || LPTIM3 || LPTIM4 || LPTIM5 */ 1536 1537 /** 1538 * @} 1539 */ 1540 1541 #ifdef __cplusplus 1542 } 1543 #endif 1544 1545 #endif /* STM32H7xx_LL_LPTIM_H */
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