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0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_i2c.h 0004 * @author MCD Application Team 0005 * @brief Header file of I2C LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_I2C_H 0021 #define STM32H7xx_LL_I2C_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5) 0035 0036 /** @defgroup I2C_LL I2C 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 0044 /* Private constants ---------------------------------------------------------*/ 0045 /** @defgroup I2C_LL_Private_Constants I2C Private Constants 0046 * @ingroup RTEMSBSPsARMSTM32H7 0047 * @{ 0048 */ 0049 /** 0050 * @} 0051 */ 0052 0053 /* Private macros ------------------------------------------------------------*/ 0054 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0055 /** @defgroup I2C_LL_Private_Macros I2C Private Macros 0056 * @ingroup RTEMSBSPsARMSTM32H7 0057 * @{ 0058 */ 0059 /** 0060 * @} 0061 */ 0062 #endif /*USE_FULL_LL_DRIVER*/ 0063 0064 /* Exported types ------------------------------------------------------------*/ 0065 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0066 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure 0067 * @ingroup RTEMSBSPsARMSTM32H7 0068 * @{ 0069 */ 0070 typedef struct 0071 { 0072 uint32_t PeripheralMode; /*!< Specifies the peripheral mode. 0073 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. 0074 0075 This feature can be modified afterwards using unitary function 0076 @ref LL_I2C_SetMode(). */ 0077 0078 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. 0079 This parameter must be set by referring to the STM32CubeMX Tool and 0080 the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). 0081 0082 This feature can be modified afterwards using unitary function 0083 @ref LL_I2C_SetTiming(). */ 0084 0085 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. 0086 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. 0087 0088 This feature can be modified afterwards using unitary functions 0089 @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ 0090 0091 uint32_t DigitalFilter; /*!< Configures the digital noise filter. 0092 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. 0093 0094 This feature can be modified afterwards using unitary function 0095 @ref LL_I2C_SetDigitalFilter(). */ 0096 0097 uint32_t OwnAddress1; /*!< Specifies the device own address 1. 0098 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. 0099 0100 This feature can be modified afterwards using unitary function 0101 @ref LL_I2C_SetOwnAddress1(). */ 0102 0103 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive 0104 match code or next received byte. 0105 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. 0106 0107 This feature can be modified afterwards using unitary function 0108 @ref LL_I2C_AcknowledgeNextData(). */ 0109 0110 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). 0111 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. 0112 0113 This feature can be modified afterwards using unitary function 0114 @ref LL_I2C_SetOwnAddress1(). */ 0115 } LL_I2C_InitTypeDef; 0116 /** 0117 * @} 0118 */ 0119 #endif /*USE_FULL_LL_DRIVER*/ 0120 0121 /* Exported constants --------------------------------------------------------*/ 0122 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants 0123 * @ingroup RTEMSBSPsARMSTM32H7 0124 * @{ 0125 */ 0126 0127 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines 0128 * @ingroup RTEMSBSPsARMSTM32H7 0129 * @brief Flags defines which can be used with LL_I2C_WriteReg function 0130 * @{ 0131 */ 0132 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ 0133 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ 0134 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ 0135 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ 0136 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ 0137 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ 0138 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ 0139 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ 0140 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ 0141 /** 0142 * @} 0143 */ 0144 0145 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines 0146 * @ingroup RTEMSBSPsARMSTM32H7 0147 * @brief Flags defines which can be used with LL_I2C_ReadReg function 0148 * @{ 0149 */ 0150 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ 0151 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ 0152 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ 0153 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ 0154 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ 0155 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ 0156 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ 0157 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ 0158 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ 0159 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ 0160 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ 0161 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ 0162 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ 0163 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ 0164 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ 0165 /** 0166 * @} 0167 */ 0168 0169 /** @defgroup I2C_LL_EC_IT IT Defines 0170 * @ingroup RTEMSBSPsARMSTM32H7 0171 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions 0172 * @{ 0173 */ 0174 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ 0175 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ 0176 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ 0177 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ 0178 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ 0179 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ 0180 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ 0181 /** 0182 * @} 0183 */ 0184 0185 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode 0186 * @ingroup RTEMSBSPsARMSTM32H7 0187 * @{ 0188 */ 0189 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ 0190 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ 0191 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode 0192 (Default address not acknowledge) */ 0193 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ 0194 /** 0195 * @} 0196 */ 0197 0198 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection 0199 * @ingroup RTEMSBSPsARMSTM32H7 0200 * @{ 0201 */ 0202 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ 0203 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ 0204 /** 0205 * @} 0206 */ 0207 0208 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode 0209 * @ingroup RTEMSBSPsARMSTM32H7 0210 * @{ 0211 */ 0212 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ 0213 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ 0214 /** 0215 * @} 0216 */ 0217 0218 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length 0219 * @ingroup RTEMSBSPsARMSTM32H7 0220 * @{ 0221 */ 0222 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ 0223 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ 0224 /** 0225 * @} 0226 */ 0227 0228 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks 0229 * @ingroup RTEMSBSPsARMSTM32H7 0230 * @{ 0231 */ 0232 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ 0233 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ 0234 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ 0235 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ 0236 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ 0237 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ 0238 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ 0239 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. 0240 All Address2 are acknowledged. */ 0241 /** 0242 * @} 0243 */ 0244 0245 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation 0246 * @ingroup RTEMSBSPsARMSTM32H7 0247 * @{ 0248 */ 0249 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ 0250 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ 0251 /** 0252 * @} 0253 */ 0254 0255 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length 0256 * @ingroup RTEMSBSPsARMSTM32H7 0257 * @{ 0258 */ 0259 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ 0260 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ 0261 /** 0262 * @} 0263 */ 0264 0265 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction 0266 * @ingroup RTEMSBSPsARMSTM32H7 0267 * @{ 0268 */ 0269 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ 0270 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ 0271 /** 0272 * @} 0273 */ 0274 0275 /** @defgroup I2C_LL_EC_MODE Transfer End Mode 0276 * @ingroup RTEMSBSPsARMSTM32H7 0277 * @{ 0278 */ 0279 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ 0280 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode 0281 with no HW PEC comparison. */ 0282 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode 0283 with no HW PEC comparison. */ 0284 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode 0285 with HW PEC comparison. */ 0286 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode 0287 with HW PEC comparison. */ 0288 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode 0289 with HW PEC comparison. */ 0290 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) 0291 /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ 0292 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) 0293 /*!< Enable SMBUS Software end mode with HW PEC comparison. */ 0294 /** 0295 * @} 0296 */ 0297 0298 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation 0299 * @ingroup RTEMSBSPsARMSTM32H7 0300 * @{ 0301 */ 0302 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U 0303 /*!< Don't Generate Stop and Start condition. */ 0304 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 0305 /*!< Generate Stop condition (Size should be set to 0). */ 0306 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 0307 /*!< Generate Start for read request. */ 0308 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 0309 /*!< Generate Start for write request. */ 0310 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 0311 /*!< Generate Restart for read request, slave 7Bit address. */ 0312 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 0313 /*!< Generate Restart for write request, slave 7Bit address. */ 0314 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ 0315 I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) 0316 /*!< Generate Restart for read request, slave 10Bit address. */ 0317 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 0318 /*!< Generate Restart for write request, slave 10Bit address.*/ 0319 /** 0320 * @} 0321 */ 0322 0323 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction 0324 * @ingroup RTEMSBSPsARMSTM32H7 0325 * @{ 0326 */ 0327 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, 0328 slave enters receiver mode. */ 0329 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, 0330 slave enters transmitter mode.*/ 0331 /** 0332 * @} 0333 */ 0334 0335 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data 0336 * @ingroup RTEMSBSPsARMSTM32H7 0337 * @{ 0338 */ 0339 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for 0340 transmission */ 0341 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for 0342 reception */ 0343 /** 0344 * @} 0345 */ 0346 0347 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout 0348 * @ingroup RTEMSBSPsARMSTM32H7 0349 * @{ 0350 */ 0351 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect 0352 SCL low level timeout. */ 0353 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect 0354 both SCL and SDA high level timeout.*/ 0355 /** 0356 * @} 0357 */ 0358 0359 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection 0360 * @ingroup RTEMSBSPsARMSTM32H7 0361 * @{ 0362 */ 0363 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ 0364 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) 0365 enable bit */ 0366 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ 0367 I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB 0368 (extended clock) enable bits */ 0369 /** 0370 * @} 0371 */ 0372 0373 /** 0374 * @} 0375 */ 0376 0377 /* Exported macro ------------------------------------------------------------*/ 0378 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros 0379 * @ingroup RTEMSBSPsARMSTM32H7 0380 * @{ 0381 */ 0382 0383 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros 0384 * @ingroup RTEMSBSPsARMSTM32H7 0385 * @{ 0386 */ 0387 0388 /** 0389 * @brief Write a value in I2C register 0390 * @param __INSTANCE__ I2C Instance 0391 * @param __REG__ Register to be written 0392 * @param __VALUE__ Value to be written in the register 0393 * @retval None 0394 */ 0395 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0396 0397 /** 0398 * @brief Read a value in I2C register 0399 * @param __INSTANCE__ I2C Instance 0400 * @param __REG__ Register to be read 0401 * @retval Register value 0402 */ 0403 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0404 /** 0405 * @} 0406 */ 0407 0408 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings 0409 * @ingroup RTEMSBSPsARMSTM32H7 0410 * @{ 0411 */ 0412 /** 0413 * @brief Configure the SDA setup, hold time and the SCL high, low period. 0414 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. 0415 * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. 0416 (tscldel = (SCLDEL+1)xtpresc) 0417 * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. 0418 (tsdadel = SDADELxtpresc) 0419 * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. 0420 (tsclh = (SCLH+1)xtpresc) 0421 * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. 0422 (tscll = (SCLL+1)xtpresc) 0423 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF 0424 */ 0425 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ 0426 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ 0427 (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ 0428 (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ 0429 (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ 0430 (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) 0431 /** 0432 * @} 0433 */ 0434 0435 /** 0436 * @} 0437 */ 0438 0439 /* Exported functions --------------------------------------------------------*/ 0440 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions 0441 * @ingroup RTEMSBSPsARMSTM32H7 0442 * @{ 0443 */ 0444 0445 /** @defgroup I2C_LL_EF_Configuration Configuration 0446 * @ingroup RTEMSBSPsARMSTM32H7 0447 * @{ 0448 */ 0449 0450 /** 0451 * @brief Enable I2C peripheral (PE = 1). 0452 * @rmtoll CR1 PE LL_I2C_Enable 0453 * @param I2Cx I2C Instance. 0454 * @retval None 0455 */ 0456 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) 0457 { 0458 SET_BIT(I2Cx->CR1, I2C_CR1_PE); 0459 } 0460 0461 /** 0462 * @brief Disable I2C peripheral (PE = 0). 0463 * @note When PE = 0, the I2C SCL and SDA lines are released. 0464 * Internal state machines and status bits are put back to their reset value. 0465 * When cleared, PE must be kept low for at least 3 APB clock cycles. 0466 * @rmtoll CR1 PE LL_I2C_Disable 0467 * @param I2Cx I2C Instance. 0468 * @retval None 0469 */ 0470 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) 0471 { 0472 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); 0473 } 0474 0475 /** 0476 * @brief Check if the I2C peripheral is enabled or disabled. 0477 * @rmtoll CR1 PE LL_I2C_IsEnabled 0478 * @param I2Cx I2C Instance. 0479 * @retval State of bit (1 or 0). 0480 */ 0481 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) 0482 { 0483 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); 0484 } 0485 0486 /** 0487 * @brief Configure Noise Filters (Analog and Digital). 0488 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 0489 * The filters can only be programmed when the I2C is disabled (PE = 0). 0490 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n 0491 * CR1 DNF LL_I2C_ConfigFilters 0492 * @param I2Cx I2C Instance. 0493 * @param AnalogFilter This parameter can be one of the following values: 0494 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE 0495 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE 0496 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) 0497 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). 0498 * This parameter is used to configure the digital noise filter on SDA and SCL input. 0499 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. 0500 * @retval None 0501 */ 0502 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) 0503 { 0504 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); 0505 } 0506 0507 /** 0508 * @brief Configure Digital Noise Filter. 0509 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 0510 * This filter can only be programmed when the I2C is disabled (PE = 0). 0511 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter 0512 * @param I2Cx I2C Instance. 0513 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) 0514 and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). 0515 * This parameter is used to configure the digital noise filter on SDA and SCL input. 0516 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. 0517 * @retval None 0518 */ 0519 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) 0520 { 0521 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); 0522 } 0523 0524 /** 0525 * @brief Get the current Digital Noise Filter configuration. 0526 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter 0527 * @param I2Cx I2C Instance. 0528 * @retval Value between Min_Data=0x0 and Max_Data=0xF 0529 */ 0530 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) 0531 { 0532 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); 0533 } 0534 0535 /** 0536 * @brief Enable Analog Noise Filter. 0537 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 0538 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter 0539 * @param I2Cx I2C Instance. 0540 * @retval None 0541 */ 0542 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) 0543 { 0544 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); 0545 } 0546 0547 /** 0548 * @brief Disable Analog Noise Filter. 0549 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 0550 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter 0551 * @param I2Cx I2C Instance. 0552 * @retval None 0553 */ 0554 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) 0555 { 0556 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); 0557 } 0558 0559 /** 0560 * @brief Check if Analog Noise Filter is enabled or disabled. 0561 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter 0562 * @param I2Cx I2C Instance. 0563 * @retval State of bit (1 or 0). 0564 */ 0565 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) 0566 { 0567 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); 0568 } 0569 0570 /** 0571 * @brief Enable DMA transmission requests. 0572 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX 0573 * @param I2Cx I2C Instance. 0574 * @retval None 0575 */ 0576 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) 0577 { 0578 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); 0579 } 0580 0581 /** 0582 * @brief Disable DMA transmission requests. 0583 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX 0584 * @param I2Cx I2C Instance. 0585 * @retval None 0586 */ 0587 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) 0588 { 0589 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); 0590 } 0591 0592 /** 0593 * @brief Check if DMA transmission requests are enabled or disabled. 0594 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX 0595 * @param I2Cx I2C Instance. 0596 * @retval State of bit (1 or 0). 0597 */ 0598 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) 0599 { 0600 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); 0601 } 0602 0603 /** 0604 * @brief Enable DMA reception requests. 0605 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX 0606 * @param I2Cx I2C Instance. 0607 * @retval None 0608 */ 0609 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) 0610 { 0611 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); 0612 } 0613 0614 /** 0615 * @brief Disable DMA reception requests. 0616 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX 0617 * @param I2Cx I2C Instance. 0618 * @retval None 0619 */ 0620 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) 0621 { 0622 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); 0623 } 0624 0625 /** 0626 * @brief Check if DMA reception requests are enabled or disabled. 0627 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX 0628 * @param I2Cx I2C Instance. 0629 * @retval State of bit (1 or 0). 0630 */ 0631 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) 0632 { 0633 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); 0634 } 0635 0636 /** 0637 * @brief Get the data register address used for DMA transfer 0638 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n 0639 * RXDR RXDATA LL_I2C_DMA_GetRegAddr 0640 * @param I2Cx I2C Instance 0641 * @param Direction This parameter can be one of the following values: 0642 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT 0643 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE 0644 * @retval Address of data register 0645 */ 0646 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) 0647 { 0648 uint32_t data_reg_addr; 0649 0650 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) 0651 { 0652 /* return address of TXDR register */ 0653 data_reg_addr = (uint32_t) &(I2Cx->TXDR); 0654 } 0655 else 0656 { 0657 /* return address of RXDR register */ 0658 data_reg_addr = (uint32_t) &(I2Cx->RXDR); 0659 } 0660 0661 return data_reg_addr; 0662 } 0663 0664 /** 0665 * @brief Enable Clock stretching. 0666 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 0667 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching 0668 * @param I2Cx I2C Instance. 0669 * @retval None 0670 */ 0671 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) 0672 { 0673 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 0674 } 0675 0676 /** 0677 * @brief Disable Clock stretching. 0678 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 0679 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching 0680 * @param I2Cx I2C Instance. 0681 * @retval None 0682 */ 0683 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) 0684 { 0685 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 0686 } 0687 0688 /** 0689 * @brief Check if Clock stretching is enabled or disabled. 0690 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching 0691 * @param I2Cx I2C Instance. 0692 * @retval State of bit (1 or 0). 0693 */ 0694 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) 0695 { 0696 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); 0697 } 0698 0699 /** 0700 * @brief Enable hardware byte control in slave mode. 0701 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl 0702 * @param I2Cx I2C Instance. 0703 * @retval None 0704 */ 0705 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) 0706 { 0707 SET_BIT(I2Cx->CR1, I2C_CR1_SBC); 0708 } 0709 0710 /** 0711 * @brief Disable hardware byte control in slave mode. 0712 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl 0713 * @param I2Cx I2C Instance. 0714 * @retval None 0715 */ 0716 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) 0717 { 0718 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); 0719 } 0720 0721 /** 0722 * @brief Check if hardware byte control in slave mode is enabled or disabled. 0723 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl 0724 * @param I2Cx I2C Instance. 0725 * @retval State of bit (1 or 0). 0726 */ 0727 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) 0728 { 0729 return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); 0730 } 0731 0732 /** 0733 * @brief Enable Wakeup from STOP. 0734 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 0735 * WakeUpFromStop feature is supported by the I2Cx Instance. 0736 * @note This bit can only be programmed when Digital Filter is disabled. 0737 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop 0738 * @param I2Cx I2C Instance. 0739 * @retval None 0740 */ 0741 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) 0742 { 0743 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); 0744 } 0745 0746 /** 0747 * @brief Disable Wakeup from STOP. 0748 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 0749 * WakeUpFromStop feature is supported by the I2Cx Instance. 0750 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop 0751 * @param I2Cx I2C Instance. 0752 * @retval None 0753 */ 0754 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) 0755 { 0756 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); 0757 } 0758 0759 /** 0760 * @brief Check if Wakeup from STOP is enabled or disabled. 0761 * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 0762 * WakeUpFromStop feature is supported by the I2Cx Instance. 0763 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop 0764 * @param I2Cx I2C Instance. 0765 * @retval State of bit (1 or 0). 0766 */ 0767 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) 0768 { 0769 return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); 0770 } 0771 0772 /** 0773 * @brief Enable General Call. 0774 * @note When enabled the Address 0x00 is ACKed. 0775 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall 0776 * @param I2Cx I2C Instance. 0777 * @retval None 0778 */ 0779 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) 0780 { 0781 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); 0782 } 0783 0784 /** 0785 * @brief Disable General Call. 0786 * @note When disabled the Address 0x00 is NACKed. 0787 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall 0788 * @param I2Cx I2C Instance. 0789 * @retval None 0790 */ 0791 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) 0792 { 0793 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); 0794 } 0795 0796 /** 0797 * @brief Check if General Call is enabled or disabled. 0798 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall 0799 * @param I2Cx I2C Instance. 0800 * @retval State of bit (1 or 0). 0801 */ 0802 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) 0803 { 0804 return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); 0805 } 0806 0807 /** 0808 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. 0809 * @note Changing this bit is not allowed, when the START bit is set. 0810 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode 0811 * @param I2Cx I2C Instance. 0812 * @param AddressingMode This parameter can be one of the following values: 0813 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT 0814 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT 0815 * @retval None 0816 */ 0817 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) 0818 { 0819 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); 0820 } 0821 0822 /** 0823 * @brief Get the Master addressing mode. 0824 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode 0825 * @param I2Cx I2C Instance. 0826 * @retval Returned value can be one of the following values: 0827 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT 0828 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT 0829 */ 0830 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) 0831 { 0832 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); 0833 } 0834 0835 /** 0836 * @brief Set the Own Address1. 0837 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n 0838 * OAR1 OA1MODE LL_I2C_SetOwnAddress1 0839 * @param I2Cx I2C Instance. 0840 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. 0841 * @param OwnAddrSize This parameter can be one of the following values: 0842 * @arg @ref LL_I2C_OWNADDRESS1_7BIT 0843 * @arg @ref LL_I2C_OWNADDRESS1_10BIT 0844 * @retval None 0845 */ 0846 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) 0847 { 0848 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); 0849 } 0850 0851 /** 0852 * @brief Enable acknowledge on Own Address1 match address. 0853 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 0854 * @param I2Cx I2C Instance. 0855 * @retval None 0856 */ 0857 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) 0858 { 0859 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); 0860 } 0861 0862 /** 0863 * @brief Disable acknowledge on Own Address1 match address. 0864 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 0865 * @param I2Cx I2C Instance. 0866 * @retval None 0867 */ 0868 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) 0869 { 0870 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); 0871 } 0872 0873 /** 0874 * @brief Check if Own Address1 acknowledge is enabled or disabled. 0875 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 0876 * @param I2Cx I2C Instance. 0877 * @retval State of bit (1 or 0). 0878 */ 0879 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) 0880 { 0881 return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); 0882 } 0883 0884 /** 0885 * @brief Set the 7bits Own Address2. 0886 * @note This action has no effect if own address2 is enabled. 0887 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n 0888 * OAR2 OA2MSK LL_I2C_SetOwnAddress2 0889 * @param I2Cx I2C Instance. 0890 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. 0891 * @param OwnAddrMask This parameter can be one of the following values: 0892 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK 0893 * @arg @ref LL_I2C_OWNADDRESS2_MASK01 0894 * @arg @ref LL_I2C_OWNADDRESS2_MASK02 0895 * @arg @ref LL_I2C_OWNADDRESS2_MASK03 0896 * @arg @ref LL_I2C_OWNADDRESS2_MASK04 0897 * @arg @ref LL_I2C_OWNADDRESS2_MASK05 0898 * @arg @ref LL_I2C_OWNADDRESS2_MASK06 0899 * @arg @ref LL_I2C_OWNADDRESS2_MASK07 0900 * @retval None 0901 */ 0902 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) 0903 { 0904 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); 0905 } 0906 0907 /** 0908 * @brief Enable acknowledge on Own Address2 match address. 0909 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 0910 * @param I2Cx I2C Instance. 0911 * @retval None 0912 */ 0913 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) 0914 { 0915 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); 0916 } 0917 0918 /** 0919 * @brief Disable acknowledge on Own Address2 match address. 0920 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 0921 * @param I2Cx I2C Instance. 0922 * @retval None 0923 */ 0924 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) 0925 { 0926 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); 0927 } 0928 0929 /** 0930 * @brief Check if Own Address1 acknowledge is enabled or disabled. 0931 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 0932 * @param I2Cx I2C Instance. 0933 * @retval State of bit (1 or 0). 0934 */ 0935 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) 0936 { 0937 return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); 0938 } 0939 0940 /** 0941 * @brief Configure the SDA setup, hold time and the SCL high, low period. 0942 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 0943 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming 0944 * @param I2Cx I2C Instance. 0945 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. 0946 * @note This parameter is computed with the STM32CubeMX Tool. 0947 * @retval None 0948 */ 0949 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) 0950 { 0951 WRITE_REG(I2Cx->TIMINGR, Timing); 0952 } 0953 0954 /** 0955 * @brief Get the Timing Prescaler setting. 0956 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler 0957 * @param I2Cx I2C Instance. 0958 * @retval Value between Min_Data=0x0 and Max_Data=0xF 0959 */ 0960 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) 0961 { 0962 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); 0963 } 0964 0965 /** 0966 * @brief Get the SCL low period setting. 0967 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod 0968 * @param I2Cx I2C Instance. 0969 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 0970 */ 0971 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) 0972 { 0973 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); 0974 } 0975 0976 /** 0977 * @brief Get the SCL high period setting. 0978 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod 0979 * @param I2Cx I2C Instance. 0980 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 0981 */ 0982 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) 0983 { 0984 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); 0985 } 0986 0987 /** 0988 * @brief Get the SDA hold time. 0989 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime 0990 * @param I2Cx I2C Instance. 0991 * @retval Value between Min_Data=0x0 and Max_Data=0xF 0992 */ 0993 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) 0994 { 0995 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); 0996 } 0997 0998 /** 0999 * @brief Get the SDA setup time. 1000 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime 1001 * @param I2Cx I2C Instance. 1002 * @retval Value between Min_Data=0x0 and Max_Data=0xF 1003 */ 1004 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) 1005 { 1006 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); 1007 } 1008 1009 /** 1010 * @brief Configure peripheral mode. 1011 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1012 * SMBus feature is supported by the I2Cx Instance. 1013 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n 1014 * CR1 SMBDEN LL_I2C_SetMode 1015 * @param I2Cx I2C Instance. 1016 * @param PeripheralMode This parameter can be one of the following values: 1017 * @arg @ref LL_I2C_MODE_I2C 1018 * @arg @ref LL_I2C_MODE_SMBUS_HOST 1019 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 1020 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 1021 * @retval None 1022 */ 1023 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) 1024 { 1025 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); 1026 } 1027 1028 /** 1029 * @brief Get peripheral mode. 1030 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1031 * SMBus feature is supported by the I2Cx Instance. 1032 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n 1033 * CR1 SMBDEN LL_I2C_GetMode 1034 * @param I2Cx I2C Instance. 1035 * @retval Returned value can be one of the following values: 1036 * @arg @ref LL_I2C_MODE_I2C 1037 * @arg @ref LL_I2C_MODE_SMBUS_HOST 1038 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 1039 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 1040 */ 1041 __STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) 1042 { 1043 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); 1044 } 1045 1046 /** 1047 * @brief Enable SMBus alert (Host or Device mode) 1048 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1049 * SMBus feature is supported by the I2Cx Instance. 1050 * @note SMBus Device mode: 1051 * - SMBus Alert pin is drived low and 1052 * Alert Response Address Header acknowledge is enabled. 1053 * SMBus Host mode: 1054 * - SMBus Alert pin management is supported. 1055 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert 1056 * @param I2Cx I2C Instance. 1057 * @retval None 1058 */ 1059 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) 1060 { 1061 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); 1062 } 1063 1064 /** 1065 * @brief Disable SMBus alert (Host or Device mode) 1066 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1067 * SMBus feature is supported by the I2Cx Instance. 1068 * @note SMBus Device mode: 1069 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and 1070 * Alert Response Address Header acknowledge is disabled. 1071 * SMBus Host mode: 1072 * - SMBus Alert pin management is not supported. 1073 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert 1074 * @param I2Cx I2C Instance. 1075 * @retval None 1076 */ 1077 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) 1078 { 1079 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); 1080 } 1081 1082 /** 1083 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. 1084 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1085 * SMBus feature is supported by the I2Cx Instance. 1086 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert 1087 * @param I2Cx I2C Instance. 1088 * @retval State of bit (1 or 0). 1089 */ 1090 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) 1091 { 1092 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); 1093 } 1094 1095 /** 1096 * @brief Enable SMBus Packet Error Calculation (PEC). 1097 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1098 * SMBus feature is supported by the I2Cx Instance. 1099 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC 1100 * @param I2Cx I2C Instance. 1101 * @retval None 1102 */ 1103 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) 1104 { 1105 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); 1106 } 1107 1108 /** 1109 * @brief Disable SMBus Packet Error Calculation (PEC). 1110 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1111 * SMBus feature is supported by the I2Cx Instance. 1112 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC 1113 * @param I2Cx I2C Instance. 1114 * @retval None 1115 */ 1116 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) 1117 { 1118 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); 1119 } 1120 1121 /** 1122 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. 1123 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1124 * SMBus feature is supported by the I2Cx Instance. 1125 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC 1126 * @param I2Cx I2C Instance. 1127 * @retval State of bit (1 or 0). 1128 */ 1129 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) 1130 { 1131 return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); 1132 } 1133 1134 /** 1135 * @brief Configure the SMBus Clock Timeout. 1136 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1137 * SMBus feature is supported by the I2Cx Instance. 1138 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). 1139 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n 1140 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n 1141 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout 1142 * @param I2Cx I2C Instance. 1143 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 1144 * @param TimeoutAMode This parameter can be one of the following values: 1145 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 1146 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 1147 * @param TimeoutB 1148 * @retval None 1149 */ 1150 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, 1151 uint32_t TimeoutB) 1152 { 1153 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, 1154 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); 1155 } 1156 1157 /** 1158 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). 1159 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1160 * SMBus feature is supported by the I2Cx Instance. 1161 * @note These bits can only be programmed when TimeoutA is disabled. 1162 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA 1163 * @param I2Cx I2C Instance. 1164 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 1165 * @retval None 1166 */ 1167 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) 1168 { 1169 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); 1170 } 1171 1172 /** 1173 * @brief Get the SMBus Clock TimeoutA setting. 1174 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1175 * SMBus feature is supported by the I2Cx Instance. 1176 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA 1177 * @param I2Cx I2C Instance. 1178 * @retval Value between Min_Data=0 and Max_Data=0xFFF 1179 */ 1180 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) 1181 { 1182 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); 1183 } 1184 1185 /** 1186 * @brief Set the SMBus Clock TimeoutA mode. 1187 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1188 * SMBus feature is supported by the I2Cx Instance. 1189 * @note This bit can only be programmed when TimeoutA is disabled. 1190 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode 1191 * @param I2Cx I2C Instance. 1192 * @param TimeoutAMode This parameter can be one of the following values: 1193 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 1194 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 1195 * @retval None 1196 */ 1197 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) 1198 { 1199 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); 1200 } 1201 1202 /** 1203 * @brief Get the SMBus Clock TimeoutA mode. 1204 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1205 * SMBus feature is supported by the I2Cx Instance. 1206 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode 1207 * @param I2Cx I2C Instance. 1208 * @retval Returned value can be one of the following values: 1209 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 1210 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 1211 */ 1212 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) 1213 { 1214 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); 1215 } 1216 1217 /** 1218 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). 1219 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1220 * SMBus feature is supported by the I2Cx Instance. 1221 * @note These bits can only be programmed when TimeoutB is disabled. 1222 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB 1223 * @param I2Cx I2C Instance. 1224 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 1225 * @retval None 1226 */ 1227 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) 1228 { 1229 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); 1230 } 1231 1232 /** 1233 * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. 1234 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1235 * SMBus feature is supported by the I2Cx Instance. 1236 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB 1237 * @param I2Cx I2C Instance. 1238 * @retval Value between Min_Data=0 and Max_Data=0xFFF 1239 */ 1240 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) 1241 { 1242 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); 1243 } 1244 1245 /** 1246 * @brief Enable the SMBus Clock Timeout. 1247 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1248 * SMBus feature is supported by the I2Cx Instance. 1249 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n 1250 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout 1251 * @param I2Cx I2C Instance. 1252 * @param ClockTimeout This parameter can be one of the following values: 1253 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 1254 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 1255 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 1256 * @retval None 1257 */ 1258 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 1259 { 1260 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); 1261 } 1262 1263 /** 1264 * @brief Disable the SMBus Clock Timeout. 1265 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1266 * SMBus feature is supported by the I2Cx Instance. 1267 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n 1268 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout 1269 * @param I2Cx I2C Instance. 1270 * @param ClockTimeout This parameter can be one of the following values: 1271 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 1272 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 1273 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 1274 * @retval None 1275 */ 1276 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 1277 { 1278 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); 1279 } 1280 1281 /** 1282 * @brief Check if the SMBus Clock Timeout is enabled or disabled. 1283 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1284 * SMBus feature is supported by the I2Cx Instance. 1285 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n 1286 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout 1287 * @param I2Cx I2C Instance. 1288 * @param ClockTimeout This parameter can be one of the following values: 1289 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 1290 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 1291 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 1292 * @retval State of bit (1 or 0). 1293 */ 1294 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 1295 { 1296 return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ 1297 (ClockTimeout)) ? 1UL : 0UL); 1298 } 1299 1300 /** 1301 * @} 1302 */ 1303 1304 /** @defgroup I2C_LL_EF_IT_Management IT_Management 1305 * @ingroup RTEMSBSPsARMSTM32H7 1306 * @{ 1307 */ 1308 1309 /** 1310 * @brief Enable TXIS interrupt. 1311 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX 1312 * @param I2Cx I2C Instance. 1313 * @retval None 1314 */ 1315 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) 1316 { 1317 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); 1318 } 1319 1320 /** 1321 * @brief Disable TXIS interrupt. 1322 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX 1323 * @param I2Cx I2C Instance. 1324 * @retval None 1325 */ 1326 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) 1327 { 1328 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); 1329 } 1330 1331 /** 1332 * @brief Check if the TXIS Interrupt is enabled or disabled. 1333 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX 1334 * @param I2Cx I2C Instance. 1335 * @retval State of bit (1 or 0). 1336 */ 1337 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) 1338 { 1339 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); 1340 } 1341 1342 /** 1343 * @brief Enable RXNE interrupt. 1344 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX 1345 * @param I2Cx I2C Instance. 1346 * @retval None 1347 */ 1348 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) 1349 { 1350 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); 1351 } 1352 1353 /** 1354 * @brief Disable RXNE interrupt. 1355 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX 1356 * @param I2Cx I2C Instance. 1357 * @retval None 1358 */ 1359 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) 1360 { 1361 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); 1362 } 1363 1364 /** 1365 * @brief Check if the RXNE Interrupt is enabled or disabled. 1366 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX 1367 * @param I2Cx I2C Instance. 1368 * @retval State of bit (1 or 0). 1369 */ 1370 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) 1371 { 1372 return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); 1373 } 1374 1375 /** 1376 * @brief Enable Address match interrupt (slave mode only). 1377 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR 1378 * @param I2Cx I2C Instance. 1379 * @retval None 1380 */ 1381 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) 1382 { 1383 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); 1384 } 1385 1386 /** 1387 * @brief Disable Address match interrupt (slave mode only). 1388 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR 1389 * @param I2Cx I2C Instance. 1390 * @retval None 1391 */ 1392 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) 1393 { 1394 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); 1395 } 1396 1397 /** 1398 * @brief Check if Address match interrupt is enabled or disabled. 1399 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR 1400 * @param I2Cx I2C Instance. 1401 * @retval State of bit (1 or 0). 1402 */ 1403 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) 1404 { 1405 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); 1406 } 1407 1408 /** 1409 * @brief Enable Not acknowledge received interrupt. 1410 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK 1411 * @param I2Cx I2C Instance. 1412 * @retval None 1413 */ 1414 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) 1415 { 1416 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); 1417 } 1418 1419 /** 1420 * @brief Disable Not acknowledge received interrupt. 1421 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK 1422 * @param I2Cx I2C Instance. 1423 * @retval None 1424 */ 1425 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) 1426 { 1427 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); 1428 } 1429 1430 /** 1431 * @brief Check if Not acknowledge received interrupt is enabled or disabled. 1432 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK 1433 * @param I2Cx I2C Instance. 1434 * @retval State of bit (1 or 0). 1435 */ 1436 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) 1437 { 1438 return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); 1439 } 1440 1441 /** 1442 * @brief Enable STOP detection interrupt. 1443 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP 1444 * @param I2Cx I2C Instance. 1445 * @retval None 1446 */ 1447 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) 1448 { 1449 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); 1450 } 1451 1452 /** 1453 * @brief Disable STOP detection interrupt. 1454 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP 1455 * @param I2Cx I2C Instance. 1456 * @retval None 1457 */ 1458 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) 1459 { 1460 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); 1461 } 1462 1463 /** 1464 * @brief Check if STOP detection interrupt is enabled or disabled. 1465 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP 1466 * @param I2Cx I2C Instance. 1467 * @retval State of bit (1 or 0). 1468 */ 1469 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) 1470 { 1471 return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); 1472 } 1473 1474 /** 1475 * @brief Enable Transfer Complete interrupt. 1476 * @note Any of these events will generate interrupt : 1477 * Transfer Complete (TC) 1478 * Transfer Complete Reload (TCR) 1479 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC 1480 * @param I2Cx I2C Instance. 1481 * @retval None 1482 */ 1483 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) 1484 { 1485 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); 1486 } 1487 1488 /** 1489 * @brief Disable Transfer Complete interrupt. 1490 * @note Any of these events will generate interrupt : 1491 * Transfer Complete (TC) 1492 * Transfer Complete Reload (TCR) 1493 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC 1494 * @param I2Cx I2C Instance. 1495 * @retval None 1496 */ 1497 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) 1498 { 1499 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); 1500 } 1501 1502 /** 1503 * @brief Check if Transfer Complete interrupt is enabled or disabled. 1504 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC 1505 * @param I2Cx I2C Instance. 1506 * @retval State of bit (1 or 0). 1507 */ 1508 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) 1509 { 1510 return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); 1511 } 1512 1513 /** 1514 * @brief Enable Error interrupts. 1515 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1516 * SMBus feature is supported by the I2Cx Instance. 1517 * @note Any of these errors will generate interrupt : 1518 * Arbitration Loss (ARLO) 1519 * Bus Error detection (BERR) 1520 * Overrun/Underrun (OVR) 1521 * SMBus Timeout detection (TIMEOUT) 1522 * SMBus PEC error detection (PECERR) 1523 * SMBus Alert pin event detection (ALERT) 1524 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR 1525 * @param I2Cx I2C Instance. 1526 * @retval None 1527 */ 1528 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) 1529 { 1530 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); 1531 } 1532 1533 /** 1534 * @brief Disable Error interrupts. 1535 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1536 * SMBus feature is supported by the I2Cx Instance. 1537 * @note Any of these errors will generate interrupt : 1538 * Arbitration Loss (ARLO) 1539 * Bus Error detection (BERR) 1540 * Overrun/Underrun (OVR) 1541 * SMBus Timeout detection (TIMEOUT) 1542 * SMBus PEC error detection (PECERR) 1543 * SMBus Alert pin event detection (ALERT) 1544 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR 1545 * @param I2Cx I2C Instance. 1546 * @retval None 1547 */ 1548 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) 1549 { 1550 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); 1551 } 1552 1553 /** 1554 * @brief Check if Error interrupts are enabled or disabled. 1555 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR 1556 * @param I2Cx I2C Instance. 1557 * @retval State of bit (1 or 0). 1558 */ 1559 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) 1560 { 1561 return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); 1562 } 1563 1564 /** 1565 * @} 1566 */ 1567 1568 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management 1569 * @ingroup RTEMSBSPsARMSTM32H7 1570 * @{ 1571 */ 1572 1573 /** 1574 * @brief Indicate the status of Transmit data register empty flag. 1575 * @note RESET: When next data is written in Transmit data register. 1576 * SET: When Transmit data register is empty. 1577 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE 1578 * @param I2Cx I2C Instance. 1579 * @retval State of bit (1 or 0). 1580 */ 1581 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) 1582 { 1583 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); 1584 } 1585 1586 /** 1587 * @brief Indicate the status of Transmit interrupt flag. 1588 * @note RESET: When next data is written in Transmit data register. 1589 * SET: When Transmit data register is empty. 1590 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS 1591 * @param I2Cx I2C Instance. 1592 * @retval State of bit (1 or 0). 1593 */ 1594 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) 1595 { 1596 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); 1597 } 1598 1599 /** 1600 * @brief Indicate the status of Receive data register not empty flag. 1601 * @note RESET: When Receive data register is read. 1602 * SET: When the received data is copied in Receive data register. 1603 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE 1604 * @param I2Cx I2C Instance. 1605 * @retval State of bit (1 or 0). 1606 */ 1607 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) 1608 { 1609 return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); 1610 } 1611 1612 /** 1613 * @brief Indicate the status of Address matched flag (slave mode). 1614 * @note RESET: Clear default value. 1615 * SET: When the received slave address matched with one of the enabled slave address. 1616 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR 1617 * @param I2Cx I2C Instance. 1618 * @retval State of bit (1 or 0). 1619 */ 1620 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) 1621 { 1622 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); 1623 } 1624 1625 /** 1626 * @brief Indicate the status of Not Acknowledge received flag. 1627 * @note RESET: Clear default value. 1628 * SET: When a NACK is received after a byte transmission. 1629 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK 1630 * @param I2Cx I2C Instance. 1631 * @retval State of bit (1 or 0). 1632 */ 1633 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) 1634 { 1635 return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); 1636 } 1637 1638 /** 1639 * @brief Indicate the status of Stop detection flag. 1640 * @note RESET: Clear default value. 1641 * SET: When a Stop condition is detected. 1642 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP 1643 * @param I2Cx I2C Instance. 1644 * @retval State of bit (1 or 0). 1645 */ 1646 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) 1647 { 1648 return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); 1649 } 1650 1651 /** 1652 * @brief Indicate the status of Transfer complete flag (master mode). 1653 * @note RESET: Clear default value. 1654 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. 1655 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC 1656 * @param I2Cx I2C Instance. 1657 * @retval State of bit (1 or 0). 1658 */ 1659 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) 1660 { 1661 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); 1662 } 1663 1664 /** 1665 * @brief Indicate the status of Transfer complete flag (master mode). 1666 * @note RESET: Clear default value. 1667 * SET: When RELOAD=1 and NBYTES date have been transferred. 1668 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR 1669 * @param I2Cx I2C Instance. 1670 * @retval State of bit (1 or 0). 1671 */ 1672 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) 1673 { 1674 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); 1675 } 1676 1677 /** 1678 * @brief Indicate the status of Bus error flag. 1679 * @note RESET: Clear default value. 1680 * SET: When a misplaced Start or Stop condition is detected. 1681 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR 1682 * @param I2Cx I2C Instance. 1683 * @retval State of bit (1 or 0). 1684 */ 1685 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) 1686 { 1687 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); 1688 } 1689 1690 /** 1691 * @brief Indicate the status of Arbitration lost flag. 1692 * @note RESET: Clear default value. 1693 * SET: When arbitration lost. 1694 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO 1695 * @param I2Cx I2C Instance. 1696 * @retval State of bit (1 or 0). 1697 */ 1698 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) 1699 { 1700 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); 1701 } 1702 1703 /** 1704 * @brief Indicate the status of Overrun/Underrun flag (slave mode). 1705 * @note RESET: Clear default value. 1706 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). 1707 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR 1708 * @param I2Cx I2C Instance. 1709 * @retval State of bit (1 or 0). 1710 */ 1711 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) 1712 { 1713 return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); 1714 } 1715 1716 /** 1717 * @brief Indicate the status of SMBus PEC error flag in reception. 1718 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1719 * SMBus feature is supported by the I2Cx Instance. 1720 * @note RESET: Clear default value. 1721 * SET: When the received PEC does not match with the PEC register content. 1722 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR 1723 * @param I2Cx I2C Instance. 1724 * @retval State of bit (1 or 0). 1725 */ 1726 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) 1727 { 1728 return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); 1729 } 1730 1731 /** 1732 * @brief Indicate the status of SMBus Timeout detection flag. 1733 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1734 * SMBus feature is supported by the I2Cx Instance. 1735 * @note RESET: Clear default value. 1736 * SET: When a timeout or extended clock timeout occurs. 1737 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT 1738 * @param I2Cx I2C Instance. 1739 * @retval State of bit (1 or 0). 1740 */ 1741 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) 1742 { 1743 return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); 1744 } 1745 1746 /** 1747 * @brief Indicate the status of SMBus alert flag. 1748 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1749 * SMBus feature is supported by the I2Cx Instance. 1750 * @note RESET: Clear default value. 1751 * SET: When SMBus host configuration, SMBus alert enabled and 1752 * a falling edge event occurs on SMBA pin. 1753 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT 1754 * @param I2Cx I2C Instance. 1755 * @retval State of bit (1 or 0). 1756 */ 1757 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) 1758 { 1759 return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); 1760 } 1761 1762 /** 1763 * @brief Indicate the status of Bus Busy flag. 1764 * @note RESET: Clear default value. 1765 * SET: When a Start condition is detected. 1766 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY 1767 * @param I2Cx I2C Instance. 1768 * @retval State of bit (1 or 0). 1769 */ 1770 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) 1771 { 1772 return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); 1773 } 1774 1775 /** 1776 * @brief Clear Address Matched flag. 1777 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR 1778 * @param I2Cx I2C Instance. 1779 * @retval None 1780 */ 1781 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) 1782 { 1783 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); 1784 } 1785 1786 /** 1787 * @brief Clear Not Acknowledge flag. 1788 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK 1789 * @param I2Cx I2C Instance. 1790 * @retval None 1791 */ 1792 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) 1793 { 1794 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); 1795 } 1796 1797 /** 1798 * @brief Clear Stop detection flag. 1799 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP 1800 * @param I2Cx I2C Instance. 1801 * @retval None 1802 */ 1803 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) 1804 { 1805 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); 1806 } 1807 1808 /** 1809 * @brief Clear Transmit data register empty flag (TXE). 1810 * @note This bit can be clear by software in order to flush the transmit data register (TXDR). 1811 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE 1812 * @param I2Cx I2C Instance. 1813 * @retval None 1814 */ 1815 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) 1816 { 1817 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); 1818 } 1819 1820 /** 1821 * @brief Clear Bus error flag. 1822 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR 1823 * @param I2Cx I2C Instance. 1824 * @retval None 1825 */ 1826 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) 1827 { 1828 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); 1829 } 1830 1831 /** 1832 * @brief Clear Arbitration lost flag. 1833 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO 1834 * @param I2Cx I2C Instance. 1835 * @retval None 1836 */ 1837 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) 1838 { 1839 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); 1840 } 1841 1842 /** 1843 * @brief Clear Overrun/Underrun flag. 1844 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR 1845 * @param I2Cx I2C Instance. 1846 * @retval None 1847 */ 1848 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) 1849 { 1850 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); 1851 } 1852 1853 /** 1854 * @brief Clear SMBus PEC error flag. 1855 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1856 * SMBus feature is supported by the I2Cx Instance. 1857 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR 1858 * @param I2Cx I2C Instance. 1859 * @retval None 1860 */ 1861 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) 1862 { 1863 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); 1864 } 1865 1866 /** 1867 * @brief Clear SMBus Timeout detection flag. 1868 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1869 * SMBus feature is supported by the I2Cx Instance. 1870 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT 1871 * @param I2Cx I2C Instance. 1872 * @retval None 1873 */ 1874 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) 1875 { 1876 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); 1877 } 1878 1879 /** 1880 * @brief Clear SMBus Alert flag. 1881 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 1882 * SMBus feature is supported by the I2Cx Instance. 1883 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT 1884 * @param I2Cx I2C Instance. 1885 * @retval None 1886 */ 1887 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) 1888 { 1889 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); 1890 } 1891 1892 /** 1893 * @} 1894 */ 1895 1896 /** @defgroup I2C_LL_EF_Data_Management Data_Management 1897 * @ingroup RTEMSBSPsARMSTM32H7 1898 * @{ 1899 */ 1900 1901 /** 1902 * @brief Enable automatic STOP condition generation (master mode). 1903 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. 1904 * This bit has no effect in slave mode or when RELOAD bit is set. 1905 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode 1906 * @param I2Cx I2C Instance. 1907 * @retval None 1908 */ 1909 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) 1910 { 1911 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); 1912 } 1913 1914 /** 1915 * @brief Disable automatic STOP condition generation (master mode). 1916 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. 1917 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode 1918 * @param I2Cx I2C Instance. 1919 * @retval None 1920 */ 1921 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) 1922 { 1923 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); 1924 } 1925 1926 /** 1927 * @brief Check if automatic STOP condition is enabled or disabled. 1928 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode 1929 * @param I2Cx I2C Instance. 1930 * @retval State of bit (1 or 0). 1931 */ 1932 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) 1933 { 1934 return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); 1935 } 1936 1937 /** 1938 * @brief Enable reload mode (master mode). 1939 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. 1940 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode 1941 * @param I2Cx I2C Instance. 1942 * @retval None 1943 */ 1944 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) 1945 { 1946 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); 1947 } 1948 1949 /** 1950 * @brief Disable reload mode (master mode). 1951 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). 1952 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode 1953 * @param I2Cx I2C Instance. 1954 * @retval None 1955 */ 1956 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) 1957 { 1958 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); 1959 } 1960 1961 /** 1962 * @brief Check if reload mode is enabled or disabled. 1963 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode 1964 * @param I2Cx I2C Instance. 1965 * @retval State of bit (1 or 0). 1966 */ 1967 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) 1968 { 1969 return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); 1970 } 1971 1972 /** 1973 * @brief Configure the number of bytes for transfer. 1974 * @note Changing these bits when START bit is set is not allowed. 1975 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize 1976 * @param I2Cx I2C Instance. 1977 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. 1978 * @retval None 1979 */ 1980 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) 1981 { 1982 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); 1983 } 1984 1985 /** 1986 * @brief Get the number of bytes configured for transfer. 1987 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize 1988 * @param I2Cx I2C Instance. 1989 * @retval Value between Min_Data=0x0 and Max_Data=0xFF 1990 */ 1991 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) 1992 { 1993 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); 1994 } 1995 1996 /** 1997 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code 1998 or next received byte. 1999 * @note Usage in Slave mode only. 2000 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData 2001 * @param I2Cx I2C Instance. 2002 * @param TypeAcknowledge This parameter can be one of the following values: 2003 * @arg @ref LL_I2C_ACK 2004 * @arg @ref LL_I2C_NACK 2005 * @retval None 2006 */ 2007 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) 2008 { 2009 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); 2010 } 2011 2012 /** 2013 * @brief Generate a START or RESTART condition 2014 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. 2015 * This action has no effect when RELOAD is set. 2016 * @rmtoll CR2 START LL_I2C_GenerateStartCondition 2017 * @param I2Cx I2C Instance. 2018 * @retval None 2019 */ 2020 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) 2021 { 2022 SET_BIT(I2Cx->CR2, I2C_CR2_START); 2023 } 2024 2025 /** 2026 * @brief Generate a STOP condition after the current byte transfer (master mode). 2027 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition 2028 * @param I2Cx I2C Instance. 2029 * @retval None 2030 */ 2031 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) 2032 { 2033 SET_BIT(I2Cx->CR2, I2C_CR2_STOP); 2034 } 2035 2036 /** 2037 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). 2038 * @note The master sends the complete 10bit slave address read sequence : 2039 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address 2040 in Read direction. 2041 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead 2042 * @param I2Cx I2C Instance. 2043 * @retval None 2044 */ 2045 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) 2046 { 2047 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); 2048 } 2049 2050 /** 2051 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). 2052 * @note The master only sends the first 7 bits of 10bit address in Read direction. 2053 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead 2054 * @param I2Cx I2C Instance. 2055 * @retval None 2056 */ 2057 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) 2058 { 2059 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); 2060 } 2061 2062 /** 2063 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. 2064 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead 2065 * @param I2Cx I2C Instance. 2066 * @retval State of bit (1 or 0). 2067 */ 2068 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) 2069 { 2070 return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); 2071 } 2072 2073 /** 2074 * @brief Configure the transfer direction (master mode). 2075 * @note Changing these bits when START bit is set is not allowed. 2076 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest 2077 * @param I2Cx I2C Instance. 2078 * @param TransferRequest This parameter can be one of the following values: 2079 * @arg @ref LL_I2C_REQUEST_WRITE 2080 * @arg @ref LL_I2C_REQUEST_READ 2081 * @retval None 2082 */ 2083 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) 2084 { 2085 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); 2086 } 2087 2088 /** 2089 * @brief Get the transfer direction requested (master mode). 2090 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest 2091 * @param I2Cx I2C Instance. 2092 * @retval Returned value can be one of the following values: 2093 * @arg @ref LL_I2C_REQUEST_WRITE 2094 * @arg @ref LL_I2C_REQUEST_READ 2095 */ 2096 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) 2097 { 2098 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); 2099 } 2100 2101 /** 2102 * @brief Configure the slave address for transfer (master mode). 2103 * @note Changing these bits when START bit is set is not allowed. 2104 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr 2105 * @param I2Cx I2C Instance. 2106 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. 2107 * @retval None 2108 */ 2109 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) 2110 { 2111 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); 2112 } 2113 2114 /** 2115 * @brief Get the slave address programmed for transfer. 2116 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr 2117 * @param I2Cx I2C Instance. 2118 * @retval Value between Min_Data=0x0 and Max_Data=0x3F 2119 */ 2120 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) 2121 { 2122 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); 2123 } 2124 2125 /** 2126 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). 2127 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n 2128 * CR2 ADD10 LL_I2C_HandleTransfer\n 2129 * CR2 RD_WRN LL_I2C_HandleTransfer\n 2130 * CR2 START LL_I2C_HandleTransfer\n 2131 * CR2 STOP LL_I2C_HandleTransfer\n 2132 * CR2 RELOAD LL_I2C_HandleTransfer\n 2133 * CR2 NBYTES LL_I2C_HandleTransfer\n 2134 * CR2 AUTOEND LL_I2C_HandleTransfer\n 2135 * CR2 HEAD10R LL_I2C_HandleTransfer 2136 * @param I2Cx I2C Instance. 2137 * @param SlaveAddr Specifies the slave address to be programmed. 2138 * @param SlaveAddrSize This parameter can be one of the following values: 2139 * @arg @ref LL_I2C_ADDRSLAVE_7BIT 2140 * @arg @ref LL_I2C_ADDRSLAVE_10BIT 2141 * @param TransferSize Specifies the number of bytes to be programmed. 2142 * This parameter must be a value between Min_Data=0 and Max_Data=255. 2143 * @param EndMode This parameter can be one of the following values: 2144 * @arg @ref LL_I2C_MODE_RELOAD 2145 * @arg @ref LL_I2C_MODE_AUTOEND 2146 * @arg @ref LL_I2C_MODE_SOFTEND 2147 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD 2148 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC 2149 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC 2150 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC 2151 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC 2152 * @param Request This parameter can be one of the following values: 2153 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP 2154 * @arg @ref LL_I2C_GENERATE_STOP 2155 * @arg @ref LL_I2C_GENERATE_START_READ 2156 * @arg @ref LL_I2C_GENERATE_START_WRITE 2157 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ 2158 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE 2159 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ 2160 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE 2161 * @retval None 2162 */ 2163 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, 2164 uint32_t TransferSize, uint32_t EndMode, uint32_t Request) 2165 { 2166 /* Declaration of tmp to prevent undefined behavior of volatile usage */ 2167 uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ 2168 ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ 2169 (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ 2170 (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); 2171 2172 /* update CR2 register */ 2173 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | 2174 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | 2175 I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | 2176 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, 2177 tmp); 2178 } 2179 2180 /** 2181 * @brief Indicate the value of transfer direction (slave mode). 2182 * @note RESET: Write transfer, Slave enters in receiver mode. 2183 * SET: Read transfer, Slave enters in transmitter mode. 2184 * @rmtoll ISR DIR LL_I2C_GetTransferDirection 2185 * @param I2Cx I2C Instance. 2186 * @retval Returned value can be one of the following values: 2187 * @arg @ref LL_I2C_DIRECTION_WRITE 2188 * @arg @ref LL_I2C_DIRECTION_READ 2189 */ 2190 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) 2191 { 2192 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); 2193 } 2194 2195 /** 2196 * @brief Return the slave matched address. 2197 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode 2198 * @param I2Cx I2C Instance. 2199 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 2200 */ 2201 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) 2202 { 2203 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); 2204 } 2205 2206 /** 2207 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). 2208 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 2209 * SMBus feature is supported by the I2Cx Instance. 2210 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition 2211 or an Address Matched is received. 2212 * This bit has no effect when RELOAD bit is set. 2213 * This bit has no effect in device mode when SBC bit is not set. 2214 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare 2215 * @param I2Cx I2C Instance. 2216 * @retval None 2217 */ 2218 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) 2219 { 2220 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); 2221 } 2222 2223 /** 2224 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. 2225 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 2226 * SMBus feature is supported by the I2Cx Instance. 2227 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare 2228 * @param I2Cx I2C Instance. 2229 * @retval State of bit (1 or 0). 2230 */ 2231 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) 2232 { 2233 return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); 2234 } 2235 2236 /** 2237 * @brief Get the SMBus Packet Error byte calculated. 2238 * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 2239 * SMBus feature is supported by the I2Cx Instance. 2240 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC 2241 * @param I2Cx I2C Instance. 2242 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 2243 */ 2244 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) 2245 { 2246 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); 2247 } 2248 2249 /** 2250 * @brief Read Receive Data register. 2251 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 2252 * @param I2Cx I2C Instance. 2253 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 2254 */ 2255 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) 2256 { 2257 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); 2258 } 2259 2260 /** 2261 * @brief Write in Transmit Data Register . 2262 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 2263 * @param I2Cx I2C Instance. 2264 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 2265 * @retval None 2266 */ 2267 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) 2268 { 2269 WRITE_REG(I2Cx->TXDR, Data); 2270 } 2271 2272 /** 2273 * @} 2274 */ 2275 2276 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 2277 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions 2278 * @ingroup RTEMSBSPsARMSTM32H7 2279 * @{ 2280 */ 2281 2282 ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); 2283 ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); 2284 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); 2285 2286 2287 /** 2288 * @} 2289 */ 2290 #endif /* USE_FULL_LL_DRIVER */ 2291 2292 /** 2293 * @} 2294 */ 2295 2296 /** 2297 * @} 2298 */ 2299 2300 #endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 */ 2301 2302 /** 2303 * @} 2304 */ 2305 2306 #ifdef __cplusplus 2307 } 2308 #endif 2309 2310 #endif /* STM32H7xx_LL_I2C_H */
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