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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_hsem.h 0004 * @author MCD Application Team 0005 * @brief Header file of HSEM LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_HSEM_H 0021 #define STM32H7xx_LL_HSEM_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined(HSEM) 0035 0036 /** @defgroup HSEM_LL HSEM 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /* Private constants ---------------------------------------------------------*/ 0044 /* Private macros ------------------------------------------------------------*/ 0045 0046 /* Exported types ------------------------------------------------------------*/ 0047 /* Exported constants --------------------------------------------------------*/ 0048 0049 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants 0050 * @ingroup RTEMSBSPsARMSTM32H7 0051 * @{ 0052 */ 0053 0054 /** @defgroup HSEM_LL_EC_COREID COREID Defines 0055 * @ingroup RTEMSBSPsARMSTM32H7 0056 * @{ 0057 */ 0058 #define LL_HSEM_COREID_NONE 0U 0059 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 0060 #if defined(DUAL_CORE) 0061 #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 0062 #endif /* DUAL_CORE */ 0063 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT 0064 /** 0065 * @} 0066 */ 0067 0068 0069 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines 0070 * @ingroup RTEMSBSPsARMSTM32H7 0071 * @brief Flags defines which can be used with LL_HSEM_ReadReg function 0072 * @{ 0073 */ 0074 0075 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0 0076 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1 0077 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2 0078 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3 0079 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4 0080 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5 0081 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6 0082 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7 0083 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8 0084 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9 0085 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10 0086 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11 0087 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12 0088 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 0089 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 0090 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 0091 #if (HSEM_SEMID_MAX == 15) 0092 #define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU 0093 #else /* HSEM_SEMID_MAX == 31 */ 0094 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 0095 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 0096 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 0097 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 0098 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 0099 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 0100 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 0101 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 0102 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 0103 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 0104 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 0105 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 0106 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 0107 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 0108 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 0109 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 0110 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU 0111 #endif /* HSEM_SEMID_MAX == 15 */ 0112 /** 0113 * @} 0114 */ 0115 0116 /** 0117 * @} 0118 */ 0119 0120 /* Exported macro ------------------------------------------------------------*/ 0121 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros 0122 * @ingroup RTEMSBSPsARMSTM32H7 0123 * @{ 0124 */ 0125 0126 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros 0127 * @ingroup RTEMSBSPsARMSTM32H7 0128 * @{ 0129 */ 0130 0131 /** 0132 * @brief Write a value in HSEM register 0133 * @param __INSTANCE__ HSEM Instance 0134 * @param __REG__ Register to be written 0135 * @param __VALUE__ Value to be written in the register 0136 * @retval None 0137 */ 0138 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0139 0140 /** 0141 * @brief Read a value in HSEM register 0142 * @param __INSTANCE__ HSEM Instance 0143 * @param __REG__ Register to be read 0144 * @retval Register value 0145 */ 0146 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0147 /** 0148 * @} 0149 */ 0150 0151 /** 0152 * @} 0153 */ 0154 0155 /* Exported functions --------------------------------------------------------*/ 0156 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions 0157 * @ingroup RTEMSBSPsARMSTM32H7 0158 * @{ 0159 */ 0160 0161 /** @defgroup HSEM_LL_EF_Data_Management Data_Management 0162 * @ingroup RTEMSBSPsARMSTM32H7 0163 * @{ 0164 */ 0165 0166 0167 /** 0168 * @brief Return 1 if the semaphore is locked, else return 0. 0169 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked 0170 * @param HSEMx HSEM Instance. 0171 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0172 * @retval State of bit (1 or 0). 0173 */ 0174 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 0175 { 0176 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); 0177 } 0178 0179 /** 0180 * @brief Get core id. 0181 * @rmtoll R COREID LL_HSEM_GetCoreId 0182 * @param HSEMx HSEM Instance. 0183 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0184 * @retval Returned value can be one of the following values: 0185 * @arg @ref LL_HSEM_COREID_NONE 0186 * @arg @ref LL_HSEM_COREID_CPU1 0187 * @arg @ref LL_HSEM_COREID_CPU2 0188 */ 0189 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 0190 { 0191 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); 0192 } 0193 0194 /** 0195 * @brief Get process id. 0196 * @rmtoll R PROCID LL_HSEM_GetProcessId 0197 * @param HSEMx HSEM Instance. 0198 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0199 * @retval Process number. Value between Min_Data=0 and Max_Data=255 0200 */ 0201 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 0202 { 0203 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); 0204 } 0205 0206 /** 0207 * @brief Get the lock by writing in R register. 0208 * @note The R register has to be read to determined if the lock is taken. 0209 * @rmtoll R LOCK LL_HSEM_SetLock 0210 * @rmtoll R COREID LL_HSEM_SetLock 0211 * @rmtoll R PROCID LL_HSEM_SetLock 0212 * @param HSEMx HSEM Instance. 0213 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0214 * @param process Process id. Value between Min_Data=0 and Max_Data=255 0215 * @retval None 0216 */ 0217 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 0218 { 0219 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); 0220 } 0221 0222 /** 0223 * @brief Get the lock with 2-step lock. 0224 * @rmtoll R LOCK LL_HSEM_2StepLock 0225 * @rmtoll R COREID LL_HSEM_2StepLock 0226 * @rmtoll R PROCID LL_HSEM_2StepLock 0227 * @param HSEMx HSEM Instance. 0228 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0229 * @param process Process id. Value between Min_Data=0 and Max_Data=255 0230 * @retval 1 lock fail, 0 lock successful or already locked by same process and core 0231 */ 0232 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 0233 { 0234 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); 0235 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL); 0236 } 0237 0238 /** 0239 * @brief Get the lock with 1-step lock. 0240 * @rmtoll RLR LOCK LL_HSEM_1StepLock 0241 * @rmtoll RLR COREID LL_HSEM_1StepLock 0242 * @rmtoll RLR PROCID LL_HSEM_1StepLock 0243 * @param HSEMx HSEM Instance. 0244 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0245 * @retval 1 lock fail, 0 lock successful or already locked by same core 0246 */ 0247 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 0248 { 0249 return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); 0250 } 0251 0252 /** 0253 * @brief Release the lock of the semaphore. 0254 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. 0255 * @rmtoll R LOCK LL_HSEM_ReleaseLock 0256 * @param HSEMx HSEM Instance. 0257 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0258 * @param process Process number. Value between Min_Data=0 and Max_Data=255 0259 * @retval None 0260 */ 0261 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) 0262 { 0263 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process)); 0264 } 0265 0266 /** 0267 * @brief Get the lock status of the semaphore. 0268 * @rmtoll R LOCK LL_HSEM_GetStatus 0269 * @param HSEMx HSEM Instance. 0270 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 0271 * @retval 0 semaphore is free, 1 semaphore is locked */ 0272 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) 0273 { 0274 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); 0275 } 0276 0277 /** 0278 * @brief Set the key. 0279 * @rmtoll KEYR KEY LL_HSEM_SetKey 0280 * @param HSEMx HSEM Instance. 0281 * @param key Key value. 0282 * @retval None 0283 */ 0284 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) 0285 { 0286 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); 0287 } 0288 0289 /** 0290 * @brief Get the key. 0291 * @rmtoll KEYR KEY LL_HSEM_GetKey 0292 * @param HSEMx HSEM Instance. 0293 * @retval key to unlock all semaphore from the same core 0294 */ 0295 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) 0296 { 0297 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); 0298 } 0299 0300 /** 0301 * @brief Release all semaphore with the same core id. 0302 * @rmtoll CR KEY LL_HSEM_ResetAllLock 0303 * @rmtoll CR SEC LL_HSEM_ResetAllLock 0304 * @rmtoll CR PRIV LL_HSEM_ResetAllLock 0305 * @param HSEMx HSEM Instance. 0306 * @param key Key value. 0307 * @param core This parameter can be one of the following values: 0308 * @arg @ref LL_HSEM_COREID_CPU1 0309 * @arg @ref LL_HSEM_COREID_CPU2 0310 * @retval None 0311 */ 0312 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) 0313 { 0314 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); 0315 } 0316 0317 /** 0318 * @} 0319 */ 0320 0321 /** @defgroup HSEM_LL_EF_IT_Management IT_Management 0322 * @ingroup RTEMSBSPsARMSTM32H7 0323 * @{ 0324 */ 0325 0326 /** 0327 * @brief Enable interrupt. 0328 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER 0329 * @param HSEMx HSEM Instance. 0330 * @param SemaphoreMask This parameter can be a combination of the following values: 0331 * @arg @ref LL_HSEM_SEMAPHORE_0 0332 * @arg @ref LL_HSEM_SEMAPHORE_1 0333 * @arg @ref LL_HSEM_SEMAPHORE_2 0334 * @arg @ref LL_HSEM_SEMAPHORE_3 0335 * @arg @ref LL_HSEM_SEMAPHORE_4 0336 * @arg @ref LL_HSEM_SEMAPHORE_5 0337 * @arg @ref LL_HSEM_SEMAPHORE_6 0338 * @arg @ref LL_HSEM_SEMAPHORE_7 0339 * @arg @ref LL_HSEM_SEMAPHORE_8 0340 * @arg @ref LL_HSEM_SEMAPHORE_9 0341 * @arg @ref LL_HSEM_SEMAPHORE_10 0342 * @arg @ref LL_HSEM_SEMAPHORE_11 0343 * @arg @ref LL_HSEM_SEMAPHORE_12 0344 * @arg @ref LL_HSEM_SEMAPHORE_13 0345 * @arg @ref LL_HSEM_SEMAPHORE_14 0346 * @arg @ref LL_HSEM_SEMAPHORE_15 0347 * @arg @ref LL_HSEM_SEMAPHORE_16 0348 * @arg @ref LL_HSEM_SEMAPHORE_17 0349 * @arg @ref LL_HSEM_SEMAPHORE_18 0350 * @arg @ref LL_HSEM_SEMAPHORE_19 0351 * @arg @ref LL_HSEM_SEMAPHORE_20 0352 * @arg @ref LL_HSEM_SEMAPHORE_21 0353 * @arg @ref LL_HSEM_SEMAPHORE_22 0354 * @arg @ref LL_HSEM_SEMAPHORE_23 0355 * @arg @ref LL_HSEM_SEMAPHORE_24 0356 * @arg @ref LL_HSEM_SEMAPHORE_25 0357 * @arg @ref LL_HSEM_SEMAPHORE_26 0358 * @arg @ref LL_HSEM_SEMAPHORE_27 0359 * @arg @ref LL_HSEM_SEMAPHORE_28 0360 * @arg @ref LL_HSEM_SEMAPHORE_29 0361 * @arg @ref LL_HSEM_SEMAPHORE_30 0362 * @arg @ref LL_HSEM_SEMAPHORE_31 0363 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0364 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0365 * depends on devices. 0366 * @retval None 0367 */ 0368 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0369 { 0370 SET_BIT(HSEMx->C1IER, SemaphoreMask); 0371 } 0372 0373 /** 0374 * @brief Disable interrupt. 0375 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER 0376 * @param HSEMx HSEM Instance. 0377 * @param SemaphoreMask This parameter can be a combination of the following values: 0378 * @arg @ref LL_HSEM_SEMAPHORE_0 0379 * @arg @ref LL_HSEM_SEMAPHORE_1 0380 * @arg @ref LL_HSEM_SEMAPHORE_2 0381 * @arg @ref LL_HSEM_SEMAPHORE_3 0382 * @arg @ref LL_HSEM_SEMAPHORE_4 0383 * @arg @ref LL_HSEM_SEMAPHORE_5 0384 * @arg @ref LL_HSEM_SEMAPHORE_6 0385 * @arg @ref LL_HSEM_SEMAPHORE_7 0386 * @arg @ref LL_HSEM_SEMAPHORE_8 0387 * @arg @ref LL_HSEM_SEMAPHORE_9 0388 * @arg @ref LL_HSEM_SEMAPHORE_10 0389 * @arg @ref LL_HSEM_SEMAPHORE_11 0390 * @arg @ref LL_HSEM_SEMAPHORE_12 0391 * @arg @ref LL_HSEM_SEMAPHORE_13 0392 * @arg @ref LL_HSEM_SEMAPHORE_14 0393 * @arg @ref LL_HSEM_SEMAPHORE_15 0394 * @arg @ref LL_HSEM_SEMAPHORE_16 0395 * @arg @ref LL_HSEM_SEMAPHORE_17 0396 * @arg @ref LL_HSEM_SEMAPHORE_18 0397 * @arg @ref LL_HSEM_SEMAPHORE_19 0398 * @arg @ref LL_HSEM_SEMAPHORE_20 0399 * @arg @ref LL_HSEM_SEMAPHORE_21 0400 * @arg @ref LL_HSEM_SEMAPHORE_22 0401 * @arg @ref LL_HSEM_SEMAPHORE_23 0402 * @arg @ref LL_HSEM_SEMAPHORE_24 0403 * @arg @ref LL_HSEM_SEMAPHORE_25 0404 * @arg @ref LL_HSEM_SEMAPHORE_26 0405 * @arg @ref LL_HSEM_SEMAPHORE_27 0406 * @arg @ref LL_HSEM_SEMAPHORE_28 0407 * @arg @ref LL_HSEM_SEMAPHORE_29 0408 * @arg @ref LL_HSEM_SEMAPHORE_30 0409 * @arg @ref LL_HSEM_SEMAPHORE_31 0410 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0411 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0412 * depends on devices. 0413 * @retval None 0414 */ 0415 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0416 { 0417 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask); 0418 } 0419 0420 /** 0421 * @brief Check if interrupt is enabled. 0422 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER 0423 * @param HSEMx HSEM Instance. 0424 * @param SemaphoreMask This parameter can be a combination of the following values: 0425 * @arg @ref LL_HSEM_SEMAPHORE_0 0426 * @arg @ref LL_HSEM_SEMAPHORE_1 0427 * @arg @ref LL_HSEM_SEMAPHORE_2 0428 * @arg @ref LL_HSEM_SEMAPHORE_3 0429 * @arg @ref LL_HSEM_SEMAPHORE_4 0430 * @arg @ref LL_HSEM_SEMAPHORE_5 0431 * @arg @ref LL_HSEM_SEMAPHORE_6 0432 * @arg @ref LL_HSEM_SEMAPHORE_7 0433 * @arg @ref LL_HSEM_SEMAPHORE_8 0434 * @arg @ref LL_HSEM_SEMAPHORE_9 0435 * @arg @ref LL_HSEM_SEMAPHORE_10 0436 * @arg @ref LL_HSEM_SEMAPHORE_11 0437 * @arg @ref LL_HSEM_SEMAPHORE_12 0438 * @arg @ref LL_HSEM_SEMAPHORE_13 0439 * @arg @ref LL_HSEM_SEMAPHORE_14 0440 * @arg @ref LL_HSEM_SEMAPHORE_15 0441 * @arg @ref LL_HSEM_SEMAPHORE_16 0442 * @arg @ref LL_HSEM_SEMAPHORE_17 0443 * @arg @ref LL_HSEM_SEMAPHORE_18 0444 * @arg @ref LL_HSEM_SEMAPHORE_19 0445 * @arg @ref LL_HSEM_SEMAPHORE_20 0446 * @arg @ref LL_HSEM_SEMAPHORE_21 0447 * @arg @ref LL_HSEM_SEMAPHORE_22 0448 * @arg @ref LL_HSEM_SEMAPHORE_23 0449 * @arg @ref LL_HSEM_SEMAPHORE_24 0450 * @arg @ref LL_HSEM_SEMAPHORE_25 0451 * @arg @ref LL_HSEM_SEMAPHORE_26 0452 * @arg @ref LL_HSEM_SEMAPHORE_27 0453 * @arg @ref LL_HSEM_SEMAPHORE_28 0454 * @arg @ref LL_HSEM_SEMAPHORE_29 0455 * @arg @ref LL_HSEM_SEMAPHORE_30 0456 * @arg @ref LL_HSEM_SEMAPHORE_31 0457 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0458 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0459 * depends on devices. 0460 * @retval State of bit (1 or 0). 0461 */ 0462 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0463 { 0464 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0465 } 0466 0467 #if defined(DUAL_CORE) 0468 /** 0469 * @brief Enable interrupt. 0470 * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER 0471 * @param HSEMx HSEM Instance. 0472 * @param SemaphoreMask This parameter can be a combination of the following values: 0473 * @arg @ref LL_HSEM_SEMAPHORE_0 0474 * @arg @ref LL_HSEM_SEMAPHORE_1 0475 * @arg @ref LL_HSEM_SEMAPHORE_2 0476 * @arg @ref LL_HSEM_SEMAPHORE_3 0477 * @arg @ref LL_HSEM_SEMAPHORE_4 0478 * @arg @ref LL_HSEM_SEMAPHORE_5 0479 * @arg @ref LL_HSEM_SEMAPHORE_6 0480 * @arg @ref LL_HSEM_SEMAPHORE_7 0481 * @arg @ref LL_HSEM_SEMAPHORE_8 0482 * @arg @ref LL_HSEM_SEMAPHORE_9 0483 * @arg @ref LL_HSEM_SEMAPHORE_10 0484 * @arg @ref LL_HSEM_SEMAPHORE_11 0485 * @arg @ref LL_HSEM_SEMAPHORE_12 0486 * @arg @ref LL_HSEM_SEMAPHORE_13 0487 * @arg @ref LL_HSEM_SEMAPHORE_14 0488 * @arg @ref LL_HSEM_SEMAPHORE_15 0489 * @arg @ref LL_HSEM_SEMAPHORE_16 0490 * @arg @ref LL_HSEM_SEMAPHORE_17 0491 * @arg @ref LL_HSEM_SEMAPHORE_18 0492 * @arg @ref LL_HSEM_SEMAPHORE_19 0493 * @arg @ref LL_HSEM_SEMAPHORE_20 0494 * @arg @ref LL_HSEM_SEMAPHORE_21 0495 * @arg @ref LL_HSEM_SEMAPHORE_22 0496 * @arg @ref LL_HSEM_SEMAPHORE_23 0497 * @arg @ref LL_HSEM_SEMAPHORE_24 0498 * @arg @ref LL_HSEM_SEMAPHORE_25 0499 * @arg @ref LL_HSEM_SEMAPHORE_26 0500 * @arg @ref LL_HSEM_SEMAPHORE_27 0501 * @arg @ref LL_HSEM_SEMAPHORE_28 0502 * @arg @ref LL_HSEM_SEMAPHORE_29 0503 * @arg @ref LL_HSEM_SEMAPHORE_30 0504 * @arg @ref LL_HSEM_SEMAPHORE_31 0505 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0506 * @retval None 0507 */ 0508 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0509 { 0510 SET_BIT(HSEMx->C2IER, SemaphoreMask); 0511 } 0512 0513 /** 0514 * @brief Disable interrupt. 0515 * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER 0516 * @param HSEMx HSEM Instance. 0517 * @param SemaphoreMask This parameter can be a combination of the following values: 0518 * @arg @ref LL_HSEM_SEMAPHORE_0 0519 * @arg @ref LL_HSEM_SEMAPHORE_1 0520 * @arg @ref LL_HSEM_SEMAPHORE_2 0521 * @arg @ref LL_HSEM_SEMAPHORE_3 0522 * @arg @ref LL_HSEM_SEMAPHORE_4 0523 * @arg @ref LL_HSEM_SEMAPHORE_5 0524 * @arg @ref LL_HSEM_SEMAPHORE_6 0525 * @arg @ref LL_HSEM_SEMAPHORE_7 0526 * @arg @ref LL_HSEM_SEMAPHORE_8 0527 * @arg @ref LL_HSEM_SEMAPHORE_9 0528 * @arg @ref LL_HSEM_SEMAPHORE_10 0529 * @arg @ref LL_HSEM_SEMAPHORE_11 0530 * @arg @ref LL_HSEM_SEMAPHORE_12 0531 * @arg @ref LL_HSEM_SEMAPHORE_13 0532 * @arg @ref LL_HSEM_SEMAPHORE_14 0533 * @arg @ref LL_HSEM_SEMAPHORE_15 0534 * @arg @ref LL_HSEM_SEMAPHORE_16 0535 * @arg @ref LL_HSEM_SEMAPHORE_17 0536 * @arg @ref LL_HSEM_SEMAPHORE_18 0537 * @arg @ref LL_HSEM_SEMAPHORE_19 0538 * @arg @ref LL_HSEM_SEMAPHORE_20 0539 * @arg @ref LL_HSEM_SEMAPHORE_21 0540 * @arg @ref LL_HSEM_SEMAPHORE_22 0541 * @arg @ref LL_HSEM_SEMAPHORE_23 0542 * @arg @ref LL_HSEM_SEMAPHORE_24 0543 * @arg @ref LL_HSEM_SEMAPHORE_25 0544 * @arg @ref LL_HSEM_SEMAPHORE_26 0545 * @arg @ref LL_HSEM_SEMAPHORE_27 0546 * @arg @ref LL_HSEM_SEMAPHORE_28 0547 * @arg @ref LL_HSEM_SEMAPHORE_29 0548 * @arg @ref LL_HSEM_SEMAPHORE_30 0549 * @arg @ref LL_HSEM_SEMAPHORE_31 0550 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0551 * @retval None 0552 */ 0553 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0554 { 0555 CLEAR_BIT(HSEMx->C2IER, SemaphoreMask); 0556 } 0557 0558 /** 0559 * @brief Check if interrupt is enabled. 0560 * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER 0561 * @param HSEMx HSEM Instance. 0562 * @param SemaphoreMask This parameter can be a combination of the following values: 0563 * @arg @ref LL_HSEM_SEMAPHORE_0 0564 * @arg @ref LL_HSEM_SEMAPHORE_1 0565 * @arg @ref LL_HSEM_SEMAPHORE_2 0566 * @arg @ref LL_HSEM_SEMAPHORE_3 0567 * @arg @ref LL_HSEM_SEMAPHORE_4 0568 * @arg @ref LL_HSEM_SEMAPHORE_5 0569 * @arg @ref LL_HSEM_SEMAPHORE_6 0570 * @arg @ref LL_HSEM_SEMAPHORE_7 0571 * @arg @ref LL_HSEM_SEMAPHORE_8 0572 * @arg @ref LL_HSEM_SEMAPHORE_9 0573 * @arg @ref LL_HSEM_SEMAPHORE_10 0574 * @arg @ref LL_HSEM_SEMAPHORE_11 0575 * @arg @ref LL_HSEM_SEMAPHORE_12 0576 * @arg @ref LL_HSEM_SEMAPHORE_13 0577 * @arg @ref LL_HSEM_SEMAPHORE_14 0578 * @arg @ref LL_HSEM_SEMAPHORE_15 0579 * @arg @ref LL_HSEM_SEMAPHORE_16 0580 * @arg @ref LL_HSEM_SEMAPHORE_17 0581 * @arg @ref LL_HSEM_SEMAPHORE_18 0582 * @arg @ref LL_HSEM_SEMAPHORE_19 0583 * @arg @ref LL_HSEM_SEMAPHORE_20 0584 * @arg @ref LL_HSEM_SEMAPHORE_21 0585 * @arg @ref LL_HSEM_SEMAPHORE_22 0586 * @arg @ref LL_HSEM_SEMAPHORE_23 0587 * @arg @ref LL_HSEM_SEMAPHORE_24 0588 * @arg @ref LL_HSEM_SEMAPHORE_25 0589 * @arg @ref LL_HSEM_SEMAPHORE_26 0590 * @arg @ref LL_HSEM_SEMAPHORE_27 0591 * @arg @ref LL_HSEM_SEMAPHORE_28 0592 * @arg @ref LL_HSEM_SEMAPHORE_29 0593 * @arg @ref LL_HSEM_SEMAPHORE_30 0594 * @arg @ref LL_HSEM_SEMAPHORE_31 0595 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0596 * @retval State of bit (1 or 0). 0597 */ 0598 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0599 { 0600 return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0601 } 0602 #endif /* DUAL_CORE */ 0603 0604 /** 0605 * @} 0606 */ 0607 0608 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management 0609 * @ingroup RTEMSBSPsARMSTM32H7 0610 * @{ 0611 */ 0612 0613 /** 0614 * @brief Clear interrupt status. 0615 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR 0616 * @param HSEMx HSEM Instance. 0617 * @param SemaphoreMask This parameter can be a combination of the following values: 0618 * @arg @ref LL_HSEM_SEMAPHORE_0 0619 * @arg @ref LL_HSEM_SEMAPHORE_1 0620 * @arg @ref LL_HSEM_SEMAPHORE_2 0621 * @arg @ref LL_HSEM_SEMAPHORE_3 0622 * @arg @ref LL_HSEM_SEMAPHORE_4 0623 * @arg @ref LL_HSEM_SEMAPHORE_5 0624 * @arg @ref LL_HSEM_SEMAPHORE_6 0625 * @arg @ref LL_HSEM_SEMAPHORE_7 0626 * @arg @ref LL_HSEM_SEMAPHORE_8 0627 * @arg @ref LL_HSEM_SEMAPHORE_9 0628 * @arg @ref LL_HSEM_SEMAPHORE_10 0629 * @arg @ref LL_HSEM_SEMAPHORE_11 0630 * @arg @ref LL_HSEM_SEMAPHORE_12 0631 * @arg @ref LL_HSEM_SEMAPHORE_13 0632 * @arg @ref LL_HSEM_SEMAPHORE_14 0633 * @arg @ref LL_HSEM_SEMAPHORE_15 0634 * @arg @ref LL_HSEM_SEMAPHORE_16 0635 * @arg @ref LL_HSEM_SEMAPHORE_17 0636 * @arg @ref LL_HSEM_SEMAPHORE_18 0637 * @arg @ref LL_HSEM_SEMAPHORE_19 0638 * @arg @ref LL_HSEM_SEMAPHORE_20 0639 * @arg @ref LL_HSEM_SEMAPHORE_21 0640 * @arg @ref LL_HSEM_SEMAPHORE_22 0641 * @arg @ref LL_HSEM_SEMAPHORE_23 0642 * @arg @ref LL_HSEM_SEMAPHORE_24 0643 * @arg @ref LL_HSEM_SEMAPHORE_25 0644 * @arg @ref LL_HSEM_SEMAPHORE_26 0645 * @arg @ref LL_HSEM_SEMAPHORE_27 0646 * @arg @ref LL_HSEM_SEMAPHORE_28 0647 * @arg @ref LL_HSEM_SEMAPHORE_29 0648 * @arg @ref LL_HSEM_SEMAPHORE_30 0649 * @arg @ref LL_HSEM_SEMAPHORE_31 0650 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0651 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0652 * depends on devices. 0653 * @retval None 0654 */ 0655 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0656 { 0657 WRITE_REG(HSEMx->C1ICR, SemaphoreMask); 0658 } 0659 0660 /** 0661 * @brief Get interrupt status from ISR register. 0662 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR 0663 * @param HSEMx HSEM Instance. 0664 * @param SemaphoreMask This parameter can be a combination of the following values: 0665 * @arg @ref LL_HSEM_SEMAPHORE_0 0666 * @arg @ref LL_HSEM_SEMAPHORE_1 0667 * @arg @ref LL_HSEM_SEMAPHORE_2 0668 * @arg @ref LL_HSEM_SEMAPHORE_3 0669 * @arg @ref LL_HSEM_SEMAPHORE_4 0670 * @arg @ref LL_HSEM_SEMAPHORE_5 0671 * @arg @ref LL_HSEM_SEMAPHORE_6 0672 * @arg @ref LL_HSEM_SEMAPHORE_7 0673 * @arg @ref LL_HSEM_SEMAPHORE_8 0674 * @arg @ref LL_HSEM_SEMAPHORE_9 0675 * @arg @ref LL_HSEM_SEMAPHORE_10 0676 * @arg @ref LL_HSEM_SEMAPHORE_11 0677 * @arg @ref LL_HSEM_SEMAPHORE_12 0678 * @arg @ref LL_HSEM_SEMAPHORE_13 0679 * @arg @ref LL_HSEM_SEMAPHORE_14 0680 * @arg @ref LL_HSEM_SEMAPHORE_15 0681 * @arg @ref LL_HSEM_SEMAPHORE_16 0682 * @arg @ref LL_HSEM_SEMAPHORE_17 0683 * @arg @ref LL_HSEM_SEMAPHORE_18 0684 * @arg @ref LL_HSEM_SEMAPHORE_19 0685 * @arg @ref LL_HSEM_SEMAPHORE_20 0686 * @arg @ref LL_HSEM_SEMAPHORE_21 0687 * @arg @ref LL_HSEM_SEMAPHORE_22 0688 * @arg @ref LL_HSEM_SEMAPHORE_23 0689 * @arg @ref LL_HSEM_SEMAPHORE_24 0690 * @arg @ref LL_HSEM_SEMAPHORE_25 0691 * @arg @ref LL_HSEM_SEMAPHORE_26 0692 * @arg @ref LL_HSEM_SEMAPHORE_27 0693 * @arg @ref LL_HSEM_SEMAPHORE_28 0694 * @arg @ref LL_HSEM_SEMAPHORE_29 0695 * @arg @ref LL_HSEM_SEMAPHORE_30 0696 * @arg @ref LL_HSEM_SEMAPHORE_31 0697 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0698 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0699 * depends on devices. 0700 * @retval State of bit (1 or 0). 0701 */ 0702 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0703 { 0704 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0705 } 0706 0707 /** 0708 * @brief Get interrupt status from MISR register. 0709 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR 0710 * @param HSEMx HSEM Instance. 0711 * @param SemaphoreMask This parameter can be a combination of the following values: 0712 * @arg @ref LL_HSEM_SEMAPHORE_0 0713 * @arg @ref LL_HSEM_SEMAPHORE_1 0714 * @arg @ref LL_HSEM_SEMAPHORE_2 0715 * @arg @ref LL_HSEM_SEMAPHORE_3 0716 * @arg @ref LL_HSEM_SEMAPHORE_4 0717 * @arg @ref LL_HSEM_SEMAPHORE_5 0718 * @arg @ref LL_HSEM_SEMAPHORE_6 0719 * @arg @ref LL_HSEM_SEMAPHORE_7 0720 * @arg @ref LL_HSEM_SEMAPHORE_8 0721 * @arg @ref LL_HSEM_SEMAPHORE_9 0722 * @arg @ref LL_HSEM_SEMAPHORE_10 0723 * @arg @ref LL_HSEM_SEMAPHORE_11 0724 * @arg @ref LL_HSEM_SEMAPHORE_12 0725 * @arg @ref LL_HSEM_SEMAPHORE_13 0726 * @arg @ref LL_HSEM_SEMAPHORE_14 0727 * @arg @ref LL_HSEM_SEMAPHORE_15 0728 * @arg @ref LL_HSEM_SEMAPHORE_16 0729 * @arg @ref LL_HSEM_SEMAPHORE_17 0730 * @arg @ref LL_HSEM_SEMAPHORE_18 0731 * @arg @ref LL_HSEM_SEMAPHORE_19 0732 * @arg @ref LL_HSEM_SEMAPHORE_20 0733 * @arg @ref LL_HSEM_SEMAPHORE_21 0734 * @arg @ref LL_HSEM_SEMAPHORE_22 0735 * @arg @ref LL_HSEM_SEMAPHORE_23 0736 * @arg @ref LL_HSEM_SEMAPHORE_24 0737 * @arg @ref LL_HSEM_SEMAPHORE_25 0738 * @arg @ref LL_HSEM_SEMAPHORE_26 0739 * @arg @ref LL_HSEM_SEMAPHORE_27 0740 * @arg @ref LL_HSEM_SEMAPHORE_28 0741 * @arg @ref LL_HSEM_SEMAPHORE_29 0742 * @arg @ref LL_HSEM_SEMAPHORE_30 0743 * @arg @ref LL_HSEM_SEMAPHORE_31 0744 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0745 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 0746 * depends on devices. 0747 * @retval State of bit (1 or 0). 0748 */ 0749 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0750 { 0751 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0752 } 0753 0754 #if defined(DUAL_CORE) 0755 /** 0756 * @brief Clear interrupt status. 0757 * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR 0758 * @param HSEMx HSEM Instance. 0759 * @param SemaphoreMask This parameter can be a combination of the following values: 0760 * @arg @ref LL_HSEM_SEMAPHORE_0 0761 * @arg @ref LL_HSEM_SEMAPHORE_1 0762 * @arg @ref LL_HSEM_SEMAPHORE_2 0763 * @arg @ref LL_HSEM_SEMAPHORE_3 0764 * @arg @ref LL_HSEM_SEMAPHORE_4 0765 * @arg @ref LL_HSEM_SEMAPHORE_5 0766 * @arg @ref LL_HSEM_SEMAPHORE_6 0767 * @arg @ref LL_HSEM_SEMAPHORE_7 0768 * @arg @ref LL_HSEM_SEMAPHORE_8 0769 * @arg @ref LL_HSEM_SEMAPHORE_9 0770 * @arg @ref LL_HSEM_SEMAPHORE_10 0771 * @arg @ref LL_HSEM_SEMAPHORE_11 0772 * @arg @ref LL_HSEM_SEMAPHORE_12 0773 * @arg @ref LL_HSEM_SEMAPHORE_13 0774 * @arg @ref LL_HSEM_SEMAPHORE_14 0775 * @arg @ref LL_HSEM_SEMAPHORE_15 0776 * @arg @ref LL_HSEM_SEMAPHORE_16 0777 * @arg @ref LL_HSEM_SEMAPHORE_17 0778 * @arg @ref LL_HSEM_SEMAPHORE_18 0779 * @arg @ref LL_HSEM_SEMAPHORE_19 0780 * @arg @ref LL_HSEM_SEMAPHORE_20 0781 * @arg @ref LL_HSEM_SEMAPHORE_21 0782 * @arg @ref LL_HSEM_SEMAPHORE_22 0783 * @arg @ref LL_HSEM_SEMAPHORE_23 0784 * @arg @ref LL_HSEM_SEMAPHORE_24 0785 * @arg @ref LL_HSEM_SEMAPHORE_25 0786 * @arg @ref LL_HSEM_SEMAPHORE_26 0787 * @arg @ref LL_HSEM_SEMAPHORE_27 0788 * @arg @ref LL_HSEM_SEMAPHORE_28 0789 * @arg @ref LL_HSEM_SEMAPHORE_29 0790 * @arg @ref LL_HSEM_SEMAPHORE_30 0791 * @arg @ref LL_HSEM_SEMAPHORE_31 0792 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0793 * @retval None 0794 */ 0795 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0796 { 0797 WRITE_REG(HSEMx->C2ICR, SemaphoreMask); 0798 } 0799 0800 /** 0801 * @brief Get interrupt status from ISR register. 0802 * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR 0803 * @param HSEMx HSEM Instance. 0804 * @param SemaphoreMask This parameter can be a combination of the following values: 0805 * @arg @ref LL_HSEM_SEMAPHORE_0 0806 * @arg @ref LL_HSEM_SEMAPHORE_1 0807 * @arg @ref LL_HSEM_SEMAPHORE_2 0808 * @arg @ref LL_HSEM_SEMAPHORE_3 0809 * @arg @ref LL_HSEM_SEMAPHORE_4 0810 * @arg @ref LL_HSEM_SEMAPHORE_5 0811 * @arg @ref LL_HSEM_SEMAPHORE_6 0812 * @arg @ref LL_HSEM_SEMAPHORE_7 0813 * @arg @ref LL_HSEM_SEMAPHORE_8 0814 * @arg @ref LL_HSEM_SEMAPHORE_9 0815 * @arg @ref LL_HSEM_SEMAPHORE_10 0816 * @arg @ref LL_HSEM_SEMAPHORE_11 0817 * @arg @ref LL_HSEM_SEMAPHORE_12 0818 * @arg @ref LL_HSEM_SEMAPHORE_13 0819 * @arg @ref LL_HSEM_SEMAPHORE_14 0820 * @arg @ref LL_HSEM_SEMAPHORE_15 0821 * @arg @ref LL_HSEM_SEMAPHORE_16 0822 * @arg @ref LL_HSEM_SEMAPHORE_17 0823 * @arg @ref LL_HSEM_SEMAPHORE_18 0824 * @arg @ref LL_HSEM_SEMAPHORE_19 0825 * @arg @ref LL_HSEM_SEMAPHORE_20 0826 * @arg @ref LL_HSEM_SEMAPHORE_21 0827 * @arg @ref LL_HSEM_SEMAPHORE_22 0828 * @arg @ref LL_HSEM_SEMAPHORE_23 0829 * @arg @ref LL_HSEM_SEMAPHORE_24 0830 * @arg @ref LL_HSEM_SEMAPHORE_25 0831 * @arg @ref LL_HSEM_SEMAPHORE_26 0832 * @arg @ref LL_HSEM_SEMAPHORE_27 0833 * @arg @ref LL_HSEM_SEMAPHORE_28 0834 * @arg @ref LL_HSEM_SEMAPHORE_29 0835 * @arg @ref LL_HSEM_SEMAPHORE_30 0836 * @arg @ref LL_HSEM_SEMAPHORE_31 0837 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0838 * @retval State of bit (1 or 0). 0839 */ 0840 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0841 { 0842 return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0843 } 0844 0845 /** 0846 * @brief Get interrupt status from MISR register. 0847 * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR 0848 * @param HSEMx HSEM Instance. 0849 * @param SemaphoreMask This parameter can be a combination of the following values: 0850 * @arg @ref LL_HSEM_SEMAPHORE_0 0851 * @arg @ref LL_HSEM_SEMAPHORE_1 0852 * @arg @ref LL_HSEM_SEMAPHORE_2 0853 * @arg @ref LL_HSEM_SEMAPHORE_3 0854 * @arg @ref LL_HSEM_SEMAPHORE_4 0855 * @arg @ref LL_HSEM_SEMAPHORE_5 0856 * @arg @ref LL_HSEM_SEMAPHORE_6 0857 * @arg @ref LL_HSEM_SEMAPHORE_7 0858 * @arg @ref LL_HSEM_SEMAPHORE_8 0859 * @arg @ref LL_HSEM_SEMAPHORE_9 0860 * @arg @ref LL_HSEM_SEMAPHORE_10 0861 * @arg @ref LL_HSEM_SEMAPHORE_11 0862 * @arg @ref LL_HSEM_SEMAPHORE_12 0863 * @arg @ref LL_HSEM_SEMAPHORE_13 0864 * @arg @ref LL_HSEM_SEMAPHORE_14 0865 * @arg @ref LL_HSEM_SEMAPHORE_15 0866 * @arg @ref LL_HSEM_SEMAPHORE_16 0867 * @arg @ref LL_HSEM_SEMAPHORE_17 0868 * @arg @ref LL_HSEM_SEMAPHORE_18 0869 * @arg @ref LL_HSEM_SEMAPHORE_19 0870 * @arg @ref LL_HSEM_SEMAPHORE_20 0871 * @arg @ref LL_HSEM_SEMAPHORE_21 0872 * @arg @ref LL_HSEM_SEMAPHORE_22 0873 * @arg @ref LL_HSEM_SEMAPHORE_23 0874 * @arg @ref LL_HSEM_SEMAPHORE_24 0875 * @arg @ref LL_HSEM_SEMAPHORE_25 0876 * @arg @ref LL_HSEM_SEMAPHORE_26 0877 * @arg @ref LL_HSEM_SEMAPHORE_27 0878 * @arg @ref LL_HSEM_SEMAPHORE_28 0879 * @arg @ref LL_HSEM_SEMAPHORE_29 0880 * @arg @ref LL_HSEM_SEMAPHORE_30 0881 * @arg @ref LL_HSEM_SEMAPHORE_31 0882 * @arg @ref LL_HSEM_SEMAPHORE_ALL 0883 * @retval State of bit (1 or 0). 0884 */ 0885 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) 0886 { 0887 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); 0888 } 0889 #endif /* DUAL_CORE */ 0890 /** 0891 * @} 0892 */ 0893 0894 /** 0895 * @} 0896 */ 0897 0898 /** 0899 * @} 0900 */ 0901 0902 #endif /* defined(HSEM) */ 0903 0904 /** 0905 * @} 0906 */ 0907 0908 #ifdef __cplusplus 0909 } 0910 #endif 0911 0912 #endif /* __STM32H7xx_LL_HSEM_H */
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