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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_hrtim.h 0004 * @author MCD Application Team 0005 * @brief Header file of HRTIM LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_HRTIM_H 0021 #define STM32H7xx_LL_HRTIM_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (HRTIM1) 0035 0036 /** @defgroup HRTIM_LL HRTIM 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables 0044 * @ingroup RTEMSBSPsARMSTM32H7 0045 * @{ 0046 */ 0047 static const uint16_t REG_OFFSET_TAB_TIMER[] = 0048 { 0049 0x00U, /* 0: MASTER */ 0050 0x80U, /* 1: TIMER A */ 0051 0x100U, /* 2: TIMER B */ 0052 0x180U, /* 3: TIMER C */ 0053 0x200U, /* 4: TIMER D */ 0054 0x280U /* 5: TIMER E */ 0055 }; 0056 0057 static const uint8_t REG_OFFSET_TAB_ADCxR[] = 0058 { 0059 0x00U, /* 0: HRTIM_ADC1R */ 0060 0x04U, /* 1: HRTIM_ADC2R */ 0061 0x08U, /* 2: HRTIM_ADC3R */ 0062 0x0CU, /* 3: HRTIM_ADC4R */ 0063 }; 0064 0065 static const uint16_t REG_OFFSET_TAB_SETxR[] = 0066 { 0067 0x00U, /* 0: TA1 */ 0068 0x08U, /* 1: TA2 */ 0069 0x80U, /* 2: TB1 */ 0070 0x88U, /* 3: TB2 */ 0071 0x100U, /* 4: TC1 */ 0072 0x108U, /* 5: TC2 */ 0073 0x180U, /* 6: TD1 */ 0074 0x188U, /* 7: TD2 */ 0075 0x200U, /* 8: TE1 */ 0076 0x208U /* 9: TE2 */ 0077 }; 0078 0079 static const uint16_t REG_OFFSET_TAB_OUTxR[] = 0080 { 0081 0x00U, /* 0: TA1 */ 0082 0x00U, /* 1: TA2 */ 0083 0x80U, /* 2: TB1 */ 0084 0x80U, /* 3: TB2 */ 0085 0x100U, /* 4: TC1 */ 0086 0x100U, /* 5: TC2 */ 0087 0x180U, /* 6: TD1 */ 0088 0x180U, /* 7: TD2 */ 0089 0x200U, /* 8: TE1 */ 0090 0x200U /* 9: TE2 */ 0091 }; 0092 0093 static const uint8_t REG_OFFSET_TAB_EECR[] = 0094 { 0095 0x00U, /* LL_HRTIM_EVENT_1 */ 0096 0x00U, /* LL_HRTIM_EVENT_2 */ 0097 0x00U, /* LL_HRTIM_EVENT_3 */ 0098 0x00U, /* LL_HRTIM_EVENT_4 */ 0099 0x00U, /* LL_HRTIM_EVENT_5 */ 0100 0x04U, /* LL_HRTIM_EVENT_6 */ 0101 0x04U, /* LL_HRTIM_EVENT_7 */ 0102 0x04U, /* LL_HRTIM_EVENT_8 */ 0103 0x04U, /* LL_HRTIM_EVENT_9 */ 0104 0x04U /* LL_HRTIM_EVENT_10 */ 0105 }; 0106 0107 static const uint8_t REG_OFFSET_TAB_FLTINR[] = 0108 { 0109 0x00U, /* LL_HRTIM_FAULT_1 */ 0110 0x00U, /* LL_HRTIM_FAULT_2 */ 0111 0x00U, /* LL_HRTIM_FAULT_3 */ 0112 0x00U, /* LL_HRTIM_FAULT_4 */ 0113 0x04U /* LL_HRTIM_FAULT_5 */ 0114 }; 0115 0116 static const uint32_t REG_MASK_TAB_UPDATETRIG[] = 0117 { 0118 0x20000000U, /* 0: MASTER */ 0119 0x01FE0000U, /* 1: TIMER A */ 0120 0x01FE0000U, /* 2: TIMER B */ 0121 0x01FE0000U, /* 3: TIMER C */ 0122 0x01FE0000U, /* 4: TIMER D */ 0123 0x01FE0000U /* 5: TIMER E */ 0124 }; 0125 0126 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] = 0127 { 0128 12U, /* 0: MASTER */ 0129 0U, /* 1: TIMER A */ 0130 0U, /* 2: TIMER B */ 0131 0U, /* 3: TIMER C */ 0132 0U, /* 4: TIMER D */ 0133 0U /* 5: TIMER E */ 0134 }; 0135 0136 static const uint8_t REG_SHIFT_TAB_EExSRC[] = 0137 { 0138 0U, /* LL_HRTIM_EVENT_1 */ 0139 6U, /* LL_HRTIM_EVENT_2 */ 0140 12U, /* LL_HRTIM_EVENT_3 */ 0141 18U, /* LL_HRTIM_EVENT_4 */ 0142 24U, /* LL_HRTIM_EVENT_5 */ 0143 0U, /* LL_HRTIM_EVENT_6 */ 0144 6U, /* LL_HRTIM_EVENT_7 */ 0145 12U, /* LL_HRTIM_EVENT_8 */ 0146 18U, /* LL_HRTIM_EVENT_9 */ 0147 24U /* LL_HRTIM_EVENT_10 */ 0148 }; 0149 0150 static const uint32_t REG_MASK_TAB_UPDATEGATING[] = 0151 { 0152 HRTIM_MCR_BRSTDMA, /* 0: MASTER */ 0153 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */ 0154 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */ 0155 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */ 0156 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */ 0157 HRTIM_TIMCR_UPDGAT /* 5: TIMER E */ 0158 }; 0159 0160 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] = 0161 { 0162 2U, /* 0: MASTER */ 0163 0U, /* 1: TIMER A */ 0164 0U, /* 2: TIMER B */ 0165 0U, /* 3: TIMER C */ 0166 0U, /* 4: TIMER D */ 0167 0U /* 5: TIMER E */ 0168 }; 0169 0170 static const uint8_t REG_SHIFT_TAB_OUTxR[] = 0171 { 0172 0U, /* 0: TA1 */ 0173 16U, /* 1: TA2 */ 0174 0U, /* 2: TB1 */ 0175 16U, /* 3: TB2 */ 0176 0U, /* 4: TC1 */ 0177 16U, /* 5: TC2 */ 0178 0U, /* 6: TD1 */ 0179 16U, /* 7: TD2 */ 0180 0U, /* 8: TE1 */ 0181 16U /* 9: TE2 */ 0182 }; 0183 0184 static const uint8_t REG_SHIFT_TAB_OxSTAT[] = 0185 { 0186 0U, /* 0: TA1 */ 0187 1U, /* 1: TA2 */ 0188 0U, /* 2: TB1 */ 0189 1U, /* 3: TB2 */ 0190 0U, /* 4: TC1 */ 0191 1U, /* 5: TC2 */ 0192 0U, /* 6: TD1 */ 0193 1U, /* 7: TD2 */ 0194 0U, /* 8: TE1 */ 0195 1U /* 9: TE2 */ 0196 }; 0197 0198 static const uint8_t REG_SHIFT_TAB_FLTxE[] = 0199 { 0200 0U, /* LL_HRTIM_FAULT_1 */ 0201 8U, /* LL_HRTIM_FAULT_2 */ 0202 16U, /* LL_HRTIM_FAULT_3 */ 0203 24U, /* LL_HRTIM_FAULT_4 */ 0204 0U /* LL_HRTIM_FAULT_5 */ 0205 }; 0206 0207 /** 0208 * @} 0209 */ 0210 0211 0212 /* Private constants ---------------------------------------------------------*/ 0213 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants 0214 * @ingroup RTEMSBSPsARMSTM32H7 0215 * @{ 0216 */ 0217 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\ 0218 HRTIM_CR1_TAUDIS |\ 0219 HRTIM_CR1_TBUDIS |\ 0220 HRTIM_CR1_TCUDIS |\ 0221 HRTIM_CR1_TDUDIS |\ 0222 HRTIM_CR1_TEUDIS)) 0223 0224 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\ 0225 HRTIM_CR2_TASWU |\ 0226 HRTIM_CR2_TBSWU |\ 0227 HRTIM_CR2_TCSWU |\ 0228 HRTIM_CR2_TDSWU |\ 0229 HRTIM_CR2_TESWU)) 0230 0231 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\ 0232 HRTIM_CR2_TARST |\ 0233 HRTIM_CR2_TBRST |\ 0234 HRTIM_CR2_TCRST |\ 0235 HRTIM_CR2_TDRST |\ 0236 HRTIM_CR2_TERST)) 0237 0238 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\ 0239 HRTIM_OENR_TA2OEN |\ 0240 HRTIM_OENR_TB1OEN |\ 0241 HRTIM_OENR_TB2OEN |\ 0242 HRTIM_OENR_TC1OEN |\ 0243 HRTIM_OENR_TC2OEN |\ 0244 HRTIM_OENR_TD1OEN |\ 0245 HRTIM_OENR_TD2OEN |\ 0246 HRTIM_OENR_TE1OEN |\ 0247 HRTIM_OENR_TE2OEN)) 0248 0249 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\ 0250 HRTIM_ODISR_TA2ODIS |\ 0251 HRTIM_ODISR_TB1ODIS |\ 0252 HRTIM_ODISR_TB2ODIS |\ 0253 HRTIM_ODISR_TC1ODIS |\ 0254 HRTIM_ODISR_TC2ODIS |\ 0255 HRTIM_ODISR_TD1ODIS |\ 0256 HRTIM_ODISR_TD2ODIS |\ 0257 HRTIM_ODISR_TE1ODIS |\ 0258 HRTIM_ODISR_TE2ODIS)) 0259 0260 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\ 0261 HRTIM_OUTR_IDLM1 |\ 0262 HRTIM_OUTR_IDLES1 |\ 0263 HRTIM_OUTR_FAULT1 |\ 0264 HRTIM_OUTR_CHP1 |\ 0265 HRTIM_OUTR_DIDL1)) 0266 0267 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\ 0268 HRTIM_EECR1_EE1POL |\ 0269 HRTIM_EECR1_EE1SNS |\ 0270 HRTIM_EECR1_EE1FAST)) 0271 0272 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\ 0273 HRTIM_FLTINR1_FLT1SRC)) 0274 0275 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\ 0276 HRTIM_BMCR_BMCLK |\ 0277 HRTIM_BMCR_BMOM)) 0278 0279 /** 0280 * @} 0281 */ 0282 0283 0284 /* Private macros ------------------------------------------------------------*/ 0285 /* Exported types ------------------------------------------------------------*/ 0286 /* Exported constants --------------------------------------------------------*/ 0287 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants 0288 * @ingroup RTEMSBSPsARMSTM32H7 0289 * @{ 0290 */ 0291 0292 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines 0293 * @ingroup RTEMSBSPsARMSTM32H7 0294 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function 0295 * @{ 0296 */ 0297 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1 0298 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2 0299 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3 0300 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4 0301 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5 0302 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT 0303 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER 0304 0305 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1 0306 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2 0307 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3 0308 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4 0309 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP 0310 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC 0311 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD 0312 0313 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1 0314 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2 0315 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3 0316 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4 0317 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP 0318 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD 0319 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1 0320 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2 0321 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1 0322 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1 0323 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2 0324 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2 0325 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST 0326 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT 0327 /** 0328 * @} 0329 */ 0330 0331 /** @defgroup HRTIM_LL_EC_IT IT Defines 0332 * @ingroup RTEMSBSPsARMSTM32H7 0333 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions 0334 * @{ 0335 */ 0336 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE 0337 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE 0338 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE 0339 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE 0340 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE 0341 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE 0342 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE 0343 0344 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE 0345 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE 0346 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE 0347 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE 0348 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE 0349 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE 0350 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE 0351 0352 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE 0353 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE 0354 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE 0355 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE 0356 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE 0357 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE 0358 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE 0359 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE 0360 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE 0361 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE 0362 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE 0363 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE 0364 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE 0365 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE 0366 /** 0367 * @} 0368 */ 0369 0370 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE 0371 * @ingroup RTEMSBSPsARMSTM32H7 0372 * @{ 0373 * @brief Constants defining defining the synchronization input source. 0374 */ 0375 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */ 0376 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */ 0377 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 0378 /** 0379 * @} 0380 */ 0381 0382 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE 0383 * @ingroup RTEMSBSPsARMSTM32H7 0384 * @{ 0385 * @brief Constants defining the source and event to be sent on the synchronization output. 0386 */ 0387 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 0388 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 0389 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 0390 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 0391 /** 0392 * @} 0393 */ 0394 0395 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY 0396 * @ingroup RTEMSBSPsARMSTM32H7 0397 * @{ 0398 * @brief Constants defining the routing and conditioning of the synchronization output event. 0399 */ 0400 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */ 0401 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 0402 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 0403 /** 0404 * @} 0405 */ 0406 0407 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID 0408 * @ingroup RTEMSBSPsARMSTM32H7 0409 * @{ 0410 * @brief Constants identifying a timing unit. 0411 */ 0412 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */ 0413 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */ 0414 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */ 0415 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */ 0416 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */ 0417 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */ 0418 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */ 0419 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TACEN |\ 0420 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\ 0421 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN ) 0422 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X) 0423 0424 /** 0425 * @} 0426 */ 0427 0428 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID 0429 * @ingroup RTEMSBSPsARMSTM32H7 0430 * @{ 0431 * @brief Constants identifying an HRTIM output. 0432 */ 0433 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */ 0434 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */ 0435 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */ 0436 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */ 0437 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */ 0438 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */ 0439 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */ 0440 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */ 0441 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */ 0442 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */ 0443 /** 0444 * @} 0445 */ 0446 0447 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID 0448 * @ingroup RTEMSBSPsARMSTM32H7 0449 * @{ 0450 * @brief Constants identifying a compare unit. 0451 */ 0452 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */ 0453 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */ 0454 /** 0455 * @} 0456 */ 0457 0458 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID 0459 * @ingroup RTEMSBSPsARMSTM32H7 0460 * @{ 0461 * @brief Constants identifying a capture unit. 0462 */ 0463 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */ 0464 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */ 0465 /** 0466 * @} 0467 */ 0468 0469 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID 0470 * @ingroup RTEMSBSPsARMSTM32H7 0471 * @{ 0472 * @brief Constants identifying a fault channel. 0473 */ 0474 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */ 0475 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */ 0476 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */ 0477 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */ 0478 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */ 0479 /** 0480 * @} 0481 */ 0482 0483 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID 0484 * @ingroup RTEMSBSPsARMSTM32H7 0485 * @{ 0486 * @brief Constants identifying an external event channel. 0487 */ 0488 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */ 0489 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */ 0490 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */ 0491 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */ 0492 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */ 0493 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */ 0494 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */ 0495 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */ 0496 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */ 0497 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */ 0498 /** 0499 * @} 0500 */ 0501 0502 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE 0503 * @ingroup RTEMSBSPsARMSTM32H7 0504 * @{ 0505 * @brief Constants defining the state of an HRTIM output. 0506 */ 0507 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */ 0508 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */ 0509 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */ 0510 /** 0511 * @} 0512 */ 0513 0514 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER 0515 * @ingroup RTEMSBSPsARMSTM32H7 0516 * @{ 0517 * @brief Constants identifying an ADC trigger. 0518 */ 0519 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */ 0520 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */ 0521 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */ 0522 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */ 0523 /** 0524 * @} 0525 */ 0526 0527 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE 0528 * @ingroup RTEMSBSPsARMSTM32H7 0529 * @{ 0530 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register). 0531 */ 0532 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */ 0533 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */ 0534 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */ 0535 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */ 0536 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */ 0537 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */ 0538 /** 0539 * @} 0540 */ 0541 0542 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE 0543 * @ingroup RTEMSBSPsARMSTM32H7 0544 * @{ 0545 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3. 0546 */ 0547 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */ 0548 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */ 0549 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */ 0550 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */ 0551 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */ 0552 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */ 0553 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */ 0554 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */ 0555 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */ 0556 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */ 0557 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */ 0558 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */ 0559 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */ 0560 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */ 0561 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */ 0562 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */ 0563 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */ 0564 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */ 0565 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */ 0566 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */ 0567 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */ 0568 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */ 0569 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */ 0570 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */ 0571 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */ 0572 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */ 0573 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */ 0574 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */ 0575 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */ 0576 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */ 0577 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */ 0578 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */ 0579 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */ 0580 /** 0581 * @} 0582 */ 0583 0584 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE 0585 * @ingroup RTEMSBSPsARMSTM32H7 0586 * @{ 0587 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4. 0588 */ 0589 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */ 0590 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */ 0591 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */ 0592 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */ 0593 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */ 0594 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */ 0595 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */ 0596 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */ 0597 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */ 0598 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */ 0599 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */ 0600 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */ 0601 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */ 0602 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */ 0603 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */ 0604 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */ 0605 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */ 0606 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */ 0607 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */ 0608 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */ 0609 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */ 0610 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */ 0611 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */ 0612 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */ 0613 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */ 0614 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */ 0615 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */ 0616 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */ 0617 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */ 0618 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */ 0619 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */ 0620 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */ 0621 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */ 0622 /** 0623 * @} 0624 */ 0625 0626 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO 0627 * @ingroup RTEMSBSPsARMSTM32H7 0628 * @{ 0629 * @brief Constants defining timer high-resolution clock prescaler ratio. 0630 */ 0631 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 0632 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 0633 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 0634 /** 0635 * @} 0636 */ 0637 0638 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE 0639 * @ingroup RTEMSBSPsARMSTM32H7 0640 * @{ 0641 * @brief Constants defining timer counter operating mode. 0642 */ 0643 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 0644 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */ 0645 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 0646 /** 0647 * @} 0648 */ 0649 0650 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER 0651 * @ingroup RTEMSBSPsARMSTM32H7 0652 * @{ 0653 * @brief Constants defining on which output the DAC synchronization event is sent. 0654 */ 0655 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */ 0656 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 0657 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 0658 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */ 0659 /** 0660 * @} 0661 */ 0662 0663 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER 0664 * @ingroup RTEMSBSPsARMSTM32H7 0665 * @{ 0666 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update. 0667 */ 0668 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */ 0669 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */ 0670 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */ 0671 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */ 0672 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/ 0673 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */ 0674 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */ 0675 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/ 0676 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */ 0677 /** 0678 * @} 0679 */ 0680 0681 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING 0682 * @ingroup RTEMSBSPsARMSTM32H7 0683 * @{ 0684 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3. 0685 */ 0686 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 0687 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 0688 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 0689 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */ 0690 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */ 0691 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */ 0692 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */ 0693 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */ 0694 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */ 0695 /** 0696 * @} 0697 */ 0698 0699 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE 0700 * @ingroup RTEMSBSPsARMSTM32H7 0701 * @{ 0702 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode. 0703 */ 0704 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */ 0705 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 0706 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 0707 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 0708 /** 0709 * @} 0710 */ 0711 0712 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER 0713 * @ingroup RTEMSBSPsARMSTM32H7 0714 * @{ 0715 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter. 0716 */ 0717 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */ 0718 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */ 0719 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */ 0720 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */ 0721 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */ 0722 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */ 0723 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */ 0724 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */ 0725 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */ 0726 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */ 0727 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */ 0728 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */ 0729 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */ 0730 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */ 0731 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */ 0732 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */ 0733 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */ 0734 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */ 0735 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */ 0736 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 0737 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 0738 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 0739 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 0740 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 0741 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 0742 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 0743 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 0744 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 0745 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 0746 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 0747 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 0748 /** 0749 * @} 0750 */ 0751 0752 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER 0753 * @ingroup RTEMSBSPsARMSTM32H7 0754 * @{ 0755 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter. 0756 */ 0757 #define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */ 0758 #define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */ 0759 #define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */ 0760 #define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */ 0761 #define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */ 0762 #define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */ 0763 #define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */ 0764 #define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */ 0765 #define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */ 0766 #define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */ 0767 #define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */ 0768 #define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */ 0769 #define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */ 0770 #define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */ 0771 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */ 0772 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */ 0773 #define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */ 0774 #define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */ 0775 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */ 0776 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */ 0777 #define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */ 0778 #define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */ 0779 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */ 0780 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */ 0781 #define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */ 0782 #define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */ 0783 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */ 0784 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */ 0785 #define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */ 0786 #define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */ 0787 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */ 0788 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */ 0789 /** 0790 * @} 0791 */ 0792 0793 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE 0794 * @ingroup RTEMSBSPsARMSTM32H7 0795 * @{ 0796 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied). 0797 */ 0798 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */ 0799 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */ 0800 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */ 0801 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */ 0802 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */ 0803 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */ 0804 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */ 0805 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */ 0806 0807 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */ 0808 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */ 0809 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */ 0810 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */ 0811 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */ 0812 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */ 0813 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */ 0814 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */ 0815 /** 0816 * @} 0817 */ 0818 0819 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE 0820 * @ingroup RTEMSBSPsARMSTM32H7 0821 * @{ 0822 * @brief Constants defining how the timer behaves during a burst mode operation. 0823 */ 0824 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */ 0825 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 0826 /** 0827 * @} 0828 */ 0829 0830 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA 0831 * @ingroup RTEMSBSPsARMSTM32H7 0832 * @{ 0833 * @brief Constants defining the registers that can be written during a burst DMA operation. 0834 */ 0835 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 0836 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */ 0837 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */ 0838 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */ 0839 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */ 0840 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */ 0841 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */ 0842 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */ 0843 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */ 0844 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */ 0845 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */ 0846 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */ 0847 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */ 0848 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */ 0849 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */ 0850 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */ 0851 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */ 0852 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */ 0853 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */ 0854 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */ 0855 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */ 0856 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */ 0857 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 0858 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 0859 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 0860 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 0861 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 0862 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 0863 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 0864 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 0865 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 0866 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 0867 /** 0868 * @} 0869 */ 0870 0871 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS 0872 * @ingroup RTEMSBSPsARMSTM32H7 0873 * @{ 0874 * @brief Constants defining on which output the signal is currently applied in push-pull mode. 0875 */ 0876 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */ 0877 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 0878 /** 0879 * @} 0880 */ 0881 0882 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS 0883 * @ingroup RTEMSBSPsARMSTM32H7 0884 * @{ 0885 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered. 0886 */ 0887 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 0888 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 0889 /** 0890 * @} 0891 */ 0892 0893 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER 0894 * @ingroup RTEMSBSPsARMSTM32H7 0895 * @{ 0896 * @brief Constants defining the event filtering applied to external events by a timer. 0897 */ 0898 #define LL_HRTIM_EEFLTR_NONE (0x00000000U) 0899 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */ 0900 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */ 0901 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */ 0902 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */ 0903 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 0904 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 0905 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 0906 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 0907 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 0908 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 0909 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 0910 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 0911 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */ 0912 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */ 0913 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 0914 /** 0915 * @} 0916 */ 0917 0918 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS 0919 * @ingroup RTEMSBSPsARMSTM32H7 0920 * @{ 0921 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends. 0922 */ 0923 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */ 0924 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 0925 /** 0926 * @} 0927 */ 0928 0929 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER 0930 * @ingroup RTEMSBSPsARMSTM32H7 0931 * @{ 0932 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG). 0933 */ 0934 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */ 0935 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */ 0936 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */ 0937 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 0938 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */ 0939 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */ 0940 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */ 0941 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */ 0942 /** 0943 * @} 0944 */ 0945 0946 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN 0947 * @ingroup RTEMSBSPsARMSTM32H7 0948 * @{ 0949 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge. 0950 */ 0951 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */ 0952 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */ 0953 /** 0954 * @} 0955 */ 0956 0957 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN 0958 * @ingroup RTEMSBSPsARMSTM32H7 0959 * @{ 0960 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge. 0961 */ 0962 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */ 0963 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */ 0964 /** 0965 * @} 0966 */ 0967 0968 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER 0969 * @ingroup RTEMSBSPsARMSTM32H7 0970 * @{ 0971 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ). 0972 */ 0973 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */ 0974 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 0975 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 0976 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 0977 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 0978 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 0979 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 0980 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 0981 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 0982 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 0983 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 0984 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 0985 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 0986 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 0987 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 0988 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 0989 /** 0990 * @} 0991 */ 0992 0993 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE 0994 * @ingroup RTEMSBSPsARMSTM32H7 0995 * @{ 0996 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8). 0997 */ 0998 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */ 0999 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */ 1000 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */ 1001 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */ 1002 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */ 1003 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */ 1004 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */ 1005 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */ 1006 /** 1007 * @} 1008 */ 1009 1010 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH 1011 * @ingroup RTEMSBSPsARMSTM32H7 1012 * @{ 1013 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier. 1014 */ 1015 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */ 1016 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 1017 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 1018 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 1019 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 1020 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 1021 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 1022 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 1023 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 1024 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 1025 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 1026 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 1027 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 1028 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 1029 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 1030 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 1031 /** 1032 * @} 1033 */ 1034 1035 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT 1036 * @ingroup RTEMSBSPsARMSTM32H7 1037 * @{ 1038 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output. 1039 */ 1040 #define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */ 1041 #define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */ 1042 #define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */ 1043 #define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */ 1044 #define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */ 1045 #define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */ 1046 #define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */ 1047 #define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */ 1048 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */ 1049 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */ 1050 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */ 1051 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */ 1052 #define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */ 1053 #define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */ 1054 #define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */ 1055 #define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */ 1056 #define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */ 1057 #define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */ 1058 #define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */ 1059 #define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */ 1060 #define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */ 1061 #define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */ 1062 #define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */ 1063 #define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */ 1064 #define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */ 1065 #define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */ 1066 #define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */ 1067 #define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */ 1068 #define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */ 1069 #define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */ 1070 #define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */ 1071 #define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */ 1072 /** 1073 * @} 1074 */ 1075 1076 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY 1077 * @ingroup RTEMSBSPsARMSTM32H7 1078 * @{ 1079 * @brief Constants defining the polarity of a timer output. 1080 */ 1081 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */ 1082 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 1083 /** 1084 * @} 1085 */ 1086 1087 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE 1088 * @ingroup RTEMSBSPsARMSTM32H7 1089 * @{ 1090 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered. 1091 */ 1092 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */ 1093 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 1094 /** 1095 * @} 1096 */ 1097 1098 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE 1099 * @ingroup RTEMSBSPsARMSTM32H7 1100 * @{ 1101 * @brief Constants defining the half mode of an HRTIM Timer instance. 1102 */ 1103 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */ 1104 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */ 1105 /** 1106 * @} 1107 */ 1108 1109 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL 1110 * @ingroup RTEMSBSPsARMSTM32H7 1111 * @{ 1112 * @brief Constants defining the output level when output is in IDLE state 1113 */ 1114 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 1115 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 1116 /** 1117 * @} 1118 */ 1119 1120 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE 1121 * @ingroup RTEMSBSPsARMSTM32H7 1122 * @{ 1123 * @brief Constants defining the output level when output is in FAULT state. 1124 */ 1125 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */ 1126 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 1127 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 1128 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 1129 /** 1130 * @} 1131 */ 1132 1133 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE 1134 * @ingroup RTEMSBSPsARMSTM32H7 1135 * @{ 1136 * @brief Constants defining whether or not chopper mode is enabled for a timer output. 1137 */ 1138 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 1139 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 1140 /** 1141 * @} 1142 */ 1143 1144 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE 1145 * @ingroup RTEMSBSPsARMSTM32H7 1146 * @{ 1147 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state 1148 during a programmable period before the output takes its idle state. 1149 */ 1150 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 1151 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */ 1152 /** 1153 * @} 1154 */ 1155 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL 1156 * @ingroup RTEMSBSPsARMSTM32H7 1157 * @{ 1158 * @brief Constants defining the level of a timer output. 1159 */ 1160 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */ 1161 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */ 1162 /** 1163 * @} 1164 */ 1165 1166 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE 1167 * @ingroup RTEMSBSPsARMSTM32H7 1168 * @{ 1169 * @brief Constants defining available sources associated to external events. 1170 */ 1171 #define LL_HRTIM_EE_SRC_1 0x00000000U /*!< External event source 1 (EExSrc1)*/ 1172 #define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */ 1173 #define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */ 1174 #define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */ 1175 /** 1176 * @} 1177 */ 1178 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY 1179 * @ingroup RTEMSBSPsARMSTM32H7 1180 * @{ 1181 * @brief Constants defining the polarity of an external event. 1182 */ 1183 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */ 1184 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 1185 /** 1186 * @} 1187 */ 1188 1189 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY 1190 * @ingroup RTEMSBSPsARMSTM32H7 1191 * @{ 1192 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event. 1193 */ 1194 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */ 1195 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 1196 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 1197 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE 1203 * @ingroup RTEMSBSPsARMSTM32H7 1204 * @{ 1205 * @brief Constants defining whether or not an external event is programmed in fast mode. 1206 */ 1207 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 1208 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 1209 /** 1210 * @} 1211 */ 1212 1213 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER 1214 * @ingroup RTEMSBSPsARMSTM32H7 1215 * @{ 1216 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied. 1217 */ 1218 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */ 1219 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */ 1220 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */ 1221 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */ 1222 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */ 1223 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */ 1224 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */ 1225 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */ 1226 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */ 1227 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */ 1228 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */ 1229 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */ 1230 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */ 1231 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */ 1232 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */ 1233 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */ 1234 /** 1235 * @} 1236 */ 1237 1238 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER 1239 * @ingroup RTEMSBSPsARMSTM32H7 1240 * @{ 1241 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters. 1242 */ 1243 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */ 1244 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */ 1245 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */ 1246 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */ 1247 /** 1248 * @} 1249 */ 1250 1251 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE 1252 * @ingroup RTEMSBSPsARMSTM32H7 1253 * @{ 1254 * @brief Constants defining whether a faults is be triggered by any external or internal fault source. 1255 */ 1256 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */ 1257 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 1258 /** 1259 * @} 1260 */ 1261 1262 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY 1263 * @ingroup RTEMSBSPsARMSTM32H7 1264 * @{ 1265 * @brief Constants defining the polarity of a fault event. 1266 */ 1267 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */ 1268 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER 1274 * @ingroup RTEMSBSPsARMSTM32H7 1275 * @{ 1276 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied. 1277 */ 1278 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */ 1279 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */ 1280 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */ 1281 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */ 1282 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */ 1283 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */ 1284 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */ 1285 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */ 1286 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */ 1287 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */ 1288 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */ 1289 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */ 1290 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */ 1291 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */ 1292 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */ 1293 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */ 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER 1299 * @ingroup RTEMSBSPsARMSTM32H7 1300 * @{ 1301 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters. 1302 */ 1303 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */ 1304 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */ 1305 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */ 1306 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */ 1307 /** 1308 * @} 1309 */ 1310 1311 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE 1312 * @ingroup RTEMSBSPsARMSTM32H7 1313 * @{ 1314 * @brief Constants defining if the burst mode is entered once or if it is continuously operating. 1315 */ 1316 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */ 1317 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 1318 /** 1319 * @} 1320 */ 1321 1322 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE 1323 * @ingroup RTEMSBSPsARMSTM32H7 1324 * @{ 1325 * @brief Constants defining the clock source for the burst mode counter. 1326 */ 1327 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 1328 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 1329 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 1330 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 1331 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 1332 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 1333 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 1334 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 1335 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 1336 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 1337 /** 1338 * @} 1339 */ 1340 1341 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER 1342 * @ingroup RTEMSBSPsARMSTM32H7 1343 * @{ 1344 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST). 1345 */ 1346 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */ 1347 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */ 1348 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */ 1349 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */ 1350 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */ 1351 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */ 1352 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */ 1353 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */ 1354 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */ 1355 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */ 1356 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */ 1357 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/ 1358 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */ 1359 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */ 1360 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */ 1361 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */ 1362 /** 1363 * @} 1364 */ 1365 1366 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER 1367 * @ingroup RTEMSBSPsARMSTM32H7 1368 * @{ 1369 * @brief Constants defining the events that can be used to trig the burst mode operation. 1370 */ 1371 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */ 1372 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */ 1373 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */ 1374 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */ 1375 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */ 1376 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */ 1377 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */ 1378 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */ 1379 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */ 1380 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */ 1381 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */ 1382 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */ 1383 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */ 1384 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */ 1385 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */ 1386 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */ 1387 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */ 1388 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */ 1389 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */ 1390 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */ 1391 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */ 1392 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */ 1393 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */ 1394 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */ 1395 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */ 1396 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */ 1397 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */ 1398 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */ 1399 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */ 1400 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */ 1401 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */ 1402 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */ 1403 /** 1404 * @} 1405 */ 1406 1407 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS 1408 * @ingroup RTEMSBSPsARMSTM32H7 1409 * @{ 1410 * @brief Constants defining the operating state of the burst mode controller. 1411 */ 1412 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */ 1413 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */ 1414 /** 1415 * @} 1416 */ 1417 1418 /** 1419 * @} 1420 */ 1421 1422 /* Exported macro ------------------------------------------------------------*/ 1423 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros 1424 * @ingroup RTEMSBSPsARMSTM32H7 1425 * @{ 1426 */ 1427 1428 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros 1429 * @ingroup RTEMSBSPsARMSTM32H7 1430 * @{ 1431 */ 1432 1433 /** 1434 * @brief Write a value in HRTIM register 1435 * @param __INSTANCE__ HRTIM Instance 1436 * @param __REG__ Register to be written 1437 * @param __VALUE__ Value to be written in the register 1438 * @retval None 1439 */ 1440 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 1441 1442 /** 1443 * @brief Read a value in HRTIM register 1444 * @param __INSTANCE__ HRTIM Instance 1445 * @param __REG__ Register to be read 1446 * @retval Register value 1447 */ 1448 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 1449 /** 1450 * @} 1451 */ 1452 1453 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros 1454 * @ingroup RTEMSBSPsARMSTM32H7 1455 * @{ 1456 */ 1457 /** 1458 * @brief HELPER macro returning the output state from output enable/disable status 1459 * @param __OUTPUT_STATUS_EN__ output enable status 1460 * @param __OUTPUT_STATUS_DIS__ output Disable status 1461 * @retval Returned value can be one of the following values: 1462 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE 1463 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN 1464 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT 1465 */ 1466 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\ 1467 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\ 1468 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT) 1469 /** 1470 * @} 1471 */ 1472 1473 /** 1474 * @} 1475 */ 1476 1477 /* Exported functions --------------------------------------------------------*/ 1478 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions 1479 * @ingroup RTEMSBSPsARMSTM32H7 1480 * @{ 1481 */ 1482 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control 1483 * @ingroup RTEMSBSPsARMSTM32H7 1484 * @{ 1485 */ 1486 1487 /** 1488 * @brief Select the HRTIM synchronization input source. 1489 * @note This function must not be called when the concerned timer(s) is (are) enabled . 1490 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc 1491 * @param HRTIMx High Resolution Timer instance 1492 * @param SyncInSrc This parameter can be one of the following values: 1493 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE 1494 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT 1495 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT 1496 * @retval None 1497 */ 1498 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc) 1499 { 1500 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc); 1501 } 1502 1503 /** 1504 * @brief Get actual HRTIM synchronization input source. 1505 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc 1506 * @param HRTIMx High Resolution Timer instance 1507 * @retval SyncInSrc Returned value can be one of the following values: 1508 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE 1509 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT 1510 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT 1511 */ 1512 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx) 1513 { 1514 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN)); 1515 } 1516 1517 /** 1518 * @brief Configure the HRTIM synchronization output. 1519 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n 1520 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut 1521 * @param HRTIMx High Resolution Timer instance 1522 * @param Config This parameter can be one of the following values: 1523 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 1524 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 1525 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 1526 * @param Src This parameter can be one of the following values: 1527 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 1528 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 1529 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 1530 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 1531 * @retval None 1532 */ 1533 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src) 1534 { 1535 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src)); 1536 } 1537 1538 /** 1539 * @brief Set the routing and conditioning of the synchronization output event. 1540 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig 1541 * @note This function can be called only when the master timer is enabled. 1542 * @param HRTIMx High Resolution Timer instance 1543 * @param SyncOutConfig This parameter can be one of the following values: 1544 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 1545 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 1546 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 1547 * @retval None 1548 */ 1549 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig) 1550 { 1551 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig); 1552 } 1553 1554 /** 1555 * @brief Get actual routing and conditioning of the synchronization output event. 1556 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig 1557 * @param HRTIMx High Resolution Timer instance 1558 * @retval SyncOutConfig Returned value can be one of the following values: 1559 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 1560 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 1561 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 1562 */ 1563 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx) 1564 { 1565 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT)); 1566 } 1567 1568 /** 1569 * @brief Set the source and event to be sent on the HRTIM synchronization output. 1570 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc 1571 * @param HRTIMx High Resolution Timer instance 1572 * @param SyncOutSrc This parameter can be one of the following values: 1573 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 1574 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 1575 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 1576 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 1577 * @retval None 1578 */ 1579 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc) 1580 { 1581 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc); 1582 } 1583 1584 /** 1585 * @brief Get actual source and event sent on the HRTIM synchronization output. 1586 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc 1587 * @param HRTIMx High Resolution Timer instance 1588 * @retval SyncOutSrc Returned value can be one of the following values: 1589 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 1590 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 1591 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 1592 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 1593 */ 1594 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx) 1595 { 1596 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC)); 1597 } 1598 1599 /** 1600 * @brief Disable (temporarily) update event generation. 1601 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n 1602 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n 1603 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n 1604 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n 1605 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n 1606 * CR1 TEUDIS LL_HRTIM_SuspendUpdate 1607 * @note Allow to temporarily disable the transfer from preload to active 1608 * registers, whatever the selected update event. This allows to modify 1609 * several registers in multiple timers. 1610 * @param HRTIMx High Resolution Timer instance 1611 * @param Timers This parameter can be a combination of the following values: 1612 * @arg @ref LL_HRTIM_TIMER_MASTER 1613 * @arg @ref LL_HRTIM_TIMER_A 1614 * @arg @ref LL_HRTIM_TIMER_B 1615 * @arg @ref LL_HRTIM_TIMER_C 1616 * @arg @ref LL_HRTIM_TIMER_D 1617 * @arg @ref LL_HRTIM_TIMER_E 1618 * @retval None 1619 */ 1620 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 1621 { 1622 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); 1623 } 1624 1625 /** 1626 * @brief Enable update event generation. 1627 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n 1628 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n 1629 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n 1630 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n 1631 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n 1632 * CR1 TEUDIS LL_HRTIM_ResumeUpdate 1633 * @note The regular update event takes place. 1634 * @param HRTIMx High Resolution Timer instance 1635 * @param Timers This parameter can be a combination of the following values: 1636 * @arg @ref LL_HRTIM_TIMER_MASTER 1637 * @arg @ref LL_HRTIM_TIMER_A 1638 * @arg @ref LL_HRTIM_TIMER_B 1639 * @arg @ref LL_HRTIM_TIMER_C 1640 * @arg @ref LL_HRTIM_TIMER_D 1641 * @arg @ref LL_HRTIM_TIMER_E 1642 * @retval None 1643 */ 1644 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 1645 { 1646 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); 1647 } 1648 1649 /** 1650 * @brief Force an immediate transfer from the preload to the active register . 1651 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n 1652 * CR2 TASWU LL_HRTIM_ForceUpdate\n 1653 * CR2 TBSWU LL_HRTIM_ForceUpdate\n 1654 * CR2 TCSWU LL_HRTIM_ForceUpdate\n 1655 * CR2 TDSWU LL_HRTIM_ForceUpdate\n 1656 * CR2 TESWU LL_HRTIM_ForceUpdate 1657 * @note Any pending update request is cancelled. 1658 * @param HRTIMx High Resolution Timer instance 1659 * @param Timers This parameter can be a combination of the following values: 1660 * @arg @ref LL_HRTIM_TIMER_MASTER 1661 * @arg @ref LL_HRTIM_TIMER_A 1662 * @arg @ref LL_HRTIM_TIMER_B 1663 * @arg @ref LL_HRTIM_TIMER_C 1664 * @arg @ref LL_HRTIM_TIMER_D 1665 * @arg @ref LL_HRTIM_TIMER_E 1666 * @retval None 1667 */ 1668 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 1669 { 1670 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); 1671 } 1672 1673 /** 1674 * @brief Reset the HRTIM timer(s) counter. 1675 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n 1676 * CR2 TARST LL_HRTIM_CounterReset\n 1677 * CR2 TBRST LL_HRTIM_CounterReset\n 1678 * CR2 TCRST LL_HRTIM_CounterReset\n 1679 * CR2 TDRST LL_HRTIM_CounterReset\n 1680 * CR2 TERST LL_HRTIM_CounterReset 1681 * @param HRTIMx High Resolution Timer instance 1682 * @param Timers This parameter can be a combination of the following values: 1683 * @arg @ref LL_HRTIM_TIMER_MASTER 1684 * @arg @ref LL_HRTIM_TIMER_A 1685 * @arg @ref LL_HRTIM_TIMER_B 1686 * @arg @ref LL_HRTIM_TIMER_C 1687 * @arg @ref LL_HRTIM_TIMER_D 1688 * @arg @ref LL_HRTIM_TIMER_E 1689 * @retval None 1690 */ 1691 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 1692 { 1693 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK)); 1694 } 1695 1696 /** 1697 * @brief Enable the HRTIM timer(s) output(s) . 1698 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n 1699 * OENR TA2OEN LL_HRTIM_EnableOutput\n 1700 * OENR TB1OEN LL_HRTIM_EnableOutput\n 1701 * OENR TB2OEN LL_HRTIM_EnableOutput\n 1702 * OENR TC1OEN LL_HRTIM_EnableOutput\n 1703 * OENR TC2OEN LL_HRTIM_EnableOutput\n 1704 * OENR TD1OEN LL_HRTIM_EnableOutput\n 1705 * OENR TD2OEN LL_HRTIM_EnableOutput\n 1706 * OENR TE1OEN LL_HRTIM_EnableOutput\n 1707 * OENR TE2OEN LL_HRTIM_EnableOutput 1708 * @param HRTIMx High Resolution Timer instance 1709 * @param Outputs This parameter can be a combination of the following values: 1710 * @arg @ref LL_HRTIM_OUTPUT_TA1 1711 * @arg @ref LL_HRTIM_OUTPUT_TA2 1712 * @arg @ref LL_HRTIM_OUTPUT_TB1 1713 * @arg @ref LL_HRTIM_OUTPUT_TB2 1714 * @arg @ref LL_HRTIM_OUTPUT_TC1 1715 * @arg @ref LL_HRTIM_OUTPUT_TC2 1716 * @arg @ref LL_HRTIM_OUTPUT_TD1 1717 * @arg @ref LL_HRTIM_OUTPUT_TD2 1718 * @arg @ref LL_HRTIM_OUTPUT_TE1 1719 * @arg @ref LL_HRTIM_OUTPUT_TE2 1720 * @retval None 1721 */ 1722 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs) 1723 { 1724 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK)); 1725 } 1726 1727 /** 1728 * @brief Disable the HRTIM timer(s) output(s) . 1729 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n 1730 * OENR TA2OEN LL_HRTIM_DisableOutput\n 1731 * OENR TB1OEN LL_HRTIM_DisableOutput\n 1732 * OENR TB2OEN LL_HRTIM_DisableOutput\n 1733 * OENR TC1OEN LL_HRTIM_DisableOutput\n 1734 * OENR TC2OEN LL_HRTIM_DisableOutput\n 1735 * OENR TD1OEN LL_HRTIM_DisableOutput\n 1736 * OENR TD2OEN LL_HRTIM_DisableOutput\n 1737 * OENR TE1OEN LL_HRTIM_DisableOutput\n 1738 * OENR TE2OEN LL_HRTIM_DisableOutput 1739 * @param HRTIMx High Resolution Timer instance 1740 * @param Outputs This parameter can be a combination of the following values: 1741 * @arg @ref LL_HRTIM_OUTPUT_TA1 1742 * @arg @ref LL_HRTIM_OUTPUT_TA2 1743 * @arg @ref LL_HRTIM_OUTPUT_TB1 1744 * @arg @ref LL_HRTIM_OUTPUT_TB2 1745 * @arg @ref LL_HRTIM_OUTPUT_TC1 1746 * @arg @ref LL_HRTIM_OUTPUT_TC2 1747 * @arg @ref LL_HRTIM_OUTPUT_TD1 1748 * @arg @ref LL_HRTIM_OUTPUT_TD2 1749 * @arg @ref LL_HRTIM_OUTPUT_TE1 1750 * @arg @ref LL_HRTIM_OUTPUT_TE2 1751 * @retval None 1752 */ 1753 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs) 1754 { 1755 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK)); 1756 } 1757 1758 /** 1759 * @brief Indicates whether the HRTIM timer output is enabled. 1760 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n 1761 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n 1762 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n 1763 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n 1764 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n 1765 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n 1766 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n 1767 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n 1768 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n 1769 * OENR TE2OEN LL_HRTIM_IsEnabledOutput 1770 * @param HRTIMx High Resolution Timer instance 1771 * @param Output This parameter can be one of the following values: 1772 * @arg @ref LL_HRTIM_OUTPUT_TA1 1773 * @arg @ref LL_HRTIM_OUTPUT_TA2 1774 * @arg @ref LL_HRTIM_OUTPUT_TB1 1775 * @arg @ref LL_HRTIM_OUTPUT_TB2 1776 * @arg @ref LL_HRTIM_OUTPUT_TC1 1777 * @arg @ref LL_HRTIM_OUTPUT_TC2 1778 * @arg @ref LL_HRTIM_OUTPUT_TD1 1779 * @arg @ref LL_HRTIM_OUTPUT_TD2 1780 * @arg @ref LL_HRTIM_OUTPUT_TE1 1781 * @arg @ref LL_HRTIM_OUTPUT_TE2 1782 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0). 1783 */ 1784 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 1785 { 1786 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL); 1787 } 1788 1789 /** 1790 * @brief Indicates whether the HRTIM timer output is disabled. 1791 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n 1792 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n 1793 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n 1794 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n 1795 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n 1796 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n 1797 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n 1798 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n 1799 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n 1800 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput 1801 * @param HRTIMx High Resolution Timer instance 1802 * @param Output This parameter can be one of the following values: 1803 * @arg @ref LL_HRTIM_OUTPUT_TA1 1804 * @arg @ref LL_HRTIM_OUTPUT_TA2 1805 * @arg @ref LL_HRTIM_OUTPUT_TB1 1806 * @arg @ref LL_HRTIM_OUTPUT_TB2 1807 * @arg @ref LL_HRTIM_OUTPUT_TC1 1808 * @arg @ref LL_HRTIM_OUTPUT_TC2 1809 * @arg @ref LL_HRTIM_OUTPUT_TD1 1810 * @arg @ref LL_HRTIM_OUTPUT_TD2 1811 * @arg @ref LL_HRTIM_OUTPUT_TE1 1812 * @arg @ref LL_HRTIM_OUTPUT_TE2 1813 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0). 1814 */ 1815 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 1816 { 1817 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL); 1818 } 1819 1820 /** 1821 * @brief Configure an ADC trigger. 1822 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n 1823 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n 1824 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n 1825 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n 1826 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n 1827 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n 1828 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n 1829 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n 1830 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n 1831 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n 1832 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n 1833 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n 1834 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n 1835 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n 1836 * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n 1837 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n 1838 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n 1839 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n 1840 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n 1841 * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n 1842 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n 1843 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n 1844 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n 1845 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n 1846 * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n 1847 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n 1848 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n 1849 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n 1850 * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n 1851 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n 1852 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n 1853 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n 1854 * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n 1855 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n 1856 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n 1857 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n 1858 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n 1859 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n 1860 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n 1861 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n 1862 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n 1863 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n 1864 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n 1865 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n 1866 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n 1867 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n 1868 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n 1869 * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n 1870 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n 1871 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n 1872 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n 1873 * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n 1874 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n 1875 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n 1876 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n 1877 * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n 1878 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n 1879 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n 1880 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n 1881 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n 1882 * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n 1883 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n 1884 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n 1885 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n 1886 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n 1887 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n 1888 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n 1889 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n 1890 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n 1891 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n 1892 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n 1893 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n 1894 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n 1895 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n 1896 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n 1897 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n 1898 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n 1899 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n 1900 * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n 1901 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n 1902 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n 1903 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n 1904 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n 1905 * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n 1906 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n 1907 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n 1908 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n 1909 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n 1910 * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n 1911 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n 1912 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n 1913 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n 1914 * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n 1915 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n 1916 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n 1917 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n 1918 * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n 1919 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n 1920 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n 1921 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n 1922 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n 1923 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n 1924 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n 1925 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n 1926 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n 1927 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n 1928 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n 1929 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n 1930 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n 1931 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n 1932 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n 1933 * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n 1934 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n 1935 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n 1936 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n 1937 * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n 1938 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n 1939 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n 1940 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n 1941 * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n 1942 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n 1943 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n 1944 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n 1945 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n 1946 * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n 1947 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n 1948 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n 1949 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n 1950 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n 1951 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n 1952 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n 1953 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig 1954 * @param HRTIMx High Resolution Timer instance 1955 * @param ADCTrig This parameter can be one of the following values: 1956 * @arg @ref LL_HRTIM_ADCTRIG_1 1957 * @arg @ref LL_HRTIM_ADCTRIG_2 1958 * @arg @ref LL_HRTIM_ADCTRIG_3 1959 * @arg @ref LL_HRTIM_ADCTRIG_4 1960 * @param Update This parameter can be one of the following values: 1961 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 1962 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 1963 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 1964 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 1965 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 1966 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 1967 * @param Src This parameter can be a combination of the following values: 1968 * 1969 * For ADC trigger 1 and ADC trigger 3: 1970 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 1971 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 1972 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 1973 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 1974 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 1975 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 1976 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 1977 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 1978 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 1979 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 1980 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 1981 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 1982 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 1983 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 1984 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 1985 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 1986 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 1987 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 1988 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 1989 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 1990 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 1991 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 1992 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 1993 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 1994 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 1995 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 1996 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 1997 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 1998 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 1999 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 2000 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 2001 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 2002 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 2003 * 2004 * For ADC trigger 2 and ADC trigger 4: 2005 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 2006 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 2007 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 2008 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 2009 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 2010 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 2011 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 2012 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 2013 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 2014 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 2015 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 2016 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 2017 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 2018 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 2019 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 2020 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 2021 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 2022 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 2023 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 2024 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 2025 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 2026 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 2027 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 2028 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 2029 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 2030 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 2031 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 2032 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 2033 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 2034 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 2035 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 2036 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 2037 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 2038 * 2039 * @retval None 2040 */ 2041 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) 2042 { 2043 uint32_t shift = ((3U * ADCTrig) & 0x1FU); 2044 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 2045 REG_OFFSET_TAB_ADCxR[ADCTrig])); 2046 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); 2047 WRITE_REG(*pReg, Src); 2048 } 2049 2050 /** 2051 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register. 2052 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n 2053 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n 2054 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n 2055 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n 2056 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR 2057 * registers are not preloaded either: a write access will result in an 2058 * immediate update of the trigger source. 2059 * @param HRTIMx High Resolution Timer instance 2060 * @param ADCTrig This parameter can be one of the following values: 2061 * @arg @ref LL_HRTIM_ADCTRIG_1 2062 * @arg @ref LL_HRTIM_ADCTRIG_2 2063 * @arg @ref LL_HRTIM_ADCTRIG_3 2064 * @arg @ref LL_HRTIM_ADCTRIG_4 2065 * @param Update This parameter can be one of the following values: 2066 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 2067 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 2068 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 2069 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 2070 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 2071 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 2072 * @retval None 2073 */ 2074 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update) 2075 { 2076 uint32_t shift = ((3U * ADCTrig) & 0x1FU); 2077 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); 2078 } 2079 2080 /** 2081 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register. 2082 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n 2083 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n 2084 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n 2085 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n 2086 * @param HRTIMx High Resolution Timer instance 2087 * @param ADCTrig This parameter can be one of the following values: 2088 * @arg @ref LL_HRTIM_ADCTRIG_1 2089 * @arg @ref LL_HRTIM_ADCTRIG_2 2090 * @arg @ref LL_HRTIM_ADCTRIG_3 2091 * @arg @ref LL_HRTIM_ADCTRIG_4 2092 * @retval Update Returned value can be one of the following values: 2093 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 2094 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 2095 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 2096 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 2097 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 2098 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 2099 */ 2100 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) 2101 { 2102 const uint32_t shift = ((3U * ADCTrig) & 0x1FU); 2103 return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift); 2104 } 2105 2106 /** 2107 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion. 2108 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n 2109 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n 2110 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n 2111 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n 2112 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n 2113 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n 2114 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n 2115 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n 2116 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n 2117 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n 2118 * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n 2119 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n 2120 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n 2121 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n 2122 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n 2123 * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n 2124 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n 2125 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n 2126 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n 2127 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n 2128 * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n 2129 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n 2130 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n 2131 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n 2132 * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n 2133 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n 2134 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n 2135 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n 2136 * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n 2137 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n 2138 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n 2139 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n 2140 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n 2141 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n 2142 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n 2143 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n 2144 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n 2145 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n 2146 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n 2147 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n 2148 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n 2149 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n 2150 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n 2151 * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n 2152 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n 2153 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n 2154 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n 2155 * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n 2156 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n 2157 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n 2158 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n 2159 * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n 2160 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n 2161 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n 2162 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n 2163 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n 2164 * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n 2165 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n 2166 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n 2167 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n 2168 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n 2169 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n 2170 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n 2171 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n 2172 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n 2173 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n 2174 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n 2175 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n 2176 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n 2177 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n 2178 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n 2179 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n 2180 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n 2181 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n 2182 * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n 2183 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n 2184 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n 2185 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n 2186 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n 2187 * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n 2188 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n 2189 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n 2190 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n 2191 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n 2192 * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n 2193 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n 2194 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n 2195 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n 2196 * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n 2197 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n 2198 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n 2199 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n 2200 * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n 2201 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n 2202 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n 2203 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n 2204 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n 2205 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n 2206 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n 2207 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n 2208 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n 2209 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n 2210 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n 2211 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n 2212 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n 2213 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n 2214 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n 2215 * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n 2216 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n 2217 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n 2218 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n 2219 * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n 2220 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n 2221 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n 2222 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n 2223 * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n 2224 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n 2225 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n 2226 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n 2227 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n 2228 * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n 2229 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n 2230 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n 2231 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n 2232 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n 2233 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n 2234 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n 2235 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n 2236 * @param HRTIMx High Resolution Timer instance 2237 * @param ADCTrig This parameter can be one of the following values: 2238 * @arg @ref LL_HRTIM_ADCTRIG_1 2239 * @arg @ref LL_HRTIM_ADCTRIG_2 2240 * @arg @ref LL_HRTIM_ADCTRIG_3 2241 * @arg @ref LL_HRTIM_ADCTRIG_4 2242 * @param Src 2243 * For ADC trigger 1 and ADC trigger 3 this parameter can be a 2244 * combination of the following values: 2245 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 2246 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 2247 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 2248 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 2249 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 2250 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 2251 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 2252 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 2253 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 2254 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 2255 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 2256 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 2257 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 2258 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 2259 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 2260 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 2261 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 2262 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 2263 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 2264 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 2265 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 2266 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 2267 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 2268 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 2269 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 2270 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 2271 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 2272 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 2273 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 2274 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 2275 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 2276 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 2277 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 2278 * 2279 * For ADC trigger 2 and ADC trigger 4 this parameter can be a 2280 * combination of the following values: 2281 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 2282 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 2283 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 2284 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 2285 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 2286 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 2287 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 2288 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 2289 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 2290 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 2291 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 2292 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 2293 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 2294 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 2295 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 2296 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 2297 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 2298 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 2299 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 2300 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 2301 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 2302 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 2303 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 2304 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 2305 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 2306 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 2307 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 2308 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 2309 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 2310 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 2311 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 2312 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 2313 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 2314 * 2315 * @retval None 2316 */ 2317 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) 2318 { 2319 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 2320 REG_OFFSET_TAB_ADCxR[ADCTrig])); 2321 WRITE_REG(*pReg, Src); 2322 } 2323 2324 /** 2325 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion. 2326 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n 2327 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n 2328 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n 2329 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n 2330 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n 2331 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n 2332 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n 2333 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n 2334 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n 2335 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n 2336 * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n 2337 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n 2338 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n 2339 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n 2340 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n 2341 * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n 2342 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n 2343 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n 2344 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n 2345 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n 2346 * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n 2347 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n 2348 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n 2349 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n 2350 * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n 2351 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n 2352 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n 2353 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n 2354 * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n 2355 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n 2356 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n 2357 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n 2358 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n 2359 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n 2360 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n 2361 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n 2362 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n 2363 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n 2364 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n 2365 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n 2366 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n 2367 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n 2368 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n 2369 * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n 2370 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n 2371 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n 2372 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n 2373 * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n 2374 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n 2375 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n 2376 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n 2377 * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n 2378 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n 2379 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n 2380 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n 2381 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n 2382 * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n 2383 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n 2384 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n 2385 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n 2386 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n 2387 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n 2388 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n 2389 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n 2390 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n 2391 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n 2392 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n 2393 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n 2394 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n 2395 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n 2396 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n 2397 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n 2398 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n 2399 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n 2400 * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n 2401 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n 2402 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n 2403 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n 2404 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n 2405 * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n 2406 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n 2407 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n 2408 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n 2409 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n 2410 * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n 2411 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n 2412 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n 2413 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n 2414 * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n 2415 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n 2416 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n 2417 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n 2418 * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n 2419 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n 2420 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n 2421 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n 2422 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n 2423 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n 2424 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n 2425 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n 2426 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n 2427 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n 2428 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n 2429 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n 2430 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n 2431 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n 2432 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n 2433 * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n 2434 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n 2435 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n 2436 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n 2437 * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n 2438 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n 2439 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n 2440 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n 2441 * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n 2442 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n 2443 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n 2444 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n 2445 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n 2446 * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n 2447 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n 2448 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n 2449 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n 2450 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n 2451 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n 2452 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n 2453 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc 2454 * @param HRTIMx High Resolution Timer instance 2455 * @param ADCTrig This parameter can be one of the following values: 2456 * @arg @ref LL_HRTIM_ADCTRIG_1 2457 * @arg @ref LL_HRTIM_ADCTRIG_2 2458 * @arg @ref LL_HRTIM_ADCTRIG_3 2459 * @arg @ref LL_HRTIM_ADCTRIG_4 2460 * @retval Src This parameter can be a combination of the following values: 2461 * 2462 * For ADC trigger 1 and ADC trigger 3 this parameter can be a 2463 * combination of the following values: 2464 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 2465 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 2466 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 2467 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 2468 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 2469 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 2470 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 2471 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 2472 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 2473 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 2474 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 2475 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 2476 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 2477 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 2478 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 2479 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 2480 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 2481 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 2482 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 2483 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 2484 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 2485 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 2486 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 2487 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 2488 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 2489 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 2490 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 2491 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 2492 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 2493 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 2494 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 2495 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 2496 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 2497 * 2498 * For ADC trigger 2 and ADC trigger 4 this parameter can be a 2499 * combination of the following values: 2500 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 2501 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 2502 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 2503 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 2504 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 2505 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 2506 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 2507 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 2508 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 2509 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 2510 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 2511 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 2512 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 2513 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 2514 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 2515 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 2516 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 2517 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 2518 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 2519 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 2520 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 2521 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 2522 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 2523 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 2524 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 2525 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 2526 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 2527 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 2528 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 2529 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 2530 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 2531 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 2532 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 2533 */ 2534 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) 2535 { 2536 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 2537 REG_OFFSET_TAB_ADCxR[ADCTrig])); 2538 return (*pReg); 2539 2540 } 2541 2542 2543 /** 2544 * @} 2545 */ 2546 2547 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control 2548 * @ingroup RTEMSBSPsARMSTM32H7 2549 * @{ 2550 */ 2551 2552 /** 2553 * @brief Enable timer(s) counter. 2554 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n 2555 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n 2556 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n 2557 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n 2558 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n 2559 * MDIER MCEN LL_HRTIM_TIM_CounterEnable 2560 * @param HRTIMx High Resolution Timer instance 2561 * @param Timers This parameter can be a combination of the following values: 2562 * @arg @ref LL_HRTIM_TIMER_MASTER 2563 * @arg @ref LL_HRTIM_TIMER_A 2564 * @arg @ref LL_HRTIM_TIMER_B 2565 * @arg @ref LL_HRTIM_TIMER_C 2566 * @arg @ref LL_HRTIM_TIMER_D 2567 * @arg @ref LL_HRTIM_TIMER_E 2568 * @retval None 2569 */ 2570 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 2571 { 2572 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers); 2573 } 2574 2575 /** 2576 * @brief Disable timer(s) counter. 2577 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n 2578 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n 2579 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n 2580 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n 2581 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n 2582 * MDIER MCEN LL_HRTIM_TIM_CounterDisable 2583 * @param HRTIMx High Resolution Timer instance 2584 * @param Timers This parameter can be a combination of the following values: 2585 * @arg @ref LL_HRTIM_TIMER_MASTER 2586 * @arg @ref LL_HRTIM_TIMER_A 2587 * @arg @ref LL_HRTIM_TIMER_B 2588 * @arg @ref LL_HRTIM_TIMER_C 2589 * @arg @ref LL_HRTIM_TIMER_D 2590 * @arg @ref LL_HRTIM_TIMER_E 2591 * @retval None 2592 */ 2593 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 2594 { 2595 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers); 2596 } 2597 2598 /** 2599 * @brief Indicate whether the timer counter is enabled. 2600 * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n 2601 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n 2602 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n 2603 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n 2604 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n 2605 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled 2606 * @param HRTIMx High Resolution Timer instance 2607 * @param Timer This parameter can be one of the following values: 2608 * @arg @ref LL_HRTIM_TIMER_MASTER 2609 * @arg @ref LL_HRTIM_TIMER_A 2610 * @arg @ref LL_HRTIM_TIMER_B 2611 * @arg @ref LL_HRTIM_TIMER_C 2612 * @arg @ref LL_HRTIM_TIMER_D 2613 * @arg @ref LL_HRTIM_TIMER_E 2614 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0). 2615 */ 2616 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2617 { 2618 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL); 2619 } 2620 2621 /** 2622 * @brief Set the timer clock prescaler ratio. 2623 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n 2624 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler 2625 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0]. 2626 * @note The prescaling ratio cannot be modified once the timer counter is enabled. 2627 * @param HRTIMx High Resolution Timer instance 2628 * @param Timer This parameter can be one of the following values: 2629 * @arg @ref LL_HRTIM_TIMER_MASTER 2630 * @arg @ref LL_HRTIM_TIMER_A 2631 * @arg @ref LL_HRTIM_TIMER_B 2632 * @arg @ref LL_HRTIM_TIMER_C 2633 * @arg @ref LL_HRTIM_TIMER_D 2634 * @arg @ref LL_HRTIM_TIMER_E 2635 * @param Prescaler This parameter can be one of the following values: 2636 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 2637 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 2638 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 2639 * @retval None 2640 */ 2641 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 2642 { 2643 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2644 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2645 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); 2646 } 2647 2648 /** 2649 * @brief Get the timer clock prescaler ratio 2650 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n 2651 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler 2652 * @param HRTIMx High Resolution Timer instance 2653 * @param Timer This parameter can be one of the following values: 2654 * @arg @ref LL_HRTIM_TIMER_MASTER 2655 * @arg @ref LL_HRTIM_TIMER_A 2656 * @arg @ref LL_HRTIM_TIMER_B 2657 * @arg @ref LL_HRTIM_TIMER_C 2658 * @arg @ref LL_HRTIM_TIMER_D 2659 * @arg @ref LL_HRTIM_TIMER_E 2660 * @retval Prescaler Returned value can be one of the following values: 2661 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 2662 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 2663 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 2664 */ 2665 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2666 { 2667 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2668 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2669 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); 2670 } 2671 2672 /** 2673 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable). 2674 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n 2675 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n 2676 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n 2677 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode 2678 * @param HRTIMx High Resolution Timer instance 2679 * @param Timer This parameter can be one of the following values: 2680 * @arg @ref LL_HRTIM_TIMER_MASTER 2681 * @arg @ref LL_HRTIM_TIMER_A 2682 * @arg @ref LL_HRTIM_TIMER_B 2683 * @arg @ref LL_HRTIM_TIMER_C 2684 * @arg @ref LL_HRTIM_TIMER_D 2685 * @arg @ref LL_HRTIM_TIMER_E 2686 * @param Mode This parameter can be one of the following values: 2687 * @arg @ref LL_HRTIM_MODE_CONTINUOUS 2688 * @arg @ref LL_HRTIM_MODE_SINGLESHOT 2689 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE 2690 * @retval None 2691 */ 2692 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) 2693 { 2694 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2695 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2696 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); 2697 } 2698 2699 /** 2700 * @brief Get the counter operating mode mode 2701 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n 2702 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n 2703 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n 2704 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode 2705 * @param HRTIMx High Resolution Timer instance 2706 * @param Timer This parameter can be one of the following values: 2707 * @arg @ref LL_HRTIM_TIMER_MASTER 2708 * @arg @ref LL_HRTIM_TIMER_A 2709 * @arg @ref LL_HRTIM_TIMER_B 2710 * @arg @ref LL_HRTIM_TIMER_C 2711 * @arg @ref LL_HRTIM_TIMER_D 2712 * @arg @ref LL_HRTIM_TIMER_E 2713 * @retval Mode Returned value can be one of the following values: 2714 * @arg @ref LL_HRTIM_MODE_CONTINUOUS 2715 * @arg @ref LL_HRTIM_MODE_SINGLESHOT 2716 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE 2717 */ 2718 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2719 { 2720 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2721 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2722 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); 2723 } 2724 2725 /** 2726 * @brief Enable the half duty-cycle mode. 2727 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n 2728 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode 2729 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR) 2730 * active register is automatically updated with HRTIM_MPER/2 2731 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written. 2732 * @param HRTIMx High Resolution Timer instance 2733 * @param Timer This parameter can be one of the following values: 2734 * @arg @ref LL_HRTIM_TIMER_MASTER 2735 * @arg @ref LL_HRTIM_TIMER_A 2736 * @arg @ref LL_HRTIM_TIMER_B 2737 * @arg @ref LL_HRTIM_TIMER_C 2738 * @arg @ref LL_HRTIM_TIMER_D 2739 * @arg @ref LL_HRTIM_TIMER_E 2740 * @retval None 2741 */ 2742 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2743 { 2744 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2745 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2746 SET_BIT(*pReg, HRTIM_MCR_HALF); 2747 } 2748 2749 /** 2750 * @brief Disable the half duty-cycle mode. 2751 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n 2752 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode 2753 * @param HRTIMx High Resolution Timer instance 2754 * @param Timer This parameter can be one of the following values: 2755 * @arg @ref LL_HRTIM_TIMER_MASTER 2756 * @arg @ref LL_HRTIM_TIMER_A 2757 * @arg @ref LL_HRTIM_TIMER_B 2758 * @arg @ref LL_HRTIM_TIMER_C 2759 * @arg @ref LL_HRTIM_TIMER_D 2760 * @arg @ref LL_HRTIM_TIMER_E 2761 * @retval None 2762 */ 2763 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2764 { 2765 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2766 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2767 CLEAR_BIT(*pReg, HRTIM_MCR_HALF); 2768 } 2769 2770 /** 2771 * @brief Indicate whether half duty-cycle mode is enabled for a given timer. 2772 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n 2773 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode 2774 * @param HRTIMx High Resolution Timer instance 2775 * @param Timer This parameter can be one of the following values: 2776 * @arg @ref LL_HRTIM_TIMER_MASTER 2777 * @arg @ref LL_HRTIM_TIMER_A 2778 * @arg @ref LL_HRTIM_TIMER_B 2779 * @arg @ref LL_HRTIM_TIMER_C 2780 * @arg @ref LL_HRTIM_TIMER_D 2781 * @arg @ref LL_HRTIM_TIMER_E 2782 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 2783 */ 2784 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2785 { 2786 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2787 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2788 2789 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL); 2790 } 2791 /** 2792 * @brief Enable the timer start when receiving a synchronization input event. 2793 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n 2794 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync 2795 * @param HRTIMx High Resolution Timer instance 2796 * @param Timer This parameter can be one of the following values: 2797 * @arg @ref LL_HRTIM_TIMER_MASTER 2798 * @arg @ref LL_HRTIM_TIMER_A 2799 * @arg @ref LL_HRTIM_TIMER_B 2800 * @arg @ref LL_HRTIM_TIMER_C 2801 * @arg @ref LL_HRTIM_TIMER_D 2802 * @arg @ref LL_HRTIM_TIMER_E 2803 * @retval None 2804 */ 2805 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2806 { 2807 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2808 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2809 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); 2810 } 2811 2812 /** 2813 * @brief Disable the timer start when receiving a synchronization input event. 2814 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n 2815 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync 2816 * @param HRTIMx High Resolution Timer instance 2817 * @param Timer This parameter can be one of the following values: 2818 * @arg @ref LL_HRTIM_TIMER_MASTER 2819 * @arg @ref LL_HRTIM_TIMER_A 2820 * @arg @ref LL_HRTIM_TIMER_B 2821 * @arg @ref LL_HRTIM_TIMER_C 2822 * @arg @ref LL_HRTIM_TIMER_D 2823 * @arg @ref LL_HRTIM_TIMER_E 2824 * @retval None 2825 */ 2826 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2827 { 2828 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2829 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2830 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); 2831 } 2832 2833 /** 2834 * @brief Indicate whether the timer start when receiving a synchronization input event. 2835 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n 2836 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync 2837 * @param HRTIMx High Resolution Timer instance 2838 * @param Timer This parameter can be one of the following values: 2839 * @arg @ref LL_HRTIM_TIMER_MASTER 2840 * @arg @ref LL_HRTIM_TIMER_A 2841 * @arg @ref LL_HRTIM_TIMER_B 2842 * @arg @ref LL_HRTIM_TIMER_C 2843 * @arg @ref LL_HRTIM_TIMER_D 2844 * @arg @ref LL_HRTIM_TIMER_E 2845 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 2846 */ 2847 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2848 { 2849 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2850 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2851 2852 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL); 2853 } 2854 2855 /** 2856 * @brief Enable the timer reset when receiving a synchronization input event. 2857 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n 2858 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync 2859 * @param HRTIMx High Resolution Timer instance 2860 * @param Timer This parameter can be one of the following values: 2861 * @arg @ref LL_HRTIM_TIMER_MASTER 2862 * @arg @ref LL_HRTIM_TIMER_A 2863 * @arg @ref LL_HRTIM_TIMER_B 2864 * @arg @ref LL_HRTIM_TIMER_C 2865 * @arg @ref LL_HRTIM_TIMER_D 2866 * @arg @ref LL_HRTIM_TIMER_E 2867 * @retval None 2868 */ 2869 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2870 { 2871 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2872 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2873 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); 2874 } 2875 2876 /** 2877 * @brief Disable the timer reset when receiving a synchronization input event. 2878 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n 2879 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync 2880 * @param HRTIMx High Resolution Timer instance 2881 * @param Timer This parameter can be one of the following values: 2882 * @arg @ref LL_HRTIM_TIMER_MASTER 2883 * @arg @ref LL_HRTIM_TIMER_A 2884 * @arg @ref LL_HRTIM_TIMER_B 2885 * @arg @ref LL_HRTIM_TIMER_C 2886 * @arg @ref LL_HRTIM_TIMER_D 2887 * @arg @ref LL_HRTIM_TIMER_E 2888 * @retval None 2889 */ 2890 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2891 { 2892 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2893 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2894 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); 2895 } 2896 2897 /** 2898 * @brief Indicate whether the timer reset when receiving a synchronization input event. 2899 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n 2900 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync 2901 * @param HRTIMx High Resolution Timer instance 2902 * @param Timer This parameter can be one of the following values: 2903 * @arg @ref LL_HRTIM_TIMER_MASTER 2904 * @arg @ref LL_HRTIM_TIMER_A 2905 * @arg @ref LL_HRTIM_TIMER_B 2906 * @arg @ref LL_HRTIM_TIMER_C 2907 * @arg @ref LL_HRTIM_TIMER_D 2908 * @arg @ref LL_HRTIM_TIMER_E 2909 * @retval None 2910 */ 2911 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2912 { 2913 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2914 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2915 2916 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL); 2917 } 2918 2919 /** 2920 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). 2921 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n 2922 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig 2923 * @param HRTIMx High Resolution Timer instance 2924 * @param Timer This parameter can be one of the following values: 2925 * @arg @ref LL_HRTIM_TIMER_MASTER 2926 * @arg @ref LL_HRTIM_TIMER_A 2927 * @arg @ref LL_HRTIM_TIMER_B 2928 * @arg @ref LL_HRTIM_TIMER_C 2929 * @arg @ref LL_HRTIM_TIMER_D 2930 * @arg @ref LL_HRTIM_TIMER_E 2931 * @param DACTrig This parameter can be one of the following values: 2932 * @arg @ref LL_HRTIM_DACTRIG_NONE 2933 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1 2934 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 2935 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 2936 * @retval None 2937 */ 2938 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) 2939 { 2940 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2941 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2942 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); 2943 } 2944 2945 /** 2946 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). 2947 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n 2948 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig 2949 * @param HRTIMx High Resolution Timer instance 2950 * @param Timer This parameter can be one of the following values: 2951 * @arg @ref LL_HRTIM_TIMER_MASTER 2952 * @arg @ref LL_HRTIM_TIMER_A 2953 * @arg @ref LL_HRTIM_TIMER_B 2954 * @arg @ref LL_HRTIM_TIMER_C 2955 * @arg @ref LL_HRTIM_TIMER_D 2956 * @arg @ref LL_HRTIM_TIMER_E 2957 * @retval DACTrig Returned value can be one of the following values: 2958 * @arg @ref LL_HRTIM_DACTRIG_NONE 2959 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1 2960 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 2961 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 2962 */ 2963 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2964 { 2965 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2966 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2967 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); 2968 } 2969 2970 /** 2971 * @brief Enable the timer registers preload mechanism. 2972 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n 2973 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload 2974 * @note When the preload mode is enabled, accessed registers are shadow registers. 2975 * Their content is transferred into the active register after an update request, 2976 * either software or synchronized with an event. 2977 * @param HRTIMx High Resolution Timer instance 2978 * @param Timer This parameter can be one of the following values: 2979 * @arg @ref LL_HRTIM_TIMER_MASTER 2980 * @arg @ref LL_HRTIM_TIMER_A 2981 * @arg @ref LL_HRTIM_TIMER_B 2982 * @arg @ref LL_HRTIM_TIMER_C 2983 * @arg @ref LL_HRTIM_TIMER_D 2984 * @arg @ref LL_HRTIM_TIMER_E 2985 * @retval None 2986 */ 2987 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 2988 { 2989 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 2990 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 2991 SET_BIT(*pReg, HRTIM_MCR_PREEN); 2992 } 2993 2994 /** 2995 * @brief Disable the timer registers preload mechanism. 2996 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n 2997 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload 2998 * @param HRTIMx High Resolution Timer instance 2999 * @param Timer This parameter can be one of the following values: 3000 * @arg @ref LL_HRTIM_TIMER_MASTER 3001 * @arg @ref LL_HRTIM_TIMER_A 3002 * @arg @ref LL_HRTIM_TIMER_B 3003 * @arg @ref LL_HRTIM_TIMER_C 3004 * @arg @ref LL_HRTIM_TIMER_D 3005 * @arg @ref LL_HRTIM_TIMER_E 3006 * @retval None 3007 */ 3008 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3009 { 3010 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3011 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3012 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); 3013 } 3014 3015 /** 3016 * @brief Indicate whether the timer registers preload mechanism is enabled. 3017 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n 3018 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload 3019 * @param HRTIMx High Resolution Timer instance 3020 * @param Timer This parameter can be one of the following values: 3021 * @arg @ref LL_HRTIM_TIMER_MASTER 3022 * @arg @ref LL_HRTIM_TIMER_A 3023 * @arg @ref LL_HRTIM_TIMER_B 3024 * @arg @ref LL_HRTIM_TIMER_C 3025 * @arg @ref LL_HRTIM_TIMER_D 3026 * @arg @ref LL_HRTIM_TIMER_E 3027 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 3028 */ 3029 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3030 { 3031 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3032 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3033 3034 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL); 3035 } 3036 3037 /** 3038 * @brief Set the timer register update trigger. 3039 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n 3040 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n 3041 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n 3042 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n 3043 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n 3044 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n 3045 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig 3046 * @param HRTIMx High Resolution Timer instance 3047 * @param Timer This parameter can be one of the following values: 3048 * @arg @ref LL_HRTIM_TIMER_MASTER 3049 * @arg @ref LL_HRTIM_TIMER_A 3050 * @arg @ref LL_HRTIM_TIMER_B 3051 * @arg @ref LL_HRTIM_TIMER_C 3052 * @arg @ref LL_HRTIM_TIMER_D 3053 * @arg @ref LL_HRTIM_TIMER_E 3054 * @param UpdateTrig This parameter can be one of the following values: 3055 * 3056 * For the master timer this parameter can be one of the following values: 3057 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 3058 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 3059 * 3060 * For timer A..E this parameter can be: 3061 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 3062 * or a combination of the following values: 3063 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER 3064 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A 3065 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B 3066 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C 3067 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D 3068 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E 3069 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 3070 * @arg @ref LL_HRTIM_UPDATETRIG_RESET 3071 * @retval None 3072 */ 3073 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) 3074 { 3075 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3076 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3077 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); 3078 } 3079 3080 /** 3081 * @brief Get the timer register update trigger. 3082 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n 3083 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n 3084 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n 3085 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n 3086 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n 3087 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig 3088 * @param HRTIMx High Resolution Timer instance 3089 * @param Timer This parameter can be one of the following values: 3090 * @arg @ref LL_HRTIM_TIMER_MASTER 3091 * @arg @ref LL_HRTIM_TIMER_A 3092 * @arg @ref LL_HRTIM_TIMER_B 3093 * @arg @ref LL_HRTIM_TIMER_C 3094 * @arg @ref LL_HRTIM_TIMER_D 3095 * @arg @ref LL_HRTIM_TIMER_E 3096 * @retval UpdateTrig Returned value can be one of the following values: 3097 * 3098 * For the master timer this parameter can be one of the following values: 3099 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 3100 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 3101 * 3102 * For timer A..E this parameter can be: 3103 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 3104 * or a combination of the following values: 3105 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER 3106 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A 3107 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B 3108 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C 3109 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D 3110 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E 3111 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 3112 * @arg @ref LL_HRTIM_UPDATETRIG_RESET 3113 */ 3114 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3115 { 3116 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3117 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3118 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); 3119 } 3120 3121 /** 3122 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])). 3123 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n 3124 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating 3125 * @param HRTIMx High Resolution Timer instance 3126 * @param Timer This parameter can be one of the following values: 3127 * @arg @ref LL_HRTIM_TIMER_MASTER 3128 * @arg @ref LL_HRTIM_TIMER_A 3129 * @arg @ref LL_HRTIM_TIMER_B 3130 * @arg @ref LL_HRTIM_TIMER_C 3131 * @arg @ref LL_HRTIM_TIMER_D 3132 * @arg @ref LL_HRTIM_TIMER_E 3133 * @param UpdateGating This parameter can be one of the following values: 3134 * 3135 * For the master timer this parameter can be one of the following values: 3136 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 3137 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 3138 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 3139 * 3140 * For the timer A..E this parameter can be one of the following values: 3141 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 3142 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 3143 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 3144 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1 3145 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2 3146 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3 3147 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE 3148 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE 3149 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE 3150 * @retval None 3151 */ 3152 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) 3153 { 3154 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3155 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3156 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); 3157 } 3158 3159 /** 3160 * @brief Get the timer registers update condition. 3161 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n 3162 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating 3163 * @param HRTIMx High Resolution Timer instance 3164 * @param Timer This parameter can be one of the following values: 3165 * @arg @ref LL_HRTIM_TIMER_MASTER 3166 * @arg @ref LL_HRTIM_TIMER_A 3167 * @arg @ref LL_HRTIM_TIMER_B 3168 * @arg @ref LL_HRTIM_TIMER_C 3169 * @arg @ref LL_HRTIM_TIMER_D 3170 * @arg @ref LL_HRTIM_TIMER_E 3171 * @retval UpdateGating Returned value can be one of the following values: 3172 * 3173 * For the master timer this parameter can be one of the following values: 3174 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 3175 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 3176 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 3177 * 3178 * For the timer A..E this parameter can be one of the following values: 3179 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 3180 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 3181 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 3182 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1 3183 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2 3184 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3 3185 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE 3186 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE 3187 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE 3188 */ 3189 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3190 { 3191 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3192 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 3193 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); 3194 } 3195 3196 /** 3197 * @brief Enable the push-pull mode. 3198 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode 3199 * @param HRTIMx High Resolution Timer instance 3200 * @param Timer This parameter can be one of the following values: 3201 * @arg @ref LL_HRTIM_TIMER_A 3202 * @arg @ref LL_HRTIM_TIMER_B 3203 * @arg @ref LL_HRTIM_TIMER_C 3204 * @arg @ref LL_HRTIM_TIMER_D 3205 * @arg @ref LL_HRTIM_TIMER_E 3206 * @retval None 3207 */ 3208 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3209 { 3210 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3211 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 3212 REG_OFFSET_TAB_TIMER[iTimer])); 3213 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); 3214 } 3215 3216 /** 3217 * @brief Disable the push-pull mode. 3218 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode 3219 * @param HRTIMx High Resolution Timer instance 3220 * @param Timer This parameter can be one of the following values: 3221 * @arg @ref LL_HRTIM_TIMER_A 3222 * @arg @ref LL_HRTIM_TIMER_B 3223 * @arg @ref LL_HRTIM_TIMER_C 3224 * @arg @ref LL_HRTIM_TIMER_D 3225 * @arg @ref LL_HRTIM_TIMER_E 3226 * @retval None 3227 */ 3228 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3229 { 3230 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3231 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 3232 REG_OFFSET_TAB_TIMER[iTimer])); 3233 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); 3234 } 3235 3236 /** 3237 * @brief Indicate whether the push-pull mode is enabled. 3238 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n 3239 * @param HRTIMx High Resolution Timer instance 3240 * @param Timer This parameter can be one of the following values: 3241 * @arg @ref LL_HRTIM_TIMER_A 3242 * @arg @ref LL_HRTIM_TIMER_B 3243 * @arg @ref LL_HRTIM_TIMER_C 3244 * @arg @ref LL_HRTIM_TIMER_D 3245 * @arg @ref LL_HRTIM_TIMER_E 3246 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0). 3247 */ 3248 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3249 { 3250 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3251 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 3252 REG_OFFSET_TAB_TIMER[iTimer])); 3253 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); 3254 } 3255 3256 /** 3257 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode). 3258 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n 3259 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode 3260 * @note In auto-delayed mode the compare match occurs independently from the timer counter value. 3261 * @param HRTIMx High Resolution Timer instance 3262 * @param Timer This parameter can be one of the following values: 3263 * @arg @ref LL_HRTIM_TIMER_A 3264 * @arg @ref LL_HRTIM_TIMER_B 3265 * @arg @ref LL_HRTIM_TIMER_C 3266 * @arg @ref LL_HRTIM_TIMER_D 3267 * @arg @ref LL_HRTIM_TIMER_E 3268 * @param CompareUnit This parameter can be one of the following values: 3269 * @arg @ref LL_HRTIM_COMPAREUNIT_2 3270 * @arg @ref LL_HRTIM_COMPAREUNIT_4 3271 * @param Mode This parameter can be one of the following values: 3272 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR 3273 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT 3274 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 3275 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 3276 * @retval None 3277 */ 3278 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, 3279 uint32_t Mode) 3280 { 3281 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 3283 REG_OFFSET_TAB_TIMER[iTimer])); 3284 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); 3285 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); 3286 } 3287 3288 /** 3289 * @brief Get the functioning mode of the compare unit. 3290 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n 3291 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode 3292 * @param HRTIMx High Resolution Timer instance 3293 * @param Timer This parameter can be one of the following values: 3294 * @arg @ref LL_HRTIM_TIMER_A 3295 * @arg @ref LL_HRTIM_TIMER_B 3296 * @arg @ref LL_HRTIM_TIMER_C 3297 * @arg @ref LL_HRTIM_TIMER_D 3298 * @arg @ref LL_HRTIM_TIMER_E 3299 * @param CompareUnit This parameter can be one of the following values: 3300 * @arg @ref LL_HRTIM_COMPAREUNIT_2 3301 * @arg @ref LL_HRTIM_COMPAREUNIT_4 3302 * @retval Mode Returned value can be one of the following values: 3303 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR 3304 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT 3305 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 3306 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 3307 */ 3308 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) 3309 { 3310 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3311 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 3312 REG_OFFSET_TAB_TIMER[iTimer])); 3313 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); 3314 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); 3315 } 3316 3317 /** 3318 * @brief Set the timer counter value. 3319 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n 3320 * CNTxR CNTx LL_HRTIM_TIM_SetCounter 3321 * @note This function can only be called when the timer is stopped. 3322 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least 3323 * significant bits of the counter are not significant. They cannot be 3324 * written and return 0 when read. 3325 * @note The timer behavior is not guaranteed if the counter value is set above 3326 * the period. 3327 * @param HRTIMx High Resolution Timer instance 3328 * @param Timer This parameter can be one of the following values: 3329 * @arg @ref LL_HRTIM_TIMER_MASTER 3330 * @arg @ref LL_HRTIM_TIMER_A 3331 * @arg @ref LL_HRTIM_TIMER_B 3332 * @arg @ref LL_HRTIM_TIMER_C 3333 * @arg @ref LL_HRTIM_TIMER_D 3334 * @arg @ref LL_HRTIM_TIMER_E 3335 * @param Counter Value between 0 and 0xFFFF 3336 * @retval None 3337 */ 3338 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) 3339 { 3340 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3341 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + 3342 REG_OFFSET_TAB_TIMER[iTimer])); 3343 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); 3344 } 3345 3346 /** 3347 * @brief Get actual timer counter value. 3348 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n 3349 * CNTxR CNTx LL_HRTIM_TIM_GetCounter 3350 * @param HRTIMx High Resolution Timer instance 3351 * @param Timer This parameter can be one of the following values: 3352 * @arg @ref LL_HRTIM_TIMER_MASTER 3353 * @arg @ref LL_HRTIM_TIMER_A 3354 * @arg @ref LL_HRTIM_TIMER_B 3355 * @arg @ref LL_HRTIM_TIMER_C 3356 * @arg @ref LL_HRTIM_TIMER_D 3357 * @arg @ref LL_HRTIM_TIMER_E 3358 * @retval Counter Value between 0 and 0xFFFF 3359 */ 3360 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3361 { 3362 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3363 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + 3364 REG_OFFSET_TAB_TIMER[iTimer])); 3365 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); 3366 } 3367 3368 /** 3369 * @brief Set the timer period value. 3370 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n 3371 * PERxR PERx LL_HRTIM_TIM_SetPeriod 3372 * @param HRTIMx High Resolution Timer instance 3373 * @param Timer This parameter can be one of the following values: 3374 * @arg @ref LL_HRTIM_TIMER_MASTER 3375 * @arg @ref LL_HRTIM_TIMER_A 3376 * @arg @ref LL_HRTIM_TIMER_B 3377 * @arg @ref LL_HRTIM_TIMER_C 3378 * @arg @ref LL_HRTIM_TIMER_D 3379 * @arg @ref LL_HRTIM_TIMER_E 3380 * @param Period Value between 0 and 0xFFFF 3381 * @retval None 3382 */ 3383 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) 3384 { 3385 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3386 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + 3387 REG_OFFSET_TAB_TIMER[iTimer])); 3388 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); 3389 } 3390 3391 /** 3392 * @brief Get actual timer period value. 3393 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n 3394 * PERxR PERx LL_HRTIM_TIM_GetPeriod 3395 * @param HRTIMx High Resolution Timer instance 3396 * @param Timer This parameter can be one of the following values: 3397 * @arg @ref LL_HRTIM_TIMER_MASTER 3398 * @arg @ref LL_HRTIM_TIMER_A 3399 * @arg @ref LL_HRTIM_TIMER_B 3400 * @arg @ref LL_HRTIM_TIMER_C 3401 * @arg @ref LL_HRTIM_TIMER_D 3402 * @arg @ref LL_HRTIM_TIMER_E 3403 * @retval Period Value between 0 and 0xFFFF 3404 */ 3405 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3406 { 3407 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3408 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + 3409 REG_OFFSET_TAB_TIMER[iTimer])); 3410 return (READ_BIT(*pReg, HRTIM_MPER_MPER)); 3411 } 3412 3413 /** 3414 * @brief Set the timer repetition period value. 3415 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n 3416 * REPxR REPx LL_HRTIM_TIM_SetRepetition 3417 * @param HRTIMx High Resolution Timer instance 3418 * @param Timer This parameter can be one of the following values: 3419 * @arg @ref LL_HRTIM_TIMER_MASTER 3420 * @arg @ref LL_HRTIM_TIMER_A 3421 * @arg @ref LL_HRTIM_TIMER_B 3422 * @arg @ref LL_HRTIM_TIMER_C 3423 * @arg @ref LL_HRTIM_TIMER_D 3424 * @arg @ref LL_HRTIM_TIMER_E 3425 * @param Repetition Value between 0 and 0xFF 3426 * @retval None 3427 */ 3428 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) 3429 { 3430 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3431 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + 3432 REG_OFFSET_TAB_TIMER[iTimer])); 3433 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); 3434 } 3435 3436 /** 3437 * @brief Get actual timer repetition period value. 3438 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n 3439 * REPxR REPx LL_HRTIM_TIM_GetRepetition 3440 * @param HRTIMx High Resolution Timer instance 3441 * @param Timer This parameter can be one of the following values: 3442 * @arg @ref LL_HRTIM_TIMER_MASTER 3443 * @arg @ref LL_HRTIM_TIMER_A 3444 * @arg @ref LL_HRTIM_TIMER_B 3445 * @arg @ref LL_HRTIM_TIMER_C 3446 * @arg @ref LL_HRTIM_TIMER_D 3447 * @arg @ref LL_HRTIM_TIMER_E 3448 * @retval Repetition Value between 0 and 0xFF 3449 */ 3450 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3451 { 3452 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3453 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + 3454 REG_OFFSET_TAB_TIMER[iTimer])); 3455 return (READ_BIT(*pReg, HRTIM_MREP_MREP)); 3456 } 3457 3458 /** 3459 * @brief Set the compare value of the compare unit 1. 3460 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n 3461 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1 3462 * @param HRTIMx High Resolution Timer instance 3463 * @param Timer This parameter can be one of the following values: 3464 * @arg @ref LL_HRTIM_TIMER_MASTER 3465 * @arg @ref LL_HRTIM_TIMER_A 3466 * @arg @ref LL_HRTIM_TIMER_B 3467 * @arg @ref LL_HRTIM_TIMER_C 3468 * @arg @ref LL_HRTIM_TIMER_D 3469 * @arg @ref LL_HRTIM_TIMER_E 3470 * @param CompareValue Compare value must be above or equal to 3 3471 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3472 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3473 * @retval None 3474 */ 3475 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 3476 { 3477 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3478 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + 3479 REG_OFFSET_TAB_TIMER[iTimer])); 3480 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); 3481 } 3482 3483 /** 3484 * @brief Get actual compare value of the compare unit 1. 3485 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n 3486 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1 3487 * @param HRTIMx High Resolution Timer instance 3488 * @param Timer This parameter can be one of the following values: 3489 * @arg @ref LL_HRTIM_TIMER_MASTER 3490 * @arg @ref LL_HRTIM_TIMER_A 3491 * @arg @ref LL_HRTIM_TIMER_B 3492 * @arg @ref LL_HRTIM_TIMER_C 3493 * @arg @ref LL_HRTIM_TIMER_D 3494 * @arg @ref LL_HRTIM_TIMER_E 3495 * @retval CompareValue Compare value must be above or equal to 3 3496 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3497 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3498 */ 3499 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3500 { 3501 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3502 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + 3503 REG_OFFSET_TAB_TIMER[iTimer])); 3504 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); 3505 } 3506 3507 /** 3508 * @brief Set the compare value of the compare unit 2. 3509 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n 3510 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2 3511 * @param HRTIMx High Resolution Timer instance 3512 * @param Timer This parameter can be one of the following values: 3513 * @arg @ref LL_HRTIM_TIMER_MASTER 3514 * @arg @ref LL_HRTIM_TIMER_A 3515 * @arg @ref LL_HRTIM_TIMER_B 3516 * @arg @ref LL_HRTIM_TIMER_C 3517 * @arg @ref LL_HRTIM_TIMER_D 3518 * @arg @ref LL_HRTIM_TIMER_E 3519 * @param CompareValue Compare value must be above or equal to 3 3520 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3521 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3522 * @retval None 3523 */ 3524 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 3525 { 3526 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3527 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + 3528 REG_OFFSET_TAB_TIMER[iTimer])); 3529 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); 3530 } 3531 3532 /** 3533 * @brief Get actual compare value of the compare unit 2. 3534 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n 3535 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n 3536 * @param HRTIMx High Resolution Timer instance 3537 * @param Timer This parameter can be one of the following values: 3538 * @arg @ref LL_HRTIM_TIMER_MASTER 3539 * @arg @ref LL_HRTIM_TIMER_A 3540 * @arg @ref LL_HRTIM_TIMER_B 3541 * @arg @ref LL_HRTIM_TIMER_C 3542 * @arg @ref LL_HRTIM_TIMER_D 3543 * @arg @ref LL_HRTIM_TIMER_E 3544 * @retval CompareValue Compare value must be above or equal to 3 3545 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3546 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3547 */ 3548 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3549 { 3550 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3551 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + 3552 REG_OFFSET_TAB_TIMER[iTimer])); 3553 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); 3554 } 3555 3556 /** 3557 * @brief Set the compare value of the compare unit 3. 3558 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n 3559 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3 3560 * @param HRTIMx High Resolution Timer instance 3561 * @param Timer This parameter can be one of the following values: 3562 * @arg @ref LL_HRTIM_TIMER_MASTER 3563 * @arg @ref LL_HRTIM_TIMER_A 3564 * @arg @ref LL_HRTIM_TIMER_B 3565 * @arg @ref LL_HRTIM_TIMER_C 3566 * @arg @ref LL_HRTIM_TIMER_D 3567 * @arg @ref LL_HRTIM_TIMER_E 3568 * @param CompareValue Compare value must be above or equal to 3 3569 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3570 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3571 * @retval None 3572 */ 3573 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 3574 { 3575 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3576 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + 3577 REG_OFFSET_TAB_TIMER[iTimer])); 3578 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); 3579 } 3580 3581 /** 3582 * @brief Get actual compare value of the compare unit 3. 3583 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n 3584 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3 3585 * @param HRTIMx High Resolution Timer instance 3586 * @param Timer This parameter can be one of the following values: 3587 * @arg @ref LL_HRTIM_TIMER_MASTER 3588 * @arg @ref LL_HRTIM_TIMER_A 3589 * @arg @ref LL_HRTIM_TIMER_B 3590 * @arg @ref LL_HRTIM_TIMER_C 3591 * @arg @ref LL_HRTIM_TIMER_D 3592 * @arg @ref LL_HRTIM_TIMER_E 3593 * @retval CompareValue Compare value must be above or equal to 3 3594 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3595 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3596 */ 3597 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3598 { 3599 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3600 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + 3601 REG_OFFSET_TAB_TIMER[iTimer])); 3602 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); 3603 } 3604 3605 /** 3606 * @brief Set the compare value of the compare unit 4. 3607 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n 3608 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4 3609 * @param HRTIMx High Resolution Timer instance 3610 * @param Timer This parameter can be one of the following values: 3611 * @arg @ref LL_HRTIM_TIMER_MASTER 3612 * @arg @ref LL_HRTIM_TIMER_A 3613 * @arg @ref LL_HRTIM_TIMER_B 3614 * @arg @ref LL_HRTIM_TIMER_C 3615 * @arg @ref LL_HRTIM_TIMER_D 3616 * @arg @ref LL_HRTIM_TIMER_E 3617 * @param CompareValue Compare value must be above or equal to 3 3618 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3619 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3620 * @retval None 3621 */ 3622 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 3623 { 3624 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3625 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + 3626 REG_OFFSET_TAB_TIMER[iTimer])); 3627 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); 3628 } 3629 3630 /** 3631 * @brief Get actual compare value of the compare unit 4. 3632 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n 3633 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4 3634 * @param HRTIMx High Resolution Timer instance 3635 * @param Timer This parameter can be one of the following values: 3636 * @arg @ref LL_HRTIM_TIMER_MASTER 3637 * @arg @ref LL_HRTIM_TIMER_A 3638 * @arg @ref LL_HRTIM_TIMER_B 3639 * @arg @ref LL_HRTIM_TIMER_C 3640 * @arg @ref LL_HRTIM_TIMER_D 3641 * @arg @ref LL_HRTIM_TIMER_E 3642 * @retval CompareValue Compare value must be above or equal to 3 3643 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 3644 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 3645 */ 3646 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3647 { 3648 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 3649 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + 3650 REG_OFFSET_TAB_TIMER[iTimer])); 3651 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); 3652 } 3653 3654 /** 3655 * @brief Set the reset trigger of a timer counter. 3656 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n 3657 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n 3658 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n 3659 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n 3660 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n 3661 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n 3662 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n 3663 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n 3664 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n 3665 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n 3666 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n 3667 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n 3668 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n 3669 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n 3670 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n 3671 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n 3672 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n 3673 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n 3674 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n 3675 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n 3676 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n 3677 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n 3678 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n 3679 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n 3680 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n 3681 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n 3682 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n 3683 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n 3684 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n 3685 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig 3686 * @note The reset of the timer counter can be triggered by up to 30 events 3687 * that can be selected among the following sources: 3688 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events). 3689 * @arg The master timer: Reset and Compare 1..4 (5 events). 3690 * @arg The external events EXTEVNT1..10 (10 events). 3691 * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events). 3692 * @param HRTIMx High Resolution Timer instance 3693 * @param Timer This parameter can be one of the following values: 3694 * @arg @ref LL_HRTIM_TIMER_A 3695 * @arg @ref LL_HRTIM_TIMER_B 3696 * @arg @ref LL_HRTIM_TIMER_C 3697 * @arg @ref LL_HRTIM_TIMER_D 3698 * @arg @ref LL_HRTIM_TIMER_E 3699 * @param ResetTrig This parameter can be a combination of the following values: 3700 * @arg @ref LL_HRTIM_RESETTRIG_NONE 3701 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE 3702 * @arg @ref LL_HRTIM_RESETTRIG_CMP2 3703 * @arg @ref LL_HRTIM_RESETTRIG_CMP4 3704 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER 3705 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1 3706 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2 3707 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3 3708 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4 3709 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1 3710 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2 3711 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3 3712 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4 3713 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5 3714 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6 3715 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7 3716 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8 3717 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9 3718 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10 3719 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1 3720 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2 3721 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4 3722 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1 3723 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2 3724 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4 3725 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1 3726 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2 3727 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4 3728 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1 3729 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2 3730 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 3731 * @retval None 3732 */ 3733 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) 3734 { 3735 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3736 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + 3737 REG_OFFSET_TAB_TIMER[iTimer])); 3738 WRITE_REG(*pReg, ResetTrig); 3739 } 3740 3741 /** 3742 * @brief Get actual reset trigger of a timer counter. 3743 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n 3744 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n 3745 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n 3746 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n 3747 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n 3748 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n 3749 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n 3750 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n 3751 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n 3752 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n 3753 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n 3754 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n 3755 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n 3756 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n 3757 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n 3758 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n 3759 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n 3760 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n 3761 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n 3762 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n 3763 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n 3764 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n 3765 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n 3766 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n 3767 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n 3768 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n 3769 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n 3770 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n 3771 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n 3772 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig 3773 * @param HRTIMx High Resolution Timer instance 3774 * @param Timer This parameter can be one of the following values: 3775 * @arg @ref LL_HRTIM_TIMER_A 3776 * @arg @ref LL_HRTIM_TIMER_B 3777 * @arg @ref LL_HRTIM_TIMER_C 3778 * @arg @ref LL_HRTIM_TIMER_D 3779 * @arg @ref LL_HRTIM_TIMER_E 3780 * @retval ResetTrig Returned value can be one of the following values: 3781 * @arg @ref LL_HRTIM_RESETTRIG_NONE 3782 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE 3783 * @arg @ref LL_HRTIM_RESETTRIG_CMP2 3784 * @arg @ref LL_HRTIM_RESETTRIG_CMP4 3785 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER 3786 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1 3787 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2 3788 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3 3789 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4 3790 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1 3791 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2 3792 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3 3793 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4 3794 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5 3795 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6 3796 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7 3797 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8 3798 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9 3799 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10 3800 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1 3801 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2 3802 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4 3803 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1 3804 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2 3805 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4 3806 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1 3807 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2 3808 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4 3809 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1 3810 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2 3811 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 3812 */ 3813 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3814 { 3815 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3816 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + 3817 REG_OFFSET_TAB_TIMER[iTimer])); 3818 return (READ_REG(*pReg)); 3819 } 3820 3821 /** 3822 * @brief Get captured value for capture unit 1. 3823 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1 3824 * @param HRTIMx High Resolution Timer instance 3825 * @param Timer This parameter can be one of the following values: 3826 * @arg @ref LL_HRTIM_TIMER_A 3827 * @arg @ref LL_HRTIM_TIMER_B 3828 * @arg @ref LL_HRTIM_TIMER_C 3829 * @arg @ref LL_HRTIM_TIMER_D 3830 * @arg @ref LL_HRTIM_TIMER_E 3831 * @retval Captured value 3832 */ 3833 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3834 { 3835 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3836 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + 3837 REG_OFFSET_TAB_TIMER[iTimer])); 3838 return (READ_REG(*pReg)); 3839 } 3840 3841 /** 3842 * @brief Get captured value for capture unit 2. 3843 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2 3844 * @param HRTIMx High Resolution Timer instance 3845 * @param Timer This parameter can be one of the following values: 3846 * @arg @ref LL_HRTIM_TIMER_A 3847 * @arg @ref LL_HRTIM_TIMER_B 3848 * @arg @ref LL_HRTIM_TIMER_C 3849 * @arg @ref LL_HRTIM_TIMER_D 3850 * @arg @ref LL_HRTIM_TIMER_E 3851 * @retval Captured value 3852 */ 3853 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 3854 { 3855 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3856 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + 3857 REG_OFFSET_TAB_TIMER[iTimer])); 3858 return (READ_REG(*pReg)); 3859 } 3860 3861 /** 3862 * @brief Set the trigger of a capture unit for a given timer. 3863 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n 3864 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n 3865 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n 3866 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n 3867 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n 3868 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n 3869 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n 3870 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n 3871 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n 3872 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n 3873 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n 3874 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n 3875 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n 3876 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n 3877 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n 3878 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n 3879 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n 3880 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n 3881 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 3882 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 3883 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n 3884 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n 3885 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 3886 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 3887 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n 3888 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n 3889 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 3890 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 3891 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n 3892 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n 3893 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n 3894 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig 3895 * @param HRTIMx High Resolution Timer instance 3896 * @param Timer This parameter can be one of the following values: 3897 * @arg @ref LL_HRTIM_TIMER_A 3898 * @arg @ref LL_HRTIM_TIMER_B 3899 * @arg @ref LL_HRTIM_TIMER_C 3900 * @arg @ref LL_HRTIM_TIMER_D 3901 * @arg @ref LL_HRTIM_TIMER_E 3902 * @param CaptureUnit This parameter can be one of the following values: 3903 * @arg @ref LL_HRTIM_CAPTUREUNIT_1 3904 * @arg @ref LL_HRTIM_CAPTUREUNIT_2 3905 * @param CaptureTrig This parameter can be a combination of the following values: 3906 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE 3907 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE 3908 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1 3909 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2 3910 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3 3911 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4 3912 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5 3913 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6 3914 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7 3915 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8 3916 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9 3917 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10 3918 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET 3919 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET 3920 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1 3921 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2 3922 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET 3923 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET 3924 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1 3925 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2 3926 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET 3927 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET 3928 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1 3929 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2 3930 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET 3931 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET 3932 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1 3933 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2 3934 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET 3935 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET 3936 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1 3937 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 3938 * @retval None 3939 */ 3940 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, 3941 uint32_t CaptureTrig) 3942 { 3943 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 3944 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + 3945 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); 3946 WRITE_REG(*pReg, CaptureTrig); 3947 } 3948 3949 /** 3950 * @brief Get actual trigger of a capture unit for a given timer. 3951 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n 3952 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n 3953 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n 3954 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n 3955 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n 3956 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n 3957 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n 3958 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n 3959 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n 3960 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n 3961 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n 3962 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n 3963 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n 3964 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n 3965 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n 3966 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n 3967 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n 3968 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n 3969 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 3970 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 3971 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n 3972 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n 3973 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 3974 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 3975 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n 3976 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n 3977 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 3978 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 3979 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n 3980 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n 3981 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n 3982 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig 3983 * @param HRTIMx High Resolution Timer instance 3984 * @param Timer This parameter can be one of the following values: 3985 * @arg @ref LL_HRTIM_TIMER_A 3986 * @arg @ref LL_HRTIM_TIMER_B 3987 * @arg @ref LL_HRTIM_TIMER_C 3988 * @arg @ref LL_HRTIM_TIMER_D 3989 * @arg @ref LL_HRTIM_TIMER_E 3990 * @param CaptureUnit This parameter can be one of the following values: 3991 * @arg @ref LL_HRTIM_CAPTUREUNIT_1 3992 * @arg @ref LL_HRTIM_CAPTUREUNIT_2 3993 * @retval CaptureTrig This parameter can be a combination of the following values: 3994 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE 3995 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE 3996 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1 3997 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2 3998 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3 3999 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4 4000 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5 4001 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6 4002 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7 4003 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8 4004 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9 4005 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10 4006 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET 4007 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET 4008 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1 4009 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2 4010 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET 4011 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET 4012 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1 4013 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2 4014 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET 4015 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET 4016 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1 4017 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2 4018 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET 4019 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET 4020 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1 4021 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2 4022 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET 4023 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET 4024 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1 4025 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 4026 */ 4027 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) 4028 { 4029 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4030 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + 4031 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); 4032 return (READ_REG(*pReg)); 4033 } 4034 4035 /** 4036 * @brief Enable deadtime insertion for a given timer. 4037 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime 4038 * @param HRTIMx High Resolution Timer instance 4039 * @param Timer This parameter can be one of the following values: 4040 * @arg @ref LL_HRTIM_TIMER_A 4041 * @arg @ref LL_HRTIM_TIMER_B 4042 * @arg @ref LL_HRTIM_TIMER_C 4043 * @arg @ref LL_HRTIM_TIMER_D 4044 * @arg @ref LL_HRTIM_TIMER_E 4045 * @retval None 4046 */ 4047 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4048 { 4049 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4050 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4051 REG_OFFSET_TAB_TIMER[iTimer])); 4052 SET_BIT(*pReg, HRTIM_OUTR_DTEN); 4053 } 4054 4055 /** 4056 * @brief Disable deadtime insertion for a given timer. 4057 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime 4058 * @param HRTIMx High Resolution Timer instance 4059 * @param Timer This parameter can be one of the following values: 4060 * @arg @ref LL_HRTIM_TIMER_A 4061 * @arg @ref LL_HRTIM_TIMER_B 4062 * @arg @ref LL_HRTIM_TIMER_C 4063 * @arg @ref LL_HRTIM_TIMER_D 4064 * @arg @ref LL_HRTIM_TIMER_E 4065 * @retval None 4066 */ 4067 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4068 { 4069 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4070 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4071 REG_OFFSET_TAB_TIMER[iTimer])); 4072 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); 4073 } 4074 4075 /** 4076 * @brief Indicate whether deadtime insertion is enabled for a given timer. 4077 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime 4078 * @param HRTIMx High Resolution Timer instance 4079 * @param Timer This parameter can be one of the following values: 4080 * @arg @ref LL_HRTIM_TIMER_A 4081 * @arg @ref LL_HRTIM_TIMER_B 4082 * @arg @ref LL_HRTIM_TIMER_C 4083 * @arg @ref LL_HRTIM_TIMER_D 4084 * @arg @ref LL_HRTIM_TIMER_E 4085 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0). 4086 */ 4087 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4088 { 4089 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4090 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4091 REG_OFFSET_TAB_TIMER[iTimer])); 4092 4093 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); 4094 } 4095 4096 /** 4097 * @brief Set the delayed protection (DLYPRT) mode. 4098 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n 4099 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode 4100 * @note This function must be called prior enabling the delayed protection 4101 * @note Balanced Idle mode is only available in push-pull mode 4102 * @param HRTIMx High Resolution Timer instance 4103 * @param Timer This parameter can be one of the following values: 4104 * @arg @ref LL_HRTIM_TIMER_A 4105 * @arg @ref LL_HRTIM_TIMER_B 4106 * @arg @ref LL_HRTIM_TIMER_C 4107 * @arg @ref LL_HRTIM_TIMER_D 4108 * @arg @ref LL_HRTIM_TIMER_E 4109 * @param DLYPRTMode Delayed protection (DLYPRT) mode 4110 * 4111 * For timers A, B and C this parameter can be one of the following values: 4112 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 4113 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 4114 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 4115 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6 4116 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 4117 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 4118 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 4119 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7 4120 * 4121 * For timers D and E this parameter can be one of the following values: 4122 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 4123 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 4124 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 4125 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8 4126 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 4127 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 4128 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 4129 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 4130 * @retval None 4131 */ 4132 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) 4133 { 4134 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4135 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4136 REG_OFFSET_TAB_TIMER[iTimer])); 4137 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); 4138 } 4139 4140 /** 4141 * @brief Get the delayed protection (DLYPRT) mode. 4142 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n 4143 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode 4144 * @param HRTIMx High Resolution Timer instance 4145 * @param Timer This parameter can be one of the following values: 4146 * @arg @ref LL_HRTIM_TIMER_A 4147 * @arg @ref LL_HRTIM_TIMER_B 4148 * @arg @ref LL_HRTIM_TIMER_C 4149 * @arg @ref LL_HRTIM_TIMER_D 4150 * @arg @ref LL_HRTIM_TIMER_E 4151 * @retval DLYPRTMode Delayed protection (DLYPRT) mode 4152 * 4153 * For timers A, B and C this parameter can be one of the following values: 4154 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 4155 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 4156 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 4157 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6 4158 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 4159 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 4160 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 4161 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7 4162 * 4163 * For timers D and E this parameter can be one of the following values: 4164 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 4165 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 4166 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 4167 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8 4168 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 4169 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 4170 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 4171 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 4172 */ 4173 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4174 { 4175 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4176 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4177 REG_OFFSET_TAB_TIMER[iTimer])); 4178 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); 4179 } 4180 4181 /** 4182 * @brief Enable delayed protection (DLYPRT) for a given timer. 4183 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT 4184 * @note This function must not be called once the concerned timer is enabled 4185 * @param HRTIMx High Resolution Timer instance 4186 * @param Timer This parameter can be one of the following values: 4187 * @arg @ref LL_HRTIM_TIMER_A 4188 * @arg @ref LL_HRTIM_TIMER_B 4189 * @arg @ref LL_HRTIM_TIMER_C 4190 * @arg @ref LL_HRTIM_TIMER_D 4191 * @arg @ref LL_HRTIM_TIMER_E 4192 * @retval None 4193 */ 4194 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4195 { 4196 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4197 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4198 REG_OFFSET_TAB_TIMER[iTimer])); 4199 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); 4200 } 4201 4202 /** 4203 * @brief Disable delayed protection (DLYPRT) for a given timer. 4204 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT 4205 * @note This function must not be called once the concerned timer is enabled 4206 * @param HRTIMx High Resolution Timer instance 4207 * @param Timer This parameter can be one of the following values: 4208 * @arg @ref LL_HRTIM_TIMER_A 4209 * @arg @ref LL_HRTIM_TIMER_B 4210 * @arg @ref LL_HRTIM_TIMER_C 4211 * @arg @ref LL_HRTIM_TIMER_D 4212 * @arg @ref LL_HRTIM_TIMER_E 4213 * @retval None 4214 */ 4215 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4216 { 4217 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4218 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4219 REG_OFFSET_TAB_TIMER[iTimer])); 4220 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); 4221 } 4222 4223 /** 4224 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer. 4225 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT 4226 * @param HRTIMx High Resolution Timer instance 4227 * @param Timer This parameter can be one of the following values: 4228 * @arg @ref LL_HRTIM_TIMER_A 4229 * @arg @ref LL_HRTIM_TIMER_B 4230 * @arg @ref LL_HRTIM_TIMER_C 4231 * @arg @ref LL_HRTIM_TIMER_D 4232 * @arg @ref LL_HRTIM_TIMER_E 4233 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0). 4234 */ 4235 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4236 { 4237 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4238 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 4239 REG_OFFSET_TAB_TIMER[iTimer])); 4240 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); 4241 } 4242 4243 /** 4244 * @brief Enable the fault channel(s) for a given timer. 4245 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n 4246 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n 4247 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n 4248 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n 4249 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault 4250 * @param HRTIMx High Resolution Timer instance 4251 * @param Timer This parameter can be one of the following values: 4252 * @arg @ref LL_HRTIM_TIMER_A 4253 * @arg @ref LL_HRTIM_TIMER_B 4254 * @arg @ref LL_HRTIM_TIMER_C 4255 * @arg @ref LL_HRTIM_TIMER_D 4256 * @arg @ref LL_HRTIM_TIMER_E 4257 * @param Faults This parameter can be a combination of the following values: 4258 * @arg @ref LL_HRTIM_FAULT_1 4259 * @arg @ref LL_HRTIM_FAULT_2 4260 * @arg @ref LL_HRTIM_FAULT_3 4261 * @arg @ref LL_HRTIM_FAULT_4 4262 * @arg @ref LL_HRTIM_FAULT_5 4263 * @retval None 4264 */ 4265 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) 4266 { 4267 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4268 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 4269 REG_OFFSET_TAB_TIMER[iTimer])); 4270 SET_BIT(*pReg, Faults); 4271 } 4272 4273 /** 4274 * @brief Disable the fault channel(s) for a given timer. 4275 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n 4276 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n 4277 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n 4278 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n 4279 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault 4280 * @param HRTIMx High Resolution Timer instance 4281 * @param Timer This parameter can be one of the following values: 4282 * @arg @ref LL_HRTIM_TIMER_A 4283 * @arg @ref LL_HRTIM_TIMER_B 4284 * @arg @ref LL_HRTIM_TIMER_C 4285 * @arg @ref LL_HRTIM_TIMER_D 4286 * @arg @ref LL_HRTIM_TIMER_E 4287 * @param Faults This parameter can be a combination of the following values: 4288 * @arg @ref LL_HRTIM_FAULT_1 4289 * @arg @ref LL_HRTIM_FAULT_2 4290 * @arg @ref LL_HRTIM_FAULT_3 4291 * @arg @ref LL_HRTIM_FAULT_4 4292 * @arg @ref LL_HRTIM_FAULT_5 4293 * @retval None 4294 */ 4295 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) 4296 { 4297 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4298 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 4299 REG_OFFSET_TAB_TIMER[iTimer])); 4300 CLEAR_BIT(*pReg, Faults); 4301 } 4302 4303 /** 4304 * @brief Indicate whether the fault channel is enabled for a given timer. 4305 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n 4306 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n 4307 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n 4308 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n 4309 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault 4310 * @param HRTIMx High Resolution Timer instance 4311 * @param Timer This parameter can be one of the following values: 4312 * @arg @ref LL_HRTIM_TIMER_A 4313 * @arg @ref LL_HRTIM_TIMER_B 4314 * @arg @ref LL_HRTIM_TIMER_C 4315 * @arg @ref LL_HRTIM_TIMER_D 4316 * @arg @ref LL_HRTIM_TIMER_E 4317 * @param Fault This parameter can be one of the following values: 4318 * @arg @ref LL_HRTIM_FAULT_1 4319 * @arg @ref LL_HRTIM_FAULT_2 4320 * @arg @ref LL_HRTIM_FAULT_3 4321 * @arg @ref LL_HRTIM_FAULT_4 4322 * @arg @ref LL_HRTIM_FAULT_5 4323 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0). 4324 */ 4325 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) 4326 { 4327 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4328 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 4329 REG_OFFSET_TAB_TIMER[iTimer])); 4330 4331 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); 4332 } 4333 4334 /** 4335 * @brief Lock the fault conditioning set-up for a given timer. 4336 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault 4337 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset 4338 * @param HRTIMx High Resolution Timer instance 4339 * @param Timer This parameter can be one of the following values: 4340 * @arg @ref LL_HRTIM_TIMER_A 4341 * @arg @ref LL_HRTIM_TIMER_B 4342 * @arg @ref LL_HRTIM_TIMER_C 4343 * @arg @ref LL_HRTIM_TIMER_D 4344 * @arg @ref LL_HRTIM_TIMER_E 4345 * @retval None 4346 */ 4347 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4348 { 4349 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4350 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 4351 REG_OFFSET_TAB_TIMER[iTimer])); 4352 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); 4353 } 4354 4355 /** 4356 * @brief Define how the timer behaves during a burst mode operation. 4357 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n 4358 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n 4359 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n 4360 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n 4361 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n 4362 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption 4363 * @note This function must not be called when the burst mode is enabled 4364 * @param HRTIMx High Resolution Timer instance 4365 * @param Timer This parameter can be one of the following values: 4366 * @arg @ref LL_HRTIM_TIMER_MASTER 4367 * @arg @ref LL_HRTIM_TIMER_A 4368 * @arg @ref LL_HRTIM_TIMER_B 4369 * @arg @ref LL_HRTIM_TIMER_C 4370 * @arg @ref LL_HRTIM_TIMER_D 4371 * @arg @ref LL_HRTIM_TIMER_E 4372 * @param BurtsModeOption This parameter can be one of the following values: 4373 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK 4374 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER 4375 * @retval None 4376 */ 4377 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption) 4378 { 4379 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); 4380 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer); 4381 } 4382 4383 /** 4384 * @brief Retrieve how the timer behaves during a burst mode operation. 4385 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n 4386 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n 4387 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n 4388 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n 4389 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n 4390 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption 4391 * @param HRTIMx High Resolution Timer instance 4392 * @param Timer This parameter can be one of the following values: 4393 * @arg @ref LL_HRTIM_TIMER_MASTER 4394 * @arg @ref LL_HRTIM_TIMER_A 4395 * @arg @ref LL_HRTIM_TIMER_B 4396 * @arg @ref LL_HRTIM_TIMER_C 4397 * @arg @ref LL_HRTIM_TIMER_D 4398 * @arg @ref LL_HRTIM_TIMER_E 4399 * @retval BurtsMode This parameter can be one of the following values: 4400 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK 4401 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER 4402 */ 4403 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4404 { 4405 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); 4406 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); 4407 } 4408 4409 /** 4410 * @brief Program which registers are to be written by Burst DMA transfers. 4411 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n 4412 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n 4413 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n 4414 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n 4415 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n 4416 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n 4417 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n 4418 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n 4419 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n 4420 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n 4421 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n 4422 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n 4423 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n 4424 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n 4425 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n 4426 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n 4427 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n 4428 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n 4429 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n 4430 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n 4431 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n 4432 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n 4433 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n 4434 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n 4435 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n 4436 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n 4437 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n 4438 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n 4439 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n 4440 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA 4441 * @param HRTIMx High Resolution Timer instance 4442 * @param Timer This parameter can be one of the following values: 4443 * @arg @ref LL_HRTIM_TIMER_MASTER 4444 * @arg @ref LL_HRTIM_TIMER_A 4445 * @arg @ref LL_HRTIM_TIMER_B 4446 * @arg @ref LL_HRTIM_TIMER_C 4447 * @arg @ref LL_HRTIM_TIMER_D 4448 * @arg @ref LL_HRTIM_TIMER_E 4449 * @param Registers Registers to be updated by the DMA request 4450 * 4451 * For Master timer this parameter can be can be a combination of the following values: 4452 * @arg @ref LL_HRTIM_BURSTDMA_NONE 4453 * @arg @ref LL_HRTIM_BURSTDMA_MCR 4454 * @arg @ref LL_HRTIM_BURSTDMA_MICR 4455 * @arg @ref LL_HRTIM_BURSTDMA_MDIER 4456 * @arg @ref LL_HRTIM_BURSTDMA_MCNT 4457 * @arg @ref LL_HRTIM_BURSTDMA_MPER 4458 * @arg @ref LL_HRTIM_BURSTDMA_MREP 4459 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1 4460 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2 4461 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3 4462 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4 4463 * 4464 * For Timers A..E this parameter can be can be a combination of the following values: 4465 * @arg @ref LL_HRTIM_BURSTDMA_NONE 4466 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR 4467 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR 4468 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER 4469 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT 4470 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER 4471 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP 4472 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1 4473 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2 4474 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3 4475 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4 4476 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR 4477 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R 4478 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R 4479 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R 4480 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R 4481 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1 4482 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2 4483 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR 4484 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR 4485 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR 4486 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR 4487 * @retval None 4488 */ 4489 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) 4490 { 4491 4492 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 4493 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer))); 4494 WRITE_REG(*pReg, Registers); 4495 } 4496 4497 /** 4498 * @brief Indicate on which output the signal is currently applied. 4499 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus 4500 * @note Only significant when the timer operates in push-pull mode. 4501 * @param HRTIMx High Resolution Timer instance 4502 * @param Timer This parameter can be one of the following values: 4503 * @arg @ref LL_HRTIM_TIMER_A 4504 * @arg @ref LL_HRTIM_TIMER_B 4505 * @arg @ref LL_HRTIM_TIMER_C 4506 * @arg @ref LL_HRTIM_TIMER_D 4507 * @arg @ref LL_HRTIM_TIMER_E 4508 * @retval CPPSTAT This parameter can be one of the following values: 4509 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1 4510 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2 4511 */ 4512 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4513 { 4514 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 4515 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 4516 REG_OFFSET_TAB_TIMER[iTimer])); 4517 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); 4518 } 4519 4520 /** 4521 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered. 4522 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus 4523 * @param HRTIMx High Resolution Timer instance 4524 * @param Timer This parameter can be one of the following values: 4525 * @arg @ref LL_HRTIM_TIMER_A 4526 * @arg @ref LL_HRTIM_TIMER_B 4527 * @arg @ref LL_HRTIM_TIMER_C 4528 * @arg @ref LL_HRTIM_TIMER_D 4529 * @arg @ref LL_HRTIM_TIMER_E 4530 * @retval IPPSTAT This parameter can be one of the following values: 4531 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1 4532 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2 4533 */ 4534 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4535 { 4536 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 4537 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 4538 REG_OFFSET_TAB_TIMER[iTimer])); 4539 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); 4540 } 4541 4542 /** 4543 * @brief Set the event filter for a given timer. 4544 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n 4545 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n 4546 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n 4547 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n 4548 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n 4549 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n 4550 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n 4551 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n 4552 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n 4553 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter 4554 * @note This function must not be called when the timer counter is enabled. 4555 * @param HRTIMx High Resolution Timer instance 4556 * @param Timer This parameter can be one of the following values: 4557 * @arg @ref LL_HRTIM_TIMER_A 4558 * @arg @ref LL_HRTIM_TIMER_B 4559 * @arg @ref LL_HRTIM_TIMER_C 4560 * @arg @ref LL_HRTIM_TIMER_D 4561 * @arg @ref LL_HRTIM_TIMER_E 4562 * @param Event This parameter can be one of the following values: 4563 * @arg @ref LL_HRTIM_EVENT_1 4564 * @arg @ref LL_HRTIM_EVENT_2 4565 * @arg @ref LL_HRTIM_EVENT_3 4566 * @arg @ref LL_HRTIM_EVENT_4 4567 * @arg @ref LL_HRTIM_EVENT_5 4568 * @arg @ref LL_HRTIM_EVENT_6 4569 * @arg @ref LL_HRTIM_EVENT_7 4570 * @arg @ref LL_HRTIM_EVENT_8 4571 * @arg @ref LL_HRTIM_EVENT_9 4572 * @arg @ref LL_HRTIM_EVENT_10 4573 * @param Filter This parameter can be one of the following values: 4574 * @arg @ref LL_HRTIM_EEFLTR_NONE 4575 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1 4576 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2 4577 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3 4578 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4 4579 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1 4580 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2 4581 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3 4582 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4 4583 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5 4584 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6 4585 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7 4586 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8 4587 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2 4588 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 4589 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM 4590 4591 * @retval None 4592 */ 4593 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) 4594 { 4595 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 4596 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 4597 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 4598 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 4599 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); 4600 } 4601 4602 /** 4603 * @brief Get actual event filter settings for a given timer. 4604 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n 4605 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n 4606 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n 4607 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n 4608 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n 4609 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n 4610 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n 4611 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n 4612 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n 4613 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter 4614 * @param HRTIMx High Resolution Timer instance 4615 * @param Timer This parameter can be one of the following values: 4616 * @arg @ref LL_HRTIM_TIMER_A 4617 * @arg @ref LL_HRTIM_TIMER_B 4618 * @arg @ref LL_HRTIM_TIMER_C 4619 * @arg @ref LL_HRTIM_TIMER_D 4620 * @arg @ref LL_HRTIM_TIMER_E 4621 * @param Event This parameter can be one of the following values: 4622 * @arg @ref LL_HRTIM_EVENT_1 4623 * @arg @ref LL_HRTIM_EVENT_2 4624 * @arg @ref LL_HRTIM_EVENT_3 4625 * @arg @ref LL_HRTIM_EVENT_4 4626 * @arg @ref LL_HRTIM_EVENT_5 4627 * @arg @ref LL_HRTIM_EVENT_6 4628 * @arg @ref LL_HRTIM_EVENT_7 4629 * @arg @ref LL_HRTIM_EVENT_8 4630 * @arg @ref LL_HRTIM_EVENT_9 4631 * @arg @ref LL_HRTIM_EVENT_10 4632 * @retval Filter This parameter can be one of the following values: 4633 * @arg @ref LL_HRTIM_EEFLTR_NONE 4634 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1 4635 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2 4636 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3 4637 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4 4638 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1 4639 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2 4640 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3 4641 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4 4642 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5 4643 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6 4644 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7 4645 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8 4646 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2 4647 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 4648 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM 4649 */ 4650 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) 4651 { 4652 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 4653 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 4654 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 4655 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 4656 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); 4657 } 4658 4659 /** 4660 * @brief Enable or disable event latch mechanism for a given timer. 4661 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4662 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4663 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4664 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4665 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4666 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4667 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4668 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4669 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 4670 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus 4671 * @note This function must not be called when the timer counter is enabled. 4672 * @param HRTIMx High Resolution Timer instance 4673 * @param Timer This parameter can be one of the following values: 4674 * @arg @ref LL_HRTIM_TIMER_A 4675 * @arg @ref LL_HRTIM_TIMER_B 4676 * @arg @ref LL_HRTIM_TIMER_C 4677 * @arg @ref LL_HRTIM_TIMER_D 4678 * @arg @ref LL_HRTIM_TIMER_E 4679 * @param Event This parameter can be one of the following values: 4680 * @arg @ref LL_HRTIM_EVENT_1 4681 * @arg @ref LL_HRTIM_EVENT_2 4682 * @arg @ref LL_HRTIM_EVENT_3 4683 * @arg @ref LL_HRTIM_EVENT_4 4684 * @arg @ref LL_HRTIM_EVENT_5 4685 * @arg @ref LL_HRTIM_EVENT_6 4686 * @arg @ref LL_HRTIM_EVENT_7 4687 * @arg @ref LL_HRTIM_EVENT_8 4688 * @arg @ref LL_HRTIM_EVENT_9 4689 * @arg @ref LL_HRTIM_EVENT_10 4690 * @param LatchStatus This parameter can be one of the following values: 4691 * @arg @ref LL_HRTIM_EELATCH_DISABLED 4692 * @arg @ref LL_HRTIM_EELATCH_ENABLED 4693 * @retval None 4694 */ 4695 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, 4696 uint32_t LatchStatus) 4697 { 4698 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 4699 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 4700 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 4701 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 4702 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); 4703 } 4704 4705 /** 4706 * @brief Get actual event latch status for a given timer. 4707 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4708 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4709 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4710 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4711 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4712 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4713 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4714 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4715 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 4716 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus 4717 * @param HRTIMx High Resolution Timer instance 4718 * @param Timer This parameter can be one of the following values: 4719 * @arg @ref LL_HRTIM_TIMER_A 4720 * @arg @ref LL_HRTIM_TIMER_B 4721 * @arg @ref LL_HRTIM_TIMER_C 4722 * @arg @ref LL_HRTIM_TIMER_D 4723 * @arg @ref LL_HRTIM_TIMER_E 4724 * @param Event This parameter can be one of the following values: 4725 * @arg @ref LL_HRTIM_EVENT_1 4726 * @arg @ref LL_HRTIM_EVENT_2 4727 * @arg @ref LL_HRTIM_EVENT_3 4728 * @arg @ref LL_HRTIM_EVENT_4 4729 * @arg @ref LL_HRTIM_EVENT_5 4730 * @arg @ref LL_HRTIM_EVENT_6 4731 * @arg @ref LL_HRTIM_EVENT_7 4732 * @arg @ref LL_HRTIM_EVENT_8 4733 * @arg @ref LL_HRTIM_EVENT_9 4734 * @arg @ref LL_HRTIM_EVENT_10 4735 * @retval LatchStatus This parameter can be one of the following values: 4736 * @arg @ref LL_HRTIM_EELATCH_DISABLED 4737 * @arg @ref LL_HRTIM_EELATCH_ENABLED 4738 */ 4739 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) 4740 { 4741 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 4742 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 4743 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 4744 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 4745 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); 4746 } 4747 4748 /** 4749 * @} 4750 */ 4751 4752 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration 4753 * @ingroup RTEMSBSPsARMSTM32H7 4754 * @{ 4755 */ 4756 4757 /** 4758 * @brief Configure the dead time insertion feature for a given timer. 4759 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n 4760 * DTxR SDTF LL_HRTIM_DT_Config\n 4761 * DTxR SDRT LL_HRTIM_DT_Config 4762 * @param HRTIMx High Resolution Timer instance 4763 * @param Timer This parameter can be one of the following values: 4764 * @arg @ref LL_HRTIM_TIMER_A 4765 * @arg @ref LL_HRTIM_TIMER_B 4766 * @arg @ref LL_HRTIM_TIMER_C 4767 * @arg @ref LL_HRTIM_TIMER_D 4768 * @arg @ref LL_HRTIM_TIMER_E 4769 * @param Configuration This parameter must be a combination of all the following values: 4770 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16 4771 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE 4772 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE 4773 * @retval None 4774 */ 4775 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) 4776 { 4777 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4778 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4779 REG_OFFSET_TAB_TIMER[iTimer])); 4780 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); 4781 } 4782 4783 /** 4784 * @brief Set the deadtime prescaler value. 4785 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler 4786 * @param HRTIMx High Resolution Timer instance 4787 * @param Timer This parameter can be one of the following values: 4788 * @arg @ref LL_HRTIM_TIMER_A 4789 * @arg @ref LL_HRTIM_TIMER_B 4790 * @arg @ref LL_HRTIM_TIMER_C 4791 * @arg @ref LL_HRTIM_TIMER_D 4792 * @arg @ref LL_HRTIM_TIMER_E 4793 * @param Prescaler This parameter can be one of the following values: 4794 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 4795 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4 4796 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2 4797 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1 4798 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2 4799 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4 4800 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 4801 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 4802 * @retval None 4803 */ 4804 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 4805 { 4806 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4807 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4808 REG_OFFSET_TAB_TIMER[iTimer])); 4809 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); 4810 } 4811 4812 /** 4813 * @brief Get actual deadtime prescaler value. 4814 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler 4815 * @param HRTIMx High Resolution Timer instance 4816 * @param Timer This parameter can be one of the following values: 4817 * @arg @ref LL_HRTIM_TIMER_A 4818 * @arg @ref LL_HRTIM_TIMER_B 4819 * @arg @ref LL_HRTIM_TIMER_C 4820 * @arg @ref LL_HRTIM_TIMER_D 4821 * @arg @ref LL_HRTIM_TIMER_E 4822 * @retval Prescaler This parameter can be one of the following values: 4823 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 4824 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4 4825 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2 4826 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1 4827 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2 4828 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4 4829 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 4830 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 4831 */ 4832 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4833 { 4834 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4835 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4836 REG_OFFSET_TAB_TIMER[iTimer])); 4837 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); 4838 } 4839 4840 /** 4841 * @brief Set the deadtime rising value. 4842 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue 4843 * @param HRTIMx High Resolution Timer instance 4844 * @param Timer This parameter can be one of the following values: 4845 * @arg @ref LL_HRTIM_TIMER_A 4846 * @arg @ref LL_HRTIM_TIMER_B 4847 * @arg @ref LL_HRTIM_TIMER_C 4848 * @arg @ref LL_HRTIM_TIMER_D 4849 * @arg @ref LL_HRTIM_TIMER_E 4850 * @param RisingValue Value between 0 and 0x1FF 4851 * @retval None 4852 */ 4853 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) 4854 { 4855 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4856 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4857 REG_OFFSET_TAB_TIMER[iTimer])); 4858 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); 4859 } 4860 4861 /** 4862 * @brief Get actual deadtime rising value. 4863 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue 4864 * @param HRTIMx High Resolution Timer instance 4865 * @param Timer This parameter can be one of the following values: 4866 * @arg @ref LL_HRTIM_TIMER_A 4867 * @arg @ref LL_HRTIM_TIMER_B 4868 * @arg @ref LL_HRTIM_TIMER_C 4869 * @arg @ref LL_HRTIM_TIMER_D 4870 * @arg @ref LL_HRTIM_TIMER_E 4871 * @retval RisingValue Value between 0 and 0x1FF 4872 */ 4873 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4874 { 4875 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4876 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4877 REG_OFFSET_TAB_TIMER[iTimer])); 4878 return (READ_BIT(*pReg, HRTIM_DTR_DTR)); 4879 } 4880 4881 /** 4882 * @brief Set the deadtime sign on rising edge. 4883 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign 4884 * @param HRTIMx High Resolution Timer instance 4885 * @param Timer This parameter can be one of the following values: 4886 * @arg @ref LL_HRTIM_TIMER_A 4887 * @arg @ref LL_HRTIM_TIMER_B 4888 * @arg @ref LL_HRTIM_TIMER_C 4889 * @arg @ref LL_HRTIM_TIMER_D 4890 * @arg @ref LL_HRTIM_TIMER_E 4891 * @param RisingSign This parameter can be one of the following values: 4892 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE 4893 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE 4894 * @retval None 4895 */ 4896 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) 4897 { 4898 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4899 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4900 REG_OFFSET_TAB_TIMER[iTimer])); 4901 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); 4902 } 4903 4904 /** 4905 * @brief Get actual deadtime sign on rising edge. 4906 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign 4907 * @param HRTIMx High Resolution Timer instance 4908 * @param Timer This parameter can be one of the following values: 4909 * @arg @ref LL_HRTIM_TIMER_A 4910 * @arg @ref LL_HRTIM_TIMER_B 4911 * @arg @ref LL_HRTIM_TIMER_C 4912 * @arg @ref LL_HRTIM_TIMER_D 4913 * @arg @ref LL_HRTIM_TIMER_E 4914 * @retval RisingSign This parameter can be one of the following values: 4915 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE 4916 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE 4917 */ 4918 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4919 { 4920 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4921 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4922 REG_OFFSET_TAB_TIMER[iTimer])); 4923 return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); 4924 } 4925 4926 /** 4927 * @brief Set the deadime falling value. 4928 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue 4929 * @param HRTIMx High Resolution Timer instance 4930 * @param Timer This parameter can be one of the following values: 4931 * @arg @ref LL_HRTIM_TIMER_A 4932 * @arg @ref LL_HRTIM_TIMER_B 4933 * @arg @ref LL_HRTIM_TIMER_C 4934 * @arg @ref LL_HRTIM_TIMER_D 4935 * @arg @ref LL_HRTIM_TIMER_E 4936 * @param FallingValue Value between 0 and 0x1FF 4937 * @retval None 4938 */ 4939 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) 4940 { 4941 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4942 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4943 REG_OFFSET_TAB_TIMER[iTimer])); 4944 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); 4945 } 4946 4947 /** 4948 * @brief Get actual deadtime falling value 4949 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue 4950 * @param HRTIMx High Resolution Timer instance 4951 * @param Timer This parameter can be one of the following values: 4952 * @arg @ref LL_HRTIM_TIMER_A 4953 * @arg @ref LL_HRTIM_TIMER_B 4954 * @arg @ref LL_HRTIM_TIMER_C 4955 * @arg @ref LL_HRTIM_TIMER_D 4956 * @arg @ref LL_HRTIM_TIMER_E 4957 * @retval FallingValue Value between 0 and 0x1FF 4958 */ 4959 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 4960 { 4961 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4962 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4963 REG_OFFSET_TAB_TIMER[iTimer])); 4964 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); 4965 } 4966 4967 /** 4968 * @brief Set the deadtime sign on falling edge. 4969 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign 4970 * @param HRTIMx High Resolution Timer instance 4971 * @param Timer This parameter can be one of the following values: 4972 * @arg @ref LL_HRTIM_TIMER_A 4973 * @arg @ref LL_HRTIM_TIMER_B 4974 * @arg @ref LL_HRTIM_TIMER_C 4975 * @arg @ref LL_HRTIM_TIMER_D 4976 * @arg @ref LL_HRTIM_TIMER_E 4977 * @param FallingSign This parameter can be one of the following values: 4978 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE 4979 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE 4980 * @retval None 4981 */ 4982 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) 4983 { 4984 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 4985 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 4986 REG_OFFSET_TAB_TIMER[iTimer])); 4987 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); 4988 } 4989 4990 /** 4991 * @brief Get actual deadtime sign on falling edge. 4992 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign 4993 * @param HRTIMx High Resolution Timer instance 4994 * @param Timer This parameter can be one of the following values: 4995 * @arg @ref LL_HRTIM_TIMER_A 4996 * @arg @ref LL_HRTIM_TIMER_B 4997 * @arg @ref LL_HRTIM_TIMER_C 4998 * @arg @ref LL_HRTIM_TIMER_D 4999 * @arg @ref LL_HRTIM_TIMER_E 5000 * @retval FallingSign This parameter can be one of the following values: 5001 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE 5002 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE 5003 */ 5004 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5005 { 5006 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5007 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 5008 REG_OFFSET_TAB_TIMER[iTimer])); 5009 return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); 5010 } 5011 5012 /** 5013 * @brief Lock the deadtime value and sign on rising edge. 5014 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising 5015 * @param HRTIMx High Resolution Timer instance 5016 * @param Timer This parameter can be one of the following values: 5017 * @arg @ref LL_HRTIM_TIMER_A 5018 * @arg @ref LL_HRTIM_TIMER_B 5019 * @arg @ref LL_HRTIM_TIMER_C 5020 * @arg @ref LL_HRTIM_TIMER_D 5021 * @arg @ref LL_HRTIM_TIMER_E 5022 * @retval None 5023 */ 5024 __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5025 { 5026 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5027 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 5028 REG_OFFSET_TAB_TIMER[iTimer])); 5029 SET_BIT(*pReg, HRTIM_DTR_DTRLK); 5030 } 5031 5032 /** 5033 * @brief Lock the deadtime sign on rising edge. 5034 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign 5035 * @param HRTIMx High Resolution Timer instance 5036 * @param Timer This parameter can be one of the following values: 5037 * @arg @ref LL_HRTIM_TIMER_A 5038 * @arg @ref LL_HRTIM_TIMER_B 5039 * @arg @ref LL_HRTIM_TIMER_C 5040 * @arg @ref LL_HRTIM_TIMER_D 5041 * @arg @ref LL_HRTIM_TIMER_E 5042 * @retval None 5043 */ 5044 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5045 { 5046 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5047 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 5048 REG_OFFSET_TAB_TIMER[iTimer])); 5049 SET_BIT(*pReg, HRTIM_DTR_DTRSLK); 5050 } 5051 5052 /** 5053 * @brief Lock the deadtime value and sign on falling edge. 5054 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling 5055 * @param HRTIMx High Resolution Timer instance 5056 * @param Timer This parameter can be one of the following values: 5057 * @arg @ref LL_HRTIM_TIMER_A 5058 * @arg @ref LL_HRTIM_TIMER_B 5059 * @arg @ref LL_HRTIM_TIMER_C 5060 * @arg @ref LL_HRTIM_TIMER_D 5061 * @arg @ref LL_HRTIM_TIMER_E 5062 * @retval None 5063 */ 5064 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5065 { 5066 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5067 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 5068 REG_OFFSET_TAB_TIMER[iTimer])); 5069 SET_BIT(*pReg, HRTIM_DTR_DTFLK); 5070 } 5071 5072 /** 5073 * @brief Lock the deadtime sign on falling edge. 5074 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign 5075 * @param HRTIMx High Resolution Timer instance 5076 * @param Timer This parameter can be one of the following values: 5077 * @arg @ref LL_HRTIM_TIMER_A 5078 * @arg @ref LL_HRTIM_TIMER_B 5079 * @arg @ref LL_HRTIM_TIMER_C 5080 * @arg @ref LL_HRTIM_TIMER_D 5081 * @arg @ref LL_HRTIM_TIMER_E 5082 * @retval None 5083 */ 5084 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5085 { 5086 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5087 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 5088 REG_OFFSET_TAB_TIMER[iTimer])); 5089 SET_BIT(*pReg, HRTIM_DTR_DTFSLK); 5090 } 5091 5092 /** 5093 * @} 5094 */ 5095 5096 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration 5097 * @ingroup RTEMSBSPsARMSTM32H7 5098 * @{ 5099 */ 5100 5101 /** 5102 * @brief Configure the chopper stage for a given timer. 5103 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n 5104 * CHPxR CARDTY LL_HRTIM_CHP_Config\n 5105 * CHPxR STRTPW LL_HRTIM_CHP_Config 5106 * @note This function must not be called if the chopper mode is already 5107 * enabled for one of the timer outputs. 5108 * @param HRTIMx High Resolution Timer instance 5109 * @param Timer This parameter can be one of the following values: 5110 * @arg @ref LL_HRTIM_TIMER_A 5111 * @arg @ref LL_HRTIM_TIMER_B 5112 * @arg @ref LL_HRTIM_TIMER_C 5113 * @arg @ref LL_HRTIM_TIMER_D 5114 * @arg @ref LL_HRTIM_TIMER_E 5115 * @param Configuration This parameter must be a combination of all the following values: 5116 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256 5117 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875 5118 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256 5119 * @retval None 5120 */ 5121 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) 5122 { 5123 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5124 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5125 REG_OFFSET_TAB_TIMER[iTimer])); 5126 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); 5127 } 5128 5129 /** 5130 * @brief Set prescaler determining the carrier frequency to be added on top 5131 * of the timer output signals when chopper mode is enabled. 5132 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler 5133 * @note This function must not be called if the chopper mode is already 5134 * enabled for one of the timer outputs. 5135 * @param HRTIMx High Resolution Timer instance 5136 * @param Timer This parameter can be one of the following values: 5137 * @arg @ref LL_HRTIM_TIMER_A 5138 * @arg @ref LL_HRTIM_TIMER_B 5139 * @arg @ref LL_HRTIM_TIMER_C 5140 * @arg @ref LL_HRTIM_TIMER_D 5141 * @arg @ref LL_HRTIM_TIMER_E 5142 * @param Prescaler This parameter can be one of the following values: 5143 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 5144 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32 5145 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48 5146 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64 5147 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80 5148 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96 5149 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112 5150 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128 5151 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144 5152 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160 5153 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176 5154 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192 5155 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208 5156 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224 5157 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 5158 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 5159 * @retval None 5160 */ 5161 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 5162 { 5163 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5164 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5165 REG_OFFSET_TAB_TIMER[iTimer])); 5166 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); 5167 } 5168 5169 /** 5170 * @brief Get actual chopper stage prescaler value. 5171 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler 5172 * @param HRTIMx High Resolution Timer instance 5173 * @param Timer This parameter can be one of the following values: 5174 * @arg @ref LL_HRTIM_TIMER_A 5175 * @arg @ref LL_HRTIM_TIMER_B 5176 * @arg @ref LL_HRTIM_TIMER_C 5177 * @arg @ref LL_HRTIM_TIMER_D 5178 * @arg @ref LL_HRTIM_TIMER_E 5179 * @retval Prescaler This parameter can be one of the following values: 5180 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 5181 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32 5182 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48 5183 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64 5184 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80 5185 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96 5186 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112 5187 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128 5188 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144 5189 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160 5190 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176 5191 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192 5192 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208 5193 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224 5194 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 5195 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 5196 */ 5197 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5198 { 5199 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5200 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5201 REG_OFFSET_TAB_TIMER[iTimer])); 5202 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); 5203 } 5204 5205 /** 5206 * @brief Set the chopper duty cycle. 5207 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle 5208 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 5209 * @note This function must not be called if the chopper mode is already 5210 * enabled for one of the timer outputs. 5211 * @param HRTIMx High Resolution Timer instance 5212 * @param Timer This parameter can be one of the following values: 5213 * @arg @ref LL_HRTIM_TIMER_A 5214 * @arg @ref LL_HRTIM_TIMER_B 5215 * @arg @ref LL_HRTIM_TIMER_C 5216 * @arg @ref LL_HRTIM_TIMER_D 5217 * @arg @ref LL_HRTIM_TIMER_E 5218 * @param DutyCycle This parameter can be one of the following values: 5219 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 5220 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125 5221 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250 5222 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375 5223 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500 5224 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625 5225 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 5226 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 5227 * @retval None 5228 */ 5229 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) 5230 { 5231 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5232 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5233 REG_OFFSET_TAB_TIMER[iTimer])); 5234 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); 5235 } 5236 5237 /** 5238 * @brief Get actual chopper duty cycle. 5239 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle 5240 * @param HRTIMx High Resolution Timer instance 5241 * @param Timer This parameter can be one of the following values: 5242 * @arg @ref LL_HRTIM_TIMER_A 5243 * @arg @ref LL_HRTIM_TIMER_B 5244 * @arg @ref LL_HRTIM_TIMER_C 5245 * @arg @ref LL_HRTIM_TIMER_D 5246 * @arg @ref LL_HRTIM_TIMER_E 5247 * @retval DutyCycle This parameter can be one of the following values: 5248 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 5249 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125 5250 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250 5251 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375 5252 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500 5253 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625 5254 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 5255 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 5256 */ 5257 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5258 { 5259 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5260 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5261 REG_OFFSET_TAB_TIMER[iTimer])); 5262 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); 5263 } 5264 5265 /** 5266 * @brief Set the start pulse width. 5267 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth 5268 * @note This function must not be called if the chopper mode is already 5269 * enabled for one of the timer outputs. 5270 * @param HRTIMx High Resolution Timer instance 5271 * @param Timer This parameter can be one of the following values: 5272 * @arg @ref LL_HRTIM_TIMER_A 5273 * @arg @ref LL_HRTIM_TIMER_B 5274 * @arg @ref LL_HRTIM_TIMER_C 5275 * @arg @ref LL_HRTIM_TIMER_D 5276 * @arg @ref LL_HRTIM_TIMER_E 5277 * @param PulseWidth This parameter can be one of the following values: 5278 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 5279 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32 5280 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48 5281 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64 5282 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80 5283 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96 5284 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112 5285 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128 5286 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144 5287 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160 5288 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176 5289 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192 5290 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208 5291 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224 5292 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 5293 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 5294 * @retval None 5295 */ 5296 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) 5297 { 5298 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5299 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5300 REG_OFFSET_TAB_TIMER[iTimer])); 5301 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); 5302 } 5303 5304 /** 5305 * @brief Get actual start pulse width. 5306 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth 5307 * @param HRTIMx High Resolution Timer instance 5308 * @param Timer This parameter can be one of the following values: 5309 * @arg @ref LL_HRTIM_TIMER_A 5310 * @arg @ref LL_HRTIM_TIMER_B 5311 * @arg @ref LL_HRTIM_TIMER_C 5312 * @arg @ref LL_HRTIM_TIMER_D 5313 * @arg @ref LL_HRTIM_TIMER_E 5314 * @retval PulseWidth This parameter can be one of the following values: 5315 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 5316 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32 5317 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48 5318 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64 5319 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80 5320 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96 5321 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112 5322 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128 5323 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144 5324 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160 5325 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176 5326 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192 5327 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208 5328 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224 5329 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 5330 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 5331 */ 5332 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 5333 { 5334 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 5335 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 5336 REG_OFFSET_TAB_TIMER[iTimer])); 5337 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); 5338 } 5339 5340 /** 5341 * @} 5342 */ 5343 5344 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management 5345 * @ingroup RTEMSBSPsARMSTM32H7 5346 * @{ 5347 */ 5348 5349 /** 5350 * @brief Set the timer output set source. 5351 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n 5352 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n 5353 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n 5354 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 5355 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 5356 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 5357 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 5358 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n 5359 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 5360 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 5361 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 5362 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 5363 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 5364 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 5365 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 5366 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 5367 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 5368 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 5369 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 5370 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 5371 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 5372 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 5373 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 5374 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 5375 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 5376 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 5377 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 5378 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 5379 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 5380 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 5381 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n 5382 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n 5383 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n 5384 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n 5385 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n 5386 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 5387 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 5388 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 5389 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 5390 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n 5391 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 5392 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 5393 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 5394 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 5395 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 5396 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 5397 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 5398 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 5399 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 5400 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 5401 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 5402 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 5403 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 5404 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 5405 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 5406 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 5407 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 5408 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 5409 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 5410 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 5411 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 5412 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 5413 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n 5414 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc 5415 * @param HRTIMx High Resolution Timer instance 5416 * @param Output This parameter can be one of the following values: 5417 * @arg @ref LL_HRTIM_OUTPUT_TA1 5418 * @arg @ref LL_HRTIM_OUTPUT_TA2 5419 * @arg @ref LL_HRTIM_OUTPUT_TB1 5420 * @arg @ref LL_HRTIM_OUTPUT_TB2 5421 * @arg @ref LL_HRTIM_OUTPUT_TC1 5422 * @arg @ref LL_HRTIM_OUTPUT_TC2 5423 * @arg @ref LL_HRTIM_OUTPUT_TD1 5424 * @arg @ref LL_HRTIM_OUTPUT_TD2 5425 * @arg @ref LL_HRTIM_OUTPUT_TE1 5426 * @arg @ref LL_HRTIM_OUTPUT_TE2 5427 * @param SetSrc This parameter can be a combination of the following values: 5428 * @arg @ref LL_HRTIM_CROSSBAR_NONE 5429 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 5430 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 5431 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 5432 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 5433 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 5434 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 5435 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 5436 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 5437 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 5438 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 5439 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 5440 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 5441 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 5442 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 5443 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 5444 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 5445 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 5446 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 5447 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 5448 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 5449 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 5450 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 5451 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 5452 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 5453 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 5454 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 5455 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 5456 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 5457 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 5458 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 5459 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 5460 * @retval None 5461 */ 5462 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) 5463 { 5464 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5465 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 5466 REG_OFFSET_TAB_SETxR[iOutput])); 5467 WRITE_REG(*pReg, SetSrc); 5468 } 5469 5470 /** 5471 * @brief Get the timer output set source. 5472 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n 5473 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n 5474 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n 5475 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 5476 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 5477 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 5478 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 5479 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n 5480 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 5481 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 5482 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 5483 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 5484 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 5485 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 5486 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 5487 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 5488 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 5489 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 5490 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 5491 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 5492 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 5493 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 5494 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 5495 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 5496 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 5497 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 5498 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 5499 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 5500 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 5501 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 5502 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n 5503 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n 5504 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n 5505 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n 5506 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n 5507 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 5508 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 5509 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 5510 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 5511 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n 5512 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 5513 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 5514 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 5515 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 5516 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 5517 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 5518 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 5519 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 5520 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 5521 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 5522 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 5523 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 5524 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 5525 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 5526 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 5527 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 5528 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 5529 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 5530 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 5531 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 5532 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 5533 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 5534 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n 5535 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc 5536 * @param HRTIMx High Resolution Timer instance 5537 * @param Output This parameter can be one of the following values: 5538 * @arg @ref LL_HRTIM_OUTPUT_TA1 5539 * @arg @ref LL_HRTIM_OUTPUT_TA2 5540 * @arg @ref LL_HRTIM_OUTPUT_TB1 5541 * @arg @ref LL_HRTIM_OUTPUT_TB2 5542 * @arg @ref LL_HRTIM_OUTPUT_TC1 5543 * @arg @ref LL_HRTIM_OUTPUT_TC2 5544 * @arg @ref LL_HRTIM_OUTPUT_TD1 5545 * @arg @ref LL_HRTIM_OUTPUT_TD2 5546 * @arg @ref LL_HRTIM_OUTPUT_TE1 5547 * @arg @ref LL_HRTIM_OUTPUT_TE2 5548 * @retval SetSrc This parameter can be a combination of the following values: 5549 * @arg @ref LL_HRTIM_CROSSBAR_NONE 5550 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 5551 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 5552 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 5553 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 5554 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 5555 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 5556 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 5557 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 5558 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 5559 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 5560 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 5561 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 5562 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 5563 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 5564 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 5565 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 5566 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 5567 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 5568 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 5569 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 5570 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 5571 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 5572 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 5573 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 5574 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 5575 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 5576 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 5577 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 5578 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 5579 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 5580 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 5581 */ 5582 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 5583 { 5584 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5585 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 5586 REG_OFFSET_TAB_SETxR[iOutput])); 5587 return (uint32_t) READ_REG(*pReg); 5588 } 5589 5590 /** 5591 * @brief Set the timer output reset source. 5592 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n 5593 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n 5594 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n 5595 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 5596 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 5597 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 5598 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 5599 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n 5600 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 5601 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 5602 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 5603 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 5604 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 5605 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 5606 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 5607 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 5608 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 5609 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 5610 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 5611 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 5612 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 5613 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 5614 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 5615 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 5616 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 5617 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 5618 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 5619 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 5620 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 5621 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 5622 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n 5623 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n 5624 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n 5625 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n 5626 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n 5627 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 5628 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 5629 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 5630 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 5631 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n 5632 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 5633 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 5634 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 5635 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 5636 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 5637 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 5638 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 5639 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 5640 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 5641 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 5642 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 5643 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 5644 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 5645 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 5646 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 5647 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 5648 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 5649 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 5650 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 5651 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 5652 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 5653 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 5654 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n 5655 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc 5656 * @param HRTIMx High Resolution Timer instance 5657 * @param Output This parameter can be one of the following values: 5658 * @arg @ref LL_HRTIM_OUTPUT_TA1 5659 * @arg @ref LL_HRTIM_OUTPUT_TA2 5660 * @arg @ref LL_HRTIM_OUTPUT_TB1 5661 * @arg @ref LL_HRTIM_OUTPUT_TB2 5662 * @arg @ref LL_HRTIM_OUTPUT_TC1 5663 * @arg @ref LL_HRTIM_OUTPUT_TC2 5664 * @arg @ref LL_HRTIM_OUTPUT_TD1 5665 * @arg @ref LL_HRTIM_OUTPUT_TD2 5666 * @arg @ref LL_HRTIM_OUTPUT_TE1 5667 * @arg @ref LL_HRTIM_OUTPUT_TE2 5668 * @param ResetSrc This parameter can be a combination of the following values: 5669 * @arg @ref LL_HRTIM_CROSSBAR_NONE 5670 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 5671 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 5672 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 5673 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 5674 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 5675 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 5676 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 5677 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 5678 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 5679 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 5680 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 5681 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 5682 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 5683 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 5684 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 5685 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 5686 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 5687 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 5688 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 5689 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 5690 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 5691 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 5692 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 5693 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 5694 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 5695 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 5696 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 5697 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 5698 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 5699 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 5700 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 5701 * @retval None 5702 */ 5703 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) 5704 { 5705 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5706 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + 5707 REG_OFFSET_TAB_SETxR[iOutput])); 5708 WRITE_REG(*pReg, ResetSrc); 5709 } 5710 5711 /** 5712 * @brief Get the timer output set source. 5713 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n 5714 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n 5715 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n 5716 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 5717 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 5718 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 5719 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 5720 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n 5721 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 5722 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 5723 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 5724 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 5725 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 5726 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 5727 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 5728 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 5729 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 5730 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 5731 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 5732 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 5733 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 5734 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 5735 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 5736 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 5737 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 5738 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 5739 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 5740 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 5741 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 5742 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 5743 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n 5744 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n 5745 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n 5746 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n 5747 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n 5748 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 5749 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 5750 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 5751 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 5752 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n 5753 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 5754 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 5755 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 5756 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 5757 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 5758 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 5759 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 5760 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 5761 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 5762 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 5763 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 5764 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 5765 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 5766 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 5767 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 5768 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 5769 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 5770 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 5771 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 5772 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 5773 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 5774 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 5775 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n 5776 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc 5777 * @param HRTIMx High Resolution Timer instance 5778 * @param Output This parameter can be one of the following values: 5779 * @arg @ref LL_HRTIM_OUTPUT_TA1 5780 * @arg @ref LL_HRTIM_OUTPUT_TA2 5781 * @arg @ref LL_HRTIM_OUTPUT_TB1 5782 * @arg @ref LL_HRTIM_OUTPUT_TB2 5783 * @arg @ref LL_HRTIM_OUTPUT_TC1 5784 * @arg @ref LL_HRTIM_OUTPUT_TC2 5785 * @arg @ref LL_HRTIM_OUTPUT_TD1 5786 * @arg @ref LL_HRTIM_OUTPUT_TD2 5787 * @arg @ref LL_HRTIM_OUTPUT_TE1 5788 * @arg @ref LL_HRTIM_OUTPUT_TE2 5789 * @retval ResetSrc This parameter can be a combination of the following values: 5790 * @arg @ref LL_HRTIM_CROSSBAR_NONE 5791 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 5792 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 5793 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 5794 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 5795 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 5796 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 5797 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 5798 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 5799 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 5800 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 5801 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 5802 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 5803 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 5804 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 5805 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 5806 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 5807 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 5808 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 5809 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 5810 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 5811 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 5812 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 5813 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 5814 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 5815 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 5816 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 5817 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 5818 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 5819 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 5820 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 5821 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 5822 */ 5823 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 5824 { 5825 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5826 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + 5827 REG_OFFSET_TAB_SETxR[iOutput])); 5828 return (uint32_t) READ_REG(*pReg); 5829 } 5830 5831 /** 5832 * @brief Configure a timer output. 5833 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n 5834 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n 5835 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n 5836 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n 5837 * OUTxR CHP1 LL_HRTIM_OUT_Config\n 5838 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n 5839 * OUTxR POL2 LL_HRTIM_OUT_Config\n 5840 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n 5841 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n 5842 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n 5843 * OUTxR CHP2 LL_HRTIM_OUT_Config\n 5844 * OUTxR DIDL2 LL_HRTIM_OUT_Config 5845 * @param HRTIMx High Resolution Timer instance 5846 * @param Output This parameter can be one of the following values: 5847 * @arg @ref LL_HRTIM_OUTPUT_TA1 5848 * @arg @ref LL_HRTIM_OUTPUT_TA2 5849 * @arg @ref LL_HRTIM_OUTPUT_TB1 5850 * @arg @ref LL_HRTIM_OUTPUT_TB2 5851 * @arg @ref LL_HRTIM_OUTPUT_TC1 5852 * @arg @ref LL_HRTIM_OUTPUT_TC2 5853 * @arg @ref LL_HRTIM_OUTPUT_TD1 5854 * @arg @ref LL_HRTIM_OUTPUT_TD2 5855 * @arg @ref LL_HRTIM_OUTPUT_TE1 5856 * @arg @ref LL_HRTIM_OUTPUT_TE2 5857 * @param Configuration This parameter must be a combination of all the following values: 5858 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 5859 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 5860 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 5861 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 5862 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 5863 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 5864 * @retval None 5865 */ 5866 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) 5867 { 5868 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5869 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 5870 REG_OFFSET_TAB_OUTxR[iOutput])); 5871 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), 5872 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); 5873 } 5874 5875 /** 5876 * @brief Set the polarity of a timer output. 5877 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n 5878 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity 5879 * @param HRTIMx High Resolution Timer instance 5880 * @param Output This parameter can be one of the following values: 5881 * @arg @ref LL_HRTIM_OUTPUT_TA1 5882 * @arg @ref LL_HRTIM_OUTPUT_TA2 5883 * @arg @ref LL_HRTIM_OUTPUT_TB1 5884 * @arg @ref LL_HRTIM_OUTPUT_TB2 5885 * @arg @ref LL_HRTIM_OUTPUT_TC1 5886 * @arg @ref LL_HRTIM_OUTPUT_TC2 5887 * @arg @ref LL_HRTIM_OUTPUT_TD1 5888 * @arg @ref LL_HRTIM_OUTPUT_TD2 5889 * @arg @ref LL_HRTIM_OUTPUT_TE1 5890 * @arg @ref LL_HRTIM_OUTPUT_TE2 5891 * @param Polarity This parameter can be one of the following values: 5892 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY 5893 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 5894 * @retval None 5895 */ 5896 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) 5897 { 5898 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5899 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 5900 REG_OFFSET_TAB_OUTxR[iOutput])); 5901 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); 5902 } 5903 5904 /** 5905 * @brief Get actual polarity of the timer output. 5906 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n 5907 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity 5908 * @param HRTIMx High Resolution Timer instance 5909 * @param Output This parameter can be one of the following values: 5910 * @arg @ref LL_HRTIM_OUTPUT_TA1 5911 * @arg @ref LL_HRTIM_OUTPUT_TA2 5912 * @arg @ref LL_HRTIM_OUTPUT_TB1 5913 * @arg @ref LL_HRTIM_OUTPUT_TB2 5914 * @arg @ref LL_HRTIM_OUTPUT_TC1 5915 * @arg @ref LL_HRTIM_OUTPUT_TC2 5916 * @arg @ref LL_HRTIM_OUTPUT_TD1 5917 * @arg @ref LL_HRTIM_OUTPUT_TD2 5918 * @arg @ref LL_HRTIM_OUTPUT_TE1 5919 * @arg @ref LL_HRTIM_OUTPUT_TE2 5920 * @retval Polarity This parameter can be one of the following values: 5921 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY 5922 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 5923 */ 5924 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 5925 { 5926 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5927 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 5928 REG_OFFSET_TAB_OUTxR[iOutput])); 5929 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 5930 } 5931 5932 /** 5933 * @brief Set the output IDLE mode. 5934 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n 5935 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode 5936 * @note This function must not be called when the burst mode is active 5937 * @param HRTIMx High Resolution Timer instance 5938 * @param Output This parameter can be one of the following values: 5939 * @arg @ref LL_HRTIM_OUTPUT_TA1 5940 * @arg @ref LL_HRTIM_OUTPUT_TA2 5941 * @arg @ref LL_HRTIM_OUTPUT_TB1 5942 * @arg @ref LL_HRTIM_OUTPUT_TB2 5943 * @arg @ref LL_HRTIM_OUTPUT_TC1 5944 * @arg @ref LL_HRTIM_OUTPUT_TC2 5945 * @arg @ref LL_HRTIM_OUTPUT_TD1 5946 * @arg @ref LL_HRTIM_OUTPUT_TD2 5947 * @arg @ref LL_HRTIM_OUTPUT_TE1 5948 * @arg @ref LL_HRTIM_OUTPUT_TE2 5949 * @param IdleMode This parameter can be one of the following values: 5950 * @arg @ref LL_HRTIM_OUT_NO_IDLE 5951 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 5952 * @retval None 5953 */ 5954 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) 5955 { 5956 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5957 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 5958 REG_OFFSET_TAB_OUTxR[iOutput])); 5959 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); 5960 } 5961 5962 /** 5963 * @brief Get actual output IDLE mode. 5964 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n 5965 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode 5966 * @param HRTIMx High Resolution Timer instance 5967 * @param Output This parameter can be one of the following values: 5968 * @arg @ref LL_HRTIM_OUTPUT_TA1 5969 * @arg @ref LL_HRTIM_OUTPUT_TA2 5970 * @arg @ref LL_HRTIM_OUTPUT_TB1 5971 * @arg @ref LL_HRTIM_OUTPUT_TB2 5972 * @arg @ref LL_HRTIM_OUTPUT_TC1 5973 * @arg @ref LL_HRTIM_OUTPUT_TC2 5974 * @arg @ref LL_HRTIM_OUTPUT_TD1 5975 * @arg @ref LL_HRTIM_OUTPUT_TD2 5976 * @arg @ref LL_HRTIM_OUTPUT_TE1 5977 * @arg @ref LL_HRTIM_OUTPUT_TE2 5978 * @retval IdleMode This parameter can be one of the following values: 5979 * @arg @ref LL_HRTIM_OUT_NO_IDLE 5980 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 5981 */ 5982 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 5983 { 5984 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 5985 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 5986 REG_OFFSET_TAB_OUTxR[iOutput])); 5987 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 5988 } 5989 5990 /** 5991 * @brief Set the output IDLE level. 5992 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n 5993 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel 5994 * @note This function must be called prior enabling the timer. 5995 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE. 5996 * @param HRTIMx High Resolution Timer instance 5997 * @param Output This parameter can be one of the following values: 5998 * @arg @ref LL_HRTIM_OUTPUT_TA1 5999 * @arg @ref LL_HRTIM_OUTPUT_TA2 6000 * @arg @ref LL_HRTIM_OUTPUT_TB1 6001 * @arg @ref LL_HRTIM_OUTPUT_TB2 6002 * @arg @ref LL_HRTIM_OUTPUT_TC1 6003 * @arg @ref LL_HRTIM_OUTPUT_TC2 6004 * @arg @ref LL_HRTIM_OUTPUT_TD1 6005 * @arg @ref LL_HRTIM_OUTPUT_TD2 6006 * @arg @ref LL_HRTIM_OUTPUT_TE1 6007 * @arg @ref LL_HRTIM_OUTPUT_TE2 6008 * @param IdleLevel This parameter can be one of the following values: 6009 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE 6010 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 6011 * @retval None 6012 */ 6013 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) 6014 { 6015 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6016 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6017 REG_OFFSET_TAB_OUTxR[iOutput])); 6018 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); 6019 } 6020 6021 /** 6022 * @brief Get actual output IDLE level. 6023 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n 6024 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel 6025 * @param HRTIMx High Resolution Timer instance 6026 * @param Output This parameter can be one of the following values: 6027 * @arg @ref LL_HRTIM_OUTPUT_TA1 6028 * @arg @ref LL_HRTIM_OUTPUT_TA2 6029 * @arg @ref LL_HRTIM_OUTPUT_TB1 6030 * @arg @ref LL_HRTIM_OUTPUT_TB2 6031 * @arg @ref LL_HRTIM_OUTPUT_TC1 6032 * @arg @ref LL_HRTIM_OUTPUT_TC2 6033 * @arg @ref LL_HRTIM_OUTPUT_TD1 6034 * @arg @ref LL_HRTIM_OUTPUT_TD2 6035 * @arg @ref LL_HRTIM_OUTPUT_TE1 6036 * @arg @ref LL_HRTIM_OUTPUT_TE2 6037 * @retval IdleLevel This parameter can be one of the following values: 6038 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE 6039 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 6040 */ 6041 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6042 { 6043 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6044 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6045 REG_OFFSET_TAB_OUTxR[iOutput])); 6046 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 6047 } 6048 6049 /** 6050 * @brief Set the output FAULT state. 6051 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n 6052 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState 6053 * @note This function must not called when the timer is enabled and a fault 6054 * channel is enabled at timer level. 6055 * @param HRTIMx High Resolution Timer instance 6056 * @param Output This parameter can be one of the following values: 6057 * @arg @ref LL_HRTIM_OUTPUT_TA1 6058 * @arg @ref LL_HRTIM_OUTPUT_TA2 6059 * @arg @ref LL_HRTIM_OUTPUT_TB1 6060 * @arg @ref LL_HRTIM_OUTPUT_TB2 6061 * @arg @ref LL_HRTIM_OUTPUT_TC1 6062 * @arg @ref LL_HRTIM_OUTPUT_TC2 6063 * @arg @ref LL_HRTIM_OUTPUT_TD1 6064 * @arg @ref LL_HRTIM_OUTPUT_TD2 6065 * @arg @ref LL_HRTIM_OUTPUT_TE1 6066 * @arg @ref LL_HRTIM_OUTPUT_TE2 6067 * @param FaultState This parameter can be one of the following values: 6068 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 6069 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE 6070 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE 6071 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 6072 * @retval None 6073 */ 6074 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) 6075 { 6076 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6077 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6078 REG_OFFSET_TAB_OUTxR[iOutput])); 6079 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); 6080 } 6081 6082 /** 6083 * @brief Get actual FAULT state. 6084 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n 6085 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState 6086 * @param HRTIMx High Resolution Timer instance 6087 * @param Output This parameter can be one of the following values: 6088 * @arg @ref LL_HRTIM_OUTPUT_TA1 6089 * @arg @ref LL_HRTIM_OUTPUT_TA2 6090 * @arg @ref LL_HRTIM_OUTPUT_TB1 6091 * @arg @ref LL_HRTIM_OUTPUT_TB2 6092 * @arg @ref LL_HRTIM_OUTPUT_TC1 6093 * @arg @ref LL_HRTIM_OUTPUT_TC2 6094 * @arg @ref LL_HRTIM_OUTPUT_TD1 6095 * @arg @ref LL_HRTIM_OUTPUT_TD2 6096 * @arg @ref LL_HRTIM_OUTPUT_TE1 6097 * @arg @ref LL_HRTIM_OUTPUT_TE2 6098 * @retval FaultState This parameter can be one of the following values: 6099 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 6100 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE 6101 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE 6102 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 6103 */ 6104 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6105 { 6106 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6107 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6108 REG_OFFSET_TAB_OUTxR[iOutput])); 6109 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 6110 } 6111 6112 /** 6113 * @brief Set the output chopper mode. 6114 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n 6115 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode 6116 * @note This function must not called when the timer is enabled. 6117 * @param HRTIMx High Resolution Timer instance 6118 * @param Output This parameter can be one of the following values: 6119 * @arg @ref LL_HRTIM_OUTPUT_TA1 6120 * @arg @ref LL_HRTIM_OUTPUT_TA2 6121 * @arg @ref LL_HRTIM_OUTPUT_TB1 6122 * @arg @ref LL_HRTIM_OUTPUT_TB2 6123 * @arg @ref LL_HRTIM_OUTPUT_TC1 6124 * @arg @ref LL_HRTIM_OUTPUT_TC2 6125 * @arg @ref LL_HRTIM_OUTPUT_TD1 6126 * @arg @ref LL_HRTIM_OUTPUT_TD2 6127 * @arg @ref LL_HRTIM_OUTPUT_TE1 6128 * @arg @ref LL_HRTIM_OUTPUT_TE2 6129 * @param ChopperMode This parameter can be one of the following values: 6130 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED 6131 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 6132 * @retval None 6133 */ 6134 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) 6135 { 6136 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6137 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6138 REG_OFFSET_TAB_OUTxR[iOutput])); 6139 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); 6140 } 6141 6142 /** 6143 * @brief Get actual output chopper mode 6144 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n 6145 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode 6146 * @param HRTIMx High Resolution Timer instance 6147 * @param Output This parameter can be one of the following values: 6148 * @arg @ref LL_HRTIM_OUTPUT_TA1 6149 * @arg @ref LL_HRTIM_OUTPUT_TA2 6150 * @arg @ref LL_HRTIM_OUTPUT_TB1 6151 * @arg @ref LL_HRTIM_OUTPUT_TB2 6152 * @arg @ref LL_HRTIM_OUTPUT_TC1 6153 * @arg @ref LL_HRTIM_OUTPUT_TC2 6154 * @arg @ref LL_HRTIM_OUTPUT_TD1 6155 * @arg @ref LL_HRTIM_OUTPUT_TD2 6156 * @arg @ref LL_HRTIM_OUTPUT_TE1 6157 * @arg @ref LL_HRTIM_OUTPUT_TE2 6158 * @retval ChopperMode This parameter can be one of the following values: 6159 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED 6160 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 6161 */ 6162 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6163 { 6164 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6165 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6166 REG_OFFSET_TAB_OUTxR[iOutput])); 6167 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 6168 } 6169 6170 /** 6171 * @brief Set the output burst mode entry mode. 6172 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n 6173 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode 6174 * @note This function must not called when the timer is enabled. 6175 * @param HRTIMx High Resolution Timer instance 6176 * @param Output This parameter can be one of the following values: 6177 * @arg @ref LL_HRTIM_OUTPUT_TA1 6178 * @arg @ref LL_HRTIM_OUTPUT_TA2 6179 * @arg @ref LL_HRTIM_OUTPUT_TB1 6180 * @arg @ref LL_HRTIM_OUTPUT_TB2 6181 * @arg @ref LL_HRTIM_OUTPUT_TC1 6182 * @arg @ref LL_HRTIM_OUTPUT_TC2 6183 * @arg @ref LL_HRTIM_OUTPUT_TD1 6184 * @arg @ref LL_HRTIM_OUTPUT_TD2 6185 * @arg @ref LL_HRTIM_OUTPUT_TE1 6186 * @arg @ref LL_HRTIM_OUTPUT_TE2 6187 * @param BMEntryMode This parameter can be one of the following values: 6188 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 6189 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 6190 * @retval None 6191 */ 6192 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) 6193 { 6194 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6195 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6196 REG_OFFSET_TAB_OUTxR[iOutput])); 6197 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); 6198 } 6199 6200 /** 6201 * @brief Get actual output burst mode entry mode. 6202 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n 6203 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode 6204 * @param HRTIMx High Resolution Timer instance 6205 * @param Output This parameter can be one of the following values: 6206 * @arg @ref LL_HRTIM_OUTPUT_TA1 6207 * @arg @ref LL_HRTIM_OUTPUT_TA2 6208 * @arg @ref LL_HRTIM_OUTPUT_TB1 6209 * @arg @ref LL_HRTIM_OUTPUT_TB2 6210 * @arg @ref LL_HRTIM_OUTPUT_TC1 6211 * @arg @ref LL_HRTIM_OUTPUT_TC2 6212 * @arg @ref LL_HRTIM_OUTPUT_TD1 6213 * @arg @ref LL_HRTIM_OUTPUT_TD2 6214 * @arg @ref LL_HRTIM_OUTPUT_TE1 6215 * @arg @ref LL_HRTIM_OUTPUT_TE2 6216 * @retval BMEntryMode This parameter can be one of the following values: 6217 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 6218 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 6219 */ 6220 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6221 { 6222 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6223 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 6224 REG_OFFSET_TAB_OUTxR[iOutput])); 6225 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 6226 } 6227 6228 /** 6229 * @brief Get the level (active or inactive) of the designated output when the 6230 * delayed protection was triggered. 6231 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n 6232 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus 6233 * @param HRTIMx High Resolution Timer instance 6234 * @param Output This parameter can be one of the following values: 6235 * @arg @ref LL_HRTIM_OUTPUT_TA1 6236 * @arg @ref LL_HRTIM_OUTPUT_TA2 6237 * @arg @ref LL_HRTIM_OUTPUT_TB1 6238 * @arg @ref LL_HRTIM_OUTPUT_TB2 6239 * @arg @ref LL_HRTIM_OUTPUT_TC1 6240 * @arg @ref LL_HRTIM_OUTPUT_TC2 6241 * @arg @ref LL_HRTIM_OUTPUT_TD1 6242 * @arg @ref LL_HRTIM_OUTPUT_TD2 6243 * @arg @ref LL_HRTIM_OUTPUT_TE1 6244 * @arg @ref LL_HRTIM_OUTPUT_TE2 6245 * @retval OutputLevel This parameter can be one of the following values: 6246 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 6247 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 6248 */ 6249 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6250 { 6251 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6252 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + 6253 REG_OFFSET_TAB_OUTxR[iOutput])); 6254 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> 6255 HRTIM_TIMISR_O1STAT_Pos); 6256 } 6257 6258 /** 6259 * @brief Force the timer output to its active or inactive level. 6260 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n 6261 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n 6262 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n 6263 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel 6264 * @param HRTIMx High Resolution Timer instance 6265 * @param Output This parameter can be one of the following values: 6266 * @arg @ref LL_HRTIM_OUTPUT_TA1 6267 * @arg @ref LL_HRTIM_OUTPUT_TA2 6268 * @arg @ref LL_HRTIM_OUTPUT_TB1 6269 * @arg @ref LL_HRTIM_OUTPUT_TB2 6270 * @arg @ref LL_HRTIM_OUTPUT_TC1 6271 * @arg @ref LL_HRTIM_OUTPUT_TC2 6272 * @arg @ref LL_HRTIM_OUTPUT_TD1 6273 * @arg @ref LL_HRTIM_OUTPUT_TD2 6274 * @arg @ref LL_HRTIM_OUTPUT_TE1 6275 * @arg @ref LL_HRTIM_OUTPUT_TE2 6276 * @param OutputLevel This parameter can be one of the following values: 6277 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 6278 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 6279 * @retval None 6280 */ 6281 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel) 6282 { 6283 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] = 6284 { 6285 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */ 6286 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */ 6287 }; 6288 6289 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6290 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 6291 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); 6292 SET_BIT(*pReg, HRTIM_SET1R_SST); 6293 } 6294 6295 /** 6296 * @brief Get actual output level, before the output stage (chopper, polarity). 6297 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n 6298 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel 6299 * @param HRTIMx High Resolution Timer instance 6300 * @param Output This parameter can be one of the following values: 6301 * @arg @ref LL_HRTIM_OUTPUT_TA1 6302 * @arg @ref LL_HRTIM_OUTPUT_TA2 6303 * @arg @ref LL_HRTIM_OUTPUT_TB1 6304 * @arg @ref LL_HRTIM_OUTPUT_TB2 6305 * @arg @ref LL_HRTIM_OUTPUT_TC1 6306 * @arg @ref LL_HRTIM_OUTPUT_TC2 6307 * @arg @ref LL_HRTIM_OUTPUT_TD1 6308 * @arg @ref LL_HRTIM_OUTPUT_TD2 6309 * @arg @ref LL_HRTIM_OUTPUT_TE1 6310 * @arg @ref LL_HRTIM_OUTPUT_TE2 6311 * @retval OutputLevel This parameter can be one of the following values: 6312 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 6313 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 6314 */ 6315 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) 6316 { 6317 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 6318 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + 6319 REG_OFFSET_TAB_OUTxR[iOutput])); 6320 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> 6321 HRTIM_TIMISR_O1CPY_Pos); 6322 } 6323 6324 /** 6325 * @} 6326 */ 6327 6328 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management 6329 * @ingroup RTEMSBSPsARMSTM32H7 6330 * @{ 6331 */ 6332 6333 /** 6334 * @brief Configure external event conditioning. 6335 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n 6336 * EECR1 EE1POL LL_HRTIM_EE_Config\n 6337 * EECR1 EE1SNS LL_HRTIM_EE_Config\n 6338 * EECR1 EE1FAST LL_HRTIM_EE_Config\n 6339 * EECR1 EE2SRC LL_HRTIM_EE_Config\n 6340 * EECR1 EE2POL LL_HRTIM_EE_Config\n 6341 * EECR1 EE2SNS LL_HRTIM_EE_Config\n 6342 * EECR1 EE2FAST LL_HRTIM_EE_Config\n 6343 * EECR1 EE3SRC LL_HRTIM_EE_Config\n 6344 * EECR1 EE3POL LL_HRTIM_EE_Config\n 6345 * EECR1 EE3SNS LL_HRTIM_EE_Config\n 6346 * EECR1 EE3FAST LL_HRTIM_EE_Config\n 6347 * EECR1 EE4SRC LL_HRTIM_EE_Config\n 6348 * EECR1 EE4POL LL_HRTIM_EE_Config\n 6349 * EECR1 EE4SNS LL_HRTIM_EE_Config\n 6350 * EECR1 EE4FAST LL_HRTIM_EE_Config\n 6351 * EECR1 EE5SRC LL_HRTIM_EE_Config\n 6352 * EECR1 EE5POL LL_HRTIM_EE_Config\n 6353 * EECR1 EE5SNS LL_HRTIM_EE_Config\n 6354 * EECR1 EE5FAST LL_HRTIM_EE_Config\n 6355 * EECR2 EE6SRC LL_HRTIM_EE_Config\n 6356 * EECR2 EE6POL LL_HRTIM_EE_Config\n 6357 * EECR2 EE6SNS LL_HRTIM_EE_Config\n 6358 * EECR2 EE6FAST LL_HRTIM_EE_Config\n 6359 * EECR2 EE7SRC LL_HRTIM_EE_Config\n 6360 * EECR2 EE7POL LL_HRTIM_EE_Config\n 6361 * EECR2 EE7SNS LL_HRTIM_EE_Config\n 6362 * EECR2 EE7FAST LL_HRTIM_EE_Config\n 6363 * EECR2 EE8SRC LL_HRTIM_EE_Config\n 6364 * EECR2 EE8POL LL_HRTIM_EE_Config\n 6365 * EECR2 EE8SNS LL_HRTIM_EE_Config\n 6366 * EECR2 EE8FAST LL_HRTIM_EE_Config\n 6367 * EECR2 EE9SRC LL_HRTIM_EE_Config\n 6368 * EECR2 EE9POL LL_HRTIM_EE_Config\n 6369 * EECR2 EE9SNS LL_HRTIM_EE_Config\n 6370 * EECR2 EE9FAST LL_HRTIM_EE_Config\n 6371 * EECR2 EE10SRC LL_HRTIM_EE_Config\n 6372 * EECR2 EE10POL LL_HRTIM_EE_Config\n 6373 * EECR2 EE10SNS LL_HRTIM_EE_Config\n 6374 * EECR2 EE10FAST LL_HRTIM_EE_Config 6375 * @note This function must not be called when the timer counter is enabled. 6376 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel. 6377 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5. 6378 * @param HRTIMx High Resolution Timer instance 6379 * @param Event This parameter can be one of the following values: 6380 * @arg @ref LL_HRTIM_EVENT_1 6381 * @arg @ref LL_HRTIM_EVENT_2 6382 * @arg @ref LL_HRTIM_EVENT_3 6383 * @arg @ref LL_HRTIM_EVENT_4 6384 * @arg @ref LL_HRTIM_EVENT_5 6385 * @arg @ref LL_HRTIM_EVENT_6 6386 * @arg @ref LL_HRTIM_EVENT_7 6387 * @arg @ref LL_HRTIM_EVENT_8 6388 * @arg @ref LL_HRTIM_EVENT_9 6389 * @arg @ref LL_HRTIM_EVENT_10 6390 * @param Configuration This parameter must be a combination of all the following values: 6391 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4 6392 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW 6393 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 6394 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE 6395 * @retval None 6396 */ 6397 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) 6398 { 6399 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6400 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6401 REG_OFFSET_TAB_EECR[iEvent])); 6402 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), 6403 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); 6404 } 6405 6406 /** 6407 * @brief Set the external event source. 6408 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n 6409 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n 6410 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n 6411 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n 6412 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n 6413 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n 6414 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n 6415 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n 6416 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n 6417 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc 6418 * @param HRTIMx High Resolution Timer instance 6419 * @param Event This parameter can be one of the following values: 6420 * @arg @ref LL_HRTIM_EVENT_1 6421 * @arg @ref LL_HRTIM_EVENT_2 6422 * @arg @ref LL_HRTIM_EVENT_3 6423 * @arg @ref LL_HRTIM_EVENT_4 6424 * @arg @ref LL_HRTIM_EVENT_5 6425 * @arg @ref LL_HRTIM_EVENT_6 6426 * @arg @ref LL_HRTIM_EVENT_7 6427 * @arg @ref LL_HRTIM_EVENT_8 6428 * @arg @ref LL_HRTIM_EVENT_9 6429 * @arg @ref LL_HRTIM_EVENT_10 6430 * @param Src This parameter can be one of the following values: 6431 * @arg External event source 1 6432 * @arg External event source 2 6433 * @arg External event source 3 6434 * @arg External event source 4 6435 * @retval None 6436 */ 6437 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) 6438 { 6439 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6440 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6441 REG_OFFSET_TAB_EECR[iEvent])); 6442 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); 6443 } 6444 6445 /** 6446 * @brief Get actual external event source. 6447 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n 6448 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n 6449 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n 6450 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n 6451 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n 6452 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n 6453 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n 6454 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n 6455 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n 6456 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc 6457 * @param HRTIMx High Resolution Timer instance 6458 * @param Event This parameter can be one of the following values: 6459 * @arg @ref LL_HRTIM_EVENT_1 6460 * @arg @ref LL_HRTIM_EVENT_2 6461 * @arg @ref LL_HRTIM_EVENT_3 6462 * @arg @ref LL_HRTIM_EVENT_4 6463 * @arg @ref LL_HRTIM_EVENT_5 6464 * @arg @ref LL_HRTIM_EVENT_6 6465 * @arg @ref LL_HRTIM_EVENT_7 6466 * @arg @ref LL_HRTIM_EVENT_8 6467 * @arg @ref LL_HRTIM_EVENT_9 6468 * @arg @ref LL_HRTIM_EVENT_10 6469 * @retval EventSrc This parameter can be one of the following values: 6470 * @arg External event source 1 6471 * @arg External event source 2 6472 * @arg External event source 3 6473 * @arg External event source 4 6474 */ 6475 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event) 6476 { 6477 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6478 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6479 REG_OFFSET_TAB_EECR[iEvent])); 6480 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 6481 } 6482 6483 /** 6484 * @brief Set the polarity of an external event. 6485 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n 6486 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n 6487 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n 6488 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n 6489 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n 6490 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n 6491 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n 6492 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n 6493 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n 6494 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity 6495 * @note This function must not be called when the timer counter is enabled. 6496 * @note Event polarity is only significant when event detection is level-sensitive. 6497 * @param HRTIMx High Resolution Timer instance 6498 * @param Event This parameter can be one of the following values: 6499 * @arg @ref LL_HRTIM_EVENT_1 6500 * @arg @ref LL_HRTIM_EVENT_2 6501 * @arg @ref LL_HRTIM_EVENT_3 6502 * @arg @ref LL_HRTIM_EVENT_4 6503 * @arg @ref LL_HRTIM_EVENT_5 6504 * @arg @ref LL_HRTIM_EVENT_6 6505 * @arg @ref LL_HRTIM_EVENT_7 6506 * @arg @ref LL_HRTIM_EVENT_8 6507 * @arg @ref LL_HRTIM_EVENT_9 6508 * @arg @ref LL_HRTIM_EVENT_10 6509 * @param Polarity This parameter can be one of the following values: 6510 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH 6511 * @arg @ref LL_HRTIM_EE_POLARITY_LOW 6512 * @retval None 6513 */ 6514 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) 6515 { 6516 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6517 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6518 REG_OFFSET_TAB_EECR[iEvent])); 6519 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); 6520 } 6521 6522 /** 6523 * @brief Get actual polarity setting of an external event. 6524 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n 6525 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n 6526 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n 6527 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n 6528 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n 6529 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n 6530 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n 6531 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n 6532 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n 6533 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity 6534 * @param HRTIMx High Resolution Timer instance 6535 * @param Event This parameter can be one of the following values: 6536 * @arg @ref LL_HRTIM_EVENT_1 6537 * @arg @ref LL_HRTIM_EVENT_2 6538 * @arg @ref LL_HRTIM_EVENT_3 6539 * @arg @ref LL_HRTIM_EVENT_4 6540 * @arg @ref LL_HRTIM_EVENT_5 6541 * @arg @ref LL_HRTIM_EVENT_6 6542 * @arg @ref LL_HRTIM_EVENT_7 6543 * @arg @ref LL_HRTIM_EVENT_8 6544 * @arg @ref LL_HRTIM_EVENT_9 6545 * @arg @ref LL_HRTIM_EVENT_10 6546 * @retval Polarity This parameter can be one of the following values: 6547 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH 6548 * @arg @ref LL_HRTIM_EE_POLARITY_LOW 6549 */ 6550 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) 6551 { 6552 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6553 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6554 REG_OFFSET_TAB_EECR[iEvent])); 6555 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 6556 } 6557 6558 /** 6559 * @brief Set the sensitivity of an external event. 6560 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n 6561 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n 6562 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n 6563 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n 6564 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n 6565 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n 6566 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n 6567 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n 6568 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n 6569 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity 6570 * @param HRTIMx High Resolution Timer instance 6571 * @param Event This parameter can be one of the following values: 6572 * @arg @ref LL_HRTIM_EVENT_1 6573 * @arg @ref LL_HRTIM_EVENT_2 6574 * @arg @ref LL_HRTIM_EVENT_3 6575 * @arg @ref LL_HRTIM_EVENT_4 6576 * @arg @ref LL_HRTIM_EVENT_5 6577 * @arg @ref LL_HRTIM_EVENT_6 6578 * @arg @ref LL_HRTIM_EVENT_7 6579 * @arg @ref LL_HRTIM_EVENT_8 6580 * @arg @ref LL_HRTIM_EVENT_9 6581 * @arg @ref LL_HRTIM_EVENT_10 6582 * @param Sensitivity This parameter can be one of the following values: 6583 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL 6584 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE 6585 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE 6586 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 6587 * @retval None 6588 */ 6589 6590 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) 6591 { 6592 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6593 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6594 REG_OFFSET_TAB_EECR[iEvent])); 6595 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); 6596 } 6597 6598 /** 6599 * @brief Get actual sensitivity setting of an external event. 6600 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n 6601 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n 6602 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n 6603 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n 6604 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n 6605 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n 6606 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n 6607 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n 6608 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n 6609 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity 6610 * @param HRTIMx High Resolution Timer instance 6611 * @param Event This parameter can be one of the following values: 6612 * @arg @ref LL_HRTIM_EVENT_1 6613 * @arg @ref LL_HRTIM_EVENT_2 6614 * @arg @ref LL_HRTIM_EVENT_3 6615 * @arg @ref LL_HRTIM_EVENT_4 6616 * @arg @ref LL_HRTIM_EVENT_5 6617 * @arg @ref LL_HRTIM_EVENT_6 6618 * @arg @ref LL_HRTIM_EVENT_7 6619 * @arg @ref LL_HRTIM_EVENT_8 6620 * @arg @ref LL_HRTIM_EVENT_9 6621 * @arg @ref LL_HRTIM_EVENT_10 6622 * @retval Polarity This parameter can be one of the following values: 6623 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL 6624 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE 6625 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE 6626 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 6627 */ 6628 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) 6629 { 6630 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6631 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6632 REG_OFFSET_TAB_EECR[iEvent])); 6633 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 6634 } 6635 6636 /** 6637 * @brief Set the fast mode of an external event. 6638 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n 6639 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n 6640 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n 6641 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n 6642 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n 6643 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n 6644 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n 6645 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n 6646 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n 6647 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode 6648 * @note This function must not be called when the timer counter is enabled. 6649 * @param HRTIMx High Resolution Timer instance 6650 * @param Event This parameter can be one of the following values: 6651 * @arg @ref LL_HRTIM_EVENT_1 6652 * @arg @ref LL_HRTIM_EVENT_2 6653 * @arg @ref LL_HRTIM_EVENT_3 6654 * @arg @ref LL_HRTIM_EVENT_4 6655 * @arg @ref LL_HRTIM_EVENT_5 6656 * @param FastMode This parameter can be one of the following values: 6657 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE 6658 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE 6659 * @retval None 6660 */ 6661 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) 6662 { 6663 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6664 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6665 REG_OFFSET_TAB_EECR[iEvent])); 6666 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); 6667 } 6668 6669 /** 6670 * @brief Get actual fast mode setting of an external event. 6671 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n 6672 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n 6673 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n 6674 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n 6675 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n 6676 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n 6677 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n 6678 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n 6679 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n 6680 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode 6681 * @param HRTIMx High Resolution Timer instance 6682 * @param Event This parameter can be one of the following values: 6683 * @arg @ref LL_HRTIM_EVENT_1 6684 * @arg @ref LL_HRTIM_EVENT_2 6685 * @arg @ref LL_HRTIM_EVENT_3 6686 * @arg @ref LL_HRTIM_EVENT_4 6687 * @arg @ref LL_HRTIM_EVENT_5 6688 * @retval FastMode This parameter can be one of the following values: 6689 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE 6690 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE 6691 */ 6692 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event) 6693 { 6694 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6695 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 6696 REG_OFFSET_TAB_EECR[iEvent])); 6697 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 6698 } 6699 6700 /** 6701 * @brief Set the digital noise filter of a external event. 6702 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n 6703 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n 6704 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n 6705 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n 6706 * EECR3 EE10F LL_HRTIM_EE_SetFilter 6707 * @param HRTIMx High Resolution Timer instance 6708 * @param Event This parameter can be one of the following values: 6709 * @arg @ref LL_HRTIM_EVENT_6 6710 * @arg @ref LL_HRTIM_EVENT_7 6711 * @arg @ref LL_HRTIM_EVENT_8 6712 * @arg @ref LL_HRTIM_EVENT_9 6713 * @arg @ref LL_HRTIM_EVENT_10 6714 * @param Filter This parameter can be one of the following values: 6715 * @arg @ref LL_HRTIM_EE_FILTER_NONE 6716 * @arg @ref LL_HRTIM_EE_FILTER_1 6717 * @arg @ref LL_HRTIM_EE_FILTER_2 6718 * @arg @ref LL_HRTIM_EE_FILTER_3 6719 * @arg @ref LL_HRTIM_EE_FILTER_4 6720 * @arg @ref LL_HRTIM_EE_FILTER_5 6721 * @arg @ref LL_HRTIM_EE_FILTER_6 6722 * @arg @ref LL_HRTIM_EE_FILTER_7 6723 * @arg @ref LL_HRTIM_EE_FILTER_8 6724 * @arg @ref LL_HRTIM_EE_FILTER_9 6725 * @arg @ref LL_HRTIM_EE_FILTER_10 6726 * @arg @ref LL_HRTIM_EE_FILTER_11 6727 * @arg @ref LL_HRTIM_EE_FILTER_12 6728 * @arg @ref LL_HRTIM_EE_FILTER_13 6729 * @arg @ref LL_HRTIM_EE_FILTER_14 6730 * @arg @ref LL_HRTIM_EE_FILTER_15 6731 * @retval None 6732 */ 6733 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter) 6734 { 6735 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 6736 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]), 6737 (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); 6738 } 6739 6740 /** 6741 * @brief Get actual digital noise filter setting of a external event. 6742 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n 6743 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n 6744 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n 6745 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n 6746 * EECR3 EE10F LL_HRTIM_EE_GetFilter 6747 * @param HRTIMx High Resolution Timer instance 6748 * @param Event This parameter can be one of the following values: 6749 * @arg @ref LL_HRTIM_EVENT_6 6750 * @arg @ref LL_HRTIM_EVENT_7 6751 * @arg @ref LL_HRTIM_EVENT_8 6752 * @arg @ref LL_HRTIM_EVENT_9 6753 * @arg @ref LL_HRTIM_EVENT_10 6754 * @retval Filter This parameter can be one of the following values: 6755 * @arg @ref LL_HRTIM_EE_FILTER_NONE 6756 * @arg @ref LL_HRTIM_EE_FILTER_1 6757 * @arg @ref LL_HRTIM_EE_FILTER_2 6758 * @arg @ref LL_HRTIM_EE_FILTER_3 6759 * @arg @ref LL_HRTIM_EE_FILTER_4 6760 * @arg @ref LL_HRTIM_EE_FILTER_5 6761 * @arg @ref LL_HRTIM_EE_FILTER_6 6762 * @arg @ref LL_HRTIM_EE_FILTER_7 6763 * @arg @ref LL_HRTIM_EE_FILTER_8 6764 * @arg @ref LL_HRTIM_EE_FILTER_9 6765 * @arg @ref LL_HRTIM_EE_FILTER_10 6766 * @arg @ref LL_HRTIM_EE_FILTER_11 6767 * @arg @ref LL_HRTIM_EE_FILTER_12 6768 * @arg @ref LL_HRTIM_EE_FILTER_13 6769 * @arg @ref LL_HRTIM_EE_FILTER_14 6770 * @arg @ref LL_HRTIM_EE_FILTER_15 6771 */ 6772 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event) 6773 { 6774 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); 6775 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, 6776 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 6777 } 6778 6779 /** 6780 * @brief Set the external event prescaler. 6781 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler 6782 * @param HRTIMx High Resolution Timer instance 6783 * @param Prescaler This parameter can be one of the following values: 6784 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1 6785 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2 6786 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4 6787 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 6788 * @retval None 6789 */ 6790 6791 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 6792 { 6793 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler); 6794 } 6795 6796 /** 6797 * @brief Get actual external event prescaler setting. 6798 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler 6799 * @param HRTIMx High Resolution Timer instance 6800 * @retval Prescaler This parameter can be one of the following values: 6801 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1 6802 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2 6803 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4 6804 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 6805 */ 6806 6807 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx) 6808 { 6809 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD)); 6810 } 6811 6812 /** 6813 * @} 6814 */ 6815 6816 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management 6817 * @ingroup RTEMSBSPsARMSTM32H7 6818 * @{ 6819 */ 6820 /** 6821 * @brief Configure fault signal conditioning Polarity and Source. 6822 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n 6823 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n 6824 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n 6825 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n 6826 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n 6827 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n 6828 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n 6829 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n 6830 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n 6831 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config 6832 * @note This function must not be called when the fault channel is enabled. 6833 * @param HRTIMx High Resolution Timer instance 6834 * @param Fault This parameter can be one of the following values: 6835 * @arg @ref LL_HRTIM_FAULT_1 6836 * @arg @ref LL_HRTIM_FAULT_2 6837 * @arg @ref LL_HRTIM_FAULT_3 6838 * @arg @ref LL_HRTIM_FAULT_4 6839 * @arg @ref LL_HRTIM_FAULT_5 6840 * @param Configuration This parameter must be a combination of all the following values: 6841 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL 6842 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH 6843 * @retval None 6844 */ 6845 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) 6846 { 6847 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6848 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 6849 REG_OFFSET_TAB_FLTINR[iFault])); 6850 MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), 6851 (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); 6852 } 6853 6854 /** 6855 * @brief Set the source of a fault signal. 6856 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n 6857 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n 6858 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n 6859 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n 6860 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc 6861 * @note This function must not be called when the fault channel is enabled. 6862 * @param HRTIMx High Resolution Timer instance 6863 * @param Fault This parameter can be one of the following values: 6864 * @arg @ref LL_HRTIM_FAULT_1 6865 * @arg @ref LL_HRTIM_FAULT_2 6866 * @arg @ref LL_HRTIM_FAULT_3 6867 * @arg @ref LL_HRTIM_FAULT_4 6868 * @arg @ref LL_HRTIM_FAULT_5 6869 * @param Src This parameter can be one of the following values: 6870 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT 6871 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL 6872 * @retval None 6873 */ 6874 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) 6875 { 6876 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6877 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 6878 REG_OFFSET_TAB_FLTINR[iFault])); 6879 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); 6880 } 6881 6882 /** 6883 * @brief Get actual source of a fault signal. 6884 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n 6885 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n 6886 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n 6887 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n 6888 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc 6889 * @param HRTIMx High Resolution Timer instance 6890 * @param Fault This parameter can be one of the following values: 6891 * @arg @ref LL_HRTIM_FAULT_1 6892 * @arg @ref LL_HRTIM_FAULT_2 6893 * @arg @ref LL_HRTIM_FAULT_3 6894 * @arg @ref LL_HRTIM_FAULT_4 6895 * @arg @ref LL_HRTIM_FAULT_5 6896 * @retval Source This parameter can be one of the following values: 6897 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT 6898 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL 6899 */ 6900 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) 6901 { 6902 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6903 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 6904 REG_OFFSET_TAB_FLTINR[iFault])); 6905 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 6906 } 6907 6908 /** 6909 * @brief Set the polarity of a fault signal. 6910 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n 6911 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n 6912 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n 6913 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n 6914 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity 6915 * @note This function must not be called when the fault channel is enabled. 6916 * @param HRTIMx High Resolution Timer instance 6917 * @param Fault This parameter can be one of the following values: 6918 * @arg @ref LL_HRTIM_FAULT_1 6919 * @arg @ref LL_HRTIM_FAULT_2 6920 * @arg @ref LL_HRTIM_FAULT_3 6921 * @arg @ref LL_HRTIM_FAULT_4 6922 * @arg @ref LL_HRTIM_FAULT_5 6923 * @param Polarity This parameter can be one of the following values: 6924 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW 6925 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH 6926 * @retval None 6927 */ 6928 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) 6929 { 6930 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6931 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 6932 REG_OFFSET_TAB_FLTINR[iFault])); 6933 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); 6934 } 6935 6936 /** 6937 * @brief Get actual polarity of a fault signal. 6938 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n 6939 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n 6940 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n 6941 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n 6942 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity 6943 * @param HRTIMx High Resolution Timer instance 6944 * @param Fault This parameter can be one of the following values: 6945 * @arg @ref LL_HRTIM_FAULT_1 6946 * @arg @ref LL_HRTIM_FAULT_2 6947 * @arg @ref LL_HRTIM_FAULT_3 6948 * @arg @ref LL_HRTIM_FAULT_4 6949 * @arg @ref LL_HRTIM_FAULT_5 6950 * @retval Polarity This parameter can be one of the following values: 6951 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW 6952 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH 6953 */ 6954 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) 6955 { 6956 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6957 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 6958 REG_OFFSET_TAB_FLTINR[iFault])); 6959 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 6960 } 6961 6962 /** 6963 * @brief Set the digital noise filter of a fault signal. 6964 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n 6965 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n 6966 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n 6967 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n 6968 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter 6969 * @note This function must not be called when the fault channel is enabled. 6970 * @param HRTIMx High Resolution Timer instance 6971 * @param Fault This parameter can be one of the following values: 6972 * @arg @ref LL_HRTIM_FAULT_1 6973 * @arg @ref LL_HRTIM_FAULT_2 6974 * @arg @ref LL_HRTIM_FAULT_3 6975 * @arg @ref LL_HRTIM_FAULT_4 6976 * @arg @ref LL_HRTIM_FAULT_5 6977 * @param Filter This parameter can be one of the following values: 6978 * @arg @ref LL_HRTIM_FLT_FILTER_NONE 6979 * @arg @ref LL_HRTIM_FLT_FILTER_1 6980 * @arg @ref LL_HRTIM_FLT_FILTER_2 6981 * @arg @ref LL_HRTIM_FLT_FILTER_3 6982 * @arg @ref LL_HRTIM_FLT_FILTER_4 6983 * @arg @ref LL_HRTIM_FLT_FILTER_5 6984 * @arg @ref LL_HRTIM_FLT_FILTER_6 6985 * @arg @ref LL_HRTIM_FLT_FILTER_7 6986 * @arg @ref LL_HRTIM_FLT_FILTER_8 6987 * @arg @ref LL_HRTIM_FLT_FILTER_9 6988 * @arg @ref LL_HRTIM_FLT_FILTER_10 6989 * @arg @ref LL_HRTIM_FLT_FILTER_11 6990 * @arg @ref LL_HRTIM_FLT_FILTER_12 6991 * @arg @ref LL_HRTIM_FLT_FILTER_13 6992 * @arg @ref LL_HRTIM_FLT_FILTER_14 6993 * @arg @ref LL_HRTIM_FLT_FILTER_15 6994 * @retval None 6995 */ 6996 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) 6997 { 6998 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 6999 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7000 REG_OFFSET_TAB_FLTINR[iFault])); 7001 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); 7002 } 7003 7004 /** 7005 * @brief Get actual digital noise filter setting of a fault signal. 7006 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n 7007 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n 7008 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n 7009 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n 7010 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter 7011 * @param HRTIMx High Resolution Timer instance 7012 * @param Fault This parameter can be one of the following values: 7013 * @arg @ref LL_HRTIM_FAULT_1 7014 * @arg @ref LL_HRTIM_FAULT_2 7015 * @arg @ref LL_HRTIM_FAULT_3 7016 * @arg @ref LL_HRTIM_FAULT_4 7017 * @arg @ref LL_HRTIM_FAULT_5 7018 * @retval Filter This parameter can be one of the following values: 7019 * @arg @ref LL_HRTIM_FLT_FILTER_NONE 7020 * @arg @ref LL_HRTIM_FLT_FILTER_1 7021 * @arg @ref LL_HRTIM_FLT_FILTER_2 7022 * @arg @ref LL_HRTIM_FLT_FILTER_3 7023 * @arg @ref LL_HRTIM_FLT_FILTER_4 7024 * @arg @ref LL_HRTIM_FLT_FILTER_5 7025 * @arg @ref LL_HRTIM_FLT_FILTER_6 7026 * @arg @ref LL_HRTIM_FLT_FILTER_7 7027 * @arg @ref LL_HRTIM_FLT_FILTER_8 7028 * @arg @ref LL_HRTIM_FLT_FILTER_9 7029 * @arg @ref LL_HRTIM_FLT_FILTER_10 7030 * @arg @ref LL_HRTIM_FLT_FILTER_11 7031 * @arg @ref LL_HRTIM_FLT_FILTER_12 7032 * @arg @ref LL_HRTIM_FLT_FILTER_13 7033 * @arg @ref LL_HRTIM_FLT_FILTER_14 7034 * @arg @ref LL_HRTIM_FLT_FILTER_15 7035 */ 7036 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) 7037 { 7038 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 7039 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7040 REG_OFFSET_TAB_FLTINR[iFault])); 7041 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 7042 7043 } 7044 7045 /** 7046 * @brief Set the fault circuitry prescaler. 7047 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler 7048 * @param HRTIMx High Resolution Timer instance 7049 * @param Prescaler This parameter can be one of the following values: 7050 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1 7051 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2 7052 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 7053 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 7054 * @retval None 7055 */ 7056 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 7057 { 7058 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler); 7059 } 7060 7061 /** 7062 * @brief Get actual fault circuitry prescaler setting. 7063 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler 7064 * @param HRTIMx High Resolution Timer instance 7065 * @retval Prescaler This parameter can be one of the following values: 7066 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1 7067 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2 7068 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 7069 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 7070 */ 7071 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx) 7072 { 7073 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD)); 7074 } 7075 7076 /** 7077 * @brief Lock the fault signal conditioning settings. 7078 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n 7079 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n 7080 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n 7081 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n 7082 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock 7083 * @param HRTIMx High Resolution Timer instance 7084 * @param Fault This parameter can be one of the following values: 7085 * @arg @ref LL_HRTIM_FAULT_1 7086 * @arg @ref LL_HRTIM_FAULT_2 7087 * @arg @ref LL_HRTIM_FAULT_3 7088 * @arg @ref LL_HRTIM_FAULT_4 7089 * @arg @ref LL_HRTIM_FAULT_5 7090 * @retval None 7091 */ 7092 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 7093 { 7094 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 7095 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7096 REG_OFFSET_TAB_FLTINR[iFault])); 7097 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); 7098 } 7099 7100 /** 7101 * @brief Enable the fault circuitry for the designated fault input. 7102 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n 7103 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n 7104 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n 7105 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n 7106 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable 7107 * @param HRTIMx High Resolution Timer instance 7108 * @param Fault This parameter can be one of the following values: 7109 * @arg @ref LL_HRTIM_FAULT_1 7110 * @arg @ref LL_HRTIM_FAULT_2 7111 * @arg @ref LL_HRTIM_FAULT_3 7112 * @arg @ref LL_HRTIM_FAULT_4 7113 * @arg @ref LL_HRTIM_FAULT_5 7114 * @retval None 7115 */ 7116 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 7117 { 7118 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 7119 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7120 REG_OFFSET_TAB_FLTINR[iFault])); 7121 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); 7122 } 7123 7124 /** 7125 * @brief Disable the fault circuitry for for the designated fault input. 7126 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n 7127 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n 7128 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n 7129 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n 7130 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable 7131 * @param HRTIMx High Resolution Timer instance 7132 * @param Fault This parameter can be one of the following values: 7133 * @arg @ref LL_HRTIM_FAULT_1 7134 * @arg @ref LL_HRTIM_FAULT_2 7135 * @arg @ref LL_HRTIM_FAULT_3 7136 * @arg @ref LL_HRTIM_FAULT_4 7137 * @arg @ref LL_HRTIM_FAULT_5 7138 * @retval None 7139 */ 7140 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 7141 { 7142 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 7143 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7144 REG_OFFSET_TAB_FLTINR[iFault])); 7145 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); 7146 } 7147 7148 /** 7149 * @brief Indicate whether the fault circuitry is enabled for a given fault input. 7150 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n 7151 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n 7152 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n 7153 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n 7154 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled 7155 * @param HRTIMx High Resolution Timer instance 7156 * @param Fault This parameter can be one of the following values: 7157 * @arg @ref LL_HRTIM_FAULT_1 7158 * @arg @ref LL_HRTIM_FAULT_2 7159 * @arg @ref LL_HRTIM_FAULT_3 7160 * @arg @ref LL_HRTIM_FAULT_4 7161 * @arg @ref LL_HRTIM_FAULT_5 7162 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0). 7163 */ 7164 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) 7165 { 7166 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 7167 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 7168 REG_OFFSET_TAB_FLTINR[iFault])); 7169 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == 7170 (HRTIM_IER_FLT1)) ? 1UL : 0UL); 7171 } 7172 7173 /** 7174 * @} 7175 */ 7176 7177 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management 7178 * @ingroup RTEMSBSPsARMSTM32H7 7179 * @{ 7180 */ 7181 7182 /** 7183 * @brief Configure the burst mode controller. 7184 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n 7185 * BMCR BMCLK LL_HRTIM_BM_Config\n 7186 * BMCR BMPRSC LL_HRTIM_BM_Config 7187 * @param HRTIMx High Resolution Timer instance 7188 * @param Configuration This parameter must be a combination of all the following values: 7189 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS 7190 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM 7191 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768 7192 * @retval None 7193 */ 7194 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration) 7195 { 7196 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration); 7197 } 7198 7199 /** 7200 * @brief Set the burst mode controller operating mode. 7201 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode 7202 * @param HRTIMx High Resolution Timer instance 7203 * @param Mode This parameter can be one of the following values: 7204 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT 7205 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS 7206 * @retval None 7207 */ 7208 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode) 7209 { 7210 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode); 7211 } 7212 7213 /** 7214 * @brief Get actual burst mode controller operating mode. 7215 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode 7216 * @param HRTIMx High Resolution Timer instance 7217 * @retval Mode This parameter can be one of the following values: 7218 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT 7219 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS 7220 */ 7221 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx) 7222 { 7223 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM); 7224 } 7225 7226 /** 7227 * @brief Set the burst mode controller clock source. 7228 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc 7229 * @param HRTIMx High Resolution Timer instance 7230 * @param ClockSrc This parameter can be one of the following values: 7231 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 7232 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 7233 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 7234 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 7235 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 7236 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 7237 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 7238 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 7239 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 7240 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 7241 * @retval None 7242 */ 7243 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc) 7244 { 7245 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc); 7246 } 7247 7248 /** 7249 * @brief Get actual burst mode controller clock source. 7250 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc 7251 * @param HRTIMx High Resolution Timer instance 7252 * @retval ClockSrc This parameter can be one of the following values: 7253 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 7254 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 7255 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 7256 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 7257 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 7258 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 7259 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 7260 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 7261 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 7262 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 7263 * @retval ClockSrc This parameter can be one of the following values: 7264 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 7265 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 7266 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 7267 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 7268 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 7269 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 7270 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 7271 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 7272 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 7273 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 7274 */ 7275 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx) 7276 { 7277 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK); 7278 } 7279 7280 /** 7281 * @brief Set the burst mode controller prescaler. 7282 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler 7283 * @param HRTIMx High Resolution Timer instance 7284 * @param Prescaler This parameter can be one of the following values: 7285 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 7286 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2 7287 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4 7288 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8 7289 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16 7290 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32 7291 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64 7292 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128 7293 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256 7294 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512 7295 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024 7296 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048 7297 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096 7298 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192 7299 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 7300 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 7301 * @retval None 7302 */ 7303 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 7304 { 7305 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler); 7306 } 7307 7308 /** 7309 * @brief Get actual burst mode controller prescaler setting. 7310 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler 7311 * @param HRTIMx High Resolution Timer instance 7312 * @retval Prescaler This parameter can be one of the following values: 7313 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 7314 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2 7315 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4 7316 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8 7317 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16 7318 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32 7319 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64 7320 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128 7321 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256 7322 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512 7323 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024 7324 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048 7325 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096 7326 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192 7327 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 7328 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 7329 */ 7330 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx) 7331 { 7332 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC); 7333 } 7334 7335 /** 7336 * @brief Enable burst mode compare and period registers preload. 7337 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload 7338 * @param HRTIMx High Resolution Timer instance 7339 * @retval None 7340 */ 7341 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx) 7342 { 7343 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 7344 } 7345 7346 /** 7347 * @brief Disable burst mode compare and period registers preload. 7348 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload 7349 * @param HRTIMx High Resolution Timer instance 7350 * @retval None 7351 */ 7352 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) 7353 { 7354 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 7355 } 7356 7357 /** 7358 * @brief Indicate whether burst mode compare and period registers are preloaded. 7359 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload 7360 * @param HRTIMx High Resolution Timer instance 7361 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0). 7362 */ 7363 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx) 7364 { 7365 uint32_t temp; /* MISRAC-2012 compliance */ 7366 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 7367 7368 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL); 7369 } 7370 7371 /** 7372 * @brief Set the burst mode controller trigger 7373 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n 7374 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n 7375 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n 7376 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n 7377 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n 7378 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n 7379 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n 7380 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n 7381 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n 7382 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n 7383 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n 7384 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n 7385 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n 7386 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n 7387 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n 7388 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n 7389 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n 7390 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n 7391 * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n 7392 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n 7393 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n 7394 * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n 7395 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n 7396 * BMTRGR TERST LL_HRTIM_BM_SetTrig\n 7397 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n 7398 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n 7399 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n 7400 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n 7401 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n 7402 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n 7403 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n 7404 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig 7405 * @param HRTIMx High Resolution Timer instance 7406 * @param Trig This parameter can be a combination of the following values: 7407 * @arg @ref LL_HRTIM_BM_TRIG_NONE 7408 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET 7409 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION 7410 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1 7411 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2 7412 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3 7413 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4 7414 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET 7415 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION 7416 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1 7417 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2 7418 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET 7419 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION 7420 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1 7421 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2 7422 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET 7423 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION 7424 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1 7425 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2 7426 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET 7427 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION 7428 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1 7429 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2 7430 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET 7431 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION 7432 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1 7433 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2 7434 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7 7435 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8 7436 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7 7437 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 7438 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP 7439 * @retval None 7440 */ 7441 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig) 7442 { 7443 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig); 7444 } 7445 7446 /** 7447 * @brief Get actual burst mode controller trigger. 7448 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n 7449 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n 7450 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n 7451 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n 7452 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n 7453 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n 7454 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n 7455 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n 7456 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n 7457 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n 7458 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n 7459 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n 7460 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n 7461 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n 7462 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n 7463 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n 7464 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n 7465 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n 7466 * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n 7467 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n 7468 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n 7469 * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n 7470 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n 7471 * BMTRGR TERST LL_HRTIM_BM_GetTrig\n 7472 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n 7473 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n 7474 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n 7475 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n 7476 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n 7477 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n 7478 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n 7479 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig 7480 * @param HRTIMx High Resolution Timer instance 7481 * @retval Trig This parameter can be a combination of the following values: 7482 * @arg @ref LL_HRTIM_BM_TRIG_NONE 7483 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET 7484 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION 7485 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1 7486 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2 7487 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3 7488 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4 7489 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET 7490 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION 7491 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1 7492 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2 7493 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET 7494 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION 7495 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1 7496 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2 7497 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET 7498 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION 7499 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1 7500 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2 7501 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET 7502 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION 7503 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1 7504 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2 7505 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET 7506 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION 7507 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1 7508 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2 7509 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7 7510 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8 7511 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7 7512 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 7513 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP 7514 */ 7515 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx) 7516 { 7517 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR); 7518 } 7519 7520 /** 7521 * @brief Set the burst mode controller compare value. 7522 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare 7523 * @param HRTIMx High Resolution Timer instance 7524 * @param CompareValue Compare value must be above or equal to 3 7525 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 7526 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 7527 * @retval None 7528 */ 7529 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue) 7530 { 7531 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue); 7532 } 7533 7534 /** 7535 * @brief Get actual burst mode controller compare value. 7536 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare 7537 * @param HRTIMx High Resolution Timer instance 7538 * @retval CompareValue Compare value must be above or equal to 3 7539 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 7540 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 7541 */ 7542 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx) 7543 { 7544 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR); 7545 } 7546 7547 /** 7548 * @brief Set the burst mode controller period. 7549 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod 7550 * @param HRTIMx High Resolution Timer instance 7551 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock, 7552 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 7553 * The maximum value is 0x0000 FFDF. 7554 * @retval None 7555 */ 7556 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period) 7557 { 7558 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period); 7559 } 7560 7561 /** 7562 * @brief Get actual burst mode controller period. 7563 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod 7564 * @param HRTIMx High Resolution Timer instance 7565 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock, 7566 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 7567 * The maximum value is 0x0000 FFDF. 7568 */ 7569 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx) 7570 { 7571 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER); 7572 } 7573 7574 /** 7575 * @brief Enable the burst mode controller 7576 * @rmtoll BMCR BME LL_HRTIM_BM_Enable 7577 * @param HRTIMx High Resolution Timer instance 7578 * @retval None 7579 */ 7580 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx) 7581 { 7582 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME); 7583 } 7584 7585 /** 7586 * @brief Disable the burst mode controller 7587 * @rmtoll BMCR BME LL_HRTIM_BM_Disable 7588 * @param HRTIMx High Resolution Timer instance 7589 * @retval None 7590 */ 7591 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx) 7592 { 7593 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME); 7594 } 7595 7596 /** 7597 * @brief Indicate whether the burst mode controller is enabled. 7598 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled 7599 * @param HRTIMx High Resolution Timer instance 7600 * @retval State of BME bit in HRTIM_BMCR register (1 or 0). 7601 */ 7602 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx) 7603 { 7604 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL); 7605 } 7606 7607 /** 7608 * @brief Trigger the burst operation (software trigger) 7609 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start 7610 * @param HRTIMx High Resolution Timer instance 7611 * @retval None 7612 */ 7613 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx) 7614 { 7615 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW); 7616 } 7617 7618 /** 7619 * @brief Stop the burst mode operation. 7620 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop 7621 * @note Causes a burst mode early termination. 7622 * @param HRTIMx High Resolution Timer instance 7623 * @retval None 7624 */ 7625 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx) 7626 { 7627 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT); 7628 } 7629 7630 /** 7631 * @brief Get actual burst mode status 7632 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus 7633 * @param HRTIMx High Resolution Timer instance 7634 * @retval Status This parameter can be one of the following values: 7635 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL 7636 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING 7637 */ 7638 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx) 7639 { 7640 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT)); 7641 } 7642 7643 /** 7644 * @} 7645 */ 7646 7647 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management 7648 * @ingroup RTEMSBSPsARMSTM32H7 7649 * @{ 7650 */ 7651 7652 /** 7653 * @brief Clear the Fault 1 interrupt flag. 7654 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1 7655 * @param HRTIMx High Resolution Timer instance 7656 * @retval None 7657 */ 7658 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx) 7659 { 7660 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C); 7661 } 7662 7663 /** 7664 * @brief Indicate whether Fault 1 interrupt occurred. 7665 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1 7666 * @param HRTIMx High Resolution Timer instance 7667 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0). 7668 */ 7669 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx) 7670 { 7671 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL); 7672 } 7673 7674 /** 7675 * @brief Clear the Fault 2 interrupt flag. 7676 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2 7677 * @param HRTIMx High Resolution Timer instance 7678 * @retval None 7679 */ 7680 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx) 7681 { 7682 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C); 7683 } 7684 7685 /** 7686 * @brief Indicate whether Fault 2 interrupt occurred. 7687 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2 7688 * @param HRTIMx High Resolution Timer instance 7689 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0). 7690 */ 7691 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx) 7692 { 7693 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL); 7694 } 7695 7696 /** 7697 * @brief Clear the Fault 3 interrupt flag. 7698 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3 7699 * @param HRTIMx High Resolution Timer instance 7700 * @retval None 7701 */ 7702 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx) 7703 { 7704 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C); 7705 } 7706 7707 /** 7708 * @brief Indicate whether Fault 3 interrupt occurred. 7709 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3 7710 * @param HRTIMx High Resolution Timer instance 7711 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0). 7712 */ 7713 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx) 7714 { 7715 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL); 7716 } 7717 7718 /** 7719 * @brief Clear the Fault 4 interrupt flag. 7720 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4 7721 * @param HRTIMx High Resolution Timer instance 7722 * @retval None 7723 */ 7724 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx) 7725 { 7726 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C); 7727 } 7728 7729 /** 7730 * @brief Indicate whether Fault 4 interrupt occurred. 7731 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4 7732 * @param HRTIMx High Resolution Timer instance 7733 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0). 7734 */ 7735 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx) 7736 { 7737 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL); 7738 } 7739 7740 /** 7741 * @brief Clear the Fault 5 interrupt flag. 7742 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5 7743 * @param HRTIMx High Resolution Timer instance 7744 * @retval None 7745 */ 7746 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx) 7747 { 7748 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C); 7749 } 7750 7751 /** 7752 * @brief Indicate whether Fault 5 interrupt occurred. 7753 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5 7754 * @param HRTIMx High Resolution Timer instance 7755 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0). 7756 */ 7757 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx) 7758 { 7759 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL); 7760 } 7761 7762 /** 7763 * @brief Clear the System Fault interrupt flag. 7764 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT 7765 * @param HRTIMx High Resolution Timer instance 7766 * @retval None 7767 */ 7768 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) 7769 { 7770 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC); 7771 } 7772 7773 /** 7774 * @brief Indicate whether System Fault interrupt occurred. 7775 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT 7776 * @param HRTIMx High Resolution Timer instance 7777 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0). 7778 */ 7779 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx) 7780 { 7781 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL); 7782 } 7783 7784 /** 7785 * @brief Clear the Burst Mode period interrupt flag. 7786 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER 7787 * @param HRTIMx High Resolution Timer instance 7788 * @retval None 7789 */ 7790 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx) 7791 { 7792 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC); 7793 } 7794 7795 /** 7796 * @brief Indicate whether Burst Mode period interrupt occurred. 7797 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER 7798 * @param HRTIMx High Resolution Timer instance 7799 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0). 7800 */ 7801 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx) 7802 { 7803 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL); 7804 } 7805 7806 /** 7807 * @brief Clear the Synchronization Input interrupt flag. 7808 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC 7809 * @param HRTIMx High Resolution Timer instance 7810 * @retval None 7811 */ 7812 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx) 7813 { 7814 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC); 7815 } 7816 7817 /** 7818 * @brief Indicate whether the Synchronization Input interrupt occurred. 7819 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC 7820 * @param HRTIMx High Resolution Timer instance 7821 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0). 7822 */ 7823 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx) 7824 { 7825 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL); 7826 } 7827 7828 /** 7829 * @brief Clear the update interrupt flag for a given timer (including the master timer) . 7830 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n 7831 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE 7832 * @param HRTIMx High Resolution Timer instance 7833 * @param Timer This parameter can be one of the following values: 7834 * @arg @ref LL_HRTIM_TIMER_MASTER 7835 * @arg @ref LL_HRTIM_TIMER_A 7836 * @arg @ref LL_HRTIM_TIMER_B 7837 * @arg @ref LL_HRTIM_TIMER_C 7838 * @arg @ref LL_HRTIM_TIMER_D 7839 * @arg @ref LL_HRTIM_TIMER_E 7840 * @retval None 7841 */ 7842 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7843 { 7844 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7845 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 7846 REG_OFFSET_TAB_TIMER[iTimer])); 7847 SET_BIT(*pReg, HRTIM_MICR_MUPD); 7848 } 7849 7850 /** 7851 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) . 7852 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n 7853 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE 7854 * @param HRTIMx High Resolution Timer instance 7855 * @param Timer This parameter can be one of the following values: 7856 * @arg @ref LL_HRTIM_TIMER_MASTER 7857 * @arg @ref LL_HRTIM_TIMER_A 7858 * @arg @ref LL_HRTIM_TIMER_B 7859 * @arg @ref LL_HRTIM_TIMER_C 7860 * @arg @ref LL_HRTIM_TIMER_D 7861 * @arg @ref LL_HRTIM_TIMER_E 7862 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 7863 */ 7864 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7865 { 7866 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7867 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 7868 REG_OFFSET_TAB_TIMER[iTimer])); 7869 7870 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); 7871 } 7872 7873 /** 7874 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) . 7875 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n 7876 * TIMxICR REPC LL_HRTIM_ClearFlag_REP 7877 * @param HRTIMx High Resolution Timer instance 7878 * @param Timer This parameter can be one of the following values: 7879 * @arg @ref LL_HRTIM_TIMER_MASTER 7880 * @arg @ref LL_HRTIM_TIMER_A 7881 * @arg @ref LL_HRTIM_TIMER_B 7882 * @arg @ref LL_HRTIM_TIMER_C 7883 * @arg @ref LL_HRTIM_TIMER_D 7884 * @arg @ref LL_HRTIM_TIMER_E 7885 * @retval None 7886 */ 7887 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7888 { 7889 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7890 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 7891 REG_OFFSET_TAB_TIMER[iTimer])); 7892 SET_BIT(*pReg, HRTIM_MICR_MREP); 7893 7894 } 7895 7896 /** 7897 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) . 7898 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n 7899 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP 7900 * @param HRTIMx High Resolution Timer instance 7901 * @param Timer This parameter can be one of the following values: 7902 * @arg @ref LL_HRTIM_TIMER_MASTER 7903 * @arg @ref LL_HRTIM_TIMER_A 7904 * @arg @ref LL_HRTIM_TIMER_B 7905 * @arg @ref LL_HRTIM_TIMER_C 7906 * @arg @ref LL_HRTIM_TIMER_D 7907 * @arg @ref LL_HRTIM_TIMER_E 7908 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 7909 */ 7910 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7911 { 7912 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7913 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 7914 REG_OFFSET_TAB_TIMER[iTimer])); 7915 7916 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); 7917 } 7918 7919 /** 7920 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer). 7921 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n 7922 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1 7923 * @param HRTIMx High Resolution Timer instance 7924 * @param Timer This parameter can be one of the following values: 7925 * @arg @ref LL_HRTIM_TIMER_MASTER 7926 * @arg @ref LL_HRTIM_TIMER_A 7927 * @arg @ref LL_HRTIM_TIMER_B 7928 * @arg @ref LL_HRTIM_TIMER_C 7929 * @arg @ref LL_HRTIM_TIMER_D 7930 * @arg @ref LL_HRTIM_TIMER_E 7931 * @retval None 7932 */ 7933 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7934 { 7935 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7936 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 7937 REG_OFFSET_TAB_TIMER[iTimer])); 7938 SET_BIT(*pReg, HRTIM_MICR_MCMP1); 7939 } 7940 7941 /** 7942 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) . 7943 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n 7944 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1 7945 * @param HRTIMx High Resolution Timer instance 7946 * @param Timer This parameter can be one of the following values: 7947 * @arg @ref LL_HRTIM_TIMER_MASTER 7948 * @arg @ref LL_HRTIM_TIMER_A 7949 * @arg @ref LL_HRTIM_TIMER_B 7950 * @arg @ref LL_HRTIM_TIMER_C 7951 * @arg @ref LL_HRTIM_TIMER_D 7952 * @arg @ref LL_HRTIM_TIMER_E 7953 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 7954 */ 7955 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7956 { 7957 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7958 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 7959 REG_OFFSET_TAB_TIMER[iTimer])); 7960 7961 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); 7962 } 7963 7964 /** 7965 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer). 7966 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n 7967 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2 7968 * @param HRTIMx High Resolution Timer instance 7969 * @param Timer This parameter can be one of the following values: 7970 * @arg @ref LL_HRTIM_TIMER_MASTER 7971 * @arg @ref LL_HRTIM_TIMER_A 7972 * @arg @ref LL_HRTIM_TIMER_B 7973 * @arg @ref LL_HRTIM_TIMER_C 7974 * @arg @ref LL_HRTIM_TIMER_D 7975 * @arg @ref LL_HRTIM_TIMER_E 7976 * @retval None 7977 */ 7978 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 7979 { 7980 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 7981 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 7982 REG_OFFSET_TAB_TIMER[iTimer])); 7983 SET_BIT(*pReg, HRTIM_MICR_MCMP2); 7984 } 7985 7986 /** 7987 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) . 7988 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n 7989 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2 7990 * @param HRTIMx High Resolution Timer instance 7991 * @param Timer This parameter can be one of the following values: 7992 * @arg @ref LL_HRTIM_TIMER_MASTER 7993 * @arg @ref LL_HRTIM_TIMER_A 7994 * @arg @ref LL_HRTIM_TIMER_B 7995 * @arg @ref LL_HRTIM_TIMER_C 7996 * @arg @ref LL_HRTIM_TIMER_D 7997 * @arg @ref LL_HRTIM_TIMER_E 7998 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 7999 */ 8000 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8001 { 8002 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8003 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8004 REG_OFFSET_TAB_TIMER[iTimer])); 8005 8006 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); 8007 } 8008 8009 /** 8010 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer). 8011 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n 8012 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3 8013 * @param HRTIMx High Resolution Timer instance 8014 * @param Timer This parameter can be one of the following values: 8015 * @arg @ref LL_HRTIM_TIMER_MASTER 8016 * @arg @ref LL_HRTIM_TIMER_A 8017 * @arg @ref LL_HRTIM_TIMER_B 8018 * @arg @ref LL_HRTIM_TIMER_C 8019 * @arg @ref LL_HRTIM_TIMER_D 8020 * @arg @ref LL_HRTIM_TIMER_E 8021 * @retval None 8022 */ 8023 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8024 { 8025 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8026 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8027 REG_OFFSET_TAB_TIMER[iTimer])); 8028 SET_BIT(*pReg, HRTIM_MICR_MCMP3); 8029 } 8030 8031 /** 8032 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) . 8033 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n 8034 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3 8035 * @param HRTIMx High Resolution Timer instance 8036 * @param Timer This parameter can be one of the following values: 8037 * @arg @ref LL_HRTIM_TIMER_MASTER 8038 * @arg @ref LL_HRTIM_TIMER_A 8039 * @arg @ref LL_HRTIM_TIMER_B 8040 * @arg @ref LL_HRTIM_TIMER_C 8041 * @arg @ref LL_HRTIM_TIMER_D 8042 * @arg @ref LL_HRTIM_TIMER_E 8043 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 8044 */ 8045 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8046 { 8047 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8048 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8049 REG_OFFSET_TAB_TIMER[iTimer])); 8050 8051 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); 8052 } 8053 8054 /** 8055 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer). 8056 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n 8057 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4 8058 * @param HRTIMx High Resolution Timer instance 8059 * @param Timer This parameter can be one of the following values: 8060 * @arg @ref LL_HRTIM_TIMER_MASTER 8061 * @arg @ref LL_HRTIM_TIMER_A 8062 * @arg @ref LL_HRTIM_TIMER_B 8063 * @arg @ref LL_HRTIM_TIMER_C 8064 * @arg @ref LL_HRTIM_TIMER_D 8065 * @arg @ref LL_HRTIM_TIMER_E 8066 * @retval None 8067 */ 8068 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8069 { 8070 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8071 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8072 REG_OFFSET_TAB_TIMER[iTimer])); 8073 SET_BIT(*pReg, HRTIM_MICR_MCMP4); 8074 } 8075 8076 /** 8077 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) . 8078 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n 8079 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4 8080 * @param HRTIMx High Resolution Timer instance 8081 * @param Timer This parameter can be one of the following values: 8082 * @arg @ref LL_HRTIM_TIMER_MASTER 8083 * @arg @ref LL_HRTIM_TIMER_A 8084 * @arg @ref LL_HRTIM_TIMER_B 8085 * @arg @ref LL_HRTIM_TIMER_C 8086 * @arg @ref LL_HRTIM_TIMER_D 8087 * @arg @ref LL_HRTIM_TIMER_E 8088 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 8089 */ 8090 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8091 { 8092 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8093 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8094 REG_OFFSET_TAB_TIMER[iTimer])); 8095 8096 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); 8097 } 8098 8099 /** 8100 * @brief Clear the capture 1 interrupt flag for a given timer. 8101 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1 8102 * @param HRTIMx High Resolution Timer instance 8103 * @param Timer This parameter can be one of the following values: 8104 * @arg @ref LL_HRTIM_TIMER_A 8105 * @arg @ref LL_HRTIM_TIMER_B 8106 * @arg @ref LL_HRTIM_TIMER_C 8107 * @arg @ref LL_HRTIM_TIMER_D 8108 * @arg @ref LL_HRTIM_TIMER_E 8109 * @retval None 8110 */ 8111 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8112 { 8113 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8114 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8115 REG_OFFSET_TAB_TIMER[iTimer])); 8116 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); 8117 } 8118 8119 /** 8120 * @brief Indicate whether the capture 1 interrupt occurred for a given timer. 8121 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1 8122 * @param HRTIMx High Resolution Timer instance 8123 * @param Timer This parameter can be one of the following values: 8124 * @arg @ref LL_HRTIM_TIMER_A 8125 * @arg @ref LL_HRTIM_TIMER_B 8126 * @arg @ref LL_HRTIM_TIMER_C 8127 * @arg @ref LL_HRTIM_TIMER_D 8128 * @arg @ref LL_HRTIM_TIMER_E 8129 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0). 8130 */ 8131 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8132 { 8133 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8134 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8135 REG_OFFSET_TAB_TIMER[iTimer])); 8136 8137 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); 8138 } 8139 8140 /** 8141 * @brief Clear the capture 2 interrupt flag for a given timer. 8142 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2 8143 * @param HRTIMx High Resolution Timer instance 8144 * @param Timer This parameter can be one of the following values: 8145 * @arg @ref LL_HRTIM_TIMER_A 8146 * @arg @ref LL_HRTIM_TIMER_B 8147 * @arg @ref LL_HRTIM_TIMER_C 8148 * @arg @ref LL_HRTIM_TIMER_D 8149 * @arg @ref LL_HRTIM_TIMER_E 8150 * @retval None 8151 */ 8152 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8153 { 8154 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8155 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8156 REG_OFFSET_TAB_TIMER[iTimer])); 8157 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); 8158 } 8159 8160 /** 8161 * @brief Indicate whether the capture 2 interrupt occurred for a given timer. 8162 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2 8163 * @param HRTIMx High Resolution Timer instance 8164 * @param Timer This parameter can be one of the following values: 8165 * @arg @ref LL_HRTIM_TIMER_A 8166 * @arg @ref LL_HRTIM_TIMER_B 8167 * @arg @ref LL_HRTIM_TIMER_C 8168 * @arg @ref LL_HRTIM_TIMER_D 8169 * @arg @ref LL_HRTIM_TIMER_E 8170 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0). 8171 */ 8172 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8173 { 8174 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8175 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8176 REG_OFFSET_TAB_TIMER[iTimer])); 8177 8178 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); 8179 } 8180 8181 /** 8182 * @brief Clear the output 1 set interrupt flag for a given timer. 8183 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1 8184 * @param HRTIMx High Resolution Timer instance 8185 * @param Timer This parameter can be one of the following values: 8186 * @arg @ref LL_HRTIM_TIMER_A 8187 * @arg @ref LL_HRTIM_TIMER_B 8188 * @arg @ref LL_HRTIM_TIMER_C 8189 * @arg @ref LL_HRTIM_TIMER_D 8190 * @arg @ref LL_HRTIM_TIMER_E 8191 * @retval None 8192 */ 8193 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8194 { 8195 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8196 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8197 REG_OFFSET_TAB_TIMER[iTimer])); 8198 SET_BIT(*pReg, HRTIM_TIMICR_SET1C); 8199 } 8200 8201 /** 8202 * @brief Indicate whether the output 1 set interrupt occurred for a given timer. 8203 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1 8204 * @param HRTIMx High Resolution Timer instance 8205 * @param Timer This parameter can be one of the following values: 8206 * @arg @ref LL_HRTIM_TIMER_A 8207 * @arg @ref LL_HRTIM_TIMER_B 8208 * @arg @ref LL_HRTIM_TIMER_C 8209 * @arg @ref LL_HRTIM_TIMER_D 8210 * @arg @ref LL_HRTIM_TIMER_E 8211 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0). 8212 */ 8213 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8214 { 8215 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8216 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8217 REG_OFFSET_TAB_TIMER[iTimer])); 8218 8219 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); 8220 } 8221 8222 /** 8223 * @brief Clear the output 1 reset interrupt flag for a given timer. 8224 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1 8225 * @param HRTIMx High Resolution Timer instance 8226 * @param Timer This parameter can be one of the following values: 8227 * @arg @ref LL_HRTIM_TIMER_A 8228 * @arg @ref LL_HRTIM_TIMER_B 8229 * @arg @ref LL_HRTIM_TIMER_C 8230 * @arg @ref LL_HRTIM_TIMER_D 8231 * @arg @ref LL_HRTIM_TIMER_E 8232 * @retval None 8233 */ 8234 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8235 { 8236 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8237 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8238 REG_OFFSET_TAB_TIMER[iTimer])); 8239 SET_BIT(*pReg, HRTIM_TIMICR_RST1C); 8240 } 8241 8242 /** 8243 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer. 8244 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1 8245 * @param HRTIMx High Resolution Timer instance 8246 * @param Timer This parameter can be one of the following values: 8247 * @arg @ref LL_HRTIM_TIMER_A 8248 * @arg @ref LL_HRTIM_TIMER_B 8249 * @arg @ref LL_HRTIM_TIMER_C 8250 * @arg @ref LL_HRTIM_TIMER_D 8251 * @arg @ref LL_HRTIM_TIMER_E 8252 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0). 8253 */ 8254 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8255 { 8256 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8257 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8258 REG_OFFSET_TAB_TIMER[iTimer])); 8259 8260 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); 8261 } 8262 8263 /** 8264 * @brief Clear the output 2 set interrupt flag for a given timer. 8265 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2 8266 * @param HRTIMx High Resolution Timer instance 8267 * @param Timer This parameter can be one of the following values: 8268 * @arg @ref LL_HRTIM_TIMER_A 8269 * @arg @ref LL_HRTIM_TIMER_B 8270 * @arg @ref LL_HRTIM_TIMER_C 8271 * @arg @ref LL_HRTIM_TIMER_D 8272 * @arg @ref LL_HRTIM_TIMER_E 8273 * @retval None 8274 */ 8275 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8276 { 8277 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8278 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8279 REG_OFFSET_TAB_TIMER[iTimer])); 8280 SET_BIT(*pReg, HRTIM_TIMICR_SET2C); 8281 } 8282 8283 /** 8284 * @brief Indicate whether the output 2 set interrupt occurred for a given timer. 8285 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2 8286 * @param HRTIMx High Resolution Timer instance 8287 * @param Timer This parameter can be one of the following values: 8288 * @arg @ref LL_HRTIM_TIMER_A 8289 * @arg @ref LL_HRTIM_TIMER_B 8290 * @arg @ref LL_HRTIM_TIMER_C 8291 * @arg @ref LL_HRTIM_TIMER_D 8292 * @arg @ref LL_HRTIM_TIMER_E 8293 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0). 8294 */ 8295 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8296 { 8297 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8298 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8299 REG_OFFSET_TAB_TIMER[iTimer])); 8300 8301 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); 8302 } 8303 8304 /** 8305 * @brief Clear the output 2reset interrupt flag for a given timer. 8306 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2 8307 * @param HRTIMx High Resolution Timer instance 8308 * @param Timer This parameter can be one of the following values: 8309 * @arg @ref LL_HRTIM_TIMER_A 8310 * @arg @ref LL_HRTIM_TIMER_B 8311 * @arg @ref LL_HRTIM_TIMER_C 8312 * @arg @ref LL_HRTIM_TIMER_D 8313 * @arg @ref LL_HRTIM_TIMER_E 8314 * @retval None 8315 */ 8316 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8317 { 8318 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8319 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8320 REG_OFFSET_TAB_TIMER[iTimer])); 8321 SET_BIT(*pReg, HRTIM_TIMICR_RST2C); 8322 } 8323 8324 /** 8325 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer. 8326 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2 8327 * @param HRTIMx High Resolution Timer instance 8328 * @param Timer This parameter can be one of the following values: 8329 * @arg @ref LL_HRTIM_TIMER_A 8330 * @arg @ref LL_HRTIM_TIMER_B 8331 * @arg @ref LL_HRTIM_TIMER_C 8332 * @arg @ref LL_HRTIM_TIMER_D 8333 * @arg @ref LL_HRTIM_TIMER_E 8334 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0). 8335 */ 8336 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8337 { 8338 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8339 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8340 REG_OFFSET_TAB_TIMER[iTimer])); 8341 8342 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); 8343 } 8344 8345 /** 8346 * @brief Clear the reset and/or roll-over interrupt flag for a given timer. 8347 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST 8348 * @param HRTIMx High Resolution Timer instance 8349 * @param Timer This parameter can be one of the following values: 8350 * @arg @ref LL_HRTIM_TIMER_A 8351 * @arg @ref LL_HRTIM_TIMER_B 8352 * @arg @ref LL_HRTIM_TIMER_C 8353 * @arg @ref LL_HRTIM_TIMER_D 8354 * @arg @ref LL_HRTIM_TIMER_E 8355 * @retval None 8356 */ 8357 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8358 { 8359 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8361 REG_OFFSET_TAB_TIMER[iTimer])); 8362 SET_BIT(*pReg, HRTIM_TIMICR_RSTC); 8363 } 8364 8365 /** 8366 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer. 8367 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST 8368 * @param HRTIMx High Resolution Timer instance 8369 * @param Timer This parameter can be one of the following values: 8370 * @arg @ref LL_HRTIM_TIMER_A 8371 * @arg @ref LL_HRTIM_TIMER_B 8372 * @arg @ref LL_HRTIM_TIMER_C 8373 * @arg @ref LL_HRTIM_TIMER_D 8374 * @arg @ref LL_HRTIM_TIMER_E 8375 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0). 8376 */ 8377 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8378 { 8379 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8380 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8381 REG_OFFSET_TAB_TIMER[iTimer])); 8382 8383 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); 8384 } 8385 8386 /** 8387 * @brief Clear the delayed protection interrupt flag for a given timer. 8388 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT 8389 * @param HRTIMx High Resolution Timer instance 8390 * @param Timer This parameter can be one of the following values: 8391 * @arg @ref LL_HRTIM_TIMER_A 8392 * @arg @ref LL_HRTIM_TIMER_B 8393 * @arg @ref LL_HRTIM_TIMER_C 8394 * @arg @ref LL_HRTIM_TIMER_D 8395 * @arg @ref LL_HRTIM_TIMER_E 8396 * @retval None 8397 */ 8398 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8399 { 8400 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8401 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 8402 REG_OFFSET_TAB_TIMER[iTimer])); 8403 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); 8404 } 8405 8406 /** 8407 * @brief Indicate whether the delayed protection interrupt occurred for a given timer. 8408 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT 8409 * @param HRTIMx High Resolution Timer instance 8410 * @param Timer This parameter can be one of the following values: 8411 * @arg @ref LL_HRTIM_TIMER_A 8412 * @arg @ref LL_HRTIM_TIMER_B 8413 * @arg @ref LL_HRTIM_TIMER_C 8414 * @arg @ref LL_HRTIM_TIMER_D 8415 * @arg @ref LL_HRTIM_TIMER_E 8416 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0). 8417 */ 8418 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8419 { 8420 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8421 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 8422 REG_OFFSET_TAB_TIMER[iTimer])); 8423 8424 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); 8425 } 8426 8427 /** 8428 * @} 8429 */ 8430 8431 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management 8432 * @ingroup RTEMSBSPsARMSTM32H7 8433 * @{ 8434 */ 8435 8436 /** 8437 * @brief Enable the fault 1 interrupt. 8438 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1 8439 * @param HRTIMx High Resolution Timer instance 8440 * @retval None 8441 */ 8442 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx) 8443 { 8444 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1); 8445 } 8446 8447 /** 8448 * @brief Disable the fault 1 interrupt. 8449 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1 8450 * @param HRTIMx High Resolution Timer instance 8451 * @retval None 8452 */ 8453 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx) 8454 { 8455 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1); 8456 } 8457 8458 /** 8459 * @brief Indicate whether the fault 1 interrupt is enabled. 8460 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1 8461 * @param HRTIMx High Resolution Timer instance 8462 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0). 8463 */ 8464 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx) 8465 { 8466 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); 8467 } 8468 8469 /** 8470 * @brief Enable the fault 2 interrupt. 8471 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2 8472 * @param HRTIMx High Resolution Timer instance 8473 * @retval None 8474 */ 8475 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx) 8476 { 8477 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2); 8478 } 8479 8480 /** 8481 * @brief Disable the fault 2 interrupt. 8482 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2 8483 * @param HRTIMx High Resolution Timer instance 8484 * @retval None 8485 */ 8486 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx) 8487 { 8488 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2); 8489 } 8490 8491 /** 8492 * @brief Indicate whether the fault 2 interrupt is enabled. 8493 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2 8494 * @param HRTIMx High Resolution Timer instance 8495 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0). 8496 */ 8497 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx) 8498 { 8499 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL); 8500 } 8501 8502 /** 8503 * @brief Enable the fault 3 interrupt. 8504 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3 8505 * @param HRTIMx High Resolution Timer instance 8506 * @retval None 8507 */ 8508 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx) 8509 { 8510 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3); 8511 } 8512 8513 /** 8514 * @brief Disable the fault 3 interrupt. 8515 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3 8516 * @param HRTIMx High Resolution Timer instance 8517 * @retval None 8518 */ 8519 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx) 8520 { 8521 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3); 8522 } 8523 8524 /** 8525 * @brief Indicate whether the fault 3 interrupt is enabled. 8526 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3 8527 * @param HRTIMx High Resolution Timer instance 8528 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0). 8529 */ 8530 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx) 8531 { 8532 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL); 8533 } 8534 8535 /** 8536 * @brief Enable the fault 4 interrupt. 8537 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4 8538 * @param HRTIMx High Resolution Timer instance 8539 * @retval None 8540 */ 8541 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx) 8542 { 8543 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4); 8544 } 8545 8546 /** 8547 * @brief Disable the fault 4 interrupt. 8548 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4 8549 * @param HRTIMx High Resolution Timer instance 8550 * @retval None 8551 */ 8552 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx) 8553 { 8554 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4); 8555 } 8556 8557 /** 8558 * @brief Indicate whether the fault 4 interrupt is enabled. 8559 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4 8560 * @param HRTIMx High Resolution Timer instance 8561 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0). 8562 */ 8563 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx) 8564 { 8565 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL); 8566 } 8567 8568 /** 8569 * @brief Enable the fault 5 interrupt. 8570 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5 8571 * @param HRTIMx High Resolution Timer instance 8572 * @retval None 8573 */ 8574 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx) 8575 { 8576 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5); 8577 } 8578 8579 /** 8580 * @brief Disable the fault 5 interrupt. 8581 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5 8582 * @param HRTIMx High Resolution Timer instance 8583 * @retval None 8584 */ 8585 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx) 8586 { 8587 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5); 8588 } 8589 8590 /** 8591 * @brief Indicate whether the fault 5 interrupt is enabled. 8592 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5 8593 * @param HRTIMx High Resolution Timer instance 8594 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0). 8595 */ 8596 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx) 8597 { 8598 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL); 8599 } 8600 8601 /** 8602 * @brief Enable the system fault interrupt. 8603 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT 8604 * @param HRTIMx High Resolution Timer instance 8605 * @retval None 8606 */ 8607 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) 8608 { 8609 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT); 8610 } 8611 8612 /** 8613 * @brief Disable the system fault interrupt. 8614 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT 8615 * @param HRTIMx High Resolution Timer instance 8616 * @retval None 8617 */ 8618 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) 8619 { 8620 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT); 8621 } 8622 8623 /** 8624 * @brief Indicate whether the system fault interrupt is enabled. 8625 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT 8626 * @param HRTIMx High Resolution Timer instance 8627 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0). 8628 */ 8629 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx) 8630 { 8631 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL); 8632 } 8633 8634 /** 8635 * @brief Enable the burst mode period interrupt. 8636 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER 8637 * @param HRTIMx High Resolution Timer instance 8638 * @retval None 8639 */ 8640 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx) 8641 { 8642 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER); 8643 } 8644 8645 /** 8646 * @brief Disable the burst mode period interrupt. 8647 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER 8648 * @param HRTIMx High Resolution Timer instance 8649 * @retval None 8650 */ 8651 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx) 8652 { 8653 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER); 8654 } 8655 8656 /** 8657 * @brief Indicate whether the burst mode period interrupt is enabled. 8658 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER 8659 * @param HRTIMx High Resolution Timer instance 8660 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0). 8661 */ 8662 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx) 8663 { 8664 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL); 8665 } 8666 8667 /** 8668 * @brief Enable the synchronization input interrupt. 8669 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC 8670 * @param HRTIMx High Resolution Timer instance 8671 * @retval None 8672 */ 8673 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx) 8674 { 8675 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); 8676 } 8677 8678 /** 8679 * @brief Disable the synchronization input interrupt. 8680 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC 8681 * @param HRTIMx High Resolution Timer instance 8682 * @retval None 8683 */ 8684 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx) 8685 { 8686 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); 8687 } 8688 8689 /** 8690 * @brief Indicate whether the synchronization input interrupt is enabled. 8691 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC 8692 * @param HRTIMx High Resolution Timer instance 8693 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0). 8694 */ 8695 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx) 8696 { 8697 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL); 8698 } 8699 8700 /** 8701 * @brief Enable the update interrupt for a given timer. 8702 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n 8703 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE 8704 * @param HRTIMx High Resolution Timer instance 8705 * @param Timer This parameter can be one of the following values: 8706 * @arg @ref LL_HRTIM_TIMER_MASTER 8707 * @arg @ref LL_HRTIM_TIMER_A 8708 * @arg @ref LL_HRTIM_TIMER_B 8709 * @arg @ref LL_HRTIM_TIMER_C 8710 * @arg @ref LL_HRTIM_TIMER_D 8711 * @arg @ref LL_HRTIM_TIMER_E 8712 * @retval None 8713 */ 8714 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8715 { 8716 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8717 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8718 REG_OFFSET_TAB_TIMER[iTimer])); 8719 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); 8720 } 8721 8722 /** 8723 * @brief Disable the update interrupt for a given timer. 8724 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n 8725 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE 8726 * @param HRTIMx High Resolution Timer instance 8727 * @param Timer This parameter can be one of the following values: 8728 * @arg @ref LL_HRTIM_TIMER_MASTER 8729 * @arg @ref LL_HRTIM_TIMER_A 8730 * @arg @ref LL_HRTIM_TIMER_B 8731 * @arg @ref LL_HRTIM_TIMER_C 8732 * @arg @ref LL_HRTIM_TIMER_D 8733 * @arg @ref LL_HRTIM_TIMER_E 8734 * @retval None 8735 */ 8736 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8737 { 8738 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8739 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8740 REG_OFFSET_TAB_TIMER[iTimer])); 8741 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); 8742 } 8743 8744 /** 8745 * @brief Indicate whether the update interrupt is enabled for a given timer. 8746 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n 8747 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE 8748 * @param HRTIMx High Resolution Timer instance 8749 * @param Timer This parameter can be one of the following values: 8750 * @arg @ref LL_HRTIM_TIMER_MASTER 8751 * @arg @ref LL_HRTIM_TIMER_A 8752 * @arg @ref LL_HRTIM_TIMER_B 8753 * @arg @ref LL_HRTIM_TIMER_C 8754 * @arg @ref LL_HRTIM_TIMER_D 8755 * @arg @ref LL_HRTIM_TIMER_E 8756 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 8757 */ 8758 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8759 { 8760 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8761 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8762 REG_OFFSET_TAB_TIMER[iTimer])); 8763 8764 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); 8765 } 8766 8767 /** 8768 * @brief Enable the repetition interrupt for a given timer. 8769 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n 8770 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP 8771 * @param HRTIMx High Resolution Timer instance 8772 * @param Timer This parameter can be one of the following values: 8773 * @arg @ref LL_HRTIM_TIMER_MASTER 8774 * @arg @ref LL_HRTIM_TIMER_A 8775 * @arg @ref LL_HRTIM_TIMER_B 8776 * @arg @ref LL_HRTIM_TIMER_C 8777 * @arg @ref LL_HRTIM_TIMER_D 8778 * @arg @ref LL_HRTIM_TIMER_E 8779 * @retval None 8780 */ 8781 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8782 { 8783 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8784 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8785 REG_OFFSET_TAB_TIMER[iTimer])); 8786 SET_BIT(*pReg, HRTIM_MDIER_MREPIE); 8787 } 8788 8789 /** 8790 * @brief Disable the repetition interrupt for a given timer. 8791 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n 8792 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP 8793 * @param HRTIMx High Resolution Timer instance 8794 * @param Timer This parameter can be one of the following values: 8795 * @arg @ref LL_HRTIM_TIMER_MASTER 8796 * @arg @ref LL_HRTIM_TIMER_A 8797 * @arg @ref LL_HRTIM_TIMER_B 8798 * @arg @ref LL_HRTIM_TIMER_C 8799 * @arg @ref LL_HRTIM_TIMER_D 8800 * @arg @ref LL_HRTIM_TIMER_E 8801 * @retval None 8802 */ 8803 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8804 { 8805 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8806 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8807 REG_OFFSET_TAB_TIMER[iTimer])); 8808 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); 8809 } 8810 8811 /** 8812 * @brief Indicate whether the repetition interrupt is enabled for a given timer. 8813 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n 8814 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP 8815 * @param HRTIMx High Resolution Timer instance 8816 * @param Timer This parameter can be one of the following values: 8817 * @arg @ref LL_HRTIM_TIMER_MASTER 8818 * @arg @ref LL_HRTIM_TIMER_A 8819 * @arg @ref LL_HRTIM_TIMER_B 8820 * @arg @ref LL_HRTIM_TIMER_C 8821 * @arg @ref LL_HRTIM_TIMER_D 8822 * @arg @ref LL_HRTIM_TIMER_E 8823 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 8824 */ 8825 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8826 { 8827 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8828 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8829 REG_OFFSET_TAB_TIMER[iTimer])); 8830 8831 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); 8832 } 8833 8834 /** 8835 * @brief Enable the compare 1 interrupt for a given timer. 8836 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n 8837 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1 8838 * @param HRTIMx High Resolution Timer instance 8839 * @param Timer This parameter can be one of the following values: 8840 * @arg @ref LL_HRTIM_TIMER_MASTER 8841 * @arg @ref LL_HRTIM_TIMER_A 8842 * @arg @ref LL_HRTIM_TIMER_B 8843 * @arg @ref LL_HRTIM_TIMER_C 8844 * @arg @ref LL_HRTIM_TIMER_D 8845 * @arg @ref LL_HRTIM_TIMER_E 8846 * @retval None 8847 */ 8848 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8849 { 8850 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8851 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8852 REG_OFFSET_TAB_TIMER[iTimer])); 8853 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); 8854 } 8855 8856 /** 8857 * @brief Disable the compare 1 interrupt for a given timer. 8858 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n 8859 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1 8860 * @param HRTIMx High Resolution Timer instance 8861 * @param Timer This parameter can be one of the following values: 8862 * @arg @ref LL_HRTIM_TIMER_MASTER 8863 * @arg @ref LL_HRTIM_TIMER_A 8864 * @arg @ref LL_HRTIM_TIMER_B 8865 * @arg @ref LL_HRTIM_TIMER_C 8866 * @arg @ref LL_HRTIM_TIMER_D 8867 * @arg @ref LL_HRTIM_TIMER_E 8868 * @retval None 8869 */ 8870 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8871 { 8872 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8873 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8874 REG_OFFSET_TAB_TIMER[iTimer])); 8875 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); 8876 } 8877 8878 /** 8879 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer. 8880 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n 8881 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1 8882 * @param HRTIMx High Resolution Timer instance 8883 * @param Timer This parameter can be one of the following values: 8884 * @arg @ref LL_HRTIM_TIMER_MASTER 8885 * @arg @ref LL_HRTIM_TIMER_A 8886 * @arg @ref LL_HRTIM_TIMER_B 8887 * @arg @ref LL_HRTIM_TIMER_C 8888 * @arg @ref LL_HRTIM_TIMER_D 8889 * @arg @ref LL_HRTIM_TIMER_E 8890 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 8891 */ 8892 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8893 { 8894 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8895 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8896 REG_OFFSET_TAB_TIMER[iTimer])); 8897 8898 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); 8899 } 8900 8901 /** 8902 * @brief Enable the compare 2 interrupt for a given timer. 8903 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n 8904 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2 8905 * @param HRTIMx High Resolution Timer instance 8906 * @param Timer This parameter can be one of the following values: 8907 * @arg @ref LL_HRTIM_TIMER_MASTER 8908 * @arg @ref LL_HRTIM_TIMER_A 8909 * @arg @ref LL_HRTIM_TIMER_B 8910 * @arg @ref LL_HRTIM_TIMER_C 8911 * @arg @ref LL_HRTIM_TIMER_D 8912 * @arg @ref LL_HRTIM_TIMER_E 8913 * @retval None 8914 */ 8915 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8916 { 8917 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8918 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8919 REG_OFFSET_TAB_TIMER[iTimer])); 8920 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); 8921 } 8922 8923 /** 8924 * @brief Disable the compare 2 interrupt for a given timer. 8925 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n 8926 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2 8927 * @param HRTIMx High Resolution Timer instance 8928 * @param Timer This parameter can be one of the following values: 8929 * @arg @ref LL_HRTIM_TIMER_MASTER 8930 * @arg @ref LL_HRTIM_TIMER_A 8931 * @arg @ref LL_HRTIM_TIMER_B 8932 * @arg @ref LL_HRTIM_TIMER_C 8933 * @arg @ref LL_HRTIM_TIMER_D 8934 * @arg @ref LL_HRTIM_TIMER_E 8935 * @retval None 8936 */ 8937 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8938 { 8939 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8941 REG_OFFSET_TAB_TIMER[iTimer])); 8942 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); 8943 } 8944 8945 /** 8946 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer. 8947 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n 8948 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2 8949 * @param HRTIMx High Resolution Timer instance 8950 * @param Timer This parameter can be one of the following values: 8951 * @arg @ref LL_HRTIM_TIMER_MASTER 8952 * @arg @ref LL_HRTIM_TIMER_A 8953 * @arg @ref LL_HRTIM_TIMER_B 8954 * @arg @ref LL_HRTIM_TIMER_C 8955 * @arg @ref LL_HRTIM_TIMER_D 8956 * @arg @ref LL_HRTIM_TIMER_E 8957 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 8958 */ 8959 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8960 { 8961 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8962 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8963 REG_OFFSET_TAB_TIMER[iTimer])); 8964 8965 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); 8966 } 8967 8968 /** 8969 * @brief Enable the compare 3 interrupt for a given timer. 8970 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n 8971 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3 8972 * @param HRTIMx High Resolution Timer instance 8973 * @param Timer This parameter can be one of the following values: 8974 * @arg @ref LL_HRTIM_TIMER_MASTER 8975 * @arg @ref LL_HRTIM_TIMER_A 8976 * @arg @ref LL_HRTIM_TIMER_B 8977 * @arg @ref LL_HRTIM_TIMER_C 8978 * @arg @ref LL_HRTIM_TIMER_D 8979 * @arg @ref LL_HRTIM_TIMER_E 8980 * @retval None 8981 */ 8982 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 8983 { 8984 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 8985 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 8986 REG_OFFSET_TAB_TIMER[iTimer])); 8987 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); 8988 } 8989 8990 /** 8991 * @brief Disable the compare 3 interrupt for a given timer. 8992 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n 8993 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3 8994 * @param HRTIMx High Resolution Timer instance 8995 * @param Timer This parameter can be one of the following values: 8996 * @arg @ref LL_HRTIM_TIMER_MASTER 8997 * @arg @ref LL_HRTIM_TIMER_A 8998 * @arg @ref LL_HRTIM_TIMER_B 8999 * @arg @ref LL_HRTIM_TIMER_C 9000 * @arg @ref LL_HRTIM_TIMER_D 9001 * @arg @ref LL_HRTIM_TIMER_E 9002 * @retval None 9003 */ 9004 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9005 { 9006 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9007 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9008 REG_OFFSET_TAB_TIMER[iTimer])); 9009 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); 9010 } 9011 9012 /** 9013 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer. 9014 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n 9015 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3 9016 * @param HRTIMx High Resolution Timer instance 9017 * @param Timer This parameter can be one of the following values: 9018 * @arg @ref LL_HRTIM_TIMER_MASTER 9019 * @arg @ref LL_HRTIM_TIMER_A 9020 * @arg @ref LL_HRTIM_TIMER_B 9021 * @arg @ref LL_HRTIM_TIMER_C 9022 * @arg @ref LL_HRTIM_TIMER_D 9023 * @arg @ref LL_HRTIM_TIMER_E 9024 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9025 */ 9026 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9027 { 9028 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9029 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9030 REG_OFFSET_TAB_TIMER[iTimer])); 9031 9032 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); 9033 } 9034 9035 /** 9036 * @brief Enable the compare 4 interrupt for a given timer. 9037 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n 9038 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4 9039 * @param HRTIMx High Resolution Timer instance 9040 * @param Timer This parameter can be one of the following values: 9041 * @arg @ref LL_HRTIM_TIMER_MASTER 9042 * @arg @ref LL_HRTIM_TIMER_A 9043 * @arg @ref LL_HRTIM_TIMER_B 9044 * @arg @ref LL_HRTIM_TIMER_C 9045 * @arg @ref LL_HRTIM_TIMER_D 9046 * @arg @ref LL_HRTIM_TIMER_E 9047 * @retval None 9048 */ 9049 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9050 { 9051 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9052 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9053 REG_OFFSET_TAB_TIMER[iTimer])); 9054 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); 9055 } 9056 9057 /** 9058 * @brief Disable the compare 4 interrupt for a given timer. 9059 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n 9060 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4 9061 * @param HRTIMx High Resolution Timer instance 9062 * @param Timer This parameter can be one of the following values: 9063 * @arg @ref LL_HRTIM_TIMER_MASTER 9064 * @arg @ref LL_HRTIM_TIMER_A 9065 * @arg @ref LL_HRTIM_TIMER_B 9066 * @arg @ref LL_HRTIM_TIMER_C 9067 * @arg @ref LL_HRTIM_TIMER_D 9068 * @arg @ref LL_HRTIM_TIMER_E 9069 * @retval None 9070 */ 9071 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9072 { 9073 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9074 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9075 REG_OFFSET_TAB_TIMER[iTimer])); 9076 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); 9077 } 9078 9079 /** 9080 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer. 9081 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n 9082 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4 9083 * @param HRTIMx High Resolution Timer instance 9084 * @param Timer This parameter can be one of the following values: 9085 * @arg @ref LL_HRTIM_TIMER_MASTER 9086 * @arg @ref LL_HRTIM_TIMER_A 9087 * @arg @ref LL_HRTIM_TIMER_B 9088 * @arg @ref LL_HRTIM_TIMER_C 9089 * @arg @ref LL_HRTIM_TIMER_D 9090 * @arg @ref LL_HRTIM_TIMER_E 9091 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9092 */ 9093 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9094 { 9095 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9096 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9097 REG_OFFSET_TAB_TIMER[iTimer])); 9098 9099 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); 9100 } 9101 9102 /** 9103 * @brief Enable the capture 1 interrupt for a given timer. 9104 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1 9105 * @param HRTIMx High Resolution Timer instance 9106 * @param Timer This parameter can be one of the following values: 9107 * @arg @ref LL_HRTIM_TIMER_A 9108 * @arg @ref LL_HRTIM_TIMER_B 9109 * @arg @ref LL_HRTIM_TIMER_C 9110 * @arg @ref LL_HRTIM_TIMER_D 9111 * @arg @ref LL_HRTIM_TIMER_E 9112 * @retval None 9113 */ 9114 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9115 { 9116 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9117 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9118 REG_OFFSET_TAB_TIMER[iTimer])); 9119 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); 9120 } 9121 9122 /** 9123 * @brief Enable the capture 1 interrupt for a given timer. 9124 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1 9125 * @param HRTIMx High Resolution Timer instance 9126 * @param Timer This parameter can be one of the following values: 9127 * @arg @ref LL_HRTIM_TIMER_A 9128 * @arg @ref LL_HRTIM_TIMER_B 9129 * @arg @ref LL_HRTIM_TIMER_C 9130 * @arg @ref LL_HRTIM_TIMER_D 9131 * @arg @ref LL_HRTIM_TIMER_E 9132 * @retval None 9133 */ 9134 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9135 { 9136 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9137 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9138 REG_OFFSET_TAB_TIMER[iTimer])); 9139 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); 9140 } 9141 9142 /** 9143 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer. 9144 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1 9145 * @param HRTIMx High Resolution Timer instance 9146 * @param Timer This parameter can be one of the following values: 9147 * @arg @ref LL_HRTIM_TIMER_A 9148 * @arg @ref LL_HRTIM_TIMER_B 9149 * @arg @ref LL_HRTIM_TIMER_C 9150 * @arg @ref LL_HRTIM_TIMER_D 9151 * @arg @ref LL_HRTIM_TIMER_E 9152 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0). 9153 */ 9154 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9155 { 9156 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9157 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9158 REG_OFFSET_TAB_TIMER[iTimer])); 9159 9160 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); 9161 } 9162 9163 /** 9164 * @brief Enable the capture 2 interrupt for a given timer. 9165 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2 9166 * @param HRTIMx High Resolution Timer instance 9167 * @param Timer This parameter can be one of the following values: 9168 * @arg @ref LL_HRTIM_TIMER_A 9169 * @arg @ref LL_HRTIM_TIMER_B 9170 * @arg @ref LL_HRTIM_TIMER_C 9171 * @arg @ref LL_HRTIM_TIMER_D 9172 * @arg @ref LL_HRTIM_TIMER_E 9173 * @retval None 9174 */ 9175 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9176 { 9177 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9178 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9179 REG_OFFSET_TAB_TIMER[iTimer])); 9180 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); 9181 } 9182 9183 /** 9184 * @brief Enable the capture 2 interrupt for a given timer. 9185 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2 9186 * @param HRTIMx High Resolution Timer instance 9187 * @param Timer This parameter can be one of the following values: 9188 * @arg @ref LL_HRTIM_TIMER_A 9189 * @arg @ref LL_HRTIM_TIMER_B 9190 * @arg @ref LL_HRTIM_TIMER_C 9191 * @arg @ref LL_HRTIM_TIMER_D 9192 * @arg @ref LL_HRTIM_TIMER_E 9193 * @retval None 9194 */ 9195 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9196 { 9197 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9198 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9199 REG_OFFSET_TAB_TIMER[iTimer])); 9200 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); 9201 } 9202 9203 /** 9204 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer. 9205 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2 9206 * @param HRTIMx High Resolution Timer instance 9207 * @param Timer This parameter can be one of the following values: 9208 * @arg @ref LL_HRTIM_TIMER_A 9209 * @arg @ref LL_HRTIM_TIMER_B 9210 * @arg @ref LL_HRTIM_TIMER_C 9211 * @arg @ref LL_HRTIM_TIMER_D 9212 * @arg @ref LL_HRTIM_TIMER_E 9213 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0). 9214 */ 9215 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9216 { 9217 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9218 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9219 REG_OFFSET_TAB_TIMER[iTimer])); 9220 9221 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); 9222 } 9223 9224 /** 9225 * @brief Enable the output 1 set interrupt for a given timer. 9226 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1 9227 * @param HRTIMx High Resolution Timer instance 9228 * @param Timer This parameter can be one of the following values: 9229 * @arg @ref LL_HRTIM_TIMER_A 9230 * @arg @ref LL_HRTIM_TIMER_B 9231 * @arg @ref LL_HRTIM_TIMER_C 9232 * @arg @ref LL_HRTIM_TIMER_D 9233 * @arg @ref LL_HRTIM_TIMER_E 9234 * @retval None 9235 */ 9236 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9237 { 9238 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9239 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9240 REG_OFFSET_TAB_TIMER[iTimer])); 9241 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); 9242 } 9243 9244 /** 9245 * @brief Disable the output 1 set interrupt for a given timer. 9246 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1 9247 * @param HRTIMx High Resolution Timer instance 9248 * @param Timer This parameter can be one of the following values: 9249 * @arg @ref LL_HRTIM_TIMER_A 9250 * @arg @ref LL_HRTIM_TIMER_B 9251 * @arg @ref LL_HRTIM_TIMER_C 9252 * @arg @ref LL_HRTIM_TIMER_D 9253 * @arg @ref LL_HRTIM_TIMER_E 9254 * @retval None 9255 */ 9256 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9257 { 9258 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9259 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9260 REG_OFFSET_TAB_TIMER[iTimer])); 9261 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); 9262 } 9263 9264 /** 9265 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer. 9266 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1 9267 * @param HRTIMx High Resolution Timer instance 9268 * @param Timer This parameter can be one of the following values: 9269 * @arg @ref LL_HRTIM_TIMER_A 9270 * @arg @ref LL_HRTIM_TIMER_B 9271 * @arg @ref LL_HRTIM_TIMER_C 9272 * @arg @ref LL_HRTIM_TIMER_D 9273 * @arg @ref LL_HRTIM_TIMER_E 9274 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0). 9275 */ 9276 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9277 { 9278 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9279 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9280 REG_OFFSET_TAB_TIMER[iTimer])); 9281 9282 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); 9283 } 9284 9285 /** 9286 * @brief Enable the output 1 reset interrupt for a given timer. 9287 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1 9288 * @param HRTIMx High Resolution Timer instance 9289 * @param Timer This parameter can be one of the following values: 9290 * @arg @ref LL_HRTIM_TIMER_A 9291 * @arg @ref LL_HRTIM_TIMER_B 9292 * @arg @ref LL_HRTIM_TIMER_C 9293 * @arg @ref LL_HRTIM_TIMER_D 9294 * @arg @ref LL_HRTIM_TIMER_E 9295 * @retval None 9296 */ 9297 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9298 { 9299 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9300 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9301 REG_OFFSET_TAB_TIMER[iTimer])); 9302 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); 9303 } 9304 9305 /** 9306 * @brief Disable the output 1 reset interrupt for a given timer. 9307 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1 9308 * @param HRTIMx High Resolution Timer instance 9309 * @param Timer This parameter can be one of the following values: 9310 * @arg @ref LL_HRTIM_TIMER_A 9311 * @arg @ref LL_HRTIM_TIMER_B 9312 * @arg @ref LL_HRTIM_TIMER_C 9313 * @arg @ref LL_HRTIM_TIMER_D 9314 * @arg @ref LL_HRTIM_TIMER_E 9315 * @retval None 9316 */ 9317 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9318 { 9319 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9320 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9321 REG_OFFSET_TAB_TIMER[iTimer])); 9322 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); 9323 } 9324 9325 /** 9326 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer. 9327 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1 9328 * @param HRTIMx High Resolution Timer instance 9329 * @param Timer This parameter can be one of the following values: 9330 * @arg @ref LL_HRTIM_TIMER_A 9331 * @arg @ref LL_HRTIM_TIMER_B 9332 * @arg @ref LL_HRTIM_TIMER_C 9333 * @arg @ref LL_HRTIM_TIMER_D 9334 * @arg @ref LL_HRTIM_TIMER_E 9335 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0). 9336 */ 9337 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9338 { 9339 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9340 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9341 REG_OFFSET_TAB_TIMER[iTimer])); 9342 9343 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); 9344 } 9345 9346 /** 9347 * @brief Enable the output 2 set interrupt for a given timer. 9348 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2 9349 * @param HRTIMx High Resolution Timer instance 9350 * @param Timer This parameter can be one of the following values: 9351 * @arg @ref LL_HRTIM_TIMER_A 9352 * @arg @ref LL_HRTIM_TIMER_B 9353 * @arg @ref LL_HRTIM_TIMER_C 9354 * @arg @ref LL_HRTIM_TIMER_D 9355 * @arg @ref LL_HRTIM_TIMER_E 9356 * @retval None 9357 */ 9358 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9359 { 9360 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9361 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9362 REG_OFFSET_TAB_TIMER[iTimer])); 9363 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); 9364 } 9365 9366 /** 9367 * @brief Disable the output 2 set interrupt for a given timer. 9368 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2 9369 * @param HRTIMx High Resolution Timer instance 9370 * @param Timer This parameter can be one of the following values: 9371 * @arg @ref LL_HRTIM_TIMER_A 9372 * @arg @ref LL_HRTIM_TIMER_B 9373 * @arg @ref LL_HRTIM_TIMER_C 9374 * @arg @ref LL_HRTIM_TIMER_D 9375 * @arg @ref LL_HRTIM_TIMER_E 9376 * @retval None 9377 */ 9378 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9379 { 9380 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9381 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9382 REG_OFFSET_TAB_TIMER[iTimer])); 9383 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); 9384 } 9385 9386 /** 9387 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer. 9388 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2 9389 * @param HRTIMx High Resolution Timer instance 9390 * @param Timer This parameter can be one of the following values: 9391 * @arg @ref LL_HRTIM_TIMER_A 9392 * @arg @ref LL_HRTIM_TIMER_B 9393 * @arg @ref LL_HRTIM_TIMER_C 9394 * @arg @ref LL_HRTIM_TIMER_D 9395 * @arg @ref LL_HRTIM_TIMER_E 9396 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0). 9397 */ 9398 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9399 { 9400 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9401 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9402 REG_OFFSET_TAB_TIMER[iTimer])); 9403 9404 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); 9405 } 9406 9407 /** 9408 * @brief Enable the output 2 reset interrupt for a given timer. 9409 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2 9410 * @param HRTIMx High Resolution Timer instance 9411 * @param Timer This parameter can be one of the following values: 9412 * @arg @ref LL_HRTIM_TIMER_A 9413 * @arg @ref LL_HRTIM_TIMER_B 9414 * @arg @ref LL_HRTIM_TIMER_C 9415 * @arg @ref LL_HRTIM_TIMER_D 9416 * @arg @ref LL_HRTIM_TIMER_E 9417 * @retval None 9418 */ 9419 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9420 { 9421 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9422 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9423 REG_OFFSET_TAB_TIMER[iTimer])); 9424 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); 9425 } 9426 9427 /** 9428 * @brief Disable the output 2 reset interrupt for a given timer. 9429 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2 9430 * @param HRTIMx High Resolution Timer instance 9431 * @param Timer This parameter can be one of the following values: 9432 * @arg @ref LL_HRTIM_TIMER_A 9433 * @arg @ref LL_HRTIM_TIMER_B 9434 * @arg @ref LL_HRTIM_TIMER_C 9435 * @arg @ref LL_HRTIM_TIMER_D 9436 * @arg @ref LL_HRTIM_TIMER_E 9437 * @retval None 9438 */ 9439 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9440 { 9441 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9442 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9443 REG_OFFSET_TAB_TIMER[iTimer])); 9444 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); 9445 } 9446 9447 /** 9448 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer. 9449 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2 9450 * @param HRTIMx High Resolution Timer instance 9451 * @param Timer This parameter can be one of the following values: 9452 * @arg @ref LL_HRTIM_TIMER_A 9453 * @arg @ref LL_HRTIM_TIMER_B 9454 * @arg @ref LL_HRTIM_TIMER_C 9455 * @arg @ref LL_HRTIM_TIMER_D 9456 * @arg @ref LL_HRTIM_TIMER_E 9457 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0). 9458 */ 9459 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9460 { 9461 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9462 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9463 REG_OFFSET_TAB_TIMER[iTimer])); 9464 9465 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); 9466 } 9467 9468 /** 9469 * @brief Enable the reset/roll-over interrupt for a given timer. 9470 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST 9471 * @param HRTIMx High Resolution Timer instance 9472 * @param Timer This parameter can be one of the following values: 9473 * @arg @ref LL_HRTIM_TIMER_A 9474 * @arg @ref LL_HRTIM_TIMER_B 9475 * @arg @ref LL_HRTIM_TIMER_C 9476 * @arg @ref LL_HRTIM_TIMER_D 9477 * @arg @ref LL_HRTIM_TIMER_E 9478 * @retval None 9479 */ 9480 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9481 { 9482 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9483 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9484 REG_OFFSET_TAB_TIMER[iTimer])); 9485 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); 9486 } 9487 9488 /** 9489 * @brief Disable the reset/roll-over interrupt for a given timer. 9490 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST 9491 * @param HRTIMx High Resolution Timer instance 9492 * @param Timer This parameter can be one of the following values: 9493 * @arg @ref LL_HRTIM_TIMER_A 9494 * @arg @ref LL_HRTIM_TIMER_B 9495 * @arg @ref LL_HRTIM_TIMER_C 9496 * @arg @ref LL_HRTIM_TIMER_D 9497 * @arg @ref LL_HRTIM_TIMER_E 9498 * @retval None 9499 */ 9500 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9501 { 9502 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9503 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9504 REG_OFFSET_TAB_TIMER[iTimer])); 9505 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); 9506 } 9507 9508 /** 9509 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer. 9510 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST 9511 * @param HRTIMx High Resolution Timer instance 9512 * @param Timer This parameter can be one of the following values: 9513 * @arg @ref LL_HRTIM_TIMER_A 9514 * @arg @ref LL_HRTIM_TIMER_B 9515 * @arg @ref LL_HRTIM_TIMER_C 9516 * @arg @ref LL_HRTIM_TIMER_D 9517 * @arg @ref LL_HRTIM_TIMER_E 9518 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0). 9519 */ 9520 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9521 { 9522 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9523 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9524 REG_OFFSET_TAB_TIMER[iTimer])); 9525 9526 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); 9527 } 9528 9529 /** 9530 * @brief Enable the delayed protection interrupt for a given timer. 9531 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT 9532 * @param HRTIMx High Resolution Timer instance 9533 * @param Timer This parameter can be one of the following values: 9534 * @arg @ref LL_HRTIM_TIMER_A 9535 * @arg @ref LL_HRTIM_TIMER_B 9536 * @arg @ref LL_HRTIM_TIMER_C 9537 * @arg @ref LL_HRTIM_TIMER_D 9538 * @arg @ref LL_HRTIM_TIMER_E 9539 * @retval None 9540 */ 9541 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9542 { 9543 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9544 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9545 REG_OFFSET_TAB_TIMER[iTimer])); 9546 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); 9547 } 9548 9549 /** 9550 * @brief Disable the delayed protection interrupt for a given timer. 9551 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT 9552 * @param HRTIMx High Resolution Timer instance 9553 * @param Timer This parameter can be one of the following values: 9554 * @arg @ref LL_HRTIM_TIMER_A 9555 * @arg @ref LL_HRTIM_TIMER_B 9556 * @arg @ref LL_HRTIM_TIMER_C 9557 * @arg @ref LL_HRTIM_TIMER_D 9558 * @arg @ref LL_HRTIM_TIMER_E 9559 * @retval None 9560 */ 9561 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9562 { 9563 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9564 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9565 REG_OFFSET_TAB_TIMER[iTimer])); 9566 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); 9567 } 9568 9569 /** 9570 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer. 9571 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT 9572 * @param HRTIMx High Resolution Timer instance 9573 * @param Timer This parameter can be one of the following values: 9574 * @arg @ref LL_HRTIM_TIMER_A 9575 * @arg @ref LL_HRTIM_TIMER_B 9576 * @arg @ref LL_HRTIM_TIMER_C 9577 * @arg @ref LL_HRTIM_TIMER_D 9578 * @arg @ref LL_HRTIM_TIMER_E 9579 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0). 9580 */ 9581 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9582 { 9583 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9584 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9585 REG_OFFSET_TAB_TIMER[iTimer])); 9586 9587 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); 9588 } 9589 9590 /** 9591 * @} 9592 */ 9593 9594 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management 9595 * @ingroup RTEMSBSPsARMSTM32H7 9596 * @{ 9597 */ 9598 9599 /** 9600 * @brief Enable the synchronization input DMA request. 9601 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC 9602 * @param HRTIMx High Resolution Timer instance 9603 * @retval None 9604 */ 9605 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) 9606 { 9607 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE); 9608 } 9609 9610 /** 9611 * @brief Disable the synchronization input DMA request 9612 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC 9613 * @param HRTIMx High Resolution Timer instance 9614 * @retval None 9615 */ 9616 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) 9617 { 9618 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE); 9619 } 9620 9621 /** 9622 * @brief Indicate whether the synchronization input DMA request is enabled. 9623 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC 9624 * @param HRTIMx High Resolution Timer instance 9625 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0). 9626 */ 9627 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx) 9628 { 9629 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL); 9630 } 9631 9632 /** 9633 * @brief Enable the update DMA request for a given timer. 9634 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n 9635 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE 9636 * @param HRTIMx High Resolution Timer instance 9637 * @param Timer This parameter can be one of the following values: 9638 * @arg @ref LL_HRTIM_TIMER_MASTER 9639 * @arg @ref LL_HRTIM_TIMER_A 9640 * @arg @ref LL_HRTIM_TIMER_B 9641 * @arg @ref LL_HRTIM_TIMER_C 9642 * @arg @ref LL_HRTIM_TIMER_D 9643 * @arg @ref LL_HRTIM_TIMER_E 9644 * @retval None 9645 */ 9646 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9647 { 9648 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9649 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9650 REG_OFFSET_TAB_TIMER[iTimer])); 9651 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); 9652 } 9653 9654 /** 9655 * @brief Disable the update DMA request for a given timer. 9656 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n 9657 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE 9658 * @param HRTIMx High Resolution Timer instance 9659 * @param Timer This parameter can be one of the following values: 9660 * @arg @ref LL_HRTIM_TIMER_MASTER 9661 * @arg @ref LL_HRTIM_TIMER_A 9662 * @arg @ref LL_HRTIM_TIMER_B 9663 * @arg @ref LL_HRTIM_TIMER_C 9664 * @arg @ref LL_HRTIM_TIMER_D 9665 * @arg @ref LL_HRTIM_TIMER_E 9666 * @retval None 9667 */ 9668 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9669 { 9670 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9671 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9672 REG_OFFSET_TAB_TIMER[iTimer])); 9673 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); 9674 } 9675 9676 /** 9677 * @brief Indicate whether the update DMA request is enabled for a given timer. 9678 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n 9679 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE 9680 * @param HRTIMx High Resolution Timer instance 9681 * @param Timer This parameter can be one of the following values: 9682 * @arg @ref LL_HRTIM_TIMER_MASTER 9683 * @arg @ref LL_HRTIM_TIMER_A 9684 * @arg @ref LL_HRTIM_TIMER_B 9685 * @arg @ref LL_HRTIM_TIMER_C 9686 * @arg @ref LL_HRTIM_TIMER_D 9687 * @arg @ref LL_HRTIM_TIMER_E 9688 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9689 */ 9690 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9691 { 9692 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9693 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9694 REG_OFFSET_TAB_TIMER[iTimer])); 9695 9696 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); 9697 } 9698 9699 /** 9700 * @brief Enable the repetition DMA request for a given timer. 9701 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n 9702 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP 9703 * @param HRTIMx High Resolution Timer instance 9704 * @param Timer This parameter can be one of the following values: 9705 * @arg @ref LL_HRTIM_TIMER_MASTER 9706 * @arg @ref LL_HRTIM_TIMER_A 9707 * @arg @ref LL_HRTIM_TIMER_B 9708 * @arg @ref LL_HRTIM_TIMER_C 9709 * @arg @ref LL_HRTIM_TIMER_D 9710 * @arg @ref LL_HRTIM_TIMER_E 9711 * @retval None 9712 */ 9713 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9714 { 9715 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9716 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9717 REG_OFFSET_TAB_TIMER[iTimer])); 9718 SET_BIT(*pReg, HRTIM_MDIER_MREPDE); 9719 } 9720 9721 /** 9722 * @brief Disable the repetition DMA request for a given timer. 9723 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n 9724 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP 9725 * @param HRTIMx High Resolution Timer instance 9726 * @param Timer This parameter can be one of the following values: 9727 * @arg @ref LL_HRTIM_TIMER_MASTER 9728 * @arg @ref LL_HRTIM_TIMER_A 9729 * @arg @ref LL_HRTIM_TIMER_B 9730 * @arg @ref LL_HRTIM_TIMER_C 9731 * @arg @ref LL_HRTIM_TIMER_D 9732 * @arg @ref LL_HRTIM_TIMER_E 9733 * @retval None 9734 */ 9735 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9736 { 9737 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9738 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9739 REG_OFFSET_TAB_TIMER[iTimer])); 9740 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); 9741 } 9742 9743 /** 9744 * @brief Indicate whether the repetition DMA request is enabled for a given timer. 9745 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n 9746 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP 9747 * @param HRTIMx High Resolution Timer instance 9748 * @param Timer This parameter can be one of the following values: 9749 * @arg @ref LL_HRTIM_TIMER_MASTER 9750 * @arg @ref LL_HRTIM_TIMER_A 9751 * @arg @ref LL_HRTIM_TIMER_B 9752 * @arg @ref LL_HRTIM_TIMER_C 9753 * @arg @ref LL_HRTIM_TIMER_D 9754 * @arg @ref LL_HRTIM_TIMER_E 9755 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9756 */ 9757 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9758 { 9759 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9760 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9761 REG_OFFSET_TAB_TIMER[iTimer])); 9762 9763 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); 9764 } 9765 9766 /** 9767 * @brief Enable the compare 1 DMA request for a given timer. 9768 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n 9769 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1 9770 * @param HRTIMx High Resolution Timer instance 9771 * @param Timer This parameter can be one of the following values: 9772 * @arg @ref LL_HRTIM_TIMER_MASTER 9773 * @arg @ref LL_HRTIM_TIMER_A 9774 * @arg @ref LL_HRTIM_TIMER_B 9775 * @arg @ref LL_HRTIM_TIMER_C 9776 * @arg @ref LL_HRTIM_TIMER_D 9777 * @arg @ref LL_HRTIM_TIMER_E 9778 * @retval None 9779 */ 9780 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9781 { 9782 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9783 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9784 REG_OFFSET_TAB_TIMER[iTimer])); 9785 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); 9786 } 9787 9788 /** 9789 * @brief Disable the compare 1 DMA request for a given timer. 9790 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n 9791 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1 9792 * @param HRTIMx High Resolution Timer instance 9793 * @param Timer This parameter can be one of the following values: 9794 * @arg @ref LL_HRTIM_TIMER_MASTER 9795 * @arg @ref LL_HRTIM_TIMER_A 9796 * @arg @ref LL_HRTIM_TIMER_B 9797 * @arg @ref LL_HRTIM_TIMER_C 9798 * @arg @ref LL_HRTIM_TIMER_D 9799 * @arg @ref LL_HRTIM_TIMER_E 9800 * @retval None 9801 */ 9802 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9803 { 9804 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9805 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9806 REG_OFFSET_TAB_TIMER[iTimer])); 9807 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); 9808 } 9809 9810 /** 9811 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer. 9812 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n 9813 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1 9814 * @param HRTIMx High Resolution Timer instance 9815 * @param Timer This parameter can be one of the following values: 9816 * @arg @ref LL_HRTIM_TIMER_MASTER 9817 * @arg @ref LL_HRTIM_TIMER_A 9818 * @arg @ref LL_HRTIM_TIMER_B 9819 * @arg @ref LL_HRTIM_TIMER_C 9820 * @arg @ref LL_HRTIM_TIMER_D 9821 * @arg @ref LL_HRTIM_TIMER_E 9822 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9823 */ 9824 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9825 { 9826 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9827 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9828 REG_OFFSET_TAB_TIMER[iTimer])); 9829 9830 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); 9831 } 9832 9833 /** 9834 * @brief Enable the compare 2 DMA request for a given timer. 9835 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n 9836 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2 9837 * @param HRTIMx High Resolution Timer instance 9838 * @param Timer This parameter can be one of the following values: 9839 * @arg @ref LL_HRTIM_TIMER_MASTER 9840 * @arg @ref LL_HRTIM_TIMER_A 9841 * @arg @ref LL_HRTIM_TIMER_B 9842 * @arg @ref LL_HRTIM_TIMER_C 9843 * @arg @ref LL_HRTIM_TIMER_D 9844 * @arg @ref LL_HRTIM_TIMER_E 9845 * @retval None 9846 */ 9847 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9848 { 9849 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9850 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9851 REG_OFFSET_TAB_TIMER[iTimer])); 9852 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); 9853 } 9854 9855 /** 9856 * @brief Disable the compare 2 DMA request for a given timer. 9857 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n 9858 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2 9859 * @param HRTIMx High Resolution Timer instance 9860 * @param Timer This parameter can be one of the following values: 9861 * @arg @ref LL_HRTIM_TIMER_MASTER 9862 * @arg @ref LL_HRTIM_TIMER_A 9863 * @arg @ref LL_HRTIM_TIMER_B 9864 * @arg @ref LL_HRTIM_TIMER_C 9865 * @arg @ref LL_HRTIM_TIMER_D 9866 * @arg @ref LL_HRTIM_TIMER_E 9867 * @retval None 9868 */ 9869 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9870 { 9871 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9872 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9873 REG_OFFSET_TAB_TIMER[iTimer])); 9874 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); 9875 } 9876 9877 /** 9878 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer. 9879 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n 9880 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2 9881 * @param HRTIMx High Resolution Timer instance 9882 * @param Timer This parameter can be one of the following values: 9883 * @arg @ref LL_HRTIM_TIMER_MASTER 9884 * @arg @ref LL_HRTIM_TIMER_A 9885 * @arg @ref LL_HRTIM_TIMER_B 9886 * @arg @ref LL_HRTIM_TIMER_C 9887 * @arg @ref LL_HRTIM_TIMER_D 9888 * @arg @ref LL_HRTIM_TIMER_E 9889 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9890 */ 9891 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9892 { 9893 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9894 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9895 REG_OFFSET_TAB_TIMER[iTimer])); 9896 9897 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); 9898 } 9899 9900 /** 9901 * @brief Enable the compare 3 DMA request for a given timer. 9902 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n 9903 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3 9904 * @param HRTIMx High Resolution Timer instance 9905 * @param Timer This parameter can be one of the following values: 9906 * @arg @ref LL_HRTIM_TIMER_MASTER 9907 * @arg @ref LL_HRTIM_TIMER_A 9908 * @arg @ref LL_HRTIM_TIMER_B 9909 * @arg @ref LL_HRTIM_TIMER_C 9910 * @arg @ref LL_HRTIM_TIMER_D 9911 * @arg @ref LL_HRTIM_TIMER_E 9912 * @retval None 9913 */ 9914 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9915 { 9916 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9917 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9918 REG_OFFSET_TAB_TIMER[iTimer])); 9919 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); 9920 } 9921 9922 /** 9923 * @brief Disable the compare 3 DMA request for a given timer. 9924 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n 9925 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3 9926 * @param HRTIMx High Resolution Timer instance 9927 * @param Timer This parameter can be one of the following values: 9928 * @arg @ref LL_HRTIM_TIMER_MASTER 9929 * @arg @ref LL_HRTIM_TIMER_A 9930 * @arg @ref LL_HRTIM_TIMER_B 9931 * @arg @ref LL_HRTIM_TIMER_C 9932 * @arg @ref LL_HRTIM_TIMER_D 9933 * @arg @ref LL_HRTIM_TIMER_E 9934 * @retval None 9935 */ 9936 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9937 { 9938 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9939 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9940 REG_OFFSET_TAB_TIMER[iTimer])); 9941 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); 9942 } 9943 9944 /** 9945 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer. 9946 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n 9947 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3 9948 * @param HRTIMx High Resolution Timer instance 9949 * @param Timer This parameter can be one of the following values: 9950 * @arg @ref LL_HRTIM_TIMER_MASTER 9951 * @arg @ref LL_HRTIM_TIMER_A 9952 * @arg @ref LL_HRTIM_TIMER_B 9953 * @arg @ref LL_HRTIM_TIMER_C 9954 * @arg @ref LL_HRTIM_TIMER_D 9955 * @arg @ref LL_HRTIM_TIMER_E 9956 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 9957 */ 9958 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9959 { 9960 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9961 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9962 REG_OFFSET_TAB_TIMER[iTimer])); 9963 9964 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); 9965 } 9966 9967 /** 9968 * @brief Enable the compare 4 DMA request for a given timer. 9969 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n 9970 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4 9971 * @param HRTIMx High Resolution Timer instance 9972 * @param Timer This parameter can be one of the following values: 9973 * @arg @ref LL_HRTIM_TIMER_MASTER 9974 * @arg @ref LL_HRTIM_TIMER_A 9975 * @arg @ref LL_HRTIM_TIMER_B 9976 * @arg @ref LL_HRTIM_TIMER_C 9977 * @arg @ref LL_HRTIM_TIMER_D 9978 * @arg @ref LL_HRTIM_TIMER_E 9979 * @retval None 9980 */ 9981 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 9982 { 9983 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 9984 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 9985 REG_OFFSET_TAB_TIMER[iTimer])); 9986 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); 9987 } 9988 9989 /** 9990 * @brief Disable the compare 4 DMA request for a given timer. 9991 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n 9992 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4 9993 * @param HRTIMx High Resolution Timer instance 9994 * @param Timer This parameter can be one of the following values: 9995 * @arg @ref LL_HRTIM_TIMER_MASTER 9996 * @arg @ref LL_HRTIM_TIMER_A 9997 * @arg @ref LL_HRTIM_TIMER_B 9998 * @arg @ref LL_HRTIM_TIMER_C 9999 * @arg @ref LL_HRTIM_TIMER_D 10000 * @arg @ref LL_HRTIM_TIMER_E 10001 * @retval None 10002 */ 10003 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10004 { 10005 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10006 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10007 REG_OFFSET_TAB_TIMER[iTimer])); 10008 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); 10009 } 10010 10011 /** 10012 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer. 10013 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n 10014 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4 10015 * @param HRTIMx High Resolution Timer instance 10016 * @param Timer This parameter can be one of the following values: 10017 * @arg @ref LL_HRTIM_TIMER_MASTER 10018 * @arg @ref LL_HRTIM_TIMER_A 10019 * @arg @ref LL_HRTIM_TIMER_B 10020 * @arg @ref LL_HRTIM_TIMER_C 10021 * @arg @ref LL_HRTIM_TIMER_D 10022 * @arg @ref LL_HRTIM_TIMER_E 10023 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 10024 */ 10025 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10026 { 10027 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10028 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10029 REG_OFFSET_TAB_TIMER[iTimer])); 10030 10031 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); 10032 } 10033 10034 /** 10035 * @brief Enable the capture 1 DMA request for a given timer. 10036 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1 10037 * @param HRTIMx High Resolution Timer instance 10038 * @param Timer This parameter can be one of the following values: 10039 * @arg @ref LL_HRTIM_TIMER_A 10040 * @arg @ref LL_HRTIM_TIMER_B 10041 * @arg @ref LL_HRTIM_TIMER_C 10042 * @arg @ref LL_HRTIM_TIMER_D 10043 * @arg @ref LL_HRTIM_TIMER_E 10044 * @retval None 10045 */ 10046 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10047 { 10048 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10049 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10050 REG_OFFSET_TAB_TIMER[iTimer])); 10051 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); 10052 } 10053 10054 /** 10055 * @brief Disable the capture 1 DMA request for a given timer. 10056 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1 10057 * @param HRTIMx High Resolution Timer instance 10058 * @param Timer This parameter can be one of the following values: 10059 * @arg @ref LL_HRTIM_TIMER_A 10060 * @arg @ref LL_HRTIM_TIMER_B 10061 * @arg @ref LL_HRTIM_TIMER_C 10062 * @arg @ref LL_HRTIM_TIMER_D 10063 * @arg @ref LL_HRTIM_TIMER_E 10064 * @retval None 10065 */ 10066 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10067 { 10068 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10069 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10070 REG_OFFSET_TAB_TIMER[iTimer])); 10071 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); 10072 } 10073 10074 /** 10075 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer. 10076 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1 10077 * @param HRTIMx High Resolution Timer instance 10078 * @param Timer This parameter can be one of the following values: 10079 * @arg @ref LL_HRTIM_TIMER_A 10080 * @arg @ref LL_HRTIM_TIMER_B 10081 * @arg @ref LL_HRTIM_TIMER_C 10082 * @arg @ref LL_HRTIM_TIMER_D 10083 * @arg @ref LL_HRTIM_TIMER_E 10084 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0). 10085 */ 10086 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10087 { 10088 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10089 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10090 REG_OFFSET_TAB_TIMER[iTimer])); 10091 10092 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); 10093 } 10094 10095 /** 10096 * @brief Enable the capture 2 DMA request for a given timer. 10097 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2 10098 * @param HRTIMx High Resolution Timer instance 10099 * @param Timer This parameter can be one of the following values: 10100 * @arg @ref LL_HRTIM_TIMER_A 10101 * @arg @ref LL_HRTIM_TIMER_B 10102 * @arg @ref LL_HRTIM_TIMER_C 10103 * @arg @ref LL_HRTIM_TIMER_D 10104 * @arg @ref LL_HRTIM_TIMER_E 10105 * @retval None 10106 */ 10107 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10108 { 10109 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10110 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10111 REG_OFFSET_TAB_TIMER[iTimer])); 10112 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); 10113 } 10114 10115 /** 10116 * @brief Disable the capture 2 DMA request for a given timer. 10117 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2 10118 * @param HRTIMx High Resolution Timer instance 10119 * @param Timer This parameter can be one of the following values: 10120 * @arg @ref LL_HRTIM_TIMER_A 10121 * @arg @ref LL_HRTIM_TIMER_B 10122 * @arg @ref LL_HRTIM_TIMER_C 10123 * @arg @ref LL_HRTIM_TIMER_D 10124 * @arg @ref LL_HRTIM_TIMER_E 10125 * @retval None 10126 */ 10127 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10128 { 10129 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10130 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10131 REG_OFFSET_TAB_TIMER[iTimer])); 10132 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); 10133 } 10134 10135 /** 10136 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer. 10137 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2 10138 * @param HRTIMx High Resolution Timer instance 10139 * @param Timer This parameter can be one of the following values: 10140 * @arg @ref LL_HRTIM_TIMER_A 10141 * @arg @ref LL_HRTIM_TIMER_B 10142 * @arg @ref LL_HRTIM_TIMER_C 10143 * @arg @ref LL_HRTIM_TIMER_D 10144 * @arg @ref LL_HRTIM_TIMER_E 10145 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0). 10146 */ 10147 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10148 { 10149 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10150 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10151 REG_OFFSET_TAB_TIMER[iTimer])); 10152 10153 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); 10154 } 10155 10156 /** 10157 * @brief Enable the output 1 set DMA request for a given timer. 10158 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1 10159 * @param HRTIMx High Resolution Timer instance 10160 * @param Timer This parameter can be one of the following values: 10161 * @arg @ref LL_HRTIM_TIMER_A 10162 * @arg @ref LL_HRTIM_TIMER_B 10163 * @arg @ref LL_HRTIM_TIMER_C 10164 * @arg @ref LL_HRTIM_TIMER_D 10165 * @arg @ref LL_HRTIM_TIMER_E 10166 * @retval None 10167 */ 10168 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10169 { 10170 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10171 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10172 REG_OFFSET_TAB_TIMER[iTimer])); 10173 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); 10174 } 10175 10176 /** 10177 * @brief Disable the output 1 set DMA request for a given timer. 10178 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1 10179 * @param HRTIMx High Resolution Timer instance 10180 * @param Timer This parameter can be one of the following values: 10181 * @arg @ref LL_HRTIM_TIMER_A 10182 * @arg @ref LL_HRTIM_TIMER_B 10183 * @arg @ref LL_HRTIM_TIMER_C 10184 * @arg @ref LL_HRTIM_TIMER_D 10185 * @arg @ref LL_HRTIM_TIMER_E 10186 * @retval None 10187 */ 10188 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10189 { 10190 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10191 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10192 REG_OFFSET_TAB_TIMER[iTimer])); 10193 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); 10194 } 10195 10196 /** 10197 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer. 10198 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1 10199 * @param HRTIMx High Resolution Timer instance 10200 * @param Timer This parameter can be one of the following values: 10201 * @arg @ref LL_HRTIM_TIMER_A 10202 * @arg @ref LL_HRTIM_TIMER_B 10203 * @arg @ref LL_HRTIM_TIMER_C 10204 * @arg @ref LL_HRTIM_TIMER_D 10205 * @arg @ref LL_HRTIM_TIMER_E 10206 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0). 10207 */ 10208 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10209 { 10210 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10211 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10212 REG_OFFSET_TAB_TIMER[iTimer])); 10213 10214 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); 10215 } 10216 10217 /** 10218 * @brief Enable the output 1 reset DMA request for a given timer. 10219 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1 10220 * @param HRTIMx High Resolution Timer instance 10221 * @param Timer This parameter can be one of the following values: 10222 * @arg @ref LL_HRTIM_TIMER_A 10223 * @arg @ref LL_HRTIM_TIMER_B 10224 * @arg @ref LL_HRTIM_TIMER_C 10225 * @arg @ref LL_HRTIM_TIMER_D 10226 * @arg @ref LL_HRTIM_TIMER_E 10227 * @retval None 10228 */ 10229 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10230 { 10231 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10232 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10233 REG_OFFSET_TAB_TIMER[iTimer])); 10234 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); 10235 } 10236 10237 /** 10238 * @brief Disable the output 1 reset DMA request for a given timer. 10239 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1 10240 * @param HRTIMx High Resolution Timer instance 10241 * @param Timer This parameter can be one of the following values: 10242 * @arg @ref LL_HRTIM_TIMER_A 10243 * @arg @ref LL_HRTIM_TIMER_B 10244 * @arg @ref LL_HRTIM_TIMER_C 10245 * @arg @ref LL_HRTIM_TIMER_D 10246 * @arg @ref LL_HRTIM_TIMER_E 10247 * @retval None 10248 */ 10249 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10250 { 10251 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10252 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10253 REG_OFFSET_TAB_TIMER[iTimer])); 10254 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); 10255 } 10256 10257 /** 10258 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer. 10259 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1 10260 * @param HRTIMx High Resolution Timer instance 10261 * @param Timer This parameter can be one of the following values: 10262 * @arg @ref LL_HRTIM_TIMER_A 10263 * @arg @ref LL_HRTIM_TIMER_B 10264 * @arg @ref LL_HRTIM_TIMER_C 10265 * @arg @ref LL_HRTIM_TIMER_D 10266 * @arg @ref LL_HRTIM_TIMER_E 10267 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0). 10268 */ 10269 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10270 { 10271 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10272 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10273 REG_OFFSET_TAB_TIMER[iTimer])); 10274 10275 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); 10276 } 10277 10278 /** 10279 * @brief Enable the output 2 set DMA request for a given timer. 10280 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2 10281 * @param HRTIMx High Resolution Timer instance 10282 * @param Timer This parameter can be one of the following values: 10283 * @arg @ref LL_HRTIM_TIMER_A 10284 * @arg @ref LL_HRTIM_TIMER_B 10285 * @arg @ref LL_HRTIM_TIMER_C 10286 * @arg @ref LL_HRTIM_TIMER_D 10287 * @arg @ref LL_HRTIM_TIMER_E 10288 * @retval None 10289 */ 10290 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10291 { 10292 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10293 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10294 REG_OFFSET_TAB_TIMER[iTimer])); 10295 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); 10296 } 10297 10298 /** 10299 * @brief Disable the output 2 set DMA request for a given timer. 10300 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2 10301 * @param HRTIMx High Resolution Timer instance 10302 * @param Timer This parameter can be one of the following values: 10303 * @arg @ref LL_HRTIM_TIMER_A 10304 * @arg @ref LL_HRTIM_TIMER_B 10305 * @arg @ref LL_HRTIM_TIMER_C 10306 * @arg @ref LL_HRTIM_TIMER_D 10307 * @arg @ref LL_HRTIM_TIMER_E 10308 * @retval None 10309 */ 10310 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10311 { 10312 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10313 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10314 REG_OFFSET_TAB_TIMER[iTimer])); 10315 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); 10316 } 10317 10318 /** 10319 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer. 10320 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2 10321 * @param HRTIMx High Resolution Timer instance 10322 * @param Timer This parameter can be one of the following values: 10323 * @arg @ref LL_HRTIM_TIMER_A 10324 * @arg @ref LL_HRTIM_TIMER_B 10325 * @arg @ref LL_HRTIM_TIMER_C 10326 * @arg @ref LL_HRTIM_TIMER_D 10327 * @arg @ref LL_HRTIM_TIMER_E 10328 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0). 10329 */ 10330 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10331 { 10332 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10333 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10334 REG_OFFSET_TAB_TIMER[iTimer])); 10335 10336 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); 10337 } 10338 10339 /** 10340 * @brief Enable the output 2 reset DMA request for a given timer. 10341 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2 10342 * @param HRTIMx High Resolution Timer instance 10343 * @param Timer This parameter can be one of the following values: 10344 * @arg @ref LL_HRTIM_TIMER_A 10345 * @arg @ref LL_HRTIM_TIMER_B 10346 * @arg @ref LL_HRTIM_TIMER_C 10347 * @arg @ref LL_HRTIM_TIMER_D 10348 * @arg @ref LL_HRTIM_TIMER_E 10349 * @retval None 10350 */ 10351 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10352 { 10353 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10354 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10355 REG_OFFSET_TAB_TIMER[iTimer])); 10356 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); 10357 } 10358 10359 /** 10360 * @brief Disable the output 2 reset DMA request for a given timer. 10361 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2 10362 * @param HRTIMx High Resolution Timer instance 10363 * @param Timer This parameter can be one of the following values: 10364 * @arg @ref LL_HRTIM_TIMER_A 10365 * @arg @ref LL_HRTIM_TIMER_B 10366 * @arg @ref LL_HRTIM_TIMER_C 10367 * @arg @ref LL_HRTIM_TIMER_D 10368 * @arg @ref LL_HRTIM_TIMER_E 10369 * @retval None 10370 */ 10371 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10372 { 10373 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10374 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10375 REG_OFFSET_TAB_TIMER[iTimer])); 10376 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); 10377 } 10378 10379 /** 10380 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer. 10381 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2 10382 * @param HRTIMx High Resolution Timer instance 10383 * @param Timer This parameter can be one of the following values: 10384 * @arg @ref LL_HRTIM_TIMER_A 10385 * @arg @ref LL_HRTIM_TIMER_B 10386 * @arg @ref LL_HRTIM_TIMER_C 10387 * @arg @ref LL_HRTIM_TIMER_D 10388 * @arg @ref LL_HRTIM_TIMER_E 10389 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0). 10390 */ 10391 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10392 { 10393 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10394 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10395 REG_OFFSET_TAB_TIMER[iTimer])); 10396 10397 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); 10398 } 10399 10400 /** 10401 * @brief Enable the reset/roll-over DMA request for a given timer. 10402 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST 10403 * @param HRTIMx High Resolution Timer instance 10404 * @param Timer This parameter can be one of the following values: 10405 * @arg @ref LL_HRTIM_TIMER_A 10406 * @arg @ref LL_HRTIM_TIMER_B 10407 * @arg @ref LL_HRTIM_TIMER_C 10408 * @arg @ref LL_HRTIM_TIMER_D 10409 * @arg @ref LL_HRTIM_TIMER_E 10410 * @retval None 10411 */ 10412 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10413 { 10414 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10415 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10416 REG_OFFSET_TAB_TIMER[iTimer])); 10417 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); 10418 } 10419 10420 /** 10421 * @brief Disable the reset/roll-over DMA request for a given timer. 10422 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST 10423 * @param HRTIMx High Resolution Timer instance 10424 * @param Timer This parameter can be one of the following values: 10425 * @arg @ref LL_HRTIM_TIMER_A 10426 * @arg @ref LL_HRTIM_TIMER_B 10427 * @arg @ref LL_HRTIM_TIMER_C 10428 * @arg @ref LL_HRTIM_TIMER_D 10429 * @arg @ref LL_HRTIM_TIMER_E 10430 * @retval None 10431 */ 10432 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10433 { 10434 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10435 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10436 REG_OFFSET_TAB_TIMER[iTimer])); 10437 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); 10438 } 10439 10440 /** 10441 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer. 10442 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST 10443 * @param HRTIMx High Resolution Timer instance 10444 * @param Timer This parameter can be one of the following values: 10445 * @arg @ref LL_HRTIM_TIMER_A 10446 * @arg @ref LL_HRTIM_TIMER_B 10447 * @arg @ref LL_HRTIM_TIMER_C 10448 * @arg @ref LL_HRTIM_TIMER_D 10449 * @arg @ref LL_HRTIM_TIMER_E 10450 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0). 10451 */ 10452 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10453 { 10454 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10455 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10456 REG_OFFSET_TAB_TIMER[iTimer])); 10457 10458 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); 10459 } 10460 10461 /** 10462 * @brief Enable the delayed protection DMA request for a given timer. 10463 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT 10464 * @param HRTIMx High Resolution Timer instance 10465 * @param Timer This parameter can be one of the following values: 10466 * @arg @ref LL_HRTIM_TIMER_A 10467 * @arg @ref LL_HRTIM_TIMER_B 10468 * @arg @ref LL_HRTIM_TIMER_C 10469 * @arg @ref LL_HRTIM_TIMER_D 10470 * @arg @ref LL_HRTIM_TIMER_E 10471 * @retval None 10472 */ 10473 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10474 { 10475 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10476 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10477 REG_OFFSET_TAB_TIMER[iTimer])); 10478 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); 10479 } 10480 10481 /** 10482 * @brief Disable the delayed protection DMA request for a given timer. 10483 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT 10484 * @param HRTIMx High Resolution Timer instance 10485 * @param Timer This parameter can be one of the following values: 10486 * @arg @ref LL_HRTIM_TIMER_A 10487 * @arg @ref LL_HRTIM_TIMER_B 10488 * @arg @ref LL_HRTIM_TIMER_C 10489 * @arg @ref LL_HRTIM_TIMER_D 10490 * @arg @ref LL_HRTIM_TIMER_E 10491 * @retval None 10492 */ 10493 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10494 { 10495 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10496 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10497 REG_OFFSET_TAB_TIMER[iTimer])); 10498 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); 10499 } 10500 10501 /** 10502 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer. 10503 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT 10504 * @param HRTIMx High Resolution Timer instance 10505 * @param Timer This parameter can be one of the following values: 10506 * @arg @ref LL_HRTIM_TIMER_A 10507 * @arg @ref LL_HRTIM_TIMER_B 10508 * @arg @ref LL_HRTIM_TIMER_C 10509 * @arg @ref LL_HRTIM_TIMER_D 10510 * @arg @ref LL_HRTIM_TIMER_E 10511 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0). 10512 */ 10513 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10514 { 10515 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10516 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10517 REG_OFFSET_TAB_TIMER[iTimer])); 10518 10519 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); 10520 } 10521 10522 /** 10523 * @} 10524 */ 10525 10526 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 10527 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions 10528 * @ingroup RTEMSBSPsARMSTM32H7 10529 * @{ 10530 */ 10531 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); 10532 /** 10533 * @} 10534 */ 10535 #endif /* USE_FULL_LL_DRIVER */ 10536 10537 /** 10538 * @} 10539 */ 10540 10541 /** 10542 * @} 10543 */ 10544 10545 #endif /* HRTIM1 */ 10546 10547 /** 10548 * @} 10549 */ 10550 10551 #ifdef __cplusplus 10552 } 10553 #endif 10554 10555 #endif /* STM32H7xx_LL_HRTIM_H */ 10556 10557
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