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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_dma2d.h 0004 * @author MCD Application Team 0005 * @brief Header file of DMA2D LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_DMA2D_H 0021 #define STM32H7xx_LL_DMA2D_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined (DMA2D) 0035 0036 /** @defgroup DMA2D_LL DMA2D 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /* Private constants ---------------------------------------------------------*/ 0044 /* Private macros ------------------------------------------------------------*/ 0045 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0046 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros 0047 * @ingroup RTEMSBSPsARMSTM32H7 0048 * @{ 0049 */ 0050 0051 /** 0052 * @} 0053 */ 0054 #endif /*USE_FULL_LL_DRIVER*/ 0055 0056 /* Exported types ------------------------------------------------------------*/ 0057 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0058 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures 0059 * @ingroup RTEMSBSPsARMSTM32H7 0060 * @{ 0061 */ 0062 0063 /** 0064 * @brief LL DMA2D Init Structure Definition 0065 */ 0066 typedef struct 0067 { 0068 uint32_t Mode; /*!< Specifies the DMA2D transfer mode. 0069 - This parameter can be one value of @ref DMA2D_LL_EC_MODE. 0070 0071 This parameter can be modified afterwards, 0072 using unitary function @ref LL_DMA2D_SetMode(). */ 0073 0074 uint32_t ColorMode; /*!< Specifies the color format of the output image. 0075 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. 0076 0077 This parameter can be modified afterwards using, 0078 unitary function @ref LL_DMA2D_SetOutputColorMode(). */ 0079 0080 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. 0081 - This parameter must be a number between: 0082 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0083 - This parameter must be a number between: 0084 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0085 - This parameter must be a number between: 0086 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 0087 - This parameter must be a number between: 0088 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0089 - This parameter must be a number between: 0090 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0091 0092 This parameter can be modified afterwards, 0093 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0094 function @ref LL_DMA2D_ConfigOutputColor(). */ 0095 0096 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. 0097 - This parameter must be a number between: 0098 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0099 - This parameter must be a number between: 0100 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0101 - This parameter must be a number between: 0102 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. 0103 - This parameter must be a number between: 0104 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0105 - This parameter must be a number between: 0106 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0107 0108 This parameter can be modified afterwards 0109 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0110 function @ref LL_DMA2D_ConfigOutputColor(). */ 0111 0112 uint32_t OutputRed; /*!< Specifies the Red value of the output image. 0113 - This parameter must be a number between: 0114 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0115 - This parameter must be a number between: 0116 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0117 - This parameter must be a number between: 0118 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 0119 - This parameter must be a number between: 0120 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0121 - This parameter must be a number between: 0122 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0123 0124 This parameter can be modified afterwards 0125 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0126 function @ref LL_DMA2D_ConfigOutputColor(). */ 0127 0128 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. 0129 - This parameter must be a number between: 0130 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0131 - This parameter must be a number between: 0132 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. 0133 - This parameter must be a number between: 0134 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0135 - This parameter is not considered if RGB888 or RGB565 color mode is selected. 0136 0137 This parameter can be modified afterwards using, 0138 unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0139 function @ref LL_DMA2D_ConfigOutputColor(). */ 0140 0141 uint32_t OutputMemoryAddress; /*!< Specifies the memory address. 0142 - This parameter must be a number between: 0143 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 0144 0145 This parameter can be modified afterwards, 0146 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ 0147 0148 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. 0149 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. 0150 0151 This parameter can be modified afterwards, 0152 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ 0153 0154 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. 0155 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. 0156 0157 This parameter can be modified afterwards, 0158 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ 0159 0160 uint32_t LineOffset; /*!< Specifies the output line offset value. 0161 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 0162 0163 This parameter can be modified afterwards, 0164 using unitary function @ref LL_DMA2D_SetLineOffset(). */ 0165 0166 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. 0167 - This parameter must be a number between: 0168 Min_Data = 0x0000 and Max_Data = 0xFFFF. 0169 0170 This parameter can be modified afterwards, 0171 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ 0172 0173 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. 0174 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. 0175 0176 This parameter can be modified afterwards using, 0177 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ 0178 0179 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. 0180 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. 0181 0182 This parameter can be modified afterwards, 0183 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ 0184 0185 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. 0186 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. 0187 0188 This parameter can be modified afterwards, 0189 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ 0190 0191 } LL_DMA2D_InitTypeDef; 0192 0193 /** 0194 * @brief LL DMA2D Layer Configuration Structure Definition 0195 */ 0196 typedef struct 0197 { 0198 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. 0199 - This parameter must be a number between: 0200 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 0201 0202 This parameter can be modified afterwards using unitary functions 0203 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, 0204 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ 0205 0206 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. 0207 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. 0208 0209 This parameter can be modified afterwards using unitary functions 0210 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, 0211 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ 0212 0213 uint32_t ColorMode; /*!< Specifies the foreground or background color mode. 0214 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. 0215 0216 This parameter can be modified afterwards using unitary functions 0217 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, 0218 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ 0219 0220 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. 0221 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. 0222 0223 This parameter can be modified afterwards using unitary functions 0224 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, 0225 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ 0226 0227 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. 0228 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0229 0230 This parameter can be modified afterwards using unitary functions 0231 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, 0232 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ 0233 0234 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. 0235 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. 0236 0237 This parameter can be modified afterwards using unitary functions 0238 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, 0239 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ 0240 0241 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. 0242 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0243 0244 This parameter can be modified afterwards using unitary functions 0245 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, 0246 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ 0247 0248 uint32_t Blue; /*!< Specifies the foreground or background Blue color value. 0249 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0250 0251 This parameter can be modified afterwards using unitary functions 0252 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, 0253 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ 0254 0255 uint32_t Green; /*!< Specifies the foreground or background Green color value. 0256 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0257 0258 This parameter can be modified afterwards using unitary functions 0259 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, 0260 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ 0261 0262 uint32_t Red; /*!< Specifies the foreground or background Red color value. 0263 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 0264 0265 This parameter can be modified afterwards using unitary functions 0266 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, 0267 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ 0268 0269 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. 0270 - This parameter must be a number between: 0271 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 0272 0273 This parameter can be modified afterwards using unitary functions 0274 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, 0275 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ 0276 0277 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. 0278 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. 0279 0280 This parameter can be modified afterwards using unitary functions 0281 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, 0282 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ 0283 0284 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. 0285 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . 0286 0287 This parameter can be modified afterwards using unitary functions 0288 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, 0289 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ 0290 0291 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode 0292 This parameter is applicable for foreground layer only. 0293 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING 0294 0295 This parameter can be modified afterwards using unitary functions 0296 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */ 0297 0298 } LL_DMA2D_LayerCfgTypeDef; 0299 0300 /** 0301 * @brief LL DMA2D Output Color Structure Definition 0302 */ 0303 typedef struct 0304 { 0305 uint32_t ColorMode; /*!< Specifies the color format of the output image. 0306 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. 0307 0308 This parameter can be modified afterwards using 0309 unitary function @ref LL_DMA2D_SetOutputColorMode(). */ 0310 0311 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. 0312 - This parameter must be a number between: 0313 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0314 - This parameter must be a number between: 0315 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0316 - This parameter must be a number between: 0317 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 0318 - This parameter must be a number between: 0319 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0320 - This parameter must be a number between: 0321 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0322 0323 This parameter can be modified afterwards using, 0324 unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0325 function @ref LL_DMA2D_ConfigOutputColor(). */ 0326 0327 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. 0328 - This parameter must be a number between: 0329 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0330 - This parameter must be a number between 0331 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0332 - This parameter must be a number between: 0333 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. 0334 - This parameter must be a number between: 0335 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0336 - This parameter must be a number between: 0337 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0338 0339 This parameter can be modified afterwards, 0340 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0341 function @ref LL_DMA2D_ConfigOutputColor(). */ 0342 0343 uint32_t OutputRed; /*!< Specifies the Red value of the output image. 0344 - This parameter must be a number between: 0345 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0346 - This parameter must be a number between: 0347 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 0348 - This parameter must be a number between: 0349 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 0350 - This parameter must be a number between: 0351 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 0352 - This parameter must be a number between: 0353 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0354 0355 This parameter can be modified afterwards, 0356 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0357 function @ref LL_DMA2D_ConfigOutputColor(). */ 0358 0359 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. 0360 - This parameter must be a number between: 0361 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 0362 - This parameter must be a number between: 0363 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. 0364 - This parameter must be a number between: 0365 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 0366 - This parameter is not considered if RGB888 or RGB565 color mode is selected. 0367 0368 This parameter can be modified afterwards, 0369 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 0370 function @ref LL_DMA2D_ConfigOutputColor(). */ 0371 0372 } LL_DMA2D_ColorTypeDef; 0373 0374 /** 0375 * @} 0376 */ 0377 #endif /* USE_FULL_LL_DRIVER */ 0378 0379 /* Exported constants --------------------------------------------------------*/ 0380 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants 0381 * @ingroup RTEMSBSPsARMSTM32H7 0382 * @{ 0383 */ 0384 0385 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines 0386 * @ingroup RTEMSBSPsARMSTM32H7 0387 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function 0388 * @{ 0389 */ 0390 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 0391 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 0392 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 0393 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 0394 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 0395 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 0396 /** 0397 * @} 0398 */ 0399 0400 /** @defgroup DMA2D_LL_EC_IT IT Defines 0401 * @ingroup RTEMSBSPsARMSTM32H7 0402 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions 0403 * @{ 0404 */ 0405 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 0406 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 0407 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 0408 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 0409 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 0410 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 0411 /** 0412 * @} 0413 */ 0414 0415 /** @defgroup DMA2D_LL_EC_MODE Mode 0416 * @ingroup RTEMSBSPsARMSTM32H7 0417 * @{ 0418 */ 0419 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 0420 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 0421 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 0422 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ 0423 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ 0424 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ 0425 /** 0426 * @} 0427 */ 0428 0429 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode 0430 * @ingroup RTEMSBSPsARMSTM32H7 0431 * @{ 0432 */ 0433 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 0434 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ 0435 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ 0436 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ 0437 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ 0438 /** 0439 * @} 0440 */ 0441 0442 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode 0443 * @ingroup RTEMSBSPsARMSTM32H7 0444 * @{ 0445 */ 0446 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 0447 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ 0448 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ 0449 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ 0450 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ 0451 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ 0452 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ 0453 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ 0454 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ 0455 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ 0456 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ 0457 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */ 0458 /** 0459 * @} 0460 */ 0461 0462 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode 0463 * @ingroup RTEMSBSPsARMSTM32H7 0464 * @{ 0465 */ 0466 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ 0467 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by 0468 programmed alpha value */ 0469 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by 0470 programmed alpha value with, 0471 original alpha channel value */ 0472 /** 0473 * @} 0474 */ 0475 0476 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode 0477 * @ingroup RTEMSBSPsARMSTM32H7 0478 * @{ 0479 */ 0480 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ 0481 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ 0482 /** 0483 * @} 0484 */ 0485 0486 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap 0487 * @ingroup RTEMSBSPsARMSTM32H7 0488 * @{ 0489 */ 0490 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ 0491 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ 0492 /** 0493 * @} 0494 */ 0495 0496 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion 0497 * @ingroup RTEMSBSPsARMSTM32H7 0498 * @{ 0499 */ 0500 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ 0501 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ 0502 /** 0503 * @} 0504 */ 0505 0506 0507 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode 0508 * @ingroup RTEMSBSPsARMSTM32H7 0509 * @{ 0510 */ 0511 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ 0512 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ 0513 /** 0514 * @} 0515 */ 0516 0517 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode 0518 * @ingroup RTEMSBSPsARMSTM32H7 0519 * @{ 0520 */ 0521 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 0522 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ 0523 /** 0524 * @} 0525 */ 0526 0527 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling 0528 * @ingroup RTEMSBSPsARMSTM32H7 0529 * @{ 0530 */ 0531 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ 0532 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */ 0533 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */ 0534 /** 0535 * @} 0536 */ 0537 0538 /** 0539 * @} 0540 */ 0541 0542 /* Exported macro ------------------------------------------------------------*/ 0543 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros 0544 * @ingroup RTEMSBSPsARMSTM32H7 0545 * @{ 0546 */ 0547 0548 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros 0549 * @ingroup RTEMSBSPsARMSTM32H7 0550 * @{ 0551 */ 0552 0553 /** 0554 * @brief Write a value in DMA2D register. 0555 * @param __INSTANCE__ DMA2D Instance 0556 * @param __REG__ Register to be written 0557 * @param __VALUE__ Value to be written in the register 0558 * @retval None 0559 */ 0560 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 0561 0562 /** 0563 * @brief Read a value in DMA2D register. 0564 * @param __INSTANCE__ DMA2D Instance 0565 * @param __REG__ Register to be read 0566 * @retval Register value 0567 */ 0568 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 0569 /** 0570 * @} 0571 */ 0572 0573 /** 0574 * @} 0575 */ 0576 0577 /* Exported functions --------------------------------------------------------*/ 0578 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions 0579 * @ingroup RTEMSBSPsARMSTM32H7 0580 * @{ 0581 */ 0582 0583 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions 0584 * @ingroup RTEMSBSPsARMSTM32H7 0585 * @{ 0586 */ 0587 0588 /** 0589 * @brief Start a DMA2D transfer. 0590 * @rmtoll CR START LL_DMA2D_Start 0591 * @param DMA2Dx DMA2D Instance 0592 * @retval None 0593 */ 0594 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) 0595 { 0596 SET_BIT(DMA2Dx->CR, DMA2D_CR_START); 0597 } 0598 0599 /** 0600 * @brief Indicate if a DMA2D transfer is ongoing. 0601 * @rmtoll CR START LL_DMA2D_IsTransferOngoing 0602 * @param DMA2Dx DMA2D Instance 0603 * @retval State of bit (1 or 0). 0604 */ 0605 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) 0606 { 0607 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); 0608 } 0609 0610 /** 0611 * @brief Suspend DMA2D transfer. 0612 * @note This API can be used to suspend automatic foreground or background CLUT loading. 0613 * @rmtoll CR SUSP LL_DMA2D_Suspend 0614 * @param DMA2Dx DMA2D Instance 0615 * @retval None 0616 */ 0617 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) 0618 { 0619 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); 0620 } 0621 0622 /** 0623 * @brief Resume DMA2D transfer. 0624 * @note This API can be used to resume automatic foreground or background CLUT loading. 0625 * @rmtoll CR SUSP LL_DMA2D_Resume 0626 * @param DMA2Dx DMA2D Instance 0627 * @retval None 0628 */ 0629 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) 0630 { 0631 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); 0632 } 0633 0634 /** 0635 * @brief Indicate if DMA2D transfer is suspended. 0636 * @note This API can be used to indicate whether or not automatic foreground or 0637 * background CLUT loading is suspended. 0638 * @rmtoll CR SUSP LL_DMA2D_IsSuspended 0639 * @param DMA2Dx DMA2D Instance 0640 * @retval State of bit (1 or 0). 0641 */ 0642 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) 0643 { 0644 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); 0645 } 0646 0647 /** 0648 * @brief Abort DMA2D transfer. 0649 * @note This API can be used to abort automatic foreground or background CLUT loading. 0650 * @rmtoll CR ABORT LL_DMA2D_Abort 0651 * @param DMA2Dx DMA2D Instance 0652 * @retval None 0653 */ 0654 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) 0655 { 0656 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); 0657 } 0658 0659 /** 0660 * @brief Indicate if DMA2D transfer is aborted. 0661 * @note This API can be used to indicate whether or not automatic foreground or 0662 * background CLUT loading is aborted. 0663 * @rmtoll CR ABORT LL_DMA2D_IsAborted 0664 * @param DMA2Dx DMA2D Instance 0665 * @retval State of bit (1 or 0). 0666 */ 0667 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) 0668 { 0669 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); 0670 } 0671 0672 /** 0673 * @brief Set DMA2D mode. 0674 * @rmtoll CR MODE LL_DMA2D_SetMode 0675 * @param DMA2Dx DMA2D Instance 0676 * @param Mode This parameter can be one of the following values: 0677 * @arg @ref LL_DMA2D_MODE_M2M 0678 * @arg @ref LL_DMA2D_MODE_M2M_PFC 0679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND 0680 * @arg @ref LL_DMA2D_MODE_R2M 0681 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG 0682 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG 0683 * @retval None 0684 */ 0685 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) 0686 { 0687 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); 0688 } 0689 0690 /** 0691 * @brief Return DMA2D mode 0692 * @rmtoll CR MODE LL_DMA2D_GetMode 0693 * @param DMA2Dx DMA2D Instance 0694 * @retval Returned value can be one of the following values: 0695 * @arg @ref LL_DMA2D_MODE_M2M 0696 * @arg @ref LL_DMA2D_MODE_M2M_PFC 0697 * @arg @ref LL_DMA2D_MODE_M2M_BLEND 0698 * @arg @ref LL_DMA2D_MODE_R2M 0699 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG 0700 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG 0701 */ 0702 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) 0703 { 0704 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); 0705 } 0706 0707 /** 0708 * @brief Set DMA2D output color mode. 0709 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode 0710 * @param DMA2Dx DMA2D Instance 0711 * @param ColorMode This parameter can be one of the following values: 0712 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 0713 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 0714 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 0715 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 0716 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 0717 * @retval None 0718 */ 0719 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 0720 { 0721 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); 0722 } 0723 0724 /** 0725 * @brief Return DMA2D output color mode. 0726 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode 0727 * @param DMA2Dx DMA2D Instance 0728 * @retval Returned value can be one of the following values: 0729 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 0730 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 0731 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 0732 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 0733 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 0734 */ 0735 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) 0736 { 0737 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); 0738 } 0739 0740 /** 0741 * @brief Set DMA2D output Red Blue swap mode. 0742 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode 0743 * @param DMA2Dx DMA2D Instance 0744 * @param RBSwapMode This parameter can be one of the following values: 0745 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 0746 * @arg @ref LL_DMA2D_RB_MODE_SWAP 0747 * @retval None 0748 */ 0749 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 0750 { 0751 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); 0752 } 0753 0754 /** 0755 * @brief Return DMA2D output Red Blue swap mode. 0756 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode 0757 * @param DMA2Dx DMA2D Instance 0758 * @retval Returned value can be one of the following values: 0759 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 0760 * @arg @ref LL_DMA2D_RB_MODE_SWAP 0761 */ 0762 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) 0763 { 0764 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); 0765 } 0766 0767 /** 0768 * @brief Set DMA2D output alpha inversion mode. 0769 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode 0770 * @param DMA2Dx DMA2D Instance 0771 * @param AlphaInversionMode This parameter can be one of the following values: 0772 * @arg @ref LL_DMA2D_ALPHA_REGULAR 0773 * @arg @ref LL_DMA2D_ALPHA_INVERTED 0774 * @retval None 0775 */ 0776 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 0777 { 0778 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); 0779 } 0780 0781 /** 0782 * @brief Return DMA2D output alpha inversion mode. 0783 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode 0784 * @param DMA2Dx DMA2D Instance 0785 * @retval Returned value can be one of the following values: 0786 * @arg @ref LL_DMA2D_ALPHA_REGULAR 0787 * @arg @ref LL_DMA2D_ALPHA_INVERTED 0788 */ 0789 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 0790 { 0791 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); 0792 } 0793 0794 0795 /** 0796 * @brief Set DMA2D output swap mode. 0797 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode 0798 * @param DMA2Dx DMA2D Instance 0799 * @param OutputSwapMode This parameter can be one of the following values: 0800 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR 0801 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO 0802 * @retval None 0803 */ 0804 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) 0805 { 0806 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); 0807 } 0808 0809 /** 0810 * @brief Return DMA2D output swap mode. 0811 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode 0812 * @param DMA2Dx DMA2D Instance 0813 * @retval Returned value can be one of the following values: 0814 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR 0815 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO 0816 */ 0817 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) 0818 { 0819 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); 0820 } 0821 0822 /** 0823 * @brief Set DMA2D line offset mode. 0824 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode 0825 * @param DMA2Dx DMA2D Instance 0826 * @param LineOffsetMode This parameter can be one of the following values: 0827 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS 0828 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES 0829 * @retval None 0830 */ 0831 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) 0832 { 0833 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); 0834 } 0835 0836 /** 0837 * @brief Return DMA2D line offset mode. 0838 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode 0839 * @param DMA2Dx DMA2D Instance 0840 * @retval Returned value can be one of the following values: 0841 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS 0842 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES 0843 */ 0844 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) 0845 { 0846 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); 0847 } 0848 0849 /** 0850 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). 0851 * @rmtoll OOR LO LL_DMA2D_SetLineOffset 0852 * @param DMA2Dx DMA2D Instance 0853 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF 0854 * @retval None 0855 */ 0856 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 0857 { 0858 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); 0859 } 0860 0861 /** 0862 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). 0863 * @rmtoll OOR LO LL_DMA2D_GetLineOffset 0864 * @param DMA2Dx DMA2D Instance 0865 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF 0866 */ 0867 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 0868 { 0869 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); 0870 } 0871 0872 /** 0873 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). 0874 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines 0875 * @param DMA2Dx DMA2D Instance 0876 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF 0877 * @retval None 0878 */ 0879 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) 0880 { 0881 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); 0882 } 0883 0884 /** 0885 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) 0886 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines 0887 * @param DMA2Dx DMA2D Instance 0888 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF 0889 */ 0890 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) 0891 { 0892 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); 0893 } 0894 0895 /** 0896 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). 0897 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines 0898 * @param DMA2Dx DMA2D Instance 0899 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF 0900 * @retval None 0901 */ 0902 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) 0903 { 0904 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); 0905 } 0906 0907 /** 0908 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). 0909 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines 0910 * @param DMA2Dx DMA2D Instance 0911 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF 0912 */ 0913 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) 0914 { 0915 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); 0916 } 0917 0918 /** 0919 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). 0920 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr 0921 * @param DMA2Dx DMA2D Instance 0922 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 0923 * @retval None 0924 */ 0925 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) 0926 { 0927 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); 0928 } 0929 0930 /** 0931 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). 0932 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr 0933 * @param DMA2Dx DMA2D Instance 0934 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 0935 */ 0936 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) 0937 { 0938 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); 0939 } 0940 0941 /** 0942 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). 0943 * @note Output color format depends on output color mode, ARGB8888, RGB888, 0944 * RGB565, ARGB1555 or ARGB4444. 0945 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting 0946 * with respect to color mode is not done by the user code. 0947 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n 0948 * OCOLR GREEN LL_DMA2D_SetOutputColor\n 0949 * OCOLR RED LL_DMA2D_SetOutputColor\n 0950 * OCOLR ALPHA LL_DMA2D_SetOutputColor 0951 * @param DMA2Dx DMA2D Instance 0952 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF 0953 * @retval None 0954 */ 0955 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) 0956 { 0957 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ 0958 OutputColor); 0959 } 0960 0961 /** 0962 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). 0963 * @note Alpha channel and red, green, blue color values must be retrieved from the returned 0964 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) 0965 * as set by @ref LL_DMA2D_SetOutputColorMode. 0966 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n 0967 * OCOLR GREEN LL_DMA2D_GetOutputColor\n 0968 * OCOLR RED LL_DMA2D_GetOutputColor\n 0969 * OCOLR ALPHA LL_DMA2D_GetOutputColor 0970 * @param DMA2Dx DMA2D Instance 0971 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF 0972 */ 0973 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) 0974 { 0975 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ 0976 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); 0977 } 0978 0979 /** 0980 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). 0981 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark 0982 * @param DMA2Dx DMA2D Instance 0983 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF 0984 * @retval None 0985 */ 0986 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) 0987 { 0988 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); 0989 } 0990 0991 /** 0992 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). 0993 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark 0994 * @param DMA2Dx DMA2D Instance 0995 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF 0996 */ 0997 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) 0998 { 0999 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); 1000 } 1001 1002 /** 1003 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). 1004 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime 1005 * @param DMA2Dx DMA2D Instance 1006 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF 1007 * @retval None 1008 */ 1009 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) 1010 { 1011 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); 1012 } 1013 1014 /** 1015 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). 1016 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime 1017 * @param DMA2Dx DMA2D Instance 1018 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF 1019 */ 1020 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) 1021 { 1022 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); 1023 } 1024 1025 /** 1026 * @brief Enable DMA2D dead time functionality. 1027 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime 1028 * @param DMA2Dx DMA2D Instance 1029 * @retval None 1030 */ 1031 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) 1032 { 1033 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); 1034 } 1035 1036 /** 1037 * @brief Disable DMA2D dead time functionality. 1038 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime 1039 * @param DMA2Dx DMA2D Instance 1040 * @retval None 1041 */ 1042 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) 1043 { 1044 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); 1045 } 1046 1047 /** 1048 * @brief Indicate if DMA2D dead time functionality is enabled. 1049 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime 1050 * @param DMA2Dx DMA2D Instance 1051 * @retval State of bit (1 or 0). 1052 */ 1053 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) 1054 { 1055 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); 1056 } 1057 1058 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions 1059 * @ingroup RTEMSBSPsARMSTM32H7 1060 * @{ 1061 */ 1062 1063 /** 1064 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). 1065 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr 1066 * @param DMA2Dx DMA2D Instance 1067 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 1068 * @retval None 1069 */ 1070 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) 1071 { 1072 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); 1073 } 1074 1075 /** 1076 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). 1077 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr 1078 * @param DMA2Dx DMA2D Instance 1079 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 1080 */ 1081 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) 1082 { 1083 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); 1084 } 1085 1086 /** 1087 * @brief Enable DMA2D foreground CLUT loading. 1088 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad 1089 * @param DMA2Dx DMA2D Instance 1090 * @retval None 1091 */ 1092 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) 1093 { 1094 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); 1095 } 1096 1097 /** 1098 * @brief Indicate if DMA2D foreground CLUT loading is enabled. 1099 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad 1100 * @param DMA2Dx DMA2D Instance 1101 * @retval State of bit (1 or 0). 1102 */ 1103 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) 1104 { 1105 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); 1106 } 1107 1108 /** 1109 * @brief Set DMA2D foreground color mode. 1110 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode 1111 * @param DMA2Dx DMA2D Instance 1112 * @param ColorMode This parameter can be one of the following values: 1113 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 1114 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 1115 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 1116 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 1117 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 1118 * @arg @ref LL_DMA2D_INPUT_MODE_L8 1119 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 1120 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 1121 * @arg @ref LL_DMA2D_INPUT_MODE_L4 1122 * @arg @ref LL_DMA2D_INPUT_MODE_A8 1123 * @arg @ref LL_DMA2D_INPUT_MODE_A4 1124 * @retval None 1125 */ 1126 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 1127 { 1128 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); 1129 } 1130 1131 /** 1132 * @brief Return DMA2D foreground color mode. 1133 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode 1134 * @param DMA2Dx DMA2D Instance 1135 * @retval Returned value can be one of the following values: 1136 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 1137 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 1138 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 1139 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 1140 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 1141 * @arg @ref LL_DMA2D_INPUT_MODE_L8 1142 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 1143 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 1144 * @arg @ref LL_DMA2D_INPUT_MODE_L4 1145 * @arg @ref LL_DMA2D_INPUT_MODE_A8 1146 * @arg @ref LL_DMA2D_INPUT_MODE_A4 1147 */ 1148 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) 1149 { 1150 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); 1151 } 1152 1153 /** 1154 * @brief Set DMA2D foreground alpha mode. 1155 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode 1156 * @param DMA2Dx DMA2D Instance 1157 * @param AphaMode This parameter can be one of the following values: 1158 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 1159 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 1160 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 1161 * @retval None 1162 */ 1163 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) 1164 { 1165 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); 1166 } 1167 1168 /** 1169 * @brief Return DMA2D foreground alpha mode. 1170 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode 1171 * @param DMA2Dx DMA2D Instance 1172 * @retval Returned value can be one of the following values: 1173 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 1174 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 1175 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 1176 */ 1177 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) 1178 { 1179 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); 1180 } 1181 1182 /** 1183 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). 1184 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha 1185 * @param DMA2Dx DMA2D Instance 1186 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF 1187 * @retval None 1188 */ 1189 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) 1190 { 1191 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); 1192 } 1193 1194 /** 1195 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). 1196 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha 1197 * @param DMA2Dx DMA2D Instance 1198 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF 1199 */ 1200 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) 1201 { 1202 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); 1203 } 1204 1205 /** 1206 * @brief Set DMA2D foreground Red Blue swap mode. 1207 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode 1208 * @param DMA2Dx DMA2D Instance 1209 * @param RBSwapMode This parameter can be one of the following values: 1210 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 1211 * @arg @ref LL_DMA2D_RB_MODE_SWAP 1212 * @retval None 1213 */ 1214 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 1215 { 1216 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); 1217 } 1218 1219 /** 1220 * @brief Return DMA2D foreground Red Blue swap mode. 1221 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode 1222 * @param DMA2Dx DMA2D Instance 1223 * @retval Returned value can be one of the following values: 1224 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 1225 * @arg @ref LL_DMA2D_RB_MODE_SWAP 1226 */ 1227 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) 1228 { 1229 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); 1230 } 1231 1232 /** 1233 * @brief Set DMA2D foreground alpha inversion mode. 1234 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode 1235 * @param DMA2Dx DMA2D Instance 1236 * @param AlphaInversionMode This parameter can be one of the following values: 1237 * @arg @ref LL_DMA2D_ALPHA_REGULAR 1238 * @arg @ref LL_DMA2D_ALPHA_INVERTED 1239 * @retval None 1240 */ 1241 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 1242 { 1243 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); 1244 } 1245 1246 /** 1247 * @brief Return DMA2D foreground alpha inversion mode. 1248 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode 1249 * @param DMA2Dx DMA2D Instance 1250 * @retval Returned value can be one of the following values: 1251 * @arg @ref LL_DMA2D_ALPHA_REGULAR 1252 * @arg @ref LL_DMA2D_ALPHA_INVERTED 1253 */ 1254 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 1255 { 1256 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); 1257 } 1258 1259 /** 1260 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). 1261 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset 1262 * @param DMA2Dx DMA2D Instance 1263 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF 1264 * @retval None 1265 */ 1266 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 1267 { 1268 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); 1269 } 1270 1271 /** 1272 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). 1273 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset 1274 * @param DMA2Dx DMA2D Instance 1275 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF 1276 */ 1277 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 1278 { 1279 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); 1280 } 1281 1282 /** 1283 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). 1284 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor 1285 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor 1286 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor 1287 * @param DMA2Dx DMA2D Instance 1288 * @param Red Value between Min_Data=0 and Max_Data=0xFF 1289 * @param Green Value between Min_Data=0 and Max_Data=0xFF 1290 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 1291 * @retval None 1292 */ 1293 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) 1294 { 1295 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ 1296 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); 1297 } 1298 1299 /** 1300 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). 1301 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor 1302 * @param DMA2Dx DMA2D Instance 1303 * @param Red Value between Min_Data=0 and Max_Data=0xFF 1304 * @retval None 1305 */ 1306 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) 1307 { 1308 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); 1309 } 1310 1311 /** 1312 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). 1313 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor 1314 * @param DMA2Dx DMA2D Instance 1315 * @retval Red color value between Min_Data=0 and Max_Data=0xFF 1316 */ 1317 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) 1318 { 1319 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); 1320 } 1321 1322 /** 1323 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). 1324 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor 1325 * @param DMA2Dx DMA2D Instance 1326 * @param Green Value between Min_Data=0 and Max_Data=0xFF 1327 * @retval None 1328 */ 1329 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) 1330 { 1331 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); 1332 } 1333 1334 /** 1335 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). 1336 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor 1337 * @param DMA2Dx DMA2D Instance 1338 * @retval Green color value between Min_Data=0 and Max_Data=0xFF 1339 */ 1340 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) 1341 { 1342 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); 1343 } 1344 1345 /** 1346 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). 1347 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor 1348 * @param DMA2Dx DMA2D Instance 1349 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 1350 * @retval None 1351 */ 1352 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) 1353 { 1354 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); 1355 } 1356 1357 /** 1358 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). 1359 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor 1360 * @param DMA2Dx DMA2D Instance 1361 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF 1362 */ 1363 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) 1364 { 1365 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); 1366 } 1367 1368 /** 1369 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). 1370 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr 1371 * @param DMA2Dx DMA2D Instance 1372 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 1373 * @retval None 1374 */ 1375 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) 1376 { 1377 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); 1378 } 1379 1380 /** 1381 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). 1382 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr 1383 * @param DMA2Dx DMA2D Instance 1384 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 1385 */ 1386 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) 1387 { 1388 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); 1389 } 1390 1391 /** 1392 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). 1393 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize 1394 * @param DMA2Dx DMA2D Instance 1395 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF 1396 * @retval None 1397 */ 1398 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) 1399 { 1400 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); 1401 } 1402 1403 /** 1404 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). 1405 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize 1406 * @param DMA2Dx DMA2D Instance 1407 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF 1408 */ 1409 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) 1410 { 1411 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); 1412 } 1413 1414 /** 1415 * @brief Set DMA2D foreground CLUT color mode. 1416 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode 1417 * @param DMA2Dx DMA2D Instance 1418 * @param CLUTColorMode This parameter can be one of the following values: 1419 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 1420 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 1421 * @retval None 1422 */ 1423 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) 1424 { 1425 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); 1426 } 1427 1428 /** 1429 * @brief Return DMA2D foreground CLUT color mode. 1430 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode 1431 * @param DMA2Dx DMA2D Instance 1432 * @retval Returned value can be one of the following values: 1433 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 1434 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 1435 */ 1436 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) 1437 { 1438 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); 1439 } 1440 1441 /** 1442 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). 1443 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling 1444 * @param DMA2Dx DMA2D Instance 1445 * @param ChromaSubSampling This parameter can be one of the following values: 1446 * @arg @ref LL_DMA2D_CSS_444 1447 * @arg @ref LL_DMA2D_CSS_422 1448 * @arg @ref LL_DMA2D_CSS_420 1449 * @retval None 1450 */ 1451 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling) 1452 { 1453 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling); 1454 } 1455 1456 /** 1457 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). 1458 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling 1459 * @param DMA2Dx DMA2D Instance 1460 * @retval Returned value can be one of the following values: 1461 * @arg @ref LL_DMA2D_CSS_444 1462 * @arg @ref LL_DMA2D_CSS_422 1463 * @arg @ref LL_DMA2D_CSS_420 1464 */ 1465 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) 1466 { 1467 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); 1468 } 1469 /** 1470 * @} 1471 */ 1472 1473 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions 1474 * @ingroup RTEMSBSPsARMSTM32H7 1475 * @{ 1476 */ 1477 1478 /** 1479 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). 1480 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr 1481 * @param DMA2Dx DMA2D Instance 1482 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 1483 * @retval None 1484 */ 1485 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) 1486 { 1487 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); 1488 } 1489 1490 /** 1491 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). 1492 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr 1493 * @param DMA2Dx DMA2D Instance 1494 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 1495 */ 1496 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) 1497 { 1498 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); 1499 } 1500 1501 /** 1502 * @brief Enable DMA2D background CLUT loading. 1503 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad 1504 * @param DMA2Dx DMA2D Instance 1505 * @retval None 1506 */ 1507 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) 1508 { 1509 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); 1510 } 1511 1512 /** 1513 * @brief Indicate if DMA2D background CLUT loading is enabled. 1514 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad 1515 * @param DMA2Dx DMA2D Instance 1516 * @retval State of bit (1 or 0). 1517 */ 1518 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) 1519 { 1520 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); 1521 } 1522 1523 /** 1524 * @brief Set DMA2D background color mode. 1525 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode 1526 * @param DMA2Dx DMA2D Instance 1527 * @param ColorMode This parameter can be one of the following values: 1528 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 1529 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 1530 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 1531 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 1532 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 1533 * @arg @ref LL_DMA2D_INPUT_MODE_L8 1534 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 1535 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 1536 * @arg @ref LL_DMA2D_INPUT_MODE_L4 1537 * @arg @ref LL_DMA2D_INPUT_MODE_A8 1538 * @arg @ref LL_DMA2D_INPUT_MODE_A4 1539 * @retval None 1540 */ 1541 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 1542 { 1543 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); 1544 } 1545 1546 /** 1547 * @brief Return DMA2D background color mode. 1548 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode 1549 * @param DMA2Dx DMA2D Instance 1550 * @retval Returned value can be one of the following values: 1551 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 1552 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 1553 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 1554 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 1555 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 1556 * @arg @ref LL_DMA2D_INPUT_MODE_L8 1557 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 1558 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 1559 * @arg @ref LL_DMA2D_INPUT_MODE_L4 1560 * @arg @ref LL_DMA2D_INPUT_MODE_A8 1561 * @arg @ref LL_DMA2D_INPUT_MODE_A4 1562 */ 1563 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) 1564 { 1565 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); 1566 } 1567 1568 /** 1569 * @brief Set DMA2D background alpha mode. 1570 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode 1571 * @param DMA2Dx DMA2D Instance 1572 * @param AphaMode This parameter can be one of the following values: 1573 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 1574 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 1575 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 1576 * @retval None 1577 */ 1578 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) 1579 { 1580 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); 1581 } 1582 1583 /** 1584 * @brief Return DMA2D background alpha mode. 1585 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode 1586 * @param DMA2Dx DMA2D Instance 1587 * @retval Returned value can be one of the following values: 1588 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 1589 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 1590 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 1591 */ 1592 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) 1593 { 1594 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); 1595 } 1596 1597 /** 1598 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). 1599 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha 1600 * @param DMA2Dx DMA2D Instance 1601 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF 1602 * @retval None 1603 */ 1604 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) 1605 { 1606 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); 1607 } 1608 1609 /** 1610 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). 1611 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha 1612 * @param DMA2Dx DMA2D Instance 1613 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF 1614 */ 1615 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) 1616 { 1617 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); 1618 } 1619 1620 /** 1621 * @brief Set DMA2D background Red Blue swap mode. 1622 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode 1623 * @param DMA2Dx DMA2D Instance 1624 * @param RBSwapMode This parameter can be one of the following values: 1625 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 1626 * @arg @ref LL_DMA2D_RB_MODE_SWAP 1627 * @retval None 1628 */ 1629 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 1630 { 1631 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); 1632 } 1633 1634 /** 1635 * @brief Return DMA2D background Red Blue swap mode. 1636 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode 1637 * @param DMA2Dx DMA2D Instance 1638 * @retval Returned value can be one of the following values: 1639 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 1640 * @arg @ref LL_DMA2D_RB_MODE_SWAP 1641 */ 1642 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) 1643 { 1644 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); 1645 } 1646 1647 /** 1648 * @brief Set DMA2D background alpha inversion mode. 1649 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode 1650 * @param DMA2Dx DMA2D Instance 1651 * @param AlphaInversionMode This parameter can be one of the following values: 1652 * @arg @ref LL_DMA2D_ALPHA_REGULAR 1653 * @arg @ref LL_DMA2D_ALPHA_INVERTED 1654 * @retval None 1655 */ 1656 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 1657 { 1658 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); 1659 } 1660 1661 /** 1662 * @brief Return DMA2D background alpha inversion mode. 1663 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode 1664 * @param DMA2Dx DMA2D Instance 1665 * @retval Returned value can be one of the following values: 1666 * @arg @ref LL_DMA2D_ALPHA_REGULAR 1667 * @arg @ref LL_DMA2D_ALPHA_INVERTED 1668 */ 1669 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 1670 { 1671 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); 1672 } 1673 1674 /** 1675 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). 1676 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset 1677 * @param DMA2Dx DMA2D Instance 1678 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF 1679 * @retval None 1680 */ 1681 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 1682 { 1683 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); 1684 } 1685 1686 /** 1687 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). 1688 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset 1689 * @param DMA2Dx DMA2D Instance 1690 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF 1691 */ 1692 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 1693 { 1694 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); 1695 } 1696 1697 /** 1698 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). 1699 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor 1700 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor 1701 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor 1702 * @param DMA2Dx DMA2D Instance 1703 * @param Red Value between Min_Data=0 and Max_Data=0xFF 1704 * @param Green Value between Min_Data=0 and Max_Data=0xFF 1705 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 1706 * @retval None 1707 */ 1708 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) 1709 { 1710 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ 1711 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); 1712 } 1713 1714 /** 1715 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). 1716 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor 1717 * @param DMA2Dx DMA2D Instance 1718 * @param Red Value between Min_Data=0 and Max_Data=0xFF 1719 * @retval None 1720 */ 1721 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) 1722 { 1723 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); 1724 } 1725 1726 /** 1727 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). 1728 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor 1729 * @param DMA2Dx DMA2D Instance 1730 * @retval Red color value between Min_Data=0 and Max_Data=0xFF 1731 */ 1732 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) 1733 { 1734 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); 1735 } 1736 1737 /** 1738 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). 1739 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor 1740 * @param DMA2Dx DMA2D Instance 1741 * @param Green Value between Min_Data=0 and Max_Data=0xFF 1742 * @retval None 1743 */ 1744 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) 1745 { 1746 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); 1747 } 1748 1749 /** 1750 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). 1751 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor 1752 * @param DMA2Dx DMA2D Instance 1753 * @retval Green color value between Min_Data=0 and Max_Data=0xFF 1754 */ 1755 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) 1756 { 1757 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); 1758 } 1759 1760 /** 1761 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). 1762 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor 1763 * @param DMA2Dx DMA2D Instance 1764 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 1765 * @retval None 1766 */ 1767 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) 1768 { 1769 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); 1770 } 1771 1772 /** 1773 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). 1774 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor 1775 * @param DMA2Dx DMA2D Instance 1776 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF 1777 */ 1778 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) 1779 { 1780 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); 1781 } 1782 1783 /** 1784 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). 1785 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr 1786 * @param DMA2Dx DMA2D Instance 1787 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 1788 * @retval None 1789 */ 1790 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) 1791 { 1792 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); 1793 } 1794 1795 /** 1796 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). 1797 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr 1798 * @param DMA2Dx DMA2D Instance 1799 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 1800 */ 1801 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) 1802 { 1803 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); 1804 } 1805 1806 /** 1807 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). 1808 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize 1809 * @param DMA2Dx DMA2D Instance 1810 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF 1811 * @retval None 1812 */ 1813 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) 1814 { 1815 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); 1816 } 1817 1818 /** 1819 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). 1820 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize 1821 * @param DMA2Dx DMA2D Instance 1822 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF 1823 */ 1824 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) 1825 { 1826 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); 1827 } 1828 1829 /** 1830 * @brief Set DMA2D background CLUT color mode. 1831 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode 1832 * @param DMA2Dx DMA2D Instance 1833 * @param CLUTColorMode This parameter can be one of the following values: 1834 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 1835 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 1836 * @retval None 1837 */ 1838 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) 1839 { 1840 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); 1841 } 1842 1843 /** 1844 * @brief Return DMA2D background CLUT color mode. 1845 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode 1846 * @param DMA2Dx DMA2D Instance 1847 * @retval Returned value can be one of the following values: 1848 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 1849 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 1850 */ 1851 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) 1852 { 1853 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); 1854 } 1855 1856 /** 1857 * @} 1858 */ 1859 1860 /** 1861 * @} 1862 */ 1863 1864 1865 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management 1866 * @ingroup RTEMSBSPsARMSTM32H7 1867 * @{ 1868 */ 1869 1870 /** 1871 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not 1872 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE 1873 * @param DMA2Dx DMA2D Instance 1874 * @retval State of bit (1 or 0). 1875 */ 1876 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) 1877 { 1878 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); 1879 } 1880 1881 /** 1882 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not 1883 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC 1884 * @param DMA2Dx DMA2D Instance 1885 * @retval State of bit (1 or 0). 1886 */ 1887 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) 1888 { 1889 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); 1890 } 1891 1892 /** 1893 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not 1894 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE 1895 * @param DMA2Dx DMA2D Instance 1896 * @retval State of bit (1 or 0). 1897 */ 1898 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) 1899 { 1900 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); 1901 } 1902 1903 /** 1904 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not 1905 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW 1906 * @param DMA2Dx DMA2D Instance 1907 * @retval State of bit (1 or 0). 1908 */ 1909 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) 1910 { 1911 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); 1912 } 1913 1914 /** 1915 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not 1916 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC 1917 * @param DMA2Dx DMA2D Instance 1918 * @retval State of bit (1 or 0). 1919 */ 1920 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) 1921 { 1922 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); 1923 } 1924 1925 /** 1926 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not 1927 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE 1928 * @param DMA2Dx DMA2D Instance 1929 * @retval State of bit (1 or 0). 1930 */ 1931 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) 1932 { 1933 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); 1934 } 1935 1936 /** 1937 * @brief Clear DMA2D Configuration Error Interrupt Flag 1938 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE 1939 * @param DMA2Dx DMA2D Instance 1940 * @retval None 1941 */ 1942 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) 1943 { 1944 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); 1945 } 1946 1947 /** 1948 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag 1949 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC 1950 * @param DMA2Dx DMA2D Instance 1951 * @retval None 1952 */ 1953 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) 1954 { 1955 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); 1956 } 1957 1958 /** 1959 * @brief Clear DMA2D CLUT Access Error Interrupt Flag 1960 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE 1961 * @param DMA2Dx DMA2D Instance 1962 * @retval None 1963 */ 1964 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) 1965 { 1966 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); 1967 } 1968 1969 /** 1970 * @brief Clear DMA2D Transfer Watermark Interrupt Flag 1971 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW 1972 * @param DMA2Dx DMA2D Instance 1973 * @retval None 1974 */ 1975 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) 1976 { 1977 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); 1978 } 1979 1980 /** 1981 * @brief Clear DMA2D Transfer Complete Interrupt Flag 1982 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC 1983 * @param DMA2Dx DMA2D Instance 1984 * @retval None 1985 */ 1986 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) 1987 { 1988 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); 1989 } 1990 1991 /** 1992 * @brief Clear DMA2D Transfer Error Interrupt Flag 1993 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE 1994 * @param DMA2Dx DMA2D Instance 1995 * @retval None 1996 */ 1997 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) 1998 { 1999 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); 2000 } 2001 2002 /** 2003 * @} 2004 */ 2005 2006 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management 2007 * @ingroup RTEMSBSPsARMSTM32H7 2008 * @{ 2009 */ 2010 2011 /** 2012 * @brief Enable Configuration Error Interrupt 2013 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE 2014 * @param DMA2Dx DMA2D Instance 2015 * @retval None 2016 */ 2017 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) 2018 { 2019 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); 2020 } 2021 2022 /** 2023 * @brief Enable CLUT Transfer Complete Interrupt 2024 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC 2025 * @param DMA2Dx DMA2D Instance 2026 * @retval None 2027 */ 2028 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) 2029 { 2030 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); 2031 } 2032 2033 /** 2034 * @brief Enable CLUT Access Error Interrupt 2035 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE 2036 * @param DMA2Dx DMA2D Instance 2037 * @retval None 2038 */ 2039 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) 2040 { 2041 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); 2042 } 2043 2044 /** 2045 * @brief Enable Transfer Watermark Interrupt 2046 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW 2047 * @param DMA2Dx DMA2D Instance 2048 * @retval None 2049 */ 2050 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) 2051 { 2052 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); 2053 } 2054 2055 /** 2056 * @brief Enable Transfer Complete Interrupt 2057 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC 2058 * @param DMA2Dx DMA2D Instance 2059 * @retval None 2060 */ 2061 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) 2062 { 2063 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); 2064 } 2065 2066 /** 2067 * @brief Enable Transfer Error Interrupt 2068 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE 2069 * @param DMA2Dx DMA2D Instance 2070 * @retval None 2071 */ 2072 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) 2073 { 2074 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); 2075 } 2076 2077 /** 2078 * @brief Disable Configuration Error Interrupt 2079 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE 2080 * @param DMA2Dx DMA2D Instance 2081 * @retval None 2082 */ 2083 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) 2084 { 2085 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); 2086 } 2087 2088 /** 2089 * @brief Disable CLUT Transfer Complete Interrupt 2090 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC 2091 * @param DMA2Dx DMA2D Instance 2092 * @retval None 2093 */ 2094 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) 2095 { 2096 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); 2097 } 2098 2099 /** 2100 * @brief Disable CLUT Access Error Interrupt 2101 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE 2102 * @param DMA2Dx DMA2D Instance 2103 * @retval None 2104 */ 2105 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) 2106 { 2107 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); 2108 } 2109 2110 /** 2111 * @brief Disable Transfer Watermark Interrupt 2112 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW 2113 * @param DMA2Dx DMA2D Instance 2114 * @retval None 2115 */ 2116 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) 2117 { 2118 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); 2119 } 2120 2121 /** 2122 * @brief Disable Transfer Complete Interrupt 2123 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC 2124 * @param DMA2Dx DMA2D Instance 2125 * @retval None 2126 */ 2127 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) 2128 { 2129 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); 2130 } 2131 2132 /** 2133 * @brief Disable Transfer Error Interrupt 2134 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE 2135 * @param DMA2Dx DMA2D Instance 2136 * @retval None 2137 */ 2138 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) 2139 { 2140 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); 2141 } 2142 2143 /** 2144 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. 2145 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE 2146 * @param DMA2Dx DMA2D Instance 2147 * @retval State of bit (1 or 0). 2148 */ 2149 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) 2150 { 2151 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); 2152 } 2153 2154 /** 2155 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. 2156 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC 2157 * @param DMA2Dx DMA2D Instance 2158 * @retval State of bit (1 or 0). 2159 */ 2160 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) 2161 { 2162 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); 2163 } 2164 2165 /** 2166 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. 2167 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE 2168 * @param DMA2Dx DMA2D Instance 2169 * @retval State of bit (1 or 0). 2170 */ 2171 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) 2172 { 2173 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); 2174 } 2175 2176 /** 2177 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. 2178 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW 2179 * @param DMA2Dx DMA2D Instance 2180 * @retval State of bit (1 or 0). 2181 */ 2182 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) 2183 { 2184 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); 2185 } 2186 2187 /** 2188 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. 2189 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC 2190 * @param DMA2Dx DMA2D Instance 2191 * @retval State of bit (1 or 0). 2192 */ 2193 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) 2194 { 2195 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); 2196 } 2197 2198 /** 2199 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. 2200 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE 2201 * @param DMA2Dx DMA2D Instance 2202 * @retval State of bit (1 or 0). 2203 */ 2204 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) 2205 { 2206 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); 2207 } 2208 2209 2210 2211 /** 2212 * @} 2213 */ 2214 2215 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 2216 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions 2217 * @ingroup RTEMSBSPsARMSTM32H7 2218 * @{ 2219 */ 2220 2221 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); 2222 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); 2223 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); 2224 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); 2225 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); 2226 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); 2227 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 2228 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 2229 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 2230 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 2231 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); 2232 2233 /** 2234 * @} 2235 */ 2236 #endif /* USE_FULL_LL_DRIVER */ 2237 2238 /** 2239 * @} 2240 */ 2241 2242 /** 2243 * @} 2244 */ 2245 2246 #endif /* defined (DMA2D) */ 2247 2248 /** 2249 * @} 2250 */ 2251 2252 #ifdef __cplusplus 2253 } 2254 #endif 2255 2256 #endif /* STM32H7xx_LL_DMA2D_H */
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