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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_dma.h 0004 * @author MCD Application Team 0005 * @brief Header file of DMA LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_DMA_H 0021 #define STM32H7xx_LL_DMA_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 #include "stm32h7xx_ll_dmamux.h" 0030 0031 /** @addtogroup STM32H7xx_LL_Driver 0032 * @{ 0033 */ 0034 0035 #if defined (DMA1) || defined (DMA2) 0036 0037 /** @defgroup DMA_LL DMA 0038 * @ingroup RTEMSBSPsARMSTM32H7 0039 * @{ 0040 */ 0041 0042 /* Private types -------------------------------------------------------------*/ 0043 /* Private variables ---------------------------------------------------------*/ 0044 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 0045 * @ingroup RTEMSBSPsARMSTM32H7 0046 * @{ 0047 */ 0048 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 0049 static const uint8_t LL_DMA_STR_OFFSET_TAB[] = 0050 { 0051 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 0052 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 0053 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 0054 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 0055 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 0056 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 0057 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 0058 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 0059 }; 0060 0061 0062 /** 0063 * @} 0064 */ 0065 0066 /* Private macros ------------------------------------------------------------*/ 0067 /** @defgroup DMA_LL_Private_Macros DMA LL Private Macros 0068 * @ingroup RTEMSBSPsARMSTM32H7 0069 * @{ 0070 */ 0071 /** 0072 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel 0073 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 0074 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 0075 * @param __DMA_INSTANCE__ DMAx 0076 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0). 0077 */ 0078 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ 0079 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) 0080 /** 0081 * @} 0082 */ 0083 0084 /* Exported types ------------------------------------------------------------*/ 0085 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0086 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 0087 * @ingroup RTEMSBSPsARMSTM32H7 0088 * @{ 0089 */ 0090 typedef struct 0091 { 0092 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 0093 or as Source base address in case of memory to memory transfer direction. 0094 0095 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 0096 0097 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 0098 or as Destination base address in case of memory to memory transfer direction. 0099 0100 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 0101 0102 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 0103 from memory to memory or from peripheral to memory. 0104 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 0105 0106 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 0107 0108 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 0109 This parameter can be a value of @ref DMA_LL_EC_MODE 0110 @note The circular buffer mode cannot be used if the memory to memory 0111 data transfer direction is configured on the selected Stream 0112 0113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 0114 0115 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 0116 is incremented or not. 0117 This parameter can be a value of @ref DMA_LL_EC_PERIPH 0118 0119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 0120 0121 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 0122 is incremented or not. 0123 This parameter can be a value of @ref DMA_LL_EC_MEMORY 0124 0125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 0126 0127 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 0128 in case of memory to memory transfer direction. 0129 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 0130 0131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 0132 0133 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 0134 in case of memory to memory transfer direction. 0135 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 0136 0137 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 0138 0139 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 0140 The data unit is equal to the source buffer configuration set in PeripheralSize 0141 or MemorySize parameters depending in the transfer direction. 0142 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 0143 0144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 0145 0146 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 0147 This parameter can be a value of @ref DMAMUX1_Request_selection 0148 0149 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ 0150 0151 uint32_t Priority; /*!< Specifies the channel priority level. 0152 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 0153 0154 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ 0155 0156 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 0157 This parameter can be a value of @ref DMA_LL_FIFOMODE 0158 @note The Direct mode (FIFO mode disabled) cannot be used if the 0159 memory-to-memory data transfer is configured on the selected stream 0160 0161 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ 0162 0163 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 0164 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD 0165 0166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ 0167 0168 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 0169 It specifies the amount of data to be transferred in a single non interruptible 0170 transaction. 0171 This parameter can be a value of @ref DMA_LL_EC_MBURST 0172 @note The burst mode is possible only if the address Increment mode is enabled. 0173 0174 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ 0175 0176 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 0177 It specifies the amount of data to be transferred in a single non interruptible 0178 transaction. 0179 This parameter can be a value of @ref DMA_LL_EC_PBURST 0180 @note The burst mode is possible only if the address Increment mode is enabled. 0181 0182 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ 0183 0184 uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode. 0185 This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE 0186 0187 This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */ 0188 0189 uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode. 0190 This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM 0191 0192 This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */ 0193 } LL_DMA_InitTypeDef; 0194 /** 0195 * @} 0196 */ 0197 #endif /*USE_FULL_LL_DRIVER*/ 0198 /* Exported constants --------------------------------------------------------*/ 0199 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 0200 * @ingroup RTEMSBSPsARMSTM32H7 0201 * @{ 0202 */ 0203 0204 /** @defgroup DMA_LL_EC_STREAM STREAM 0205 * @ingroup RTEMSBSPsARMSTM32H7 0206 * @{ 0207 */ 0208 #define LL_DMA_STREAM_0 0x00000000U 0209 #define LL_DMA_STREAM_1 0x00000001U 0210 #define LL_DMA_STREAM_2 0x00000002U 0211 #define LL_DMA_STREAM_3 0x00000003U 0212 #define LL_DMA_STREAM_4 0x00000004U 0213 #define LL_DMA_STREAM_5 0x00000005U 0214 #define LL_DMA_STREAM_6 0x00000006U 0215 #define LL_DMA_STREAM_7 0x00000007U 0216 #define LL_DMA_STREAM_ALL 0xFFFF0000U 0217 /** 0218 * @} 0219 */ 0220 0221 0222 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 0223 * @ingroup RTEMSBSPsARMSTM32H7 0224 * @{ 0225 */ 0226 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 0227 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ 0228 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ 0229 /** 0230 * @} 0231 */ 0232 0233 /** @defgroup DMA_LL_EC_MODE MODE 0234 * @ingroup RTEMSBSPsARMSTM32H7 0235 * @{ 0236 */ 0237 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 0238 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ 0239 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ 0240 /** 0241 * @} 0242 */ 0243 0244 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 0245 * @ingroup RTEMSBSPsARMSTM32H7 0246 * @{ 0247 */ 0248 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 0249 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ 0250 /** 0251 * @} 0252 */ 0253 0254 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 0255 * @{ 0256 */ 0257 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 0258 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 0259 /** 0260 * @} 0261 */ 0262 0263 /** @defgroup DMA_LL_EC_PERIPH PERIPH 0264 * @ingroup RTEMSBSPsARMSTM32H7 0265 * @{ 0266 */ 0267 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 0268 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ 0269 /** 0270 * @} 0271 */ 0272 0273 /** @defgroup DMA_LL_EC_MEMORY MEMORY 0274 * @ingroup RTEMSBSPsARMSTM32H7 0275 * @{ 0276 */ 0277 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 0278 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ 0279 /** 0280 * @} 0281 */ 0282 0283 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 0284 * @ingroup RTEMSBSPsARMSTM32H7 0285 * @{ 0286 */ 0287 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 0288 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 0289 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 0290 /** 0291 * @} 0292 */ 0293 0294 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 0295 * @ingroup RTEMSBSPsARMSTM32H7 0296 * @{ 0297 */ 0298 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 0299 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 0300 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ 0301 /** 0302 * @} 0303 */ 0304 0305 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 0306 * @ingroup RTEMSBSPsARMSTM32H7 0307 * @{ 0308 */ 0309 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ 0310 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ 0311 /** 0312 * @} 0313 */ 0314 0315 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 0316 * @ingroup RTEMSBSPsARMSTM32H7 0317 * @{ 0318 */ 0319 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 0320 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ 0321 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ 0322 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ 0323 /** 0324 * @} 0325 */ 0326 0327 0328 /** @defgroup DMA_LL_EC_MBURST MBURST 0329 * @ingroup RTEMSBSPsARMSTM32H7 0330 * @{ 0331 */ 0332 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ 0333 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ 0334 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ 0335 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ 0336 /** 0337 * @} 0338 */ 0339 0340 /** @defgroup DMA_LL_EC_PBURST PBURST 0341 * @ingroup RTEMSBSPsARMSTM32H7 0342 * @{ 0343 */ 0344 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ 0345 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ 0346 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ 0347 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ 0348 /** 0349 * @} 0350 */ 0351 0352 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 0353 * @ingroup RTEMSBSPsARMSTM32H7 0354 * @{ 0355 */ 0356 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ 0357 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ 0358 /** 0359 * @} 0360 */ 0361 0362 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 0363 * @ingroup RTEMSBSPsARMSTM32H7 0364 * @{ 0365 */ 0366 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ 0367 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ 0368 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ 0369 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ 0370 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ 0371 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ 0372 /** 0373 * @} 0374 */ 0375 0376 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 0377 * @ingroup RTEMSBSPsARMSTM32H7 0378 * @{ 0379 */ 0380 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 0381 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ 0382 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ 0383 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ 0384 /** 0385 * @} 0386 */ 0387 0388 /** 0389 * @} 0390 */ 0391 0392 /* Exported macro ------------------------------------------------------------*/ 0393 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 0394 * @ingroup RTEMSBSPsARMSTM32H7 0395 * @{ 0396 */ 0397 0398 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 0399 * @ingroup RTEMSBSPsARMSTM32H7 0400 * @{ 0401 */ 0402 /** 0403 * @brief Write a value in DMA register 0404 * @param __INSTANCE__ DMA Instance 0405 * @param __REG__ Register to be written 0406 * @param __VALUE__ Value to be written in the register 0407 * @retval None 0408 */ 0409 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 0410 0411 /** 0412 * @brief Read a value in DMA register 0413 * @param __INSTANCE__ DMA Instance 0414 * @param __REG__ Register to be read 0415 * @retval Register value 0416 */ 0417 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0418 /** 0419 * @} 0420 */ 0421 0422 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 0423 * @ingroup RTEMSBSPsARMSTM32H7 0424 * @{ 0425 */ 0426 /** 0427 * @brief Convert DMAx_Streamy into DMAx 0428 * @param __STREAM_INSTANCE__ DMAx_Streamy 0429 * @retval DMAx 0430 */ 0431 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 0432 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 0433 0434 /** 0435 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 0436 * @param __STREAM_INSTANCE__ DMAx_Streamy 0437 * @retval LL_DMA_STREAM_y 0438 */ 0439 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 0440 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 0441 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 0442 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 0443 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 0444 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 0445 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 0446 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 0447 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 0448 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 0449 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 0450 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 0451 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 0452 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 0453 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 0454 LL_DMA_STREAM_7) 0455 0456 /** 0457 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 0458 * @param __DMA_INSTANCE__ DMAx 0459 * @param __STREAM__ LL_DMA_STREAM_y 0460 * @retval DMAx_Streamy 0461 */ 0462 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 0463 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ 0464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ 0465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ 0466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ 0467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ 0468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ 0469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ 0470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ 0471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ 0472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ 0473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ 0474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ 0475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ 0476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ 0477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ 0478 DMA2_Stream7) 0479 0480 /** 0481 * @} 0482 */ 0483 0484 /** 0485 * @} 0486 */ 0487 0488 0489 /* Exported functions --------------------------------------------------------*/ 0490 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 0491 * @ingroup RTEMSBSPsARMSTM32H7 0492 * @{ 0493 */ 0494 0495 /** @defgroup DMA_LL_EF_Configuration Configuration 0496 * @ingroup RTEMSBSPsARMSTM32H7 0497 * @{ 0498 */ 0499 /** 0500 * @brief Enable DMA stream. 0501 * @rmtoll CR EN LL_DMA_EnableStream 0502 * @param DMAx DMAx Instance 0503 * @param Stream This parameter can be one of the following values: 0504 * @arg @ref LL_DMA_STREAM_0 0505 * @arg @ref LL_DMA_STREAM_1 0506 * @arg @ref LL_DMA_STREAM_2 0507 * @arg @ref LL_DMA_STREAM_3 0508 * @arg @ref LL_DMA_STREAM_4 0509 * @arg @ref LL_DMA_STREAM_5 0510 * @arg @ref LL_DMA_STREAM_6 0511 * @arg @ref LL_DMA_STREAM_7 0512 * @retval None 0513 */ 0514 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 0515 { 0516 uint32_t dma_base_addr = (uint32_t)DMAx; 0517 0518 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); 0519 } 0520 0521 /** 0522 * @brief Disable DMA stream. 0523 * @rmtoll CR EN LL_DMA_DisableStream 0524 * @param DMAx DMAx Instance 0525 * @param Stream This parameter can be one of the following values: 0526 * @arg @ref LL_DMA_STREAM_0 0527 * @arg @ref LL_DMA_STREAM_1 0528 * @arg @ref LL_DMA_STREAM_2 0529 * @arg @ref LL_DMA_STREAM_3 0530 * @arg @ref LL_DMA_STREAM_4 0531 * @arg @ref LL_DMA_STREAM_5 0532 * @arg @ref LL_DMA_STREAM_6 0533 * @arg @ref LL_DMA_STREAM_7 0534 * @retval None 0535 */ 0536 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 0537 { 0538 uint32_t dma_base_addr = (uint32_t)DMAx; 0539 0540 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); 0541 } 0542 0543 /** 0544 * @brief Check if DMA stream is enabled or disabled. 0545 * @rmtoll CR EN LL_DMA_IsEnabledStream 0546 * @param DMAx DMAx Instance 0547 * @param Stream This parameter can be one of the following values: 0548 * @arg @ref LL_DMA_STREAM_0 0549 * @arg @ref LL_DMA_STREAM_1 0550 * @arg @ref LL_DMA_STREAM_2 0551 * @arg @ref LL_DMA_STREAM_3 0552 * @arg @ref LL_DMA_STREAM_4 0553 * @arg @ref LL_DMA_STREAM_5 0554 * @arg @ref LL_DMA_STREAM_6 0555 * @arg @ref LL_DMA_STREAM_7 0556 * @retval State of bit (1 or 0). 0557 */ 0558 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 0559 { 0560 uint32_t dma_base_addr = (uint32_t)DMAx; 0561 0562 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); 0563 } 0564 0565 /** 0566 * @brief Configure all parameters linked to DMA transfer. 0567 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 0568 * CR CIRC LL_DMA_ConfigTransfer\n 0569 * CR PINC LL_DMA_ConfigTransfer\n 0570 * CR MINC LL_DMA_ConfigTransfer\n 0571 * CR PSIZE LL_DMA_ConfigTransfer\n 0572 * CR MSIZE LL_DMA_ConfigTransfer\n 0573 * CR PL LL_DMA_ConfigTransfer\n 0574 * CR PFCTRL LL_DMA_ConfigTransfer\n 0575 * CR DBM LL_DMA_ConfigTransfer\n 0576 * CR CT LL_DMA_ConfigTransfer 0577 * @param DMAx DMAx Instance 0578 * @param Stream This parameter can be one of the following values: 0579 * @arg @ref LL_DMA_STREAM_0 0580 * @arg @ref LL_DMA_STREAM_1 0581 * @arg @ref LL_DMA_STREAM_2 0582 * @arg @ref LL_DMA_STREAM_3 0583 * @arg @ref LL_DMA_STREAM_4 0584 * @arg @ref LL_DMA_STREAM_5 0585 * @arg @ref LL_DMA_STREAM_6 0586 * @arg @ref LL_DMA_STREAM_7 0587 * @param Configuration This parameter must be a combination of all the following values: 0588 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 0589 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 0590 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 0591 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 0592 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 0593 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 0594 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 0595 * @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE 0596 * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 0597 *@retval None 0598 */ 0599 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) 0600 { 0601 uint32_t dma_base_addr = (uint32_t)DMAx; 0602 0603 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, 0604 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \ 0605 DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration); 0606 } 0607 0608 /** 0609 * @brief Set Data transfer direction (read from peripheral or from memory). 0610 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 0611 * @param DMAx DMAx Instance 0612 * @param Stream This parameter can be one of the following values: 0613 * @arg @ref LL_DMA_STREAM_0 0614 * @arg @ref LL_DMA_STREAM_1 0615 * @arg @ref LL_DMA_STREAM_2 0616 * @arg @ref LL_DMA_STREAM_3 0617 * @arg @ref LL_DMA_STREAM_4 0618 * @arg @ref LL_DMA_STREAM_5 0619 * @arg @ref LL_DMA_STREAM_6 0620 * @arg @ref LL_DMA_STREAM_7 0621 * @param Direction This parameter can be one of the following values: 0622 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0623 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 0624 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 0625 * @retval None 0626 */ 0627 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) 0628 { 0629 uint32_t dma_base_addr = (uint32_t)DMAx; 0630 0631 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); 0632 } 0633 0634 /** 0635 * @brief Get Data transfer direction (read from peripheral or from memory). 0636 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 0637 * @param DMAx DMAx Instance 0638 * @param Stream This parameter can be one of the following values: 0639 * @arg @ref LL_DMA_STREAM_0 0640 * @arg @ref LL_DMA_STREAM_1 0641 * @arg @ref LL_DMA_STREAM_2 0642 * @arg @ref LL_DMA_STREAM_3 0643 * @arg @ref LL_DMA_STREAM_4 0644 * @arg @ref LL_DMA_STREAM_5 0645 * @arg @ref LL_DMA_STREAM_6 0646 * @arg @ref LL_DMA_STREAM_7 0647 * @retval Returned value can be one of the following values: 0648 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0649 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 0650 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 0651 */ 0652 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 0653 { 0654 uint32_t dma_base_addr = (uint32_t)DMAx; 0655 0656 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); 0657 } 0658 0659 /** 0660 * @brief Set DMA mode normal, circular or peripheral flow control. 0661 * @rmtoll CR CIRC LL_DMA_SetMode\n 0662 * CR PFCTRL LL_DMA_SetMode 0663 * @param DMAx DMAx Instance 0664 * @param Stream This parameter can be one of the following values: 0665 * @arg @ref LL_DMA_STREAM_0 0666 * @arg @ref LL_DMA_STREAM_1 0667 * @arg @ref LL_DMA_STREAM_2 0668 * @arg @ref LL_DMA_STREAM_3 0669 * @arg @ref LL_DMA_STREAM_4 0670 * @arg @ref LL_DMA_STREAM_5 0671 * @arg @ref LL_DMA_STREAM_6 0672 * @arg @ref LL_DMA_STREAM_7 0673 * @param Mode This parameter can be one of the following values: 0674 * @arg @ref LL_DMA_MODE_NORMAL 0675 * @arg @ref LL_DMA_MODE_CIRCULAR 0676 * @arg @ref LL_DMA_MODE_PFCTRL 0677 * @retval None 0678 */ 0679 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 0680 { 0681 uint32_t dma_base_addr = (uint32_t)DMAx; 0682 0683 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); 0684 } 0685 0686 /** 0687 * @brief Get DMA mode normal, circular or peripheral flow control. 0688 * @rmtoll CR CIRC LL_DMA_GetMode\n 0689 * CR PFCTRL LL_DMA_GetMode 0690 * @param DMAx DMAx Instance 0691 * @param Stream This parameter can be one of the following values: 0692 * @arg @ref LL_DMA_STREAM_0 0693 * @arg @ref LL_DMA_STREAM_1 0694 * @arg @ref LL_DMA_STREAM_2 0695 * @arg @ref LL_DMA_STREAM_3 0696 * @arg @ref LL_DMA_STREAM_4 0697 * @arg @ref LL_DMA_STREAM_5 0698 * @arg @ref LL_DMA_STREAM_6 0699 * @arg @ref LL_DMA_STREAM_7 0700 * @retval Returned value can be one of the following values: 0701 * @arg @ref LL_DMA_MODE_NORMAL 0702 * @arg @ref LL_DMA_MODE_CIRCULAR 0703 * @arg @ref LL_DMA_MODE_PFCTRL 0704 */ 0705 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 0706 { 0707 uint32_t dma_base_addr = (uint32_t)DMAx; 0708 0709 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); 0710 } 0711 0712 /** 0713 * @brief Set Peripheral increment mode. 0714 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 0715 * @param DMAx DMAx Instance 0716 * @param Stream This parameter can be one of the following values: 0717 * @arg @ref LL_DMA_STREAM_0 0718 * @arg @ref LL_DMA_STREAM_1 0719 * @arg @ref LL_DMA_STREAM_2 0720 * @arg @ref LL_DMA_STREAM_3 0721 * @arg @ref LL_DMA_STREAM_4 0722 * @arg @ref LL_DMA_STREAM_5 0723 * @arg @ref LL_DMA_STREAM_6 0724 * @arg @ref LL_DMA_STREAM_7 0725 * @param IncrementMode This parameter can be one of the following values: 0726 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 0727 * @arg @ref LL_DMA_PERIPH_INCREMENT 0728 * @retval None 0729 */ 0730 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 0731 { 0732 uint32_t dma_base_addr = (uint32_t)DMAx; 0733 0734 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); 0735 } 0736 0737 /** 0738 * @brief Get Peripheral increment mode. 0739 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 0740 * @param DMAx DMAx Instance 0741 * @param Stream This parameter can be one of the following values: 0742 * @arg @ref LL_DMA_STREAM_0 0743 * @arg @ref LL_DMA_STREAM_1 0744 * @arg @ref LL_DMA_STREAM_2 0745 * @arg @ref LL_DMA_STREAM_3 0746 * @arg @ref LL_DMA_STREAM_4 0747 * @arg @ref LL_DMA_STREAM_5 0748 * @arg @ref LL_DMA_STREAM_6 0749 * @arg @ref LL_DMA_STREAM_7 0750 * @retval Returned value can be one of the following values: 0751 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 0752 * @arg @ref LL_DMA_PERIPH_INCREMENT 0753 */ 0754 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 0755 { 0756 uint32_t dma_base_addr = (uint32_t)DMAx; 0757 0758 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); 0759 } 0760 0761 /** 0762 * @brief Set Memory increment mode. 0763 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 0764 * @param DMAx DMAx Instance 0765 * @param Stream This parameter can be one of the following values: 0766 * @arg @ref LL_DMA_STREAM_0 0767 * @arg @ref LL_DMA_STREAM_1 0768 * @arg @ref LL_DMA_STREAM_2 0769 * @arg @ref LL_DMA_STREAM_3 0770 * @arg @ref LL_DMA_STREAM_4 0771 * @arg @ref LL_DMA_STREAM_5 0772 * @arg @ref LL_DMA_STREAM_6 0773 * @arg @ref LL_DMA_STREAM_7 0774 * @param IncrementMode This parameter can be one of the following values: 0775 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 0776 * @arg @ref LL_DMA_MEMORY_INCREMENT 0777 * @retval None 0778 */ 0779 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 0780 { 0781 uint32_t dma_base_addr = (uint32_t)DMAx; 0782 0783 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); 0784 } 0785 0786 /** 0787 * @brief Get Memory increment mode. 0788 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 0789 * @param DMAx DMAx Instance 0790 * @param Stream This parameter can be one of the following values: 0791 * @arg @ref LL_DMA_STREAM_0 0792 * @arg @ref LL_DMA_STREAM_1 0793 * @arg @ref LL_DMA_STREAM_2 0794 * @arg @ref LL_DMA_STREAM_3 0795 * @arg @ref LL_DMA_STREAM_4 0796 * @arg @ref LL_DMA_STREAM_5 0797 * @arg @ref LL_DMA_STREAM_6 0798 * @arg @ref LL_DMA_STREAM_7 0799 * @retval Returned value can be one of the following values: 0800 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 0801 * @arg @ref LL_DMA_MEMORY_INCREMENT 0802 */ 0803 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 0804 { 0805 uint32_t dma_base_addr = (uint32_t)DMAx; 0806 0807 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); 0808 } 0809 0810 /** 0811 * @brief Set Peripheral size. 0812 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 0813 * @param DMAx DMAx Instance 0814 * @param Stream This parameter can be one of the following values: 0815 * @arg @ref LL_DMA_STREAM_0 0816 * @arg @ref LL_DMA_STREAM_1 0817 * @arg @ref LL_DMA_STREAM_2 0818 * @arg @ref LL_DMA_STREAM_3 0819 * @arg @ref LL_DMA_STREAM_4 0820 * @arg @ref LL_DMA_STREAM_5 0821 * @arg @ref LL_DMA_STREAM_6 0822 * @arg @ref LL_DMA_STREAM_7 0823 * @param Size This parameter can be one of the following values: 0824 * @arg @ref LL_DMA_PDATAALIGN_BYTE 0825 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 0826 * @arg @ref LL_DMA_PDATAALIGN_WORD 0827 * @retval None 0828 */ 0829 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 0830 { 0831 uint32_t dma_base_addr = (uint32_t)DMAx; 0832 0833 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); 0834 } 0835 0836 /** 0837 * @brief Get Peripheral size. 0838 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 0839 * @param DMAx DMAx Instance 0840 * @param Stream This parameter can be one of the following values: 0841 * @arg @ref LL_DMA_STREAM_0 0842 * @arg @ref LL_DMA_STREAM_1 0843 * @arg @ref LL_DMA_STREAM_2 0844 * @arg @ref LL_DMA_STREAM_3 0845 * @arg @ref LL_DMA_STREAM_4 0846 * @arg @ref LL_DMA_STREAM_5 0847 * @arg @ref LL_DMA_STREAM_6 0848 * @arg @ref LL_DMA_STREAM_7 0849 * @retval Returned value can be one of the following values: 0850 * @arg @ref LL_DMA_PDATAALIGN_BYTE 0851 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 0852 * @arg @ref LL_DMA_PDATAALIGN_WORD 0853 */ 0854 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 0855 { 0856 uint32_t dma_base_addr = (uint32_t)DMAx; 0857 0858 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); 0859 } 0860 0861 /** 0862 * @brief Set Memory size. 0863 * @rmtoll CR MSIZE LL_DMA_SetMemorySize 0864 * @param DMAx DMAx Instance 0865 * @param Stream This parameter can be one of the following values: 0866 * @arg @ref LL_DMA_STREAM_0 0867 * @arg @ref LL_DMA_STREAM_1 0868 * @arg @ref LL_DMA_STREAM_2 0869 * @arg @ref LL_DMA_STREAM_3 0870 * @arg @ref LL_DMA_STREAM_4 0871 * @arg @ref LL_DMA_STREAM_5 0872 * @arg @ref LL_DMA_STREAM_6 0873 * @arg @ref LL_DMA_STREAM_7 0874 * @param Size This parameter can be one of the following values: 0875 * @arg @ref LL_DMA_MDATAALIGN_BYTE 0876 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 0877 * @arg @ref LL_DMA_MDATAALIGN_WORD 0878 * @retval None 0879 */ 0880 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 0881 { 0882 uint32_t dma_base_addr = (uint32_t)DMAx; 0883 0884 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); 0885 } 0886 0887 /** 0888 * @brief Get Memory size. 0889 * @rmtoll CR MSIZE LL_DMA_GetMemorySize 0890 * @param DMAx DMAx Instance 0891 * @param Stream This parameter can be one of the following values: 0892 * @arg @ref LL_DMA_STREAM_0 0893 * @arg @ref LL_DMA_STREAM_1 0894 * @arg @ref LL_DMA_STREAM_2 0895 * @arg @ref LL_DMA_STREAM_3 0896 * @arg @ref LL_DMA_STREAM_4 0897 * @arg @ref LL_DMA_STREAM_5 0898 * @arg @ref LL_DMA_STREAM_6 0899 * @arg @ref LL_DMA_STREAM_7 0900 * @retval Returned value can be one of the following values: 0901 * @arg @ref LL_DMA_MDATAALIGN_BYTE 0902 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 0903 * @arg @ref LL_DMA_MDATAALIGN_WORD 0904 */ 0905 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 0906 { 0907 uint32_t dma_base_addr = (uint32_t)DMAx; 0908 0909 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); 0910 } 0911 0912 /** 0913 * @brief Set Peripheral increment offset size. 0914 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 0915 * @param DMAx DMAx Instance 0916 * @param Stream This parameter can be one of the following values: 0917 * @arg @ref LL_DMA_STREAM_0 0918 * @arg @ref LL_DMA_STREAM_1 0919 * @arg @ref LL_DMA_STREAM_2 0920 * @arg @ref LL_DMA_STREAM_3 0921 * @arg @ref LL_DMA_STREAM_4 0922 * @arg @ref LL_DMA_STREAM_5 0923 * @arg @ref LL_DMA_STREAM_6 0924 * @arg @ref LL_DMA_STREAM_7 0925 * @param OffsetSize This parameter can be one of the following values: 0926 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 0927 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 0928 * @retval None 0929 */ 0930 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) 0931 { 0932 uint32_t dma_base_addr = (uint32_t)DMAx; 0933 0934 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); 0935 } 0936 0937 /** 0938 * @brief Get Peripheral increment offset size. 0939 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 0940 * @param DMAx DMAx Instance 0941 * @param Stream This parameter can be one of the following values: 0942 * @arg @ref LL_DMA_STREAM_0 0943 * @arg @ref LL_DMA_STREAM_1 0944 * @arg @ref LL_DMA_STREAM_2 0945 * @arg @ref LL_DMA_STREAM_3 0946 * @arg @ref LL_DMA_STREAM_4 0947 * @arg @ref LL_DMA_STREAM_5 0948 * @arg @ref LL_DMA_STREAM_6 0949 * @arg @ref LL_DMA_STREAM_7 0950 * @retval Returned value can be one of the following values: 0951 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 0952 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 0953 */ 0954 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 0955 { 0956 uint32_t dma_base_addr = (uint32_t)DMAx; 0957 0958 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); 0959 } 0960 0961 /** 0962 * @brief Set Stream priority level. 0963 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 0964 * @param DMAx DMAx Instance 0965 * @param Stream This parameter can be one of the following values: 0966 * @arg @ref LL_DMA_STREAM_0 0967 * @arg @ref LL_DMA_STREAM_1 0968 * @arg @ref LL_DMA_STREAM_2 0969 * @arg @ref LL_DMA_STREAM_3 0970 * @arg @ref LL_DMA_STREAM_4 0971 * @arg @ref LL_DMA_STREAM_5 0972 * @arg @ref LL_DMA_STREAM_6 0973 * @arg @ref LL_DMA_STREAM_7 0974 * @param Priority This parameter can be one of the following values: 0975 * @arg @ref LL_DMA_PRIORITY_LOW 0976 * @arg @ref LL_DMA_PRIORITY_MEDIUM 0977 * @arg @ref LL_DMA_PRIORITY_HIGH 0978 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 0979 * @retval None 0980 */ 0981 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) 0982 { 0983 uint32_t dma_base_addr = (uint32_t)DMAx; 0984 0985 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); 0986 } 0987 0988 /** 0989 * @brief Get Stream priority level. 0990 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 0991 * @param DMAx DMAx Instance 0992 * @param Stream This parameter can be one of the following values: 0993 * @arg @ref LL_DMA_STREAM_0 0994 * @arg @ref LL_DMA_STREAM_1 0995 * @arg @ref LL_DMA_STREAM_2 0996 * @arg @ref LL_DMA_STREAM_3 0997 * @arg @ref LL_DMA_STREAM_4 0998 * @arg @ref LL_DMA_STREAM_5 0999 * @arg @ref LL_DMA_STREAM_6 1000 * @arg @ref LL_DMA_STREAM_7 1001 * @retval Returned value can be one of the following values: 1002 * @arg @ref LL_DMA_PRIORITY_LOW 1003 * @arg @ref LL_DMA_PRIORITY_MEDIUM 1004 * @arg @ref LL_DMA_PRIORITY_HIGH 1005 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 1006 */ 1007 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 1008 { 1009 uint32_t dma_base_addr = (uint32_t)DMAx; 1010 1011 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); 1012 } 1013 1014 /** 1015 * @brief Enable DMA stream bufferable transfer. 1016 * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer 1017 * @param DMAx DMAx Instance 1018 * @param Stream This parameter can be one of the following values: 1019 * @arg @ref LL_DMA_STREAM_0 1020 * @arg @ref LL_DMA_STREAM_1 1021 * @arg @ref LL_DMA_STREAM_2 1022 * @arg @ref LL_DMA_STREAM_3 1023 * @arg @ref LL_DMA_STREAM_4 1024 * @arg @ref LL_DMA_STREAM_5 1025 * @arg @ref LL_DMA_STREAM_6 1026 * @arg @ref LL_DMA_STREAM_7 1027 * @retval None 1028 */ 1029 __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) 1030 { 1031 uint32_t dma_base_addr = (uint32_t)DMAx; 1032 1033 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); 1034 } 1035 1036 /** 1037 * @brief Disable DMA stream bufferable transfer. 1038 * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer 1039 * @param DMAx DMAx Instance 1040 * @param Stream This parameter can be one of the following values: 1041 * @arg @ref LL_DMA_STREAM_0 1042 * @arg @ref LL_DMA_STREAM_1 1043 * @arg @ref LL_DMA_STREAM_2 1044 * @arg @ref LL_DMA_STREAM_3 1045 * @arg @ref LL_DMA_STREAM_4 1046 * @arg @ref LL_DMA_STREAM_5 1047 * @arg @ref LL_DMA_STREAM_6 1048 * @arg @ref LL_DMA_STREAM_7 1049 * @retval None 1050 */ 1051 __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) 1052 { 1053 uint32_t dma_base_addr = (uint32_t)DMAx; 1054 1055 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); 1056 } 1057 1058 /** 1059 * @brief Set Number of data to transfer. 1060 * @rmtoll NDTR NDT LL_DMA_SetDataLength 1061 * @note This action has no effect if 1062 * stream is enabled. 1063 * @param DMAx DMAx Instance 1064 * @param Stream This parameter can be one of the following values: 1065 * @arg @ref LL_DMA_STREAM_0 1066 * @arg @ref LL_DMA_STREAM_1 1067 * @arg @ref LL_DMA_STREAM_2 1068 * @arg @ref LL_DMA_STREAM_3 1069 * @arg @ref LL_DMA_STREAM_4 1070 * @arg @ref LL_DMA_STREAM_5 1071 * @arg @ref LL_DMA_STREAM_6 1072 * @arg @ref LL_DMA_STREAM_7 1073 * @param NbData Between 0 to 0xFFFFFFFF 1074 * @retval None 1075 */ 1076 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) 1077 { 1078 uint32_t dma_base_addr = (uint32_t)DMAx; 1079 1080 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); 1081 } 1082 1083 /** 1084 * @brief Get Number of data to transfer. 1085 * @rmtoll NDTR NDT LL_DMA_GetDataLength 1086 * @note Once the stream is enabled, the return value indicate the 1087 * remaining bytes to be transmitted. 1088 * @param DMAx DMAx Instance 1089 * @param Stream This parameter can be one of the following values: 1090 * @arg @ref LL_DMA_STREAM_0 1091 * @arg @ref LL_DMA_STREAM_1 1092 * @arg @ref LL_DMA_STREAM_2 1093 * @arg @ref LL_DMA_STREAM_3 1094 * @arg @ref LL_DMA_STREAM_4 1095 * @arg @ref LL_DMA_STREAM_5 1096 * @arg @ref LL_DMA_STREAM_6 1097 * @arg @ref LL_DMA_STREAM_7 1098 * @retval Between 0 to 0xFFFFFFFF 1099 */ 1100 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) 1101 { 1102 uint32_t dma_base_addr = (uint32_t)DMAx; 1103 1104 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); 1105 } 1106 /** 1107 * @brief Set DMA request for DMA Streams on DMAMUX Channel x. 1108 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 1109 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 1110 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest 1111 * @param DMAx DMAx Instance 1112 * @param Stream This parameter can be one of the following values: 1113 * @arg @ref LL_DMA_STREAM_0 1114 * @arg @ref LL_DMA_STREAM_1 1115 * @arg @ref LL_DMA_STREAM_2 1116 * @arg @ref LL_DMA_STREAM_3 1117 * @arg @ref LL_DMA_STREAM_4 1118 * @arg @ref LL_DMA_STREAM_5 1119 * @arg @ref LL_DMA_STREAM_6 1120 * @arg @ref LL_DMA_STREAM_7 1121 * @param Request This parameter can be one of the following values: 1122 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM 1123 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 1124 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 1125 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 1126 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 1127 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 1128 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 1129 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 1130 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 1131 * @arg @ref LL_DMAMUX1_REQ_ADC1 1132 * @arg @ref LL_DMAMUX1_REQ_ADC2 1133 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 1134 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 1135 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 1136 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 1137 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP 1138 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG 1139 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM 1140 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 1141 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 1142 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 1143 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 1144 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP 1145 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 1146 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 1147 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 1148 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 1149 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP 1150 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG 1151 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 1152 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 1153 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 1154 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP 1155 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX 1156 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX 1157 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX 1158 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX 1159 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX 1160 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX 1161 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX 1162 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX 1163 * @arg @ref LL_DMAMUX1_REQ_USART1_RX 1164 * @arg @ref LL_DMAMUX1_REQ_USART1_TX 1165 * @arg @ref LL_DMAMUX1_REQ_USART2_RX 1166 * @arg @ref LL_DMAMUX1_REQ_USART2_TX 1167 * @arg @ref LL_DMAMUX1_REQ_USART3_RX 1168 * @arg @ref LL_DMAMUX1_REQ_USART3_TX 1169 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 1170 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 1171 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 1172 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 1173 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP 1174 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG 1175 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM 1176 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 1177 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 1178 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 1179 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 1180 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP 1181 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG 1182 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX 1183 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX 1184 * @arg @ref LL_DMAMUX1_REQ_UART4_RX 1185 * @arg @ref LL_DMAMUX1_REQ_UART4_TX 1186 * @arg @ref LL_DMAMUX1_REQ_UART5_RX 1187 * @arg @ref LL_DMAMUX1_REQ_UART5_TX 1188 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 1189 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 1190 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP 1191 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP 1192 * @arg @ref LL_DMAMUX1_REQ_USART6_RX 1193 * @arg @ref LL_DMAMUX1_REQ_USART6_TX 1194 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX 1195 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX 1196 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) 1197 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN 1198 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT 1199 * @arg @ref LL_DMAMUX1_REQ_HASH_IN 1200 * @arg @ref LL_DMAMUX1_REQ_UART7_RX 1201 * @arg @ref LL_DMAMUX1_REQ_UART7_TX 1202 * @arg @ref LL_DMAMUX1_REQ_UART8_RX 1203 * @arg @ref LL_DMAMUX1_REQ_UART8_TX 1204 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX 1205 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX 1206 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX 1207 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX 1208 * @arg @ref LL_DMAMUX1_REQ_SAI1_A 1209 * @arg @ref LL_DMAMUX1_REQ_SAI1_B 1210 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) 1211 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) 1212 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX 1213 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX 1214 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT 1215 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS 1216 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) 1217 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) 1218 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) 1219 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) 1220 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) 1221 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) 1222 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 1223 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 1224 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 1225 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 1226 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 1227 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP 1228 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG 1229 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM 1230 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 1231 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP 1232 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 1233 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP 1234 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) 1235 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) 1236 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) 1237 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) 1238 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) 1239 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) 1240 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) 1241 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) 1242 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) 1243 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) 1244 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) 1245 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) 1246 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) 1247 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) 1248 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) 1249 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) 1250 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) 1251 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) 1252 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) 1253 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) 1254 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) 1255 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) 1256 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) 1257 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) 1258 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) 1259 * 1260 * @note (*) Availability depends on devices. 1261 * @retval None 1262 */ 1263 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request) 1264 { 1265 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); 1266 } 1267 1268 /** 1269 * @brief Get DMA request for DMA Channels on DMAMUX Channel x. 1270 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 1271 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 1272 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest 1273 * @param DMAx DMAx Instance 1274 * @param Stream This parameter can be one of the following values: 1275 * @arg @ref LL_DMA_STREAM_0 1276 * @arg @ref LL_DMA_STREAM_1 1277 * @arg @ref LL_DMA_STREAM_2 1278 * @arg @ref LL_DMA_STREAM_3 1279 * @arg @ref LL_DMA_STREAM_4 1280 * @arg @ref LL_DMA_STREAM_5 1281 * @arg @ref LL_DMA_STREAM_6 1282 * @arg @ref LL_DMA_STREAM_7 1283 * @retval Returned value can be one of the following values: 1284 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM 1285 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 1286 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 1287 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 1288 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 1289 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 1290 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 1291 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 1292 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 1293 * @arg @ref LL_DMAMUX1_REQ_ADC1 1294 * @arg @ref LL_DMAMUX1_REQ_ADC2 1295 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 1296 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 1297 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 1298 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 1299 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP 1300 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG 1301 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM 1302 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 1303 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 1304 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 1305 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 1306 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP 1307 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 1308 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 1309 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 1310 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 1311 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP 1312 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG 1313 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 1314 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 1315 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 1316 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP 1317 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX 1318 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX 1319 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX 1320 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX 1321 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX 1322 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX 1323 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX 1324 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX 1325 * @arg @ref LL_DMAMUX1_REQ_USART1_RX 1326 * @arg @ref LL_DMAMUX1_REQ_USART1_TX 1327 * @arg @ref LL_DMAMUX1_REQ_USART2_RX 1328 * @arg @ref LL_DMAMUX1_REQ_USART2_TX 1329 * @arg @ref LL_DMAMUX1_REQ_USART3_RX 1330 * @arg @ref LL_DMAMUX1_REQ_USART3_TX 1331 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 1332 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 1333 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 1334 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 1335 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP 1336 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG 1337 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM 1338 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 1339 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 1340 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 1341 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 1342 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP 1343 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG 1344 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX 1345 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX 1346 * @arg @ref LL_DMAMUX1_REQ_UART4_RX 1347 * @arg @ref LL_DMAMUX1_REQ_UART4_TX 1348 * @arg @ref LL_DMAMUX1_REQ_UART5_RX 1349 * @arg @ref LL_DMAMUX1_REQ_UART5_TX 1350 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 1351 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 1352 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP 1353 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP 1354 * @arg @ref LL_DMAMUX1_REQ_USART6_RX 1355 * @arg @ref LL_DMAMUX1_REQ_USART6_TX 1356 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX 1357 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX 1358 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) 1359 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN 1360 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT 1361 * @arg @ref LL_DMAMUX1_REQ_HASH_IN 1362 * @arg @ref LL_DMAMUX1_REQ_UART7_RX 1363 * @arg @ref LL_DMAMUX1_REQ_UART7_TX 1364 * @arg @ref LL_DMAMUX1_REQ_UART8_RX 1365 * @arg @ref LL_DMAMUX1_REQ_UART8_TX 1366 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX 1367 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX 1368 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX 1369 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX 1370 * @arg @ref LL_DMAMUX1_REQ_SAI1_A 1371 * @arg @ref LL_DMAMUX1_REQ_SAI1_B 1372 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) 1373 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) 1374 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX 1375 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX 1376 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT 1377 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS 1378 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) 1379 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) 1380 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) 1381 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) 1382 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) 1383 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) 1384 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 1385 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 1386 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 1387 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 1388 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 1389 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP 1390 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG 1391 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM 1392 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 1393 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP 1394 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 1395 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP 1396 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) 1397 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) 1398 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) 1399 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) 1400 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) 1401 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) 1402 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) 1403 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) 1404 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) 1405 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) 1406 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) 1407 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) 1408 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) 1409 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) 1410 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) 1411 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) 1412 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) 1413 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) 1414 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) 1415 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) 1416 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) 1417 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) 1418 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) 1419 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) 1420 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) 1421 * 1422 * @note (*) Availability depends on devices. 1423 */ 1424 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) 1425 { 1426 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); 1427 } 1428 1429 /** 1430 * @brief Set Memory burst transfer configuration. 1431 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 1432 * @param DMAx DMAx Instance 1433 * @param Stream This parameter can be one of the following values: 1434 * @arg @ref LL_DMA_STREAM_0 1435 * @arg @ref LL_DMA_STREAM_1 1436 * @arg @ref LL_DMA_STREAM_2 1437 * @arg @ref LL_DMA_STREAM_3 1438 * @arg @ref LL_DMA_STREAM_4 1439 * @arg @ref LL_DMA_STREAM_5 1440 * @arg @ref LL_DMA_STREAM_6 1441 * @arg @ref LL_DMA_STREAM_7 1442 * @param Mburst This parameter can be one of the following values: 1443 * @arg @ref LL_DMA_MBURST_SINGLE 1444 * @arg @ref LL_DMA_MBURST_INC4 1445 * @arg @ref LL_DMA_MBURST_INC8 1446 * @arg @ref LL_DMA_MBURST_INC16 1447 * @retval None 1448 */ 1449 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 1450 { 1451 uint32_t dma_base_addr = (uint32_t)DMAx; 1452 1453 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); 1454 } 1455 1456 /** 1457 * @brief Get Memory burst transfer configuration. 1458 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 1459 * @param DMAx DMAx Instance 1460 * @param Stream This parameter can be one of the following values: 1461 * @arg @ref LL_DMA_STREAM_0 1462 * @arg @ref LL_DMA_STREAM_1 1463 * @arg @ref LL_DMA_STREAM_2 1464 * @arg @ref LL_DMA_STREAM_3 1465 * @arg @ref LL_DMA_STREAM_4 1466 * @arg @ref LL_DMA_STREAM_5 1467 * @arg @ref LL_DMA_STREAM_6 1468 * @arg @ref LL_DMA_STREAM_7 1469 * @retval Returned value can be one of the following values: 1470 * @arg @ref LL_DMA_MBURST_SINGLE 1471 * @arg @ref LL_DMA_MBURST_INC4 1472 * @arg @ref LL_DMA_MBURST_INC8 1473 * @arg @ref LL_DMA_MBURST_INC16 1474 */ 1475 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1476 { 1477 uint32_t dma_base_addr = (uint32_t)DMAx; 1478 1479 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); 1480 } 1481 1482 /** 1483 * @brief Set Peripheral burst transfer configuration. 1484 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 1485 * @param DMAx DMAx Instance 1486 * @param Stream This parameter can be one of the following values: 1487 * @arg @ref LL_DMA_STREAM_0 1488 * @arg @ref LL_DMA_STREAM_1 1489 * @arg @ref LL_DMA_STREAM_2 1490 * @arg @ref LL_DMA_STREAM_3 1491 * @arg @ref LL_DMA_STREAM_4 1492 * @arg @ref LL_DMA_STREAM_5 1493 * @arg @ref LL_DMA_STREAM_6 1494 * @arg @ref LL_DMA_STREAM_7 1495 * @param Pburst This parameter can be one of the following values: 1496 * @arg @ref LL_DMA_PBURST_SINGLE 1497 * @arg @ref LL_DMA_PBURST_INC4 1498 * @arg @ref LL_DMA_PBURST_INC8 1499 * @arg @ref LL_DMA_PBURST_INC16 1500 * @retval None 1501 */ 1502 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 1503 { 1504 uint32_t dma_base_addr = (uint32_t)DMAx; 1505 1506 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); 1507 } 1508 1509 /** 1510 * @brief Get Peripheral burst transfer configuration. 1511 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 1512 * @param DMAx DMAx Instance 1513 * @param Stream This parameter can be one of the following values: 1514 * @arg @ref LL_DMA_STREAM_0 1515 * @arg @ref LL_DMA_STREAM_1 1516 * @arg @ref LL_DMA_STREAM_2 1517 * @arg @ref LL_DMA_STREAM_3 1518 * @arg @ref LL_DMA_STREAM_4 1519 * @arg @ref LL_DMA_STREAM_5 1520 * @arg @ref LL_DMA_STREAM_6 1521 * @arg @ref LL_DMA_STREAM_7 1522 * @retval Returned value can be one of the following values: 1523 * @arg @ref LL_DMA_PBURST_SINGLE 1524 * @arg @ref LL_DMA_PBURST_INC4 1525 * @arg @ref LL_DMA_PBURST_INC8 1526 * @arg @ref LL_DMA_PBURST_INC16 1527 */ 1528 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 1529 { 1530 uint32_t dma_base_addr = (uint32_t)DMAx; 1531 1532 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); 1533 } 1534 1535 /** 1536 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1537 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 1538 * @param DMAx DMAx Instance 1539 * @param Stream This parameter can be one of the following values: 1540 * @arg @ref LL_DMA_STREAM_0 1541 * @arg @ref LL_DMA_STREAM_1 1542 * @arg @ref LL_DMA_STREAM_2 1543 * @arg @ref LL_DMA_STREAM_3 1544 * @arg @ref LL_DMA_STREAM_4 1545 * @arg @ref LL_DMA_STREAM_5 1546 * @arg @ref LL_DMA_STREAM_6 1547 * @arg @ref LL_DMA_STREAM_7 1548 * @param CurrentMemory This parameter can be one of the following values: 1549 * @arg @ref LL_DMA_CURRENTTARGETMEM0 1550 * @arg @ref LL_DMA_CURRENTTARGETMEM1 1551 * @retval None 1552 */ 1553 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) 1554 { 1555 uint32_t dma_base_addr = (uint32_t)DMAx; 1556 1557 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); 1558 } 1559 1560 /** 1561 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1562 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 1563 * @param DMAx DMAx Instance 1564 * @param Stream This parameter can be one of the following values: 1565 * @arg @ref LL_DMA_STREAM_0 1566 * @arg @ref LL_DMA_STREAM_1 1567 * @arg @ref LL_DMA_STREAM_2 1568 * @arg @ref LL_DMA_STREAM_3 1569 * @arg @ref LL_DMA_STREAM_4 1570 * @arg @ref LL_DMA_STREAM_5 1571 * @arg @ref LL_DMA_STREAM_6 1572 * @arg @ref LL_DMA_STREAM_7 1573 * @retval Returned value can be one of the following values: 1574 * @arg @ref LL_DMA_CURRENTTARGETMEM0 1575 * @arg @ref LL_DMA_CURRENTTARGETMEM1 1576 */ 1577 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 1578 { 1579 uint32_t dma_base_addr = (uint32_t)DMAx; 1580 1581 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); 1582 } 1583 1584 /** 1585 * @brief Enable the double buffer mode. 1586 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 1587 * @param DMAx DMAx Instance 1588 * @param Stream This parameter can be one of the following values: 1589 * @arg @ref LL_DMA_STREAM_0 1590 * @arg @ref LL_DMA_STREAM_1 1591 * @arg @ref LL_DMA_STREAM_2 1592 * @arg @ref LL_DMA_STREAM_3 1593 * @arg @ref LL_DMA_STREAM_4 1594 * @arg @ref LL_DMA_STREAM_5 1595 * @arg @ref LL_DMA_STREAM_6 1596 * @arg @ref LL_DMA_STREAM_7 1597 * @retval None 1598 */ 1599 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1600 { 1601 uint32_t dma_base_addr = (uint32_t)DMAx; 1602 1603 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); 1604 } 1605 1606 /** 1607 * @brief Disable the double buffer mode. 1608 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 1609 * @param DMAx DMAx Instance 1610 * @param Stream This parameter can be one of the following values: 1611 * @arg @ref LL_DMA_STREAM_0 1612 * @arg @ref LL_DMA_STREAM_1 1613 * @arg @ref LL_DMA_STREAM_2 1614 * @arg @ref LL_DMA_STREAM_3 1615 * @arg @ref LL_DMA_STREAM_4 1616 * @arg @ref LL_DMA_STREAM_5 1617 * @arg @ref LL_DMA_STREAM_6 1618 * @arg @ref LL_DMA_STREAM_7 1619 * @retval None 1620 */ 1621 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1622 { 1623 uint32_t dma_base_addr = (uint32_t)DMAx; 1624 1625 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); 1626 } 1627 1628 /** 1629 * @brief Check if double buffer mode is enabled or not. 1630 * @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode 1631 * @param DMAx DMAx Instance 1632 * @param Stream This parameter can be one of the following values: 1633 * @arg @ref LL_DMA_STREAM_0 1634 * @arg @ref LL_DMA_STREAM_1 1635 * @arg @ref LL_DMA_STREAM_2 1636 * @arg @ref LL_DMA_STREAM_3 1637 * @arg @ref LL_DMA_STREAM_4 1638 * @arg @ref LL_DMA_STREAM_5 1639 * @arg @ref LL_DMA_STREAM_6 1640 * @arg @ref LL_DMA_STREAM_7 1641 * @retval State of bit (1 or 0). 1642 */ 1643 __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 1644 { 1645 register uint32_t dma_base_addr = (uint32_t)DMAx; 1646 1647 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); 1648 } 1649 1650 /** 1651 * @brief Get FIFO status. 1652 * @rmtoll FCR FS LL_DMA_GetFIFOStatus 1653 * @param DMAx DMAx Instance 1654 * @param Stream This parameter can be one of the following values: 1655 * @arg @ref LL_DMA_STREAM_0 1656 * @arg @ref LL_DMA_STREAM_1 1657 * @arg @ref LL_DMA_STREAM_2 1658 * @arg @ref LL_DMA_STREAM_3 1659 * @arg @ref LL_DMA_STREAM_4 1660 * @arg @ref LL_DMA_STREAM_5 1661 * @arg @ref LL_DMA_STREAM_6 1662 * @arg @ref LL_DMA_STREAM_7 1663 * @retval Returned value can be one of the following values: 1664 * @arg @ref LL_DMA_FIFOSTATUS_0_25 1665 * @arg @ref LL_DMA_FIFOSTATUS_25_50 1666 * @arg @ref LL_DMA_FIFOSTATUS_50_75 1667 * @arg @ref LL_DMA_FIFOSTATUS_75_100 1668 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 1669 * @arg @ref LL_DMA_FIFOSTATUS_FULL 1670 */ 1671 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 1672 { 1673 uint32_t dma_base_addr = (uint32_t)DMAx; 1674 1675 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); 1676 } 1677 1678 /** 1679 * @brief Disable Fifo mode. 1680 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 1681 * @param DMAx DMAx Instance 1682 * @param Stream This parameter can be one of the following values: 1683 * @arg @ref LL_DMA_STREAM_0 1684 * @arg @ref LL_DMA_STREAM_1 1685 * @arg @ref LL_DMA_STREAM_2 1686 * @arg @ref LL_DMA_STREAM_3 1687 * @arg @ref LL_DMA_STREAM_4 1688 * @arg @ref LL_DMA_STREAM_5 1689 * @arg @ref LL_DMA_STREAM_6 1690 * @arg @ref LL_DMA_STREAM_7 1691 * @retval None 1692 */ 1693 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1694 { 1695 uint32_t dma_base_addr = (uint32_t)DMAx; 1696 1697 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); 1698 } 1699 1700 /** 1701 * @brief Enable Fifo mode. 1702 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 1703 * @param DMAx DMAx Instance 1704 * @param Stream This parameter can be one of the following values: 1705 * @arg @ref LL_DMA_STREAM_0 1706 * @arg @ref LL_DMA_STREAM_1 1707 * @arg @ref LL_DMA_STREAM_2 1708 * @arg @ref LL_DMA_STREAM_3 1709 * @arg @ref LL_DMA_STREAM_4 1710 * @arg @ref LL_DMA_STREAM_5 1711 * @arg @ref LL_DMA_STREAM_6 1712 * @arg @ref LL_DMA_STREAM_7 1713 * @retval None 1714 */ 1715 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 1716 { 1717 uint32_t dma_base_addr = (uint32_t)DMAx; 1718 1719 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); 1720 } 1721 1722 /** 1723 * @brief Select FIFO threshold. 1724 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 1725 * @param DMAx DMAx Instance 1726 * @param Stream This parameter can be one of the following values: 1727 * @arg @ref LL_DMA_STREAM_0 1728 * @arg @ref LL_DMA_STREAM_1 1729 * @arg @ref LL_DMA_STREAM_2 1730 * @arg @ref LL_DMA_STREAM_3 1731 * @arg @ref LL_DMA_STREAM_4 1732 * @arg @ref LL_DMA_STREAM_5 1733 * @arg @ref LL_DMA_STREAM_6 1734 * @arg @ref LL_DMA_STREAM_7 1735 * @param Threshold This parameter can be one of the following values: 1736 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1737 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1738 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1739 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1740 * @retval None 1741 */ 1742 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) 1743 { 1744 uint32_t dma_base_addr = (uint32_t)DMAx; 1745 1746 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); 1747 } 1748 1749 /** 1750 * @brief Get FIFO threshold. 1751 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 1752 * @param DMAx DMAx Instance 1753 * @param Stream This parameter can be one of the following values: 1754 * @arg @ref LL_DMA_STREAM_0 1755 * @arg @ref LL_DMA_STREAM_1 1756 * @arg @ref LL_DMA_STREAM_2 1757 * @arg @ref LL_DMA_STREAM_3 1758 * @arg @ref LL_DMA_STREAM_4 1759 * @arg @ref LL_DMA_STREAM_5 1760 * @arg @ref LL_DMA_STREAM_6 1761 * @arg @ref LL_DMA_STREAM_7 1762 * @retval Returned value can be one of the following values: 1763 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1764 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1765 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1766 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1767 */ 1768 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 1769 { 1770 uint32_t dma_base_addr = (uint32_t)DMAx; 1771 1772 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); 1773 } 1774 1775 /** 1776 * @brief Configure the FIFO . 1777 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 1778 * FCR DMDIS LL_DMA_ConfigFifo 1779 * @param DMAx DMAx Instance 1780 * @param Stream This parameter can be one of the following values: 1781 * @arg @ref LL_DMA_STREAM_0 1782 * @arg @ref LL_DMA_STREAM_1 1783 * @arg @ref LL_DMA_STREAM_2 1784 * @arg @ref LL_DMA_STREAM_3 1785 * @arg @ref LL_DMA_STREAM_4 1786 * @arg @ref LL_DMA_STREAM_5 1787 * @arg @ref LL_DMA_STREAM_6 1788 * @arg @ref LL_DMA_STREAM_7 1789 * @param FifoMode This parameter can be one of the following values: 1790 * @arg @ref LL_DMA_FIFOMODE_ENABLE 1791 * @arg @ref LL_DMA_FIFOMODE_DISABLE 1792 * @param FifoThreshold This parameter can be one of the following values: 1793 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 1794 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 1795 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 1796 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 1797 * @retval None 1798 */ 1799 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) 1800 { 1801 uint32_t dma_base_addr = (uint32_t)DMAx; 1802 1803 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); 1804 } 1805 1806 /** 1807 * @brief Configure the Source and Destination addresses. 1808 * @note This API must not be called when the DMA stream is enabled. 1809 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 1810 * PAR PA LL_DMA_ConfigAddresses 1811 * @param DMAx DMAx Instance 1812 * @param Stream This parameter can be one of the following values: 1813 * @arg @ref LL_DMA_STREAM_0 1814 * @arg @ref LL_DMA_STREAM_1 1815 * @arg @ref LL_DMA_STREAM_2 1816 * @arg @ref LL_DMA_STREAM_3 1817 * @arg @ref LL_DMA_STREAM_4 1818 * @arg @ref LL_DMA_STREAM_5 1819 * @arg @ref LL_DMA_STREAM_6 1820 * @arg @ref LL_DMA_STREAM_7 1821 * @param SrcAddress Between 0 to 0xFFFFFFFF 1822 * @param DstAddress Between 0 to 0xFFFFFFFF 1823 * @param Direction This parameter can be one of the following values: 1824 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 1825 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 1826 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 1827 * @retval None 1828 */ 1829 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 1830 { 1831 uint32_t dma_base_addr = (uint32_t)DMAx; 1832 1833 /* Direction Memory to Periph */ 1834 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 1835 { 1836 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress); 1837 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress); 1838 } 1839 /* Direction Periph to Memory and Memory to Memory */ 1840 else 1841 { 1842 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress); 1843 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress); 1844 } 1845 } 1846 1847 /** 1848 * @brief Set the Memory address. 1849 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 1850 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1851 * @note This API must not be called when the DMA stream is enabled. 1852 * @param DMAx DMAx Instance 1853 * @param Stream This parameter can be one of the following values: 1854 * @arg @ref LL_DMA_STREAM_0 1855 * @arg @ref LL_DMA_STREAM_1 1856 * @arg @ref LL_DMA_STREAM_2 1857 * @arg @ref LL_DMA_STREAM_3 1858 * @arg @ref LL_DMA_STREAM_4 1859 * @arg @ref LL_DMA_STREAM_5 1860 * @arg @ref LL_DMA_STREAM_6 1861 * @arg @ref LL_DMA_STREAM_7 1862 * @param MemoryAddress Between 0 to 0xFFFFFFFF 1863 * @retval None 1864 */ 1865 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 1866 { 1867 uint32_t dma_base_addr = (uint32_t)DMAx; 1868 1869 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); 1870 } 1871 1872 /** 1873 * @brief Set the Peripheral address. 1874 * @rmtoll PAR PA LL_DMA_SetPeriphAddress 1875 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1876 * @note This API must not be called when the DMA stream is enabled. 1877 * @param DMAx DMAx Instance 1878 * @param Stream This parameter can be one of the following values: 1879 * @arg @ref LL_DMA_STREAM_0 1880 * @arg @ref LL_DMA_STREAM_1 1881 * @arg @ref LL_DMA_STREAM_2 1882 * @arg @ref LL_DMA_STREAM_3 1883 * @arg @ref LL_DMA_STREAM_4 1884 * @arg @ref LL_DMA_STREAM_5 1885 * @arg @ref LL_DMA_STREAM_6 1886 * @arg @ref LL_DMA_STREAM_7 1887 * @param PeriphAddress Between 0 to 0xFFFFFFFF 1888 * @retval None 1889 */ 1890 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) 1891 { 1892 uint32_t dma_base_addr = (uint32_t)DMAx; 1893 1894 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); 1895 } 1896 1897 /** 1898 * @brief Get the Memory address. 1899 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 1900 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1901 * @param DMAx DMAx Instance 1902 * @param Stream This parameter can be one of the following values: 1903 * @arg @ref LL_DMA_STREAM_0 1904 * @arg @ref LL_DMA_STREAM_1 1905 * @arg @ref LL_DMA_STREAM_2 1906 * @arg @ref LL_DMA_STREAM_3 1907 * @arg @ref LL_DMA_STREAM_4 1908 * @arg @ref LL_DMA_STREAM_5 1909 * @arg @ref LL_DMA_STREAM_6 1910 * @arg @ref LL_DMA_STREAM_7 1911 * @retval Between 0 to 0xFFFFFFFF 1912 */ 1913 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) 1914 { 1915 uint32_t dma_base_addr = (uint32_t)DMAx; 1916 1917 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); 1918 } 1919 1920 /** 1921 * @brief Get the Peripheral address. 1922 * @rmtoll PAR PA LL_DMA_GetPeriphAddress 1923 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1924 * @param DMAx DMAx Instance 1925 * @param Stream This parameter can be one of the following values: 1926 * @arg @ref LL_DMA_STREAM_0 1927 * @arg @ref LL_DMA_STREAM_1 1928 * @arg @ref LL_DMA_STREAM_2 1929 * @arg @ref LL_DMA_STREAM_3 1930 * @arg @ref LL_DMA_STREAM_4 1931 * @arg @ref LL_DMA_STREAM_5 1932 * @arg @ref LL_DMA_STREAM_6 1933 * @arg @ref LL_DMA_STREAM_7 1934 * @retval Between 0 to 0xFFFFFFFF 1935 */ 1936 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) 1937 { 1938 uint32_t dma_base_addr = (uint32_t)DMAx; 1939 1940 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); 1941 } 1942 1943 /** 1944 * @brief Set the Memory to Memory Source address. 1945 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 1946 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1947 * @note This API must not be called when the DMA stream is enabled. 1948 * @param DMAx DMAx Instance 1949 * @param Stream This parameter can be one of the following values: 1950 * @arg @ref LL_DMA_STREAM_0 1951 * @arg @ref LL_DMA_STREAM_1 1952 * @arg @ref LL_DMA_STREAM_2 1953 * @arg @ref LL_DMA_STREAM_3 1954 * @arg @ref LL_DMA_STREAM_4 1955 * @arg @ref LL_DMA_STREAM_5 1956 * @arg @ref LL_DMA_STREAM_6 1957 * @arg @ref LL_DMA_STREAM_7 1958 * @param MemoryAddress Between 0 to 0xFFFFFFFF 1959 * @retval None 1960 */ 1961 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 1962 { 1963 uint32_t dma_base_addr = (uint32_t)DMAx; 1964 1965 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); 1966 } 1967 1968 /** 1969 * @brief Set the Memory to Memory Destination address. 1970 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 1971 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1972 * @note This API must not be called when the DMA stream is enabled. 1973 * @param DMAx DMAx Instance 1974 * @param Stream This parameter can be one of the following values: 1975 * @arg @ref LL_DMA_STREAM_0 1976 * @arg @ref LL_DMA_STREAM_1 1977 * @arg @ref LL_DMA_STREAM_2 1978 * @arg @ref LL_DMA_STREAM_3 1979 * @arg @ref LL_DMA_STREAM_4 1980 * @arg @ref LL_DMA_STREAM_5 1981 * @arg @ref LL_DMA_STREAM_6 1982 * @arg @ref LL_DMA_STREAM_7 1983 * @param MemoryAddress Between 0 to 0xFFFFFFFF 1984 * @retval None 1985 */ 1986 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 1987 { 1988 uint32_t dma_base_addr = (uint32_t)DMAx; 1989 1990 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); 1991 } 1992 1993 /** 1994 * @brief Get the Memory to Memory Source address. 1995 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 1996 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1997 * @param DMAx DMAx Instance 1998 * @param Stream This parameter can be one of the following values: 1999 * @arg @ref LL_DMA_STREAM_0 2000 * @arg @ref LL_DMA_STREAM_1 2001 * @arg @ref LL_DMA_STREAM_2 2002 * @arg @ref LL_DMA_STREAM_3 2003 * @arg @ref LL_DMA_STREAM_4 2004 * @arg @ref LL_DMA_STREAM_5 2005 * @arg @ref LL_DMA_STREAM_6 2006 * @arg @ref LL_DMA_STREAM_7 2007 * @retval Between 0 to 0xFFFFFFFF 2008 */ 2009 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) 2010 { 2011 uint32_t dma_base_addr = (uint32_t)DMAx; 2012 2013 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); 2014 } 2015 2016 /** 2017 * @brief Get the Memory to Memory Destination address. 2018 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 2019 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 2020 * @param DMAx DMAx Instance 2021 * @param Stream This parameter can be one of the following values: 2022 * @arg @ref LL_DMA_STREAM_0 2023 * @arg @ref LL_DMA_STREAM_1 2024 * @arg @ref LL_DMA_STREAM_2 2025 * @arg @ref LL_DMA_STREAM_3 2026 * @arg @ref LL_DMA_STREAM_4 2027 * @arg @ref LL_DMA_STREAM_5 2028 * @arg @ref LL_DMA_STREAM_6 2029 * @arg @ref LL_DMA_STREAM_7 2030 * @retval Between 0 to 0xFFFFFFFF 2031 */ 2032 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) 2033 { 2034 uint32_t dma_base_addr = (uint32_t)DMAx; 2035 2036 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); 2037 } 2038 2039 /** 2040 * @brief Set Memory 1 address (used in case of Double buffer mode). 2041 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 2042 * @param DMAx DMAx Instance 2043 * @param Stream This parameter can be one of the following values: 2044 * @arg @ref LL_DMA_STREAM_0 2045 * @arg @ref LL_DMA_STREAM_1 2046 * @arg @ref LL_DMA_STREAM_2 2047 * @arg @ref LL_DMA_STREAM_3 2048 * @arg @ref LL_DMA_STREAM_4 2049 * @arg @ref LL_DMA_STREAM_5 2050 * @arg @ref LL_DMA_STREAM_6 2051 * @arg @ref LL_DMA_STREAM_7 2052 * @param Address Between 0 to 0xFFFFFFFF 2053 * @retval None 2054 */ 2055 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 2056 { 2057 uint32_t dma_base_addr = (uint32_t)DMAx; 2058 2059 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); 2060 } 2061 2062 /** 2063 * @brief Get Memory 1 address (used in case of Double buffer mode). 2064 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 2065 * @param DMAx DMAx Instance 2066 * @param Stream This parameter can be one of the following values: 2067 * @arg @ref LL_DMA_STREAM_0 2068 * @arg @ref LL_DMA_STREAM_1 2069 * @arg @ref LL_DMA_STREAM_2 2070 * @arg @ref LL_DMA_STREAM_3 2071 * @arg @ref LL_DMA_STREAM_4 2072 * @arg @ref LL_DMA_STREAM_5 2073 * @arg @ref LL_DMA_STREAM_6 2074 * @arg @ref LL_DMA_STREAM_7 2075 * @retval Between 0 to 0xFFFFFFFF 2076 */ 2077 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 2078 { 2079 uint32_t dma_base_addr = (uint32_t)DMAx; 2080 2081 return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); 2082 } 2083 2084 /** 2085 * @} 2086 */ 2087 2088 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 2089 * @ingroup RTEMSBSPsARMSTM32H7 2090 * @{ 2091 */ 2092 2093 /** 2094 * @brief Get Stream 0 half transfer flag. 2095 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 2096 * @param DMAx DMAx Instance 2097 * @retval State of bit (1 or 0). 2098 */ 2099 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 2100 { 2101 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); 2102 } 2103 2104 /** 2105 * @brief Get Stream 1 half transfer flag. 2106 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 2107 * @param DMAx DMAx Instance 2108 * @retval State of bit (1 or 0). 2109 */ 2110 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 2111 { 2112 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); 2113 } 2114 2115 /** 2116 * @brief Get Stream 2 half transfer flag. 2117 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 2118 * @param DMAx DMAx Instance 2119 * @retval State of bit (1 or 0). 2120 */ 2121 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 2122 { 2123 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); 2124 } 2125 2126 /** 2127 * @brief Get Stream 3 half transfer flag. 2128 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 2129 * @param DMAx DMAx Instance 2130 * @retval State of bit (1 or 0). 2131 */ 2132 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 2133 { 2134 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); 2135 } 2136 2137 /** 2138 * @brief Get Stream 4 half transfer flag. 2139 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 2140 * @param DMAx DMAx Instance 2141 * @retval State of bit (1 or 0). 2142 */ 2143 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 2144 { 2145 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); 2146 } 2147 2148 /** 2149 * @brief Get Stream 5 half transfer flag. 2150 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 2151 * @param DMAx DMAx Instance 2152 * @retval State of bit (1 or 0). 2153 */ 2154 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 2155 { 2156 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); 2157 } 2158 2159 /** 2160 * @brief Get Stream 6 half transfer flag. 2161 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 2162 * @param DMAx DMAx Instance 2163 * @retval State of bit (1 or 0). 2164 */ 2165 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 2166 { 2167 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); 2168 } 2169 2170 /** 2171 * @brief Get Stream 7 half transfer flag. 2172 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 2173 * @param DMAx DMAx Instance 2174 * @retval State of bit (1 or 0). 2175 */ 2176 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 2177 { 2178 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); 2179 } 2180 2181 /** 2182 * @brief Get Stream 0 transfer complete flag. 2183 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 2184 * @param DMAx DMAx Instance 2185 * @retval State of bit (1 or 0). 2186 */ 2187 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 2188 { 2189 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); 2190 } 2191 2192 /** 2193 * @brief Get Stream 1 transfer complete flag. 2194 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 2195 * @param DMAx DMAx Instance 2196 * @retval State of bit (1 or 0). 2197 */ 2198 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 2199 { 2200 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); 2201 } 2202 2203 /** 2204 * @brief Get Stream 2 transfer complete flag. 2205 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 2206 * @param DMAx DMAx Instance 2207 * @retval State of bit (1 or 0). 2208 */ 2209 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 2210 { 2211 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); 2212 } 2213 2214 /** 2215 * @brief Get Stream 3 transfer complete flag. 2216 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 2217 * @param DMAx DMAx Instance 2218 * @retval State of bit (1 or 0). 2219 */ 2220 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 2221 { 2222 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); 2223 } 2224 2225 /** 2226 * @brief Get Stream 4 transfer complete flag. 2227 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 2228 * @param DMAx DMAx Instance 2229 * @retval State of bit (1 or 0). 2230 */ 2231 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 2232 { 2233 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); 2234 } 2235 2236 /** 2237 * @brief Get Stream 5 transfer complete flag. 2238 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 2239 * @param DMAx DMAx Instance 2240 * @retval State of bit (1 or 0). 2241 */ 2242 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 2243 { 2244 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); 2245 } 2246 2247 /** 2248 * @brief Get Stream 6 transfer complete flag. 2249 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 2250 * @param DMAx DMAx Instance 2251 * @retval State of bit (1 or 0). 2252 */ 2253 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 2254 { 2255 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); 2256 } 2257 2258 /** 2259 * @brief Get Stream 7 transfer complete flag. 2260 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 2261 * @param DMAx DMAx Instance 2262 * @retval State of bit (1 or 0). 2263 */ 2264 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 2265 { 2266 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); 2267 } 2268 2269 /** 2270 * @brief Get Stream 0 transfer error flag. 2271 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 2272 * @param DMAx DMAx Instance 2273 * @retval State of bit (1 or 0). 2274 */ 2275 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 2276 { 2277 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); 2278 } 2279 2280 /** 2281 * @brief Get Stream 1 transfer error flag. 2282 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 2283 * @param DMAx DMAx Instance 2284 * @retval State of bit (1 or 0). 2285 */ 2286 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 2287 { 2288 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); 2289 } 2290 2291 /** 2292 * @brief Get Stream 2 transfer error flag. 2293 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 2294 * @param DMAx DMAx Instance 2295 * @retval State of bit (1 or 0). 2296 */ 2297 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 2298 { 2299 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); 2300 } 2301 2302 /** 2303 * @brief Get Stream 3 transfer error flag. 2304 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 2305 * @param DMAx DMAx Instance 2306 * @retval State of bit (1 or 0). 2307 */ 2308 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 2309 { 2310 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); 2311 } 2312 2313 /** 2314 * @brief Get Stream 4 transfer error flag. 2315 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 2316 * @param DMAx DMAx Instance 2317 * @retval State of bit (1 or 0). 2318 */ 2319 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 2320 { 2321 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); 2322 } 2323 2324 /** 2325 * @brief Get Stream 5 transfer error flag. 2326 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 2327 * @param DMAx DMAx Instance 2328 * @retval State of bit (1 or 0). 2329 */ 2330 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 2331 { 2332 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); 2333 } 2334 2335 /** 2336 * @brief Get Stream 6 transfer error flag. 2337 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 2338 * @param DMAx DMAx Instance 2339 * @retval State of bit (1 or 0). 2340 */ 2341 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 2342 { 2343 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); 2344 } 2345 2346 /** 2347 * @brief Get Stream 7 transfer error flag. 2348 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 2349 * @param DMAx DMAx Instance 2350 * @retval State of bit (1 or 0). 2351 */ 2352 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 2353 { 2354 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); 2355 } 2356 2357 /** 2358 * @brief Get Stream 0 direct mode error flag. 2359 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 2360 * @param DMAx DMAx Instance 2361 * @retval State of bit (1 or 0). 2362 */ 2363 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 2364 { 2365 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); 2366 } 2367 2368 /** 2369 * @brief Get Stream 1 direct mode error flag. 2370 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 2371 * @param DMAx DMAx Instance 2372 * @retval State of bit (1 or 0). 2373 */ 2374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 2375 { 2376 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); 2377 } 2378 2379 /** 2380 * @brief Get Stream 2 direct mode error flag. 2381 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 2382 * @param DMAx DMAx Instance 2383 * @retval State of bit (1 or 0). 2384 */ 2385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 2386 { 2387 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); 2388 } 2389 2390 /** 2391 * @brief Get Stream 3 direct mode error flag. 2392 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 2393 * @param DMAx DMAx Instance 2394 * @retval State of bit (1 or 0). 2395 */ 2396 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 2397 { 2398 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); 2399 } 2400 2401 /** 2402 * @brief Get Stream 4 direct mode error flag. 2403 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 2404 * @param DMAx DMAx Instance 2405 * @retval State of bit (1 or 0). 2406 */ 2407 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 2408 { 2409 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); 2410 } 2411 2412 /** 2413 * @brief Get Stream 5 direct mode error flag. 2414 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 2415 * @param DMAx DMAx Instance 2416 * @retval State of bit (1 or 0). 2417 */ 2418 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 2419 { 2420 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); 2421 } 2422 2423 /** 2424 * @brief Get Stream 6 direct mode error flag. 2425 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 2426 * @param DMAx DMAx Instance 2427 * @retval State of bit (1 or 0). 2428 */ 2429 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 2430 { 2431 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); 2432 } 2433 2434 /** 2435 * @brief Get Stream 7 direct mode error flag. 2436 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 2437 * @param DMAx DMAx Instance 2438 * @retval State of bit (1 or 0). 2439 */ 2440 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 2441 { 2442 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); 2443 } 2444 2445 /** 2446 * @brief Get Stream 0 FIFO error flag. 2447 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 2448 * @param DMAx DMAx Instance 2449 * @retval State of bit (1 or 0). 2450 */ 2451 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 2452 { 2453 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); 2454 } 2455 2456 /** 2457 * @brief Get Stream 1 FIFO error flag. 2458 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 2459 * @param DMAx DMAx Instance 2460 * @retval State of bit (1 or 0). 2461 */ 2462 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 2463 { 2464 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); 2465 } 2466 2467 /** 2468 * @brief Get Stream 2 FIFO error flag. 2469 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 2470 * @param DMAx DMAx Instance 2471 * @retval State of bit (1 or 0). 2472 */ 2473 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 2474 { 2475 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); 2476 } 2477 2478 /** 2479 * @brief Get Stream 3 FIFO error flag. 2480 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 2481 * @param DMAx DMAx Instance 2482 * @retval State of bit (1 or 0). 2483 */ 2484 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 2485 { 2486 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); 2487 } 2488 2489 /** 2490 * @brief Get Stream 4 FIFO error flag. 2491 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 2492 * @param DMAx DMAx Instance 2493 * @retval State of bit (1 or 0). 2494 */ 2495 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 2496 { 2497 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); 2498 } 2499 2500 /** 2501 * @brief Get Stream 5 FIFO error flag. 2502 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 2503 * @param DMAx DMAx Instance 2504 * @retval State of bit (1 or 0). 2505 */ 2506 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 2507 { 2508 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); 2509 } 2510 2511 /** 2512 * @brief Get Stream 6 FIFO error flag. 2513 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 2514 * @param DMAx DMAx Instance 2515 * @retval State of bit (1 or 0). 2516 */ 2517 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 2518 { 2519 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); 2520 } 2521 2522 /** 2523 * @brief Get Stream 7 FIFO error flag. 2524 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 2525 * @param DMAx DMAx Instance 2526 * @retval State of bit (1 or 0). 2527 */ 2528 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 2529 { 2530 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); 2531 } 2532 2533 /** 2534 * @brief Clear Stream 0 half transfer flag. 2535 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 2536 * @param DMAx DMAx Instance 2537 * @retval None 2538 */ 2539 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 2540 { 2541 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); 2542 } 2543 2544 /** 2545 * @brief Clear Stream 1 half transfer flag. 2546 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 2547 * @param DMAx DMAx Instance 2548 * @retval None 2549 */ 2550 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 2551 { 2552 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1); 2553 } 2554 2555 /** 2556 * @brief Clear Stream 2 half transfer flag. 2557 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 2558 * @param DMAx DMAx Instance 2559 * @retval None 2560 */ 2561 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 2562 { 2563 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2); 2564 } 2565 2566 /** 2567 * @brief Clear Stream 3 half transfer flag. 2568 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 2569 * @param DMAx DMAx Instance 2570 * @retval None 2571 */ 2572 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 2573 { 2574 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3); 2575 } 2576 2577 /** 2578 * @brief Clear Stream 4 half transfer flag. 2579 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 2580 * @param DMAx DMAx Instance 2581 * @retval None 2582 */ 2583 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 2584 { 2585 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4); 2586 } 2587 2588 /** 2589 * @brief Clear Stream 5 half transfer flag. 2590 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 2591 * @param DMAx DMAx Instance 2592 * @retval None 2593 */ 2594 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 2595 { 2596 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5); 2597 } 2598 2599 /** 2600 * @brief Clear Stream 6 half transfer flag. 2601 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 2602 * @param DMAx DMAx Instance 2603 * @retval None 2604 */ 2605 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 2606 { 2607 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6); 2608 } 2609 2610 /** 2611 * @brief Clear Stream 7 half transfer flag. 2612 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 2613 * @param DMAx DMAx Instance 2614 * @retval None 2615 */ 2616 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 2617 { 2618 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7); 2619 } 2620 2621 /** 2622 * @brief Clear Stream 0 transfer complete flag. 2623 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 2624 * @param DMAx DMAx Instance 2625 * @retval None 2626 */ 2627 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 2628 { 2629 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0); 2630 } 2631 2632 /** 2633 * @brief Clear Stream 1 transfer complete flag. 2634 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 2635 * @param DMAx DMAx Instance 2636 * @retval None 2637 */ 2638 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 2639 { 2640 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1); 2641 } 2642 2643 /** 2644 * @brief Clear Stream 2 transfer complete flag. 2645 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 2646 * @param DMAx DMAx Instance 2647 * @retval None 2648 */ 2649 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 2650 { 2651 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2); 2652 } 2653 2654 /** 2655 * @brief Clear Stream 3 transfer complete flag. 2656 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 2657 * @param DMAx DMAx Instance 2658 * @retval None 2659 */ 2660 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 2661 { 2662 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3); 2663 } 2664 2665 /** 2666 * @brief Clear Stream 4 transfer complete flag. 2667 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 2668 * @param DMAx DMAx Instance 2669 * @retval None 2670 */ 2671 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 2672 { 2673 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4); 2674 } 2675 2676 /** 2677 * @brief Clear Stream 5 transfer complete flag. 2678 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 2679 * @param DMAx DMAx Instance 2680 * @retval None 2681 */ 2682 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 2683 { 2684 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5); 2685 } 2686 2687 /** 2688 * @brief Clear Stream 6 transfer complete flag. 2689 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 2690 * @param DMAx DMAx Instance 2691 * @retval None 2692 */ 2693 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 2694 { 2695 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6); 2696 } 2697 2698 /** 2699 * @brief Clear Stream 7 transfer complete flag. 2700 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 2701 * @param DMAx DMAx Instance 2702 * @retval None 2703 */ 2704 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 2705 { 2706 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7); 2707 } 2708 2709 /** 2710 * @brief Clear Stream 0 transfer error flag. 2711 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 2712 * @param DMAx DMAx Instance 2713 * @retval None 2714 */ 2715 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 2716 { 2717 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0); 2718 } 2719 2720 /** 2721 * @brief Clear Stream 1 transfer error flag. 2722 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 2723 * @param DMAx DMAx Instance 2724 * @retval None 2725 */ 2726 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 2727 { 2728 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1); 2729 } 2730 2731 /** 2732 * @brief Clear Stream 2 transfer error flag. 2733 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 2734 * @param DMAx DMAx Instance 2735 * @retval None 2736 */ 2737 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 2738 { 2739 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2); 2740 } 2741 2742 /** 2743 * @brief Clear Stream 3 transfer error flag. 2744 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 2745 * @param DMAx DMAx Instance 2746 * @retval None 2747 */ 2748 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 2749 { 2750 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3); 2751 } 2752 2753 /** 2754 * @brief Clear Stream 4 transfer error flag. 2755 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 2756 * @param DMAx DMAx Instance 2757 * @retval None 2758 */ 2759 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 2760 { 2761 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4); 2762 } 2763 2764 /** 2765 * @brief Clear Stream 5 transfer error flag. 2766 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 2767 * @param DMAx DMAx Instance 2768 * @retval None 2769 */ 2770 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 2771 { 2772 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5); 2773 } 2774 2775 /** 2776 * @brief Clear Stream 6 transfer error flag. 2777 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 2778 * @param DMAx DMAx Instance 2779 * @retval None 2780 */ 2781 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 2782 { 2783 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6); 2784 } 2785 2786 /** 2787 * @brief Clear Stream 7 transfer error flag. 2788 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 2789 * @param DMAx DMAx Instance 2790 * @retval None 2791 */ 2792 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 2793 { 2794 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7); 2795 } 2796 2797 /** 2798 * @brief Clear Stream 0 direct mode error flag. 2799 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 2800 * @param DMAx DMAx Instance 2801 * @retval None 2802 */ 2803 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 2804 { 2805 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0); 2806 } 2807 2808 /** 2809 * @brief Clear Stream 1 direct mode error flag. 2810 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 2811 * @param DMAx DMAx Instance 2812 * @retval None 2813 */ 2814 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 2815 { 2816 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1); 2817 } 2818 2819 /** 2820 * @brief Clear Stream 2 direct mode error flag. 2821 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 2822 * @param DMAx DMAx Instance 2823 * @retval None 2824 */ 2825 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 2826 { 2827 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2); 2828 } 2829 2830 /** 2831 * @brief Clear Stream 3 direct mode error flag. 2832 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 2833 * @param DMAx DMAx Instance 2834 * @retval None 2835 */ 2836 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 2837 { 2838 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3); 2839 } 2840 2841 /** 2842 * @brief Clear Stream 4 direct mode error flag. 2843 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 2844 * @param DMAx DMAx Instance 2845 * @retval None 2846 */ 2847 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 2848 { 2849 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4); 2850 } 2851 2852 /** 2853 * @brief Clear Stream 5 direct mode error flag. 2854 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 2855 * @param DMAx DMAx Instance 2856 * @retval None 2857 */ 2858 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 2859 { 2860 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5); 2861 } 2862 2863 /** 2864 * @brief Clear Stream 6 direct mode error flag. 2865 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 2866 * @param DMAx DMAx Instance 2867 * @retval None 2868 */ 2869 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 2870 { 2871 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6); 2872 } 2873 2874 /** 2875 * @brief Clear Stream 7 direct mode error flag. 2876 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 2877 * @param DMAx DMAx Instance 2878 * @retval None 2879 */ 2880 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 2881 { 2882 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7); 2883 } 2884 2885 /** 2886 * @brief Clear Stream 0 FIFO error flag. 2887 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 2888 * @param DMAx DMAx Instance 2889 * @retval None 2890 */ 2891 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 2892 { 2893 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0); 2894 } 2895 2896 /** 2897 * @brief Clear Stream 1 FIFO error flag. 2898 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 2899 * @param DMAx DMAx Instance 2900 * @retval None 2901 */ 2902 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 2903 { 2904 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1); 2905 } 2906 2907 /** 2908 * @brief Clear Stream 2 FIFO error flag. 2909 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 2910 * @param DMAx DMAx Instance 2911 * @retval None 2912 */ 2913 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 2914 { 2915 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2); 2916 } 2917 2918 /** 2919 * @brief Clear Stream 3 FIFO error flag. 2920 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 2921 * @param DMAx DMAx Instance 2922 * @retval None 2923 */ 2924 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 2925 { 2926 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3); 2927 } 2928 2929 /** 2930 * @brief Clear Stream 4 FIFO error flag. 2931 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 2932 * @param DMAx DMAx Instance 2933 * @retval None 2934 */ 2935 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 2936 { 2937 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4); 2938 } 2939 2940 /** 2941 * @brief Clear Stream 5 FIFO error flag. 2942 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 2943 * @param DMAx DMAx Instance 2944 * @retval None 2945 */ 2946 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 2947 { 2948 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5); 2949 } 2950 2951 /** 2952 * @brief Clear Stream 6 FIFO error flag. 2953 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 2954 * @param DMAx DMAx Instance 2955 * @retval None 2956 */ 2957 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 2958 { 2959 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6); 2960 } 2961 2962 /** 2963 * @brief Clear Stream 7 FIFO error flag. 2964 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 2965 * @param DMAx DMAx Instance 2966 * @retval None 2967 */ 2968 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 2969 { 2970 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7); 2971 } 2972 2973 /** 2974 * @} 2975 */ 2976 2977 /** @defgroup DMA_LL_EF_IT_Management IT_Management 2978 * @ingroup RTEMSBSPsARMSTM32H7 2979 * @{ 2980 */ 2981 2982 /** 2983 * @brief Enable Half transfer interrupt. 2984 * @rmtoll CR HTIE LL_DMA_EnableIT_HT 2985 * @param DMAx DMAx Instance 2986 * @param Stream This parameter can be one of the following values: 2987 * @arg @ref LL_DMA_STREAM_0 2988 * @arg @ref LL_DMA_STREAM_1 2989 * @arg @ref LL_DMA_STREAM_2 2990 * @arg @ref LL_DMA_STREAM_3 2991 * @arg @ref LL_DMA_STREAM_4 2992 * @arg @ref LL_DMA_STREAM_5 2993 * @arg @ref LL_DMA_STREAM_6 2994 * @arg @ref LL_DMA_STREAM_7 2995 * @retval None 2996 */ 2997 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 2998 { 2999 uint32_t dma_base_addr = (uint32_t)DMAx; 3000 3001 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); 3002 } 3003 3004 /** 3005 * @brief Enable Transfer error interrupt. 3006 * @rmtoll CR TEIE LL_DMA_EnableIT_TE 3007 * @param DMAx DMAx Instance 3008 * @param Stream This parameter can be one of the following values: 3009 * @arg @ref LL_DMA_STREAM_0 3010 * @arg @ref LL_DMA_STREAM_1 3011 * @arg @ref LL_DMA_STREAM_2 3012 * @arg @ref LL_DMA_STREAM_3 3013 * @arg @ref LL_DMA_STREAM_4 3014 * @arg @ref LL_DMA_STREAM_5 3015 * @arg @ref LL_DMA_STREAM_6 3016 * @arg @ref LL_DMA_STREAM_7 3017 * @retval None 3018 */ 3019 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 3020 { 3021 uint32_t dma_base_addr = (uint32_t)DMAx; 3022 3023 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); 3024 } 3025 3026 /** 3027 * @brief Enable Transfer complete interrupt. 3028 * @rmtoll CR TCIE LL_DMA_EnableIT_TC 3029 * @param DMAx DMAx Instance 3030 * @param Stream This parameter can be one of the following values: 3031 * @arg @ref LL_DMA_STREAM_0 3032 * @arg @ref LL_DMA_STREAM_1 3033 * @arg @ref LL_DMA_STREAM_2 3034 * @arg @ref LL_DMA_STREAM_3 3035 * @arg @ref LL_DMA_STREAM_4 3036 * @arg @ref LL_DMA_STREAM_5 3037 * @arg @ref LL_DMA_STREAM_6 3038 * @arg @ref LL_DMA_STREAM_7 3039 * @retval None 3040 */ 3041 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 3042 { 3043 uint32_t dma_base_addr = (uint32_t)DMAx; 3044 3045 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); 3046 } 3047 3048 /** 3049 * @brief Enable Direct mode error interrupt. 3050 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME 3051 * @param DMAx DMAx Instance 3052 * @param Stream This parameter can be one of the following values: 3053 * @arg @ref LL_DMA_STREAM_0 3054 * @arg @ref LL_DMA_STREAM_1 3055 * @arg @ref LL_DMA_STREAM_2 3056 * @arg @ref LL_DMA_STREAM_3 3057 * @arg @ref LL_DMA_STREAM_4 3058 * @arg @ref LL_DMA_STREAM_5 3059 * @arg @ref LL_DMA_STREAM_6 3060 * @arg @ref LL_DMA_STREAM_7 3061 * @retval None 3062 */ 3063 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 3064 { 3065 uint32_t dma_base_addr = (uint32_t)DMAx; 3066 3067 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); 3068 } 3069 3070 /** 3071 * @brief Enable FIFO error interrupt. 3072 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE 3073 * @param DMAx DMAx Instance 3074 * @param Stream This parameter can be one of the following values: 3075 * @arg @ref LL_DMA_STREAM_0 3076 * @arg @ref LL_DMA_STREAM_1 3077 * @arg @ref LL_DMA_STREAM_2 3078 * @arg @ref LL_DMA_STREAM_3 3079 * @arg @ref LL_DMA_STREAM_4 3080 * @arg @ref LL_DMA_STREAM_5 3081 * @arg @ref LL_DMA_STREAM_6 3082 * @arg @ref LL_DMA_STREAM_7 3083 * @retval None 3084 */ 3085 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 3086 { 3087 uint32_t dma_base_addr = (uint32_t)DMAx; 3088 3089 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); 3090 } 3091 3092 /** 3093 * @brief Disable Half transfer interrupt. 3094 * @rmtoll CR HTIE LL_DMA_DisableIT_HT 3095 * @param DMAx DMAx Instance 3096 * @param Stream This parameter can be one of the following values: 3097 * @arg @ref LL_DMA_STREAM_0 3098 * @arg @ref LL_DMA_STREAM_1 3099 * @arg @ref LL_DMA_STREAM_2 3100 * @arg @ref LL_DMA_STREAM_3 3101 * @arg @ref LL_DMA_STREAM_4 3102 * @arg @ref LL_DMA_STREAM_5 3103 * @arg @ref LL_DMA_STREAM_6 3104 * @arg @ref LL_DMA_STREAM_7 3105 * @retval None 3106 */ 3107 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 3108 { 3109 uint32_t dma_base_addr = (uint32_t)DMAx; 3110 3111 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); 3112 } 3113 3114 /** 3115 * @brief Disable Transfer error interrupt. 3116 * @rmtoll CR TEIE LL_DMA_DisableIT_TE 3117 * @param DMAx DMAx Instance 3118 * @param Stream This parameter can be one of the following values: 3119 * @arg @ref LL_DMA_STREAM_0 3120 * @arg @ref LL_DMA_STREAM_1 3121 * @arg @ref LL_DMA_STREAM_2 3122 * @arg @ref LL_DMA_STREAM_3 3123 * @arg @ref LL_DMA_STREAM_4 3124 * @arg @ref LL_DMA_STREAM_5 3125 * @arg @ref LL_DMA_STREAM_6 3126 * @arg @ref LL_DMA_STREAM_7 3127 * @retval None 3128 */ 3129 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 3130 { 3131 uint32_t dma_base_addr = (uint32_t)DMAx; 3132 3133 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); 3134 } 3135 3136 /** 3137 * @brief Disable Transfer complete interrupt. 3138 * @rmtoll CR TCIE LL_DMA_DisableIT_TC 3139 * @param DMAx DMAx Instance 3140 * @param Stream This parameter can be one of the following values: 3141 * @arg @ref LL_DMA_STREAM_0 3142 * @arg @ref LL_DMA_STREAM_1 3143 * @arg @ref LL_DMA_STREAM_2 3144 * @arg @ref LL_DMA_STREAM_3 3145 * @arg @ref LL_DMA_STREAM_4 3146 * @arg @ref LL_DMA_STREAM_5 3147 * @arg @ref LL_DMA_STREAM_6 3148 * @arg @ref LL_DMA_STREAM_7 3149 * @retval None 3150 */ 3151 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 3152 { 3153 uint32_t dma_base_addr = (uint32_t)DMAx; 3154 3155 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); 3156 } 3157 3158 /** 3159 * @brief Disable Direct mode error interrupt. 3160 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME 3161 * @param DMAx DMAx Instance 3162 * @param Stream This parameter can be one of the following values: 3163 * @arg @ref LL_DMA_STREAM_0 3164 * @arg @ref LL_DMA_STREAM_1 3165 * @arg @ref LL_DMA_STREAM_2 3166 * @arg @ref LL_DMA_STREAM_3 3167 * @arg @ref LL_DMA_STREAM_4 3168 * @arg @ref LL_DMA_STREAM_5 3169 * @arg @ref LL_DMA_STREAM_6 3170 * @arg @ref LL_DMA_STREAM_7 3171 * @retval None 3172 */ 3173 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 3174 { 3175 uint32_t dma_base_addr = (uint32_t)DMAx; 3176 3177 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); 3178 } 3179 3180 /** 3181 * @brief Disable FIFO error interrupt. 3182 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE 3183 * @param DMAx DMAx Instance 3184 * @param Stream This parameter can be one of the following values: 3185 * @arg @ref LL_DMA_STREAM_0 3186 * @arg @ref LL_DMA_STREAM_1 3187 * @arg @ref LL_DMA_STREAM_2 3188 * @arg @ref LL_DMA_STREAM_3 3189 * @arg @ref LL_DMA_STREAM_4 3190 * @arg @ref LL_DMA_STREAM_5 3191 * @arg @ref LL_DMA_STREAM_6 3192 * @arg @ref LL_DMA_STREAM_7 3193 * @retval None 3194 */ 3195 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 3196 { 3197 uint32_t dma_base_addr = (uint32_t)DMAx; 3198 3199 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); 3200 } 3201 3202 /** 3203 * @brief Check if Half transfer interrupt is enabled. 3204 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT 3205 * @param DMAx DMAx Instance 3206 * @param Stream This parameter can be one of the following values: 3207 * @arg @ref LL_DMA_STREAM_0 3208 * @arg @ref LL_DMA_STREAM_1 3209 * @arg @ref LL_DMA_STREAM_2 3210 * @arg @ref LL_DMA_STREAM_3 3211 * @arg @ref LL_DMA_STREAM_4 3212 * @arg @ref LL_DMA_STREAM_5 3213 * @arg @ref LL_DMA_STREAM_6 3214 * @arg @ref LL_DMA_STREAM_7 3215 * @retval State of bit (1 or 0). 3216 */ 3217 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 3218 { 3219 uint32_t dma_base_addr = (uint32_t)DMAx; 3220 3221 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); 3222 } 3223 3224 /** 3225 * @brief Check if Transfer error nterrup is enabled. 3226 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE 3227 * @param DMAx DMAx Instance 3228 * @param Stream This parameter can be one of the following values: 3229 * @arg @ref LL_DMA_STREAM_0 3230 * @arg @ref LL_DMA_STREAM_1 3231 * @arg @ref LL_DMA_STREAM_2 3232 * @arg @ref LL_DMA_STREAM_3 3233 * @arg @ref LL_DMA_STREAM_4 3234 * @arg @ref LL_DMA_STREAM_5 3235 * @arg @ref LL_DMA_STREAM_6 3236 * @arg @ref LL_DMA_STREAM_7 3237 * @retval State of bit (1 or 0). 3238 */ 3239 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 3240 { 3241 uint32_t dma_base_addr = (uint32_t)DMAx; 3242 3243 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); 3244 } 3245 3246 /** 3247 * @brief Check if Transfer complete interrupt is enabled. 3248 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC 3249 * @param DMAx DMAx Instance 3250 * @param Stream This parameter can be one of the following values: 3251 * @arg @ref LL_DMA_STREAM_0 3252 * @arg @ref LL_DMA_STREAM_1 3253 * @arg @ref LL_DMA_STREAM_2 3254 * @arg @ref LL_DMA_STREAM_3 3255 * @arg @ref LL_DMA_STREAM_4 3256 * @arg @ref LL_DMA_STREAM_5 3257 * @arg @ref LL_DMA_STREAM_6 3258 * @arg @ref LL_DMA_STREAM_7 3259 * @retval State of bit (1 or 0). 3260 */ 3261 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 3262 { 3263 uint32_t dma_base_addr = (uint32_t)DMAx; 3264 3265 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); 3266 } 3267 3268 /** 3269 * @brief Check if Direct mode error interrupt is enabled. 3270 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME 3271 * @param DMAx DMAx Instance 3272 * @param Stream This parameter can be one of the following values: 3273 * @arg @ref LL_DMA_STREAM_0 3274 * @arg @ref LL_DMA_STREAM_1 3275 * @arg @ref LL_DMA_STREAM_2 3276 * @arg @ref LL_DMA_STREAM_3 3277 * @arg @ref LL_DMA_STREAM_4 3278 * @arg @ref LL_DMA_STREAM_5 3279 * @arg @ref LL_DMA_STREAM_6 3280 * @arg @ref LL_DMA_STREAM_7 3281 * @retval State of bit (1 or 0). 3282 */ 3283 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 3284 { 3285 uint32_t dma_base_addr = (uint32_t)DMAx; 3286 3287 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); 3288 } 3289 3290 /** 3291 * @brief Check if FIFO error interrupt is enabled. 3292 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE 3293 * @param DMAx DMAx Instance 3294 * @param Stream This parameter can be one of the following values: 3295 * @arg @ref LL_DMA_STREAM_0 3296 * @arg @ref LL_DMA_STREAM_1 3297 * @arg @ref LL_DMA_STREAM_2 3298 * @arg @ref LL_DMA_STREAM_3 3299 * @arg @ref LL_DMA_STREAM_4 3300 * @arg @ref LL_DMA_STREAM_5 3301 * @arg @ref LL_DMA_STREAM_6 3302 * @arg @ref LL_DMA_STREAM_7 3303 * @retval State of bit (1 or 0). 3304 */ 3305 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 3306 { 3307 uint32_t dma_base_addr = (uint32_t)DMAx; 3308 3309 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); 3310 } 3311 3312 /** 3313 * @} 3314 */ 3315 3316 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 3317 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 3318 * @ingroup RTEMSBSPsARMSTM32H7 3319 * @{ 3320 */ 3321 3322 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); 3323 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); 3324 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 3325 3326 /** 3327 * @} 3328 */ 3329 #endif /* USE_FULL_LL_DRIVER */ 3330 3331 /** 3332 * @} 3333 */ 3334 3335 /** 3336 * @} 3337 */ 3338 3339 #endif /* DMA1 || DMA2 */ 3340 3341 /** 3342 * @} 3343 */ 3344 3345 #ifdef __cplusplus 3346 } 3347 #endif 3348 3349 #endif /* __STM32H7xx_LL_DMA_H */ 3350
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