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0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_dac.h 0004 * @author MCD Application Team 0005 * @brief Header file of DAC LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_DAC_H 0021 #define STM32H7xx_LL_DAC_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined(DAC1) || defined(DAC2) 0035 0036 /** @defgroup DAC_LL DAC 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 0044 /* Private constants ---------------------------------------------------------*/ 0045 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 0046 * @ingroup RTEMSBSPsARMSTM32H7 0047 * @{ 0048 */ 0049 0050 /* Internal masks for DAC channels definition */ 0051 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 0052 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 0053 /* - channel bits position into register SWTRIG */ 0054 /* - channel register offset of data holding register DHRx */ 0055 /* - channel register offset of data output register DORx */ 0056 /* - channel register offset of sample-and-hold sample time register SHSRx */ 0057 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers 0058 CR, MCR, CCR, SHHR, SHRR of channel 1 */ 0059 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers 0060 CR, MCR, CCR, SHHR, SHRR of channel 2 */ 0061 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 0062 0063 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 0064 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 0065 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 0066 0067 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ 0068 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus 0069 DHR12Rx channel 1 (shifted left of 20 bits) */ 0070 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus 0071 DHR12Rx channel 1 (shifted left of 24 bits) */ 0072 0073 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus 0074 DHR12Rx channel 1 (shifted left of 28 bits) */ 0075 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus 0076 DHR12Rx channel 1 (shifted left of 20 bits) */ 0077 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus 0078 DHR12Rx channel 1 (shifted left of 24 bits) */ 0079 0080 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL 0081 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL 0082 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL 0083 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ 0084 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 0085 0086 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ 0087 0088 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus 0089 DORx channel 2 (shifted left of 5 bits) */ 0090 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 0091 0092 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ 0093 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus 0094 SHSRx channel 2 (shifted left of 6 bits) */ 0095 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) 0096 0097 0098 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, 0099 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 0100 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted 0101 to position 0 */ 0102 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted 0103 to position 0 */ 0104 0105 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx 0106 channel 1 or 2 versus DHR12Rx channel 1 0107 (shifted left of 28 bits) */ 0108 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx 0109 channel 1 or 2 versus DHR12Rx channel 1 0110 (shifted left of 20 bits) */ 0111 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx 0112 channel 1 or 2 versus DHR12Rx channel 1 0113 (shifted left of 24 bits) */ 0114 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx 0115 channel 1 or 2 versus DORx channel 1 0116 (shifted left of 5 bits) */ 0117 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx 0118 channel 1 or 2 versus SHSRx channel 1 0119 (shifted left of 6 bits) */ 0120 0121 /* DAC registers bits positions */ 0122 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos 0123 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos 0124 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos 0125 0126 /* Miscellaneous data */ 0127 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 0128 bits (voltage range determined by analog voltage 0129 references Vref+ and Vref-, refer to reference manual) */ 0130 0131 /** 0132 * @} 0133 */ 0134 0135 0136 /* Private macros ------------------------------------------------------------*/ 0137 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 0138 * @ingroup RTEMSBSPsARMSTM32H7 0139 * @{ 0140 */ 0141 0142 /** 0143 * @brief Driver macro reserved for internal use: set a pointer to 0144 * a register from a register basis from which an offset 0145 * is applied. 0146 * @param __REG__ Register basis from which the offset is applied. 0147 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 0148 * @retval Pointer to register address 0149 */ 0150 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 0151 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) 0152 0153 /** 0154 * @} 0155 */ 0156 0157 0158 /* Exported types ------------------------------------------------------------*/ 0159 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0160 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 0161 * @ingroup RTEMSBSPsARMSTM32H7 0162 * @{ 0163 */ 0164 0165 /** 0166 * @brief Structure definition of some features of DAC instance. 0167 */ 0168 typedef struct 0169 { 0170 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: 0171 internal (SW start) or from external peripheral 0172 (timer event, external interrupt line). 0173 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 0174 0175 This feature can be modified afterwards using unitary 0176 function @ref LL_DAC_SetTriggerSource(). */ 0177 0178 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 0179 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 0180 0181 This feature can be modified afterwards using unitary 0182 function @ref LL_DAC_SetWaveAutoGeneration(). */ 0183 0184 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 0185 If waveform automatic generation mode is set to noise, this parameter 0186 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 0187 If waveform automatic generation mode is set to triangle, 0188 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 0189 @note If waveform automatic generation mode is disabled, 0190 this parameter is discarded. 0191 0192 This feature can be modified afterwards using unitary 0193 function @ref LL_DAC_SetWaveNoiseLFSR(), 0194 @ref LL_DAC_SetWaveTriangleAmplitude() 0195 depending on the wave automatic generation selected. */ 0196 0197 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 0198 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 0199 0200 This feature can be modified afterwards using unitary 0201 function @ref LL_DAC_SetOutputBuffer(). */ 0202 0203 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. 0204 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION 0205 0206 This feature can be modified afterwards using unitary 0207 function @ref LL_DAC_SetOutputConnection(). */ 0208 0209 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC 0210 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE 0211 0212 This feature can be modified afterwards using unitary 0213 function @ref LL_DAC_SetOutputMode(). */ 0214 } LL_DAC_InitTypeDef; 0215 0216 /** 0217 * @} 0218 */ 0219 #endif /* USE_FULL_LL_DRIVER */ 0220 0221 /* Exported constants --------------------------------------------------------*/ 0222 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 0223 * @ingroup RTEMSBSPsARMSTM32H7 0224 * @{ 0225 */ 0226 0227 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 0228 * @ingroup RTEMSBSPsARMSTM32H7 0229 * @brief Flags defines which can be used with LL_DAC_ReadReg function 0230 * @{ 0231 */ 0232 /* DAC channel 1 flags */ 0233 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 0234 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ 0235 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ 0236 0237 /* DAC channel 2 flags */ 0238 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 0239 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ 0240 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ 0241 0242 /** 0243 * @} 0244 */ 0245 0246 /** @defgroup DAC_LL_EC_IT DAC interruptions 0247 * @ingroup RTEMSBSPsARMSTM32H7 0248 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 0249 * @{ 0250 */ 0251 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 0252 0253 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 0254 0255 /** 0256 * @} 0257 */ 0258 0259 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 0260 * @ingroup RTEMSBSPsARMSTM32H7 0261 * @{ 0262 */ 0263 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 0264 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 0265 /** 0266 * @} 0267 */ 0268 0269 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode 0270 * @ingroup RTEMSBSPsARMSTM32H7 0271 * @{ 0272 */ 0273 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */ 0274 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ 0275 /** 0276 * @} 0277 */ 0278 0279 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 0280 * @ingroup RTEMSBSPsARMSTM32H7 0281 * @{ 0282 */ 0283 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ 0284 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */ 0285 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ 0286 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ 0287 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ 0288 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ 0289 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ 0290 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ 0291 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ 0292 #if defined (HRTIM1) 0293 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */ 0294 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */ 0295 #endif /* HRTIM1 */ 0296 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */ 0297 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */ 0298 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ 0299 #if defined(TIM23) 0300 #define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */ 0301 #endif /* TIM23 */ 0302 #if defined(TIM24) 0303 #define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */ 0304 #endif /* TIM24 */ 0305 #if defined (DAC2) 0306 #define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */ 0307 #endif /* DAC2 */ 0308 /** 0309 * @} 0310 */ 0311 0312 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 0313 * @ingroup RTEMSBSPsARMSTM32H7 0314 * @{ 0315 */ 0316 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ 0317 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 0318 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 0319 /** 0320 * @} 0321 */ 0322 0323 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 0324 * @ingroup RTEMSBSPsARMSTM32H7 0325 * @{ 0326 */ 0327 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 0328 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 0329 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 0330 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 0331 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 0332 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 0333 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 0334 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 0335 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 0336 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 0337 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 0338 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 0339 /** 0340 * @} 0341 */ 0342 0343 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 0344 * @ingroup RTEMSBSPsARMSTM32H7 0345 * @{ 0346 */ 0347 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 0348 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 0349 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 0350 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 0351 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 0352 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 0353 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 0354 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 0355 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 0356 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 0357 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 0358 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 0359 /** 0360 * @} 0361 */ 0362 0363 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode 0364 * @ingroup RTEMSBSPsARMSTM32H7 0365 * @{ 0366 */ 0367 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */ 0368 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ 0369 /** 0370 * @} 0371 */ 0372 0373 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 0374 * @ingroup RTEMSBSPsARMSTM32H7 0375 * @{ 0376 */ 0377 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 0378 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 0379 /** 0380 * @} 0381 */ 0382 0383 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection 0384 * @ingroup RTEMSBSPsARMSTM32H7 0385 * @{ 0386 */ 0387 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */ 0388 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ 0389 /** 0390 * @} 0391 */ 0392 0393 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming 0394 * @ingroup RTEMSBSPsARMSTM32H7 0395 * @{ 0396 */ 0397 #define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE) 0398 #define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO) 0399 #define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO) 0400 #define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO) 0401 #define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO) 0402 #define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO) 0403 #define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9) 0404 0405 #define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE) 0406 #define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE) 0407 #define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) 0408 0409 #define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO) 0410 #define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL) 0411 /** 0412 * @} 0413 */ 0414 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 0415 * @ingroup RTEMSBSPsARMSTM32H7 0416 * @{ 0417 */ 0418 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ 0419 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ 0420 /** 0421 * @} 0422 */ 0423 0424 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 0425 * @ingroup RTEMSBSPsARMSTM32H7 0426 * @{ 0427 */ 0428 /* List of DAC registers intended to be used (most commonly) with */ 0429 /* DMA transfer. */ 0430 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 0431 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ 0432 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ 0433 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ 0434 /** 0435 * @} 0436 */ 0437 0438 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 0439 * @ingroup RTEMSBSPsARMSTM32H7 0440 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, 0441 * not timeout values. 0442 * For details on delays values, refer to descriptions in source code 0443 * above each literal definition. 0444 * @{ 0445 */ 0446 0447 /* Delay for DAC channel voltage settling time from DAC channel startup */ 0448 /* (transition from disable to enable). */ 0449 /* Note: DAC channel startup time depends on board application environment: */ 0450 /* impedance connected to DAC channel output. */ 0451 /* The delay below is specified under conditions: */ 0452 /* - voltage maximum transition (lowest to highest value) */ 0453 /* - until voltage reaches final value +-1LSB */ 0454 /* - DAC channel output buffer enabled */ 0455 /* - load impedance of 5kOhm (min), 50pF (max) */ 0456 /* Literal set to maximum value (refer to device datasheet, */ 0457 /* parameter "tWAKEUP"). */ 0458 /* Unit: us */ 0459 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 0460 0461 /* Delay for DAC channel voltage settling time. */ 0462 /* Note: DAC channel startup time depends on board application environment: */ 0463 /* impedance connected to DAC channel output. */ 0464 /* The delay below is specified under conditions: */ 0465 /* - voltage maximum transition (lowest to highest value) */ 0466 /* - until voltage reaches final value +-1LSB */ 0467 /* - DAC channel output buffer enabled */ 0468 /* - load impedance of 5kOhm min, 50pF max */ 0469 /* Literal set to maximum value (refer to device datasheet, */ 0470 /* parameter "tSETTLING"). */ 0471 /* Unit: us */ 0472 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */ 0473 0474 /** 0475 * @} 0476 */ 0477 0478 /** 0479 * @} 0480 */ 0481 0482 /* Exported macro ------------------------------------------------------------*/ 0483 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 0484 * @ingroup RTEMSBSPsARMSTM32H7 0485 * @{ 0486 */ 0487 0488 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 0489 * @ingroup RTEMSBSPsARMSTM32H7 0490 * @{ 0491 */ 0492 0493 /** 0494 * @brief Write a value in DAC register 0495 * @param __INSTANCE__ DAC Instance 0496 * @param __REG__ Register to be written 0497 * @param __VALUE__ Value to be written in the register 0498 * @retval None 0499 */ 0500 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0501 0502 /** 0503 * @brief Read a value in DAC register 0504 * @param __INSTANCE__ DAC Instance 0505 * @param __REG__ Register to be read 0506 * @retval Register value 0507 */ 0508 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0509 0510 /** 0511 * @} 0512 */ 0513 0514 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 0515 * @ingroup RTEMSBSPsARMSTM32H7 0516 * @{ 0517 */ 0518 0519 /** 0520 * @brief Helper macro to get DAC channel number in decimal format 0521 * from literals LL_DAC_CHANNEL_x. 0522 * Example: 0523 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 0524 * will return decimal number "1". 0525 * @note The input can be a value from functions where a channel 0526 * number is returned. 0527 * @param __CHANNEL__ This parameter can be one of the following values: 0528 * @arg @ref LL_DAC_CHANNEL_1 0529 * @arg @ref LL_DAC_CHANNEL_2 0530 * @retval 1...2 0531 */ 0532 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 0533 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 0534 0535 /** 0536 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 0537 * from number in decimal format. 0538 * Example: 0539 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 0540 * will return a data equivalent to "LL_DAC_CHANNEL_1". 0541 * @note If the input parameter does not correspond to a DAC channel, 0542 * this macro returns value '0'. 0543 * @param __DECIMAL_NB__ 1...2 0544 * @retval Returned value can be one of the following values: 0545 * @arg @ref LL_DAC_CHANNEL_1 0546 * @arg @ref LL_DAC_CHANNEL_2 0547 */ 0548 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ 0549 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) 0550 0551 /** 0552 * @brief Helper macro to define the DAC conversion data full-scale digital 0553 * value corresponding to the selected DAC resolution. 0554 * @note DAC conversion data full-scale corresponds to voltage range 0555 * determined by analog voltage references Vref+ and Vref- 0556 * (refer to reference manual). 0557 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 0558 * @arg @ref LL_DAC_RESOLUTION_12B 0559 * @arg @ref LL_DAC_RESOLUTION_8B 0560 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 0561 */ 0562 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 0563 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) 0564 0565 /** 0566 * @brief Helper macro to calculate the DAC conversion data (unit: digital 0567 * value) corresponding to a voltage (unit: mVolt). 0568 * @note This helper macro is intended to provide input data in voltage 0569 * rather than digital value, 0570 * to be used with LL DAC functions such as 0571 * @ref LL_DAC_ConvertData12RightAligned(). 0572 * @note Analog reference voltage (Vref+) must be either known from 0573 * user board environment or can be calculated using ADC measurement 0574 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 0575 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 0576 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 0577 * (unit: mVolt). 0578 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 0579 * @arg @ref LL_DAC_RESOLUTION_12B 0580 * @arg @ref LL_DAC_RESOLUTION_8B 0581 * @retval DAC conversion data (unit: digital value) 0582 */ 0583 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ 0584 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 0585 / (__VREFANALOG_VOLTAGE__) \ 0586 ) 0587 0588 /** 0589 * @} 0590 */ 0591 0592 /** 0593 * @} 0594 */ 0595 0596 0597 /* Exported functions --------------------------------------------------------*/ 0598 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 0599 * @ingroup RTEMSBSPsARMSTM32H7 0600 * @{ 0601 */ 0602 0603 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels 0604 * @ingroup RTEMSBSPsARMSTM32H7 0605 * @{ 0606 */ 0607 0608 /** 0609 * @brief Set the operating mode for the selected DAC channel: 0610 * calibration or normal operating mode. 0611 * @rmtoll CR CEN1 LL_DAC_SetMode\n 0612 * CR CEN2 LL_DAC_SetMode 0613 * @param DACx DAC instance 0614 * @param DAC_Channel This parameter can be one of the following values: 0615 * @arg @ref LL_DAC_CHANNEL_1 0616 * @arg @ref LL_DAC_CHANNEL_2 0617 * @param ChannelMode This parameter can be one of the following values: 0618 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 0619 * @arg @ref LL_DAC_MODE_CALIBRATION 0620 * @retval None 0621 */ 0622 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode) 0623 { 0624 MODIFY_REG(DACx->CR, 0625 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0626 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0627 } 0628 0629 /** 0630 * @brief Get the operating mode for the selected DAC channel: 0631 * calibration or normal operating mode. 0632 * @rmtoll CR CEN1 LL_DAC_GetMode\n 0633 * CR CEN2 LL_DAC_GetMode 0634 * @param DACx DAC instance 0635 * @param DAC_Channel This parameter can be one of the following values: 0636 * @arg @ref LL_DAC_CHANNEL_1 0637 * @arg @ref LL_DAC_CHANNEL_2 0638 * @retval Returned value can be one of the following values: 0639 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 0640 * @arg @ref LL_DAC_MODE_CALIBRATION 0641 */ 0642 __STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0643 { 0644 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0645 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0646 ); 0647 } 0648 0649 /** 0650 * @brief Set the offset trimming value for the selected DAC channel. 0651 * Trimming has an impact when output buffer is enabled 0652 * and is intended to replace factory calibration default values. 0653 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n 0654 * CCR OTRIM2 LL_DAC_SetTrimmingValue 0655 * @param DACx DAC instance 0656 * @param DAC_Channel This parameter can be one of the following values: 0657 * @arg @ref LL_DAC_CHANNEL_1 0658 * @arg @ref LL_DAC_CHANNEL_2 0659 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 0660 * @retval None 0661 */ 0662 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue) 0663 { 0664 MODIFY_REG(DACx->CCR, 0665 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0666 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0667 } 0668 0669 /** 0670 * @brief Get the offset trimming value for the selected DAC channel. 0671 * Trimming has an impact when output buffer is enabled 0672 * and is intended to replace factory calibration default values. 0673 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n 0674 * CCR OTRIM2 LL_DAC_GetTrimmingValue 0675 * @param DACx DAC instance 0676 * @param DAC_Channel This parameter can be one of the following values: 0677 * @arg @ref LL_DAC_CHANNEL_1 0678 * @arg @ref LL_DAC_CHANNEL_2 0679 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 0680 */ 0681 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0682 { 0683 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0684 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0685 ); 0686 } 0687 0688 /** 0689 * @brief Set the conversion trigger source for the selected DAC channel. 0690 * @note For conversion trigger source to be effective, DAC trigger 0691 * must be enabled using function @ref LL_DAC_EnableTrigger(). 0692 * @note To set conversion trigger source, DAC channel must be disabled. 0693 * Otherwise, the setting is discarded. 0694 * @note Availability of parameters of trigger sources from timer 0695 * depends on timers availability on the selected device. 0696 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 0697 * CR TSEL2 LL_DAC_SetTriggerSource 0698 * @param DACx DAC instance 0699 * @param DAC_Channel This parameter can be one of the following values: 0700 * @arg @ref LL_DAC_CHANNEL_1 0701 * @arg @ref LL_DAC_CHANNEL_2 0702 * @param TriggerSource This parameter can be one of the following values: 0703 * @arg @ref LL_DAC_TRIG_SOFTWARE 0704 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 0705 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 0706 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 0707 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 0708 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 0709 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 0710 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 0711 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 0712 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1) 0713 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1) 0714 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 0715 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 0716 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2) 0717 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 0718 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) 0719 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) 0720 * 0721 * (1) On this STM32 series, parameter not available on all devices. 0722 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) 0723 * (2) On this STM32 series, parameter only available on DAC2. 0724 * (3) On this STM32 series, parameter not available on all devices. 0725 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) 0726 * (4) On this STM32 series, parameter not available on all devices. 0727 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) 0728 * @retval None 0729 */ 0730 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 0731 { 0732 MODIFY_REG(DACx->CR, 0733 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0734 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0735 } 0736 0737 /** 0738 * @brief Get the conversion trigger source for the selected DAC channel. 0739 * @note For conversion trigger source to be effective, DAC trigger 0740 * must be enabled using function @ref LL_DAC_EnableTrigger(). 0741 * @note Availability of parameters of trigger sources from timer 0742 * depends on timers availability on the selected device. 0743 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 0744 * CR TSEL2 LL_DAC_GetTriggerSource 0745 * @param DACx DAC instance 0746 * @param DAC_Channel This parameter can be one of the following values: 0747 * @arg @ref LL_DAC_CHANNEL_1 0748 * @arg @ref LL_DAC_CHANNEL_2 0749 * @retval Returned value can be one of the following values: 0750 * @arg @ref LL_DAC_TRIG_SOFTWARE 0751 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 0752 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 0753 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 0754 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 0755 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 0756 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 0757 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 0758 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 0759 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1) 0760 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1) 0761 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 0762 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 0763 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2) 0764 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 0765 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) 0766 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) 0767 * 0768 * (1) On this STM32 series, parameter not available on all devices. 0769 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) 0770 * (2) On this STM32 series, parameter only available on DAC2. 0771 * (3) On this STM32 series, parameter not available on all devices. 0772 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) 0773 * (4) On this STM32 series, parameter not available on all devices. 0774 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) 0775 */ 0776 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0777 { 0778 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0779 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0780 ); 0781 } 0782 0783 /** 0784 * @brief Set the waveform automatic generation mode 0785 * for the selected DAC channel. 0786 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 0787 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 0788 * @param DACx DAC instance 0789 * @param DAC_Channel This parameter can be one of the following values: 0790 * @arg @ref LL_DAC_CHANNEL_1 0791 * @arg @ref LL_DAC_CHANNEL_2 0792 * @param WaveAutoGeneration This parameter can be one of the following values: 0793 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 0794 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 0795 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 0796 * @retval None 0797 */ 0798 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 0799 { 0800 MODIFY_REG(DACx->CR, 0801 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0802 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0803 } 0804 0805 /** 0806 * @brief Get the waveform automatic generation mode 0807 * for the selected DAC channel. 0808 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 0809 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 0810 * @param DACx DAC instance 0811 * @param DAC_Channel This parameter can be one of the following values: 0812 * @arg @ref LL_DAC_CHANNEL_1 0813 * @arg @ref LL_DAC_CHANNEL_2 0814 * @retval Returned value can be one of the following values: 0815 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 0816 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 0817 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 0818 */ 0819 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0820 { 0821 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0822 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0823 ); 0824 } 0825 0826 /** 0827 * @brief Set the noise waveform generation for the selected DAC channel: 0828 * Noise mode and parameters LFSR (linear feedback shift register). 0829 * @note For wave generation to be effective, DAC channel 0830 * wave generation mode must be enabled using 0831 * function @ref LL_DAC_SetWaveAutoGeneration(). 0832 * @note This setting can be set when the selected DAC channel is disabled 0833 * (otherwise, the setting operation is ignored). 0834 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 0835 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 0836 * @param DACx DAC instance 0837 * @param DAC_Channel This parameter can be one of the following values: 0838 * @arg @ref LL_DAC_CHANNEL_1 0839 * @arg @ref LL_DAC_CHANNEL_2 0840 * @param NoiseLFSRMask This parameter can be one of the following values: 0841 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 0842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 0843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 0844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 0845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 0846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 0847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 0848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 0849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 0850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 0851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 0852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 0853 * @retval None 0854 */ 0855 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 0856 { 0857 MODIFY_REG(DACx->CR, 0858 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0859 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0860 } 0861 0862 /** 0863 * @brief Get the noise waveform generation for the selected DAC channel: 0864 * Noise mode and parameters LFSR (linear feedback shift register). 0865 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 0866 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 0867 * @param DACx DAC instance 0868 * @param DAC_Channel This parameter can be one of the following values: 0869 * @arg @ref LL_DAC_CHANNEL_1 0870 * @arg @ref LL_DAC_CHANNEL_2 0871 * @retval Returned value can be one of the following values: 0872 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 0873 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 0874 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 0875 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 0876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 0877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 0878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 0879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 0880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 0881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 0882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 0883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 0884 */ 0885 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0886 { 0887 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0888 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0889 ); 0890 } 0891 0892 /** 0893 * @brief Set the triangle waveform generation for the selected DAC channel: 0894 * triangle mode and amplitude. 0895 * @note For wave generation to be effective, DAC channel 0896 * wave generation mode must be enabled using 0897 * function @ref LL_DAC_SetWaveAutoGeneration(). 0898 * @note This setting can be set when the selected DAC channel is disabled 0899 * (otherwise, the setting operation is ignored). 0900 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 0901 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 0902 * @param DACx DAC instance 0903 * @param DAC_Channel This parameter can be one of the following values: 0904 * @arg @ref LL_DAC_CHANNEL_1 0905 * @arg @ref LL_DAC_CHANNEL_2 0906 * @param TriangleAmplitude This parameter can be one of the following values: 0907 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 0908 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 0909 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 0910 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 0911 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 0912 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 0913 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 0914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 0915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 0916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 0917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 0918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 0919 * @retval None 0920 */ 0921 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, 0922 uint32_t TriangleAmplitude) 0923 { 0924 MODIFY_REG(DACx->CR, 0925 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 0926 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 0927 } 0928 0929 /** 0930 * @brief Get the triangle waveform generation for the selected DAC channel: 0931 * triangle mode and amplitude. 0932 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 0933 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 0934 * @param DACx DAC instance 0935 * @param DAC_Channel This parameter can be one of the following values: 0936 * @arg @ref LL_DAC_CHANNEL_1 0937 * @arg @ref LL_DAC_CHANNEL_2 0938 * @retval Returned value can be one of the following values: 0939 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 0940 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 0941 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 0942 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 0943 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 0944 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 0945 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 0946 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 0947 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 0948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 0949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 0950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 0951 */ 0952 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 0953 { 0954 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 0955 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 0956 ); 0957 } 0958 0959 /** 0960 * @brief Set the output for the selected DAC channel. 0961 * @note This function set several features: 0962 * - mode normal or sample-and-hold 0963 * - buffer 0964 * - connection to GPIO or internal path. 0965 * These features can also be set individually using 0966 * dedicated functions: 0967 * - @ref LL_DAC_SetOutputBuffer() 0968 * - @ref LL_DAC_SetOutputMode() 0969 * - @ref LL_DAC_SetOutputConnection() 0970 * @note On this STM32 series, output connection depends on output mode 0971 * (normal or sample and hold) and output buffer state. 0972 * - if output connection is set to internal path and output buffer 0973 * is enabled (whatever output mode): 0974 * output connection is also connected to GPIO pin 0975 * (both connections to GPIO pin and internal path). 0976 * - if output connection is set to GPIO pin, output buffer 0977 * is disabled, output mode set to sample and hold: 0978 * output connection is also connected to internal path 0979 * (both connections to GPIO pin and internal path). 0980 * @note Mode sample-and-hold requires an external capacitor 0981 * to be connected between DAC channel output and ground. 0982 * Capacitor value depends on load on DAC channel output and 0983 * sample-and-hold timings configured. 0984 * As indication, capacitor typical value is 100nF 0985 * (refer to device datasheet, parameter "CSH"). 0986 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n 0987 * CR MODE2 LL_DAC_ConfigOutput 0988 * @param DACx DAC instance 0989 * @param DAC_Channel This parameter can be one of the following values: 0990 * @arg @ref LL_DAC_CHANNEL_1 0991 * @arg @ref LL_DAC_CHANNEL_2 0992 * @param OutputMode This parameter can be one of the following values: 0993 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 0994 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 0995 * @param OutputBuffer This parameter can be one of the following values: 0996 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 0997 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 0998 * @param OutputConnection This parameter can be one of the following values: 0999 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 1000 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 1001 * @retval None 1002 */ 1003 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, 1004 uint32_t OutputBuffer, uint32_t OutputConnection) 1005 { 1006 MODIFY_REG(DACx->MCR, 1007 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1008 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1009 } 1010 1011 /** 1012 * @brief Set the output mode normal or sample-and-hold 1013 * for the selected DAC channel. 1014 * @note Mode sample-and-hold requires an external capacitor 1015 * to be connected between DAC channel output and ground. 1016 * Capacitor value depends on load on DAC channel output and 1017 * sample-and-hold timings configured. 1018 * As indication, capacitor typical value is 100nF 1019 * (refer to device datasheet, parameter "CSH"). 1020 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n 1021 * CR MODE2 LL_DAC_SetOutputMode 1022 * @param DACx DAC instance 1023 * @param DAC_Channel This parameter can be one of the following values: 1024 * @arg @ref LL_DAC_CHANNEL_1 1025 * @arg @ref LL_DAC_CHANNEL_2 1026 * @param OutputMode This parameter can be one of the following values: 1027 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 1028 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 1029 * @retval None 1030 */ 1031 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) 1032 { 1033 MODIFY_REG(DACx->MCR, 1034 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1035 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1036 } 1037 1038 /** 1039 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. 1040 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n 1041 * CR MODE2 LL_DAC_GetOutputMode 1042 * @param DACx DAC instance 1043 * @param DAC_Channel This parameter can be one of the following values: 1044 * @arg @ref LL_DAC_CHANNEL_1 1045 * @arg @ref LL_DAC_CHANNEL_2 1046 * @retval Returned value can be one of the following values: 1047 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 1048 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 1049 */ 1050 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1051 { 1052 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1053 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 1054 ); 1055 } 1056 1057 /** 1058 * @brief Set the output buffer for the selected DAC channel. 1059 * @note On this STM32 series, when buffer is enabled, its offset can be 1060 * trimmed: factory calibration default values can be 1061 * replaced by user trimming values, using function 1062 * @ref LL_DAC_SetTrimmingValue(). 1063 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n 1064 * CR MODE2 LL_DAC_SetOutputBuffer 1065 * @param DACx DAC instance 1066 * @param DAC_Channel This parameter can be one of the following values: 1067 * @arg @ref LL_DAC_CHANNEL_1 1068 * @arg @ref LL_DAC_CHANNEL_2 1069 * @param OutputBuffer This parameter can be one of the following values: 1070 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 1071 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 1072 * @retval None 1073 */ 1074 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 1075 { 1076 MODIFY_REG(DACx->MCR, 1077 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1078 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1079 } 1080 1081 /** 1082 * @brief Get the output buffer state for the selected DAC channel. 1083 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n 1084 * CR MODE2 LL_DAC_GetOutputBuffer 1085 * @param DACx DAC instance 1086 * @param DAC_Channel This parameter can be one of the following values: 1087 * @arg @ref LL_DAC_CHANNEL_1 1088 * @arg @ref LL_DAC_CHANNEL_2 1089 * @retval Returned value can be one of the following values: 1090 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 1091 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 1092 */ 1093 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1094 { 1095 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1096 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 1097 ); 1098 } 1099 1100 /** 1101 * @brief Set the output connection for the selected DAC channel. 1102 * @note On this STM32 series, output connection depends on output mode (normal or 1103 * sample and hold) and output buffer state. 1104 * - if output connection is set to internal path and output buffer 1105 * is enabled (whatever output mode): 1106 * output connection is also connected to GPIO pin 1107 * (both connections to GPIO pin and internal path). 1108 * - if output connection is set to GPIO pin, output buffer 1109 * is disabled, output mode set to sample and hold: 1110 * output connection is also connected to internal path 1111 * (both connections to GPIO pin and internal path). 1112 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n 1113 * CR MODE2 LL_DAC_SetOutputConnection 1114 * @param DACx DAC instance 1115 * @param DAC_Channel This parameter can be one of the following values: 1116 * @arg @ref LL_DAC_CHANNEL_1 1117 * @arg @ref LL_DAC_CHANNEL_2 1118 * @param OutputConnection This parameter can be one of the following values: 1119 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 1120 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 1121 * @retval None 1122 */ 1123 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) 1124 { 1125 MODIFY_REG(DACx->MCR, 1126 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1127 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1128 } 1129 1130 /** 1131 * @brief Get the output connection for the selected DAC channel. 1132 * @note On this STM32 series, output connection depends on output mode (normal or 1133 * sample and hold) and output buffer state. 1134 * - if output connection is set to internal path and output buffer 1135 * is enabled (whatever output mode): 1136 * output connection is also connected to GPIO pin 1137 * (both connections to GPIO pin and internal path). 1138 * - if output connection is set to GPIO pin, output buffer 1139 * is disabled, output mode set to sample and hold: 1140 * output connection is also connected to internal path 1141 * (both connections to GPIO pin and internal path). 1142 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n 1143 * CR MODE2 LL_DAC_GetOutputConnection 1144 * @param DACx DAC instance 1145 * @param DAC_Channel This parameter can be one of the following values: 1146 * @arg @ref LL_DAC_CHANNEL_1 1147 * @arg @ref LL_DAC_CHANNEL_2 1148 * @retval Returned value can be one of the following values: 1149 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 1150 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 1151 */ 1152 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1153 { 1154 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1155 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 1156 ); 1157 } 1158 1159 /** 1160 * @brief Set the sample-and-hold timing for the selected DAC channel: 1161 * sample time 1162 * @note Sample time must be set when DAC channel is disabled 1163 * or during DAC operation when DAC channel flag BWSTx is reset, 1164 * otherwise the setting is ignored. 1165 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". 1166 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n 1167 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime 1168 * @param DACx DAC instance 1169 * @param DAC_Channel This parameter can be one of the following values: 1170 * @arg @ref LL_DAC_CHANNEL_1 1171 * @arg @ref LL_DAC_CHANNEL_2 1172 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF 1173 * @retval None 1174 */ 1175 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) 1176 { 1177 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) 1178 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 1179 1180 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); 1181 } 1182 1183 /** 1184 * @brief Get the sample-and-hold timing for the selected DAC channel: 1185 * sample time 1186 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n 1187 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime 1188 * @param DACx DAC instance 1189 * @param DAC_Channel This parameter can be one of the following values: 1190 * @arg @ref LL_DAC_CHANNEL_1 1191 * @arg @ref LL_DAC_CHANNEL_2 1192 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 1193 */ 1194 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1195 { 1196 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) 1197 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 1198 1199 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); 1200 } 1201 1202 /** 1203 * @brief Set the sample-and-hold timing for the selected DAC channel: 1204 * hold time 1205 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n 1206 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime 1207 * @param DACx DAC instance 1208 * @param DAC_Channel This parameter can be one of the following values: 1209 * @arg @ref LL_DAC_CHANNEL_1 1210 * @arg @ref LL_DAC_CHANNEL_2 1211 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF 1212 * @retval None 1213 */ 1214 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime) 1215 { 1216 MODIFY_REG(DACx->SHHR, 1217 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1218 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1219 } 1220 1221 /** 1222 * @brief Get the sample-and-hold timing for the selected DAC channel: 1223 * hold time 1224 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n 1225 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime 1226 * @param DACx DAC instance 1227 * @param DAC_Channel This parameter can be one of the following values: 1228 * @arg @ref LL_DAC_CHANNEL_1 1229 * @arg @ref LL_DAC_CHANNEL_2 1230 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 1231 */ 1232 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1233 { 1234 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1235 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 1236 ); 1237 } 1238 1239 /** 1240 * @brief Set the sample-and-hold timing for the selected DAC channel: 1241 * refresh time 1242 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n 1243 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime 1244 * @param DACx DAC instance 1245 * @param DAC_Channel This parameter can be one of the following values: 1246 * @arg @ref LL_DAC_CHANNEL_1 1247 * @arg @ref LL_DAC_CHANNEL_2 1248 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF 1249 * @retval None 1250 */ 1251 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime) 1252 { 1253 MODIFY_REG(DACx->SHRR, 1254 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 1255 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1256 } 1257 1258 /** 1259 * @brief Get the sample-and-hold timing for the selected DAC channel: 1260 * refresh time 1261 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n 1262 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime 1263 * @param DACx DAC instance 1264 * @param DAC_Channel This parameter can be one of the following values: 1265 * @arg @ref LL_DAC_CHANNEL_1 1266 * @arg @ref LL_DAC_CHANNEL_2 1267 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 1268 */ 1269 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1270 { 1271 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1272 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 1273 ); 1274 } 1275 1276 /** 1277 * @} 1278 */ 1279 1280 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 1281 * @ingroup RTEMSBSPsARMSTM32H7 1282 * @{ 1283 */ 1284 1285 /** 1286 * @brief Enable DAC DMA transfer request of the selected channel. 1287 * @note To configure DMA source address (peripheral address), 1288 * use function @ref LL_DAC_DMA_GetRegAddr(). 1289 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 1290 * CR DMAEN2 LL_DAC_EnableDMAReq 1291 * @param DACx DAC instance 1292 * @param DAC_Channel This parameter can be one of the following values: 1293 * @arg @ref LL_DAC_CHANNEL_1 1294 * @arg @ref LL_DAC_CHANNEL_2 1295 * @retval None 1296 */ 1297 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1298 { 1299 SET_BIT(DACx->CR, 1300 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1301 } 1302 1303 /** 1304 * @brief Disable DAC DMA transfer request of the selected channel. 1305 * @note To configure DMA source address (peripheral address), 1306 * use function @ref LL_DAC_DMA_GetRegAddr(). 1307 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 1308 * CR DMAEN2 LL_DAC_DisableDMAReq 1309 * @param DACx DAC instance 1310 * @param DAC_Channel This parameter can be one of the following values: 1311 * @arg @ref LL_DAC_CHANNEL_1 1312 * @arg @ref LL_DAC_CHANNEL_2 1313 * @retval None 1314 */ 1315 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1316 { 1317 CLEAR_BIT(DACx->CR, 1318 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1319 } 1320 1321 /** 1322 * @brief Get DAC DMA transfer request state of the selected channel. 1323 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 1324 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 1325 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 1326 * @param DACx DAC instance 1327 * @param DAC_Channel This parameter can be one of the following values: 1328 * @arg @ref LL_DAC_CHANNEL_1 1329 * @arg @ref LL_DAC_CHANNEL_2 1330 * @retval State of bit (1 or 0). 1331 */ 1332 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1333 { 1334 return ((READ_BIT(DACx->CR, 1335 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1336 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 1337 } 1338 1339 /** 1340 * @brief Function to help to configure DMA transfer to DAC: retrieve the 1341 * DAC register address from DAC instance and a list of DAC registers 1342 * intended to be used (most commonly) with DMA transfer. 1343 * @note These DAC registers are data holding registers: 1344 * when DAC conversion is requested, DAC generates a DMA transfer 1345 * request to have data available in DAC data holding registers. 1346 * @note This macro is intended to be used with LL DMA driver, refer to 1347 * function "LL_DMA_ConfigAddresses()". 1348 * Example: 1349 * LL_DMA_ConfigAddresses(DMA1, 1350 * LL_DMA_CHANNEL_1, 1351 * (uint32_t)&< array or variable >, 1352 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, 1353 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 1354 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 1355 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 1356 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 1357 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 1358 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 1359 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 1360 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 1361 * @param DACx DAC instance 1362 * @param DAC_Channel This parameter can be one of the following values: 1363 * @arg @ref LL_DAC_CHANNEL_1 1364 * @arg @ref LL_DAC_CHANNEL_2 1365 * @param Register This parameter can be one of the following values: 1366 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 1367 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 1368 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 1369 * @retval DAC register address 1370 */ 1371 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 1372 { 1373 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 1374 /* DAC channel selected. */ 1375 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) 1376 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); 1377 } 1378 /** 1379 * @} 1380 */ 1381 1382 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 1383 * @ingroup RTEMSBSPsARMSTM32H7 1384 * @{ 1385 */ 1386 1387 /** 1388 * @brief Enable DAC selected channel. 1389 * @rmtoll CR EN1 LL_DAC_Enable\n 1390 * CR EN2 LL_DAC_Enable 1391 * @note After enable from off state, DAC channel requires a delay 1392 * for output voltage to reach accuracy +/- 1 LSB. 1393 * Refer to device datasheet, parameter "tWAKEUP". 1394 * @param DACx DAC instance 1395 * @param DAC_Channel This parameter can be one of the following values: 1396 * @arg @ref LL_DAC_CHANNEL_1 1397 * @arg @ref LL_DAC_CHANNEL_2 1398 * @retval None 1399 */ 1400 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1401 { 1402 SET_BIT(DACx->CR, 1403 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1404 } 1405 1406 /** 1407 * @brief Disable DAC selected channel. 1408 * @rmtoll CR EN1 LL_DAC_Disable\n 1409 * CR EN2 LL_DAC_Disable 1410 * @param DACx DAC instance 1411 * @param DAC_Channel This parameter can be one of the following values: 1412 * @arg @ref LL_DAC_CHANNEL_1 1413 * @arg @ref LL_DAC_CHANNEL_2 1414 * @retval None 1415 */ 1416 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1417 { 1418 CLEAR_BIT(DACx->CR, 1419 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1420 } 1421 1422 /** 1423 * @brief Get DAC enable state of the selected channel. 1424 * (0: DAC channel is disabled, 1: DAC channel is enabled) 1425 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 1426 * CR EN2 LL_DAC_IsEnabled 1427 * @param DACx DAC instance 1428 * @param DAC_Channel This parameter can be one of the following values: 1429 * @arg @ref LL_DAC_CHANNEL_1 1430 * @arg @ref LL_DAC_CHANNEL_2 1431 * @retval State of bit (1 or 0). 1432 */ 1433 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1434 { 1435 return ((READ_BIT(DACx->CR, 1436 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1437 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 1438 } 1439 1440 /** 1441 * @brief Enable DAC trigger of the selected channel. 1442 * @note - If DAC trigger is disabled, DAC conversion is performed 1443 * automatically once the data holding register is updated, 1444 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 1445 * @ref LL_DAC_ConvertData12RightAligned(), ... 1446 * - If DAC trigger is enabled, DAC conversion is performed 1447 * only when a hardware of software trigger event is occurring. 1448 * Select trigger source using 1449 * function @ref LL_DAC_SetTriggerSource(). 1450 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 1451 * CR TEN2 LL_DAC_EnableTrigger 1452 * @param DACx DAC instance 1453 * @param DAC_Channel This parameter can be one of the following values: 1454 * @arg @ref LL_DAC_CHANNEL_1 1455 * @arg @ref LL_DAC_CHANNEL_2 1456 * @retval None 1457 */ 1458 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1459 { 1460 SET_BIT(DACx->CR, 1461 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1462 } 1463 1464 /** 1465 * @brief Disable DAC trigger of the selected channel. 1466 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 1467 * CR TEN2 LL_DAC_DisableTrigger 1468 * @param DACx DAC instance 1469 * @param DAC_Channel This parameter can be one of the following values: 1470 * @arg @ref LL_DAC_CHANNEL_1 1471 * @arg @ref LL_DAC_CHANNEL_2 1472 * @retval None 1473 */ 1474 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1475 { 1476 CLEAR_BIT(DACx->CR, 1477 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 1478 } 1479 1480 /** 1481 * @brief Get DAC trigger state of the selected channel. 1482 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 1483 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 1484 * CR TEN2 LL_DAC_IsTriggerEnabled 1485 * @param DACx DAC instance 1486 * @param DAC_Channel This parameter can be one of the following values: 1487 * @arg @ref LL_DAC_CHANNEL_1 1488 * @arg @ref LL_DAC_CHANNEL_2 1489 * @retval State of bit (1 or 0). 1490 */ 1491 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1492 { 1493 return ((READ_BIT(DACx->CR, 1494 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 1495 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 1496 } 1497 1498 /** 1499 * @brief Trig DAC conversion by software for the selected DAC channel. 1500 * @note Preliminarily, DAC trigger must be set to software trigger 1501 * using function 1502 * @ref LL_DAC_Init() 1503 * @ref LL_DAC_SetTriggerSource() 1504 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 1505 * and DAC trigger must be enabled using 1506 * function @ref LL_DAC_EnableTrigger(). 1507 * @note For devices featuring DAC with 2 channels: this function 1508 * can perform a SW start of both DAC channels simultaneously. 1509 * Two channels can be selected as parameter. 1510 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 1511 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 1512 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 1513 * @param DACx DAC instance 1514 * @param DAC_Channel This parameter can a combination of the following values: 1515 * @arg @ref LL_DAC_CHANNEL_1 1516 * @arg @ref LL_DAC_CHANNEL_2 1517 * @retval None 1518 */ 1519 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 1520 { 1521 SET_BIT(DACx->SWTRIGR, 1522 (DAC_Channel & DAC_SWTR_CHX_MASK)); 1523 } 1524 1525 /** 1526 * @brief Set the data to be loaded in the data holding register 1527 * in format 12 bits left alignment (LSB aligned on bit 0), 1528 * for the selected DAC channel. 1529 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 1530 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 1531 * @param DACx DAC instance 1532 * @param DAC_Channel This parameter can be one of the following values: 1533 * @arg @ref LL_DAC_CHANNEL_1 1534 * @arg @ref LL_DAC_CHANNEL_2 1535 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 1536 * @retval None 1537 */ 1538 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 1539 { 1540 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) 1541 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 1542 1543 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); 1544 } 1545 1546 /** 1547 * @brief Set the data to be loaded in the data holding register 1548 * in format 12 bits left alignment (MSB aligned on bit 15), 1549 * for the selected DAC channel. 1550 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 1551 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 1552 * @param DACx DAC instance 1553 * @param DAC_Channel This parameter can be one of the following values: 1554 * @arg @ref LL_DAC_CHANNEL_1 1555 * @arg @ref LL_DAC_CHANNEL_2 1556 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 1557 * @retval None 1558 */ 1559 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 1560 { 1561 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) 1562 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 1563 1564 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); 1565 } 1566 1567 /** 1568 * @brief Set the data to be loaded in the data holding register 1569 * in format 8 bits left alignment (LSB aligned on bit 0), 1570 * for the selected DAC channel. 1571 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 1572 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 1573 * @param DACx DAC instance 1574 * @param DAC_Channel This parameter can be one of the following values: 1575 * @arg @ref LL_DAC_CHANNEL_1 1576 * @arg @ref LL_DAC_CHANNEL_2 1577 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 1578 * @retval None 1579 */ 1580 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 1581 { 1582 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) 1583 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 1584 1585 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); 1586 } 1587 1588 1589 /** 1590 * @brief Set the data to be loaded in the data holding register 1591 * in format 12 bits left alignment (LSB aligned on bit 0), 1592 * for both DAC channels. 1593 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 1594 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 1595 * @param DACx DAC instance 1596 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 1597 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 1598 * @retval None 1599 */ 1600 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 1601 uint32_t DataChannel2) 1602 { 1603 MODIFY_REG(DACx->DHR12RD, 1604 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 1605 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 1606 } 1607 1608 /** 1609 * @brief Set the data to be loaded in the data holding register 1610 * in format 12 bits left alignment (MSB aligned on bit 15), 1611 * for both DAC channels. 1612 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 1613 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 1614 * @param DACx DAC instance 1615 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 1616 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 1617 * @retval None 1618 */ 1619 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 1620 uint32_t DataChannel2) 1621 { 1622 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 1623 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 1624 /* the 4 LSB must be taken into account for the shift value. */ 1625 MODIFY_REG(DACx->DHR12LD, 1626 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 1627 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 1628 } 1629 1630 /** 1631 * @brief Set the data to be loaded in the data holding register 1632 * in format 8 bits left alignment (LSB aligned on bit 0), 1633 * for both DAC channels. 1634 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 1635 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 1636 * @param DACx DAC instance 1637 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 1638 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 1639 * @retval None 1640 */ 1641 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 1642 uint32_t DataChannel2) 1643 { 1644 MODIFY_REG(DACx->DHR8RD, 1645 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 1646 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 1647 } 1648 1649 1650 /** 1651 * @brief Retrieve output data currently generated for the selected DAC channel. 1652 * @note Whatever alignment and resolution settings 1653 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 1654 * @ref LL_DAC_ConvertData12RightAligned(), ...), 1655 * output data format is 12 bits right aligned (LSB aligned on bit 0). 1656 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 1657 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 1658 * @param DACx DAC instance 1659 * @param DAC_Channel This parameter can be one of the following values: 1660 * @arg @ref LL_DAC_CHANNEL_1 1661 * @arg @ref LL_DAC_CHANNEL_2 1662 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1663 */ 1664 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) 1665 { 1666 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) 1667 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); 1668 1669 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 1670 } 1671 1672 /** 1673 * @} 1674 */ 1675 1676 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 1677 * @ingroup RTEMSBSPsARMSTM32H7 1678 * @{ 1679 */ 1680 1681 /** 1682 * @brief Get DAC calibration offset flag for DAC channel 1 1683 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 1684 * @param DACx DAC instance 1685 * @retval State of bit (1 or 0). 1686 */ 1687 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx) 1688 { 1689 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); 1690 } 1691 1692 1693 /** 1694 * @brief Get DAC calibration offset flag for DAC channel 2 1695 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 1696 * @param DACx DAC instance 1697 * @retval State of bit (1 or 0). 1698 */ 1699 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx) 1700 { 1701 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); 1702 } 1703 1704 1705 /** 1706 * @brief Get DAC busy writing sample time flag for DAC channel 1 1707 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1 1708 * @param DACx DAC instance 1709 * @retval State of bit (1 or 0). 1710 */ 1711 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx) 1712 { 1713 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); 1714 } 1715 1716 /** 1717 * @brief Get DAC busy writing sample time flag for DAC channel 2 1718 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 1719 * @param DACx DAC instance 1720 * @retval State of bit (1 or 0). 1721 */ 1722 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx) 1723 { 1724 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); 1725 } 1726 1727 1728 /** 1729 * @brief Get DAC underrun flag for DAC channel 1 1730 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 1731 * @param DACx DAC instance 1732 * @retval State of bit (1 or 0). 1733 */ 1734 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) 1735 { 1736 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); 1737 } 1738 1739 1740 /** 1741 * @brief Get DAC underrun flag for DAC channel 2 1742 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 1743 * @param DACx DAC instance 1744 * @retval State of bit (1 or 0). 1745 */ 1746 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) 1747 { 1748 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); 1749 } 1750 1751 1752 /** 1753 * @brief Clear DAC underrun flag for DAC channel 1 1754 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 1755 * @param DACx DAC instance 1756 * @retval None 1757 */ 1758 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 1759 { 1760 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 1761 } 1762 1763 1764 /** 1765 * @brief Clear DAC underrun flag for DAC channel 2 1766 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 1767 * @param DACx DAC instance 1768 * @retval None 1769 */ 1770 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 1771 { 1772 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 1773 } 1774 1775 1776 /** 1777 * @} 1778 */ 1779 1780 /** @defgroup DAC_LL_EF_IT_Management IT management 1781 * @ingroup RTEMSBSPsARMSTM32H7 1782 * @{ 1783 */ 1784 1785 /** 1786 * @brief Enable DMA underrun interrupt for DAC channel 1 1787 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 1788 * @param DACx DAC instance 1789 * @retval None 1790 */ 1791 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 1792 { 1793 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 1794 } 1795 1796 1797 /** 1798 * @brief Enable DMA underrun interrupt for DAC channel 2 1799 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 1800 * @param DACx DAC instance 1801 * @retval None 1802 */ 1803 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 1804 { 1805 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 1806 } 1807 1808 1809 /** 1810 * @brief Disable DMA underrun interrupt for DAC channel 1 1811 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 1812 * @param DACx DAC instance 1813 * @retval None 1814 */ 1815 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 1816 { 1817 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 1818 } 1819 1820 1821 /** 1822 * @brief Disable DMA underrun interrupt for DAC channel 2 1823 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 1824 * @param DACx DAC instance 1825 * @retval None 1826 */ 1827 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 1828 { 1829 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 1830 } 1831 1832 1833 /** 1834 * @brief Get DMA underrun interrupt for DAC channel 1 1835 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 1836 * @param DACx DAC instance 1837 * @retval State of bit (1 or 0). 1838 */ 1839 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) 1840 { 1841 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); 1842 } 1843 1844 1845 /** 1846 * @brief Get DMA underrun interrupt for DAC channel 2 1847 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 1848 * @param DACx DAC instance 1849 * @retval State of bit (1 or 0). 1850 */ 1851 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) 1852 { 1853 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); 1854 } 1855 1856 1857 /** 1858 * @} 1859 */ 1860 1861 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 1862 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 1863 * @ingroup RTEMSBSPsARMSTM32H7 1864 * @{ 1865 */ 1866 1867 ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); 1868 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); 1869 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); 1870 1871 /** 1872 * @} 1873 */ 1874 #endif /* USE_FULL_LL_DRIVER */ 1875 1876 /** 1877 * @} 1878 */ 1879 1880 /** 1881 * @} 1882 */ 1883 1884 #endif /* DAC1 || DAC2 */ 1885 1886 /** 1887 * @} 1888 */ 1889 1890 #ifdef __cplusplus 1891 } 1892 #endif 1893 1894 #endif /* STM32H7xx_LL_DAC_H */
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