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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_crs.h 0004 * @author MCD Application Team 0005 * @brief Header file of CRS LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_CRS_H 0021 #define STM32H7xx_LL_CRS_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 0030 /** @addtogroup STM32H7xx_LL_Driver 0031 * @{ 0032 */ 0033 0034 #if defined(CRS) 0035 0036 /** @defgroup CRS_LL CRS 0037 * @ingroup RTEMSBSPsARMSTM32H7 0038 * @{ 0039 */ 0040 0041 /* Private types -------------------------------------------------------------*/ 0042 /* Private variables ---------------------------------------------------------*/ 0043 /* Private constants ---------------------------------------------------------*/ 0044 /* Private macros ------------------------------------------------------------*/ 0045 0046 /* Exported types ------------------------------------------------------------*/ 0047 /* Exported constants --------------------------------------------------------*/ 0048 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants 0049 * @ingroup RTEMSBSPsARMSTM32H7 0050 * @{ 0051 */ 0052 0053 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines 0054 * @ingroup RTEMSBSPsARMSTM32H7 0055 * @brief Flags defines which can be used with LL_CRS_ReadReg function 0056 * @{ 0057 */ 0058 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF 0059 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF 0060 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF 0061 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF 0062 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR 0063 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS 0064 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF 0065 /** 0066 * @} 0067 */ 0068 0069 /** @defgroup CRS_LL_EC_IT IT Defines 0070 * @ingroup RTEMSBSPsARMSTM32H7 0071 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions 0072 * @{ 0073 */ 0074 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE 0075 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE 0076 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE 0077 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE 0078 /** 0079 * @} 0080 */ 0081 0082 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider 0083 * @ingroup RTEMSBSPsARMSTM32H7 0084 * @{ 0085 */ 0086 #define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ 0087 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 0088 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 0089 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 0090 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 0091 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 0092 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 0093 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 0094 /** 0095 * @} 0096 */ 0097 0098 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source 0099 * @ingroup RTEMSBSPsARMSTM32H7 0100 * @{ 0101 */ 0102 #define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ 0103 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 0104 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 0105 /** 0106 * @} 0107 */ 0108 0109 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity 0110 * @ingroup RTEMSBSPsARMSTM32H7 0111 * @{ 0112 */ 0113 #define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ 0114 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 0115 /** 0116 * @} 0117 */ 0118 0119 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction 0120 * @ingroup RTEMSBSPsARMSTM32H7 0121 * @{ 0122 */ 0123 #define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ 0124 #define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ 0125 /** 0126 * @} 0127 */ 0128 0129 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values 0130 * @ingroup RTEMSBSPsARMSTM32H7 0131 * @{ 0132 */ 0133 /** 0134 * @brief Reset value of the RELOAD field 0135 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz 0136 * and a synchronization signal frequency of 1 kHz (SOF signal from USB) 0137 */ 0138 #define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU 0139 0140 /** 0141 * @brief Reset value of Frequency error limit. 0142 */ 0143 #define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U 0144 0145 /** 0146 * @brief Reset value of the HSI48 Calibration field 0147 * @note The default value is 64, which corresponds to the middle of the trimming interval. 0148 * The trimming step is specified in the product datasheet. 0149 * A higher TRIM value corresponds to a higher output frequency. 0150 */ 0151 #define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U 0152 /** 0153 * @} 0154 */ 0155 0156 /** 0157 * @} 0158 */ 0159 0160 /* Exported macro ------------------------------------------------------------*/ 0161 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros 0162 * @ingroup RTEMSBSPsARMSTM32H7 0163 * @{ 0164 */ 0165 0166 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros 0167 * @ingroup RTEMSBSPsARMSTM32H7 0168 * @{ 0169 */ 0170 0171 /** 0172 * @brief Write a value in CRS register 0173 * @param __INSTANCE__ CRS Instance 0174 * @param __REG__ Register to be written 0175 * @param __VALUE__ Value to be written in the register 0176 * @retval None 0177 */ 0178 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 0179 0180 /** 0181 * @brief Read a value in CRS register 0182 * @param __INSTANCE__ CRS Instance 0183 * @param __REG__ Register to be read 0184 * @retval Register value 0185 */ 0186 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0187 /** 0188 * @} 0189 */ 0190 0191 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload 0192 * @ingroup RTEMSBSPsARMSTM32H7 0193 * @{ 0194 */ 0195 0196 /** 0197 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 0198 * @note The RELOAD value should be selected according to the ratio between 0199 * the target frequency and the frequency of the synchronization source after 0200 * prescaling. It is then decreased by one in order to reach the expected 0201 * synchronization on the zero value. The formula is the following: 0202 * RELOAD = (fTARGET / fSYNC) -1 0203 * @param __FTARGET__ Target frequency (value in Hz) 0204 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 0205 * @retval Reload value (in Hz) 0206 */ 0207 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 0208 0209 /** 0210 * @} 0211 */ 0212 0213 /** 0214 * @} 0215 */ 0216 0217 /* Exported functions --------------------------------------------------------*/ 0218 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions 0219 * @ingroup RTEMSBSPsARMSTM32H7 0220 * @{ 0221 */ 0222 0223 /** @defgroup CRS_LL_EF_Configuration Configuration 0224 * @ingroup RTEMSBSPsARMSTM32H7 0225 * @{ 0226 */ 0227 0228 /** 0229 * @brief Enable Frequency error counter 0230 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified 0231 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter 0232 * @retval None 0233 */ 0234 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) 0235 { 0236 SET_BIT(CRS->CR, CRS_CR_CEN); 0237 } 0238 0239 /** 0240 * @brief Disable Frequency error counter 0241 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter 0242 * @retval None 0243 */ 0244 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) 0245 { 0246 CLEAR_BIT(CRS->CR, CRS_CR_CEN); 0247 } 0248 0249 /** 0250 * @brief Check if Frequency error counter is enabled or not 0251 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter 0252 * @retval State of bit (1 or 0). 0253 */ 0254 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) 0255 { 0256 return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); 0257 } 0258 0259 /** 0260 * @brief Enable Automatic trimming counter 0261 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming 0262 * @retval None 0263 */ 0264 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) 0265 { 0266 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); 0267 } 0268 0269 /** 0270 * @brief Disable Automatic trimming counter 0271 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming 0272 * @retval None 0273 */ 0274 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) 0275 { 0276 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); 0277 } 0278 0279 /** 0280 * @brief Check if Automatic trimming is enabled or not 0281 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming 0282 * @retval State of bit (1 or 0). 0283 */ 0284 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) 0285 { 0286 return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); 0287 } 0288 0289 /** 0290 * @brief Set HSI48 oscillator smooth trimming 0291 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only 0292 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming 0293 * @param Value a number between Min_Data = 0 and Max_Data = 127 0294 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 0295 * @retval None 0296 */ 0297 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) 0298 { 0299 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); 0300 } 0301 0302 /** 0303 * @brief Get HSI48 oscillator smooth trimming 0304 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming 0305 * @retval a number between Min_Data = 0 and Max_Data = 127 0306 */ 0307 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) 0308 { 0309 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); 0310 } 0311 0312 /** 0313 * @brief Set counter reload value 0314 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter 0315 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF 0316 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 0317 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) 0318 * @retval None 0319 */ 0320 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) 0321 { 0322 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); 0323 } 0324 0325 /** 0326 * @brief Get counter reload value 0327 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter 0328 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF 0329 */ 0330 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) 0331 { 0332 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); 0333 } 0334 0335 /** 0336 * @brief Set frequency error limit 0337 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit 0338 * @param Value a number between Min_Data = 0 and Max_Data = 255 0339 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 0340 * @retval None 0341 */ 0342 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) 0343 { 0344 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); 0345 } 0346 0347 /** 0348 * @brief Get frequency error limit 0349 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit 0350 * @retval A number between Min_Data = 0 and Max_Data = 255 0351 */ 0352 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) 0353 { 0354 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); 0355 } 0356 0357 /** 0358 * @brief Set division factor for SYNC signal 0359 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider 0360 * @param Divider This parameter can be one of the following values: 0361 * @arg @ref LL_CRS_SYNC_DIV_1 0362 * @arg @ref LL_CRS_SYNC_DIV_2 0363 * @arg @ref LL_CRS_SYNC_DIV_4 0364 * @arg @ref LL_CRS_SYNC_DIV_8 0365 * @arg @ref LL_CRS_SYNC_DIV_16 0366 * @arg @ref LL_CRS_SYNC_DIV_32 0367 * @arg @ref LL_CRS_SYNC_DIV_64 0368 * @arg @ref LL_CRS_SYNC_DIV_128 0369 * @retval None 0370 */ 0371 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) 0372 { 0373 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); 0374 } 0375 0376 /** 0377 * @brief Get division factor for SYNC signal 0378 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider 0379 * @retval Returned value can be one of the following values: 0380 * @arg @ref LL_CRS_SYNC_DIV_1 0381 * @arg @ref LL_CRS_SYNC_DIV_2 0382 * @arg @ref LL_CRS_SYNC_DIV_4 0383 * @arg @ref LL_CRS_SYNC_DIV_8 0384 * @arg @ref LL_CRS_SYNC_DIV_16 0385 * @arg @ref LL_CRS_SYNC_DIV_32 0386 * @arg @ref LL_CRS_SYNC_DIV_64 0387 * @arg @ref LL_CRS_SYNC_DIV_128 0388 */ 0389 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) 0390 { 0391 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); 0392 } 0393 0394 /** 0395 * @brief Set SYNC signal source 0396 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource 0397 * @param Source This parameter can be one of the following values: 0398 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO 0399 * @arg @ref LL_CRS_SYNC_SOURCE_LSE 0400 * @arg @ref LL_CRS_SYNC_SOURCE_USB 0401 * @retval None 0402 */ 0403 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) 0404 { 0405 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); 0406 } 0407 0408 /** 0409 * @brief Get SYNC signal source 0410 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource 0411 * @retval Returned value can be one of the following values: 0412 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO 0413 * @arg @ref LL_CRS_SYNC_SOURCE_LSE 0414 * @arg @ref LL_CRS_SYNC_SOURCE_USB 0415 */ 0416 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) 0417 { 0418 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); 0419 } 0420 0421 /** 0422 * @brief Set input polarity for the SYNC signal source 0423 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity 0424 * @param Polarity This parameter can be one of the following values: 0425 * @arg @ref LL_CRS_SYNC_POLARITY_RISING 0426 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING 0427 * @retval None 0428 */ 0429 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) 0430 { 0431 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); 0432 } 0433 0434 /** 0435 * @brief Get input polarity for the SYNC signal source 0436 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity 0437 * @retval Returned value can be one of the following values: 0438 * @arg @ref LL_CRS_SYNC_POLARITY_RISING 0439 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING 0440 */ 0441 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) 0442 { 0443 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); 0444 } 0445 0446 /** 0447 * @brief Configure CRS for the synchronization 0448 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n 0449 * CFGR RELOAD LL_CRS_ConfigSynchronization\n 0450 * CFGR FELIM LL_CRS_ConfigSynchronization\n 0451 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n 0452 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n 0453 * CFGR SYNCPOL LL_CRS_ConfigSynchronization 0454 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 0455 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF 0456 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 0457 * @param Settings This parameter can be a combination of the following values: 0458 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 0459 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 0460 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB 0461 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING 0462 * @retval None 0463 */ 0464 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) 0465 { 0466 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); 0467 MODIFY_REG(CRS->CFGR, 0468 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 0469 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); 0470 } 0471 0472 /** 0473 * @} 0474 */ 0475 0476 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management 0477 * @ingroup RTEMSBSPsARMSTM32H7 0478 * @{ 0479 */ 0480 0481 /** 0482 * @brief Generate software SYNC event 0483 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC 0484 * @retval None 0485 */ 0486 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) 0487 { 0488 SET_BIT(CRS->CR, CRS_CR_SWSYNC); 0489 } 0490 0491 /** 0492 * @brief Get the frequency error direction latched in the time of the last 0493 * SYNC event 0494 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection 0495 * @retval Returned value can be one of the following values: 0496 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP 0497 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN 0498 */ 0499 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) 0500 { 0501 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); 0502 } 0503 0504 /** 0505 * @brief Get the frequency error counter value latched in the time of the last SYNC event 0506 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture 0507 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF 0508 */ 0509 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) 0510 { 0511 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); 0512 } 0513 0514 /** 0515 * @} 0516 */ 0517 0518 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management 0519 * @ingroup RTEMSBSPsARMSTM32H7 0520 * @{ 0521 */ 0522 0523 /** 0524 * @brief Check if SYNC event OK signal occurred or not 0525 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK 0526 * @retval State of bit (1 or 0). 0527 */ 0528 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) 0529 { 0530 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); 0531 } 0532 0533 /** 0534 * @brief Check if SYNC warning signal occurred or not 0535 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN 0536 * @retval State of bit (1 or 0). 0537 */ 0538 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) 0539 { 0540 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); 0541 } 0542 0543 /** 0544 * @brief Check if Synchronization or trimming error signal occurred or not 0545 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR 0546 * @retval State of bit (1 or 0). 0547 */ 0548 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) 0549 { 0550 return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); 0551 } 0552 0553 /** 0554 * @brief Check if Expected SYNC signal occurred or not 0555 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC 0556 * @retval State of bit (1 or 0). 0557 */ 0558 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) 0559 { 0560 return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); 0561 } 0562 0563 /** 0564 * @brief Check if SYNC error signal occurred or not 0565 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR 0566 * @retval State of bit (1 or 0). 0567 */ 0568 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) 0569 { 0570 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); 0571 } 0572 0573 /** 0574 * @brief Check if SYNC missed error signal occurred or not 0575 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS 0576 * @retval State of bit (1 or 0). 0577 */ 0578 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) 0579 { 0580 return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); 0581 } 0582 0583 /** 0584 * @brief Check if Trimming overflow or underflow occurred or not 0585 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF 0586 * @retval State of bit (1 or 0). 0587 */ 0588 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) 0589 { 0590 return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); 0591 } 0592 0593 /** 0594 * @brief Clear the SYNC event OK flag 0595 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK 0596 * @retval None 0597 */ 0598 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) 0599 { 0600 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); 0601 } 0602 0603 /** 0604 * @brief Clear the SYNC warning flag 0605 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN 0606 * @retval None 0607 */ 0608 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) 0609 { 0610 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); 0611 } 0612 0613 /** 0614 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 0615 * the ERR flag 0616 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR 0617 * @retval None 0618 */ 0619 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) 0620 { 0621 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); 0622 } 0623 0624 /** 0625 * @brief Clear Expected SYNC flag 0626 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC 0627 * @retval None 0628 */ 0629 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) 0630 { 0631 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); 0632 } 0633 0634 /** 0635 * @} 0636 */ 0637 0638 /** @defgroup CRS_LL_EF_IT_Management IT_Management 0639 * @ingroup RTEMSBSPsARMSTM32H7 0640 * @{ 0641 */ 0642 0643 /** 0644 * @brief Enable SYNC event OK interrupt 0645 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK 0646 * @retval None 0647 */ 0648 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) 0649 { 0650 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); 0651 } 0652 0653 /** 0654 * @brief Disable SYNC event OK interrupt 0655 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK 0656 * @retval None 0657 */ 0658 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) 0659 { 0660 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); 0661 } 0662 0663 /** 0664 * @brief Check if SYNC event OK interrupt is enabled or not 0665 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK 0666 * @retval State of bit (1 or 0). 0667 */ 0668 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) 0669 { 0670 return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); 0671 } 0672 0673 /** 0674 * @brief Enable SYNC warning interrupt 0675 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN 0676 * @retval None 0677 */ 0678 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) 0679 { 0680 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); 0681 } 0682 0683 /** 0684 * @brief Disable SYNC warning interrupt 0685 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN 0686 * @retval None 0687 */ 0688 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) 0689 { 0690 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); 0691 } 0692 0693 /** 0694 * @brief Check if SYNC warning interrupt is enabled or not 0695 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN 0696 * @retval State of bit (1 or 0). 0697 */ 0698 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) 0699 { 0700 return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); 0701 } 0702 0703 /** 0704 * @brief Enable Synchronization or trimming error interrupt 0705 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR 0706 * @retval None 0707 */ 0708 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void) 0709 { 0710 SET_BIT(CRS->CR, CRS_CR_ERRIE); 0711 } 0712 0713 /** 0714 * @brief Disable Synchronization or trimming error interrupt 0715 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR 0716 * @retval None 0717 */ 0718 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void) 0719 { 0720 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); 0721 } 0722 0723 /** 0724 * @brief Check if Synchronization or trimming error interrupt is enabled or not 0725 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR 0726 * @retval State of bit (1 or 0). 0727 */ 0728 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) 0729 { 0730 return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); 0731 } 0732 0733 /** 0734 * @brief Enable Expected SYNC interrupt 0735 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC 0736 * @retval None 0737 */ 0738 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) 0739 { 0740 SET_BIT(CRS->CR, CRS_CR_ESYNCIE); 0741 } 0742 0743 /** 0744 * @brief Disable Expected SYNC interrupt 0745 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC 0746 * @retval None 0747 */ 0748 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) 0749 { 0750 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); 0751 } 0752 0753 /** 0754 * @brief Check if Expected SYNC interrupt is enabled or not 0755 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC 0756 * @retval State of bit (1 or 0). 0757 */ 0758 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) 0759 { 0760 return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); 0761 } 0762 0763 /** 0764 * @} 0765 */ 0766 0767 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0768 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions 0769 * @ingroup RTEMSBSPsARMSTM32H7 0770 * @{ 0771 */ 0772 0773 ErrorStatus LL_CRS_DeInit(void); 0774 0775 /** 0776 * @} 0777 */ 0778 #endif /* USE_FULL_LL_DRIVER */ 0779 0780 /** 0781 * @} 0782 */ 0783 0784 /** 0785 * @} 0786 */ 0787 0788 #endif /* defined(CRS) */ 0789 0790 /** 0791 * @} 0792 */ 0793 0794 #ifdef __cplusplus 0795 } 0796 #endif 0797 0798 #endif /* STM32H7xx_LL_CRS_H */
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