stm32h7/include/stm32h7xx_ll_cortex.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_cortex.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of CORTEX LL module.
0006   @verbatim
0007   ==============================================================================
0008                      ##### How to use this driver #####
0009   ==============================================================================
0010     [..]
0011     The LL CORTEX driver contains a set of generic APIs that can be
0012     used by user:
0013       (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
0014           functions
0015       (+) Low power mode configuration (SCB register of Cortex-MCU)
0016       (+) MPU API to configure and enable regions
0017       (+) API to access to MCU info (CPUID register)
0018       (+) API to enable fault handler (SHCSR accesses)
0019
0020   @endverbatim
0021   ******************************************************************************
0022   * @attention
0023   *
0024   * Copyright (c) 2017 STMicroelectronics.
0025   * All rights reserved.
0026   *
0027   * This software is licensed under terms that can be found in the LICENSE file in
0028   * the root directory of this software component.
0029   * If no LICENSE file comes with this software, it is provided AS-IS.
0030   *
0031   ******************************************************************************
0032   */
0033
0034 /* Define to prevent recursive inclusion -------------------------------------*/
0035 #ifndef STM32H7xx_LL_CORTEX_H
0036 #define STM32H7xx_LL_CORTEX_H
0037
0038 #ifdef __cplusplus
0039 extern "C" {
0040 #endif
0041
0042 /* Includes ------------------------------------------------------------------*/
0043 #include "stm32h7xx.h"
0044
0045 /** @addtogroup STM32H7xx_LL_Driver
0046   * @{
0047   */
0048
0049 /** @defgroup CORTEX_LL CORTEX
0050   * @ingroup RTEMSBSPsARMSTM32H7
0051   * @{
0052   */
0053
0054 /* Private types -------------------------------------------------------------*/
0055 /* Private variables ---------------------------------------------------------*/
0056
0057 /* Private constants ---------------------------------------------------------*/
0058
0059 /* Private macros ------------------------------------------------------------*/
0060
0061 /* Exported types ------------------------------------------------------------*/
0062 /* Exported constants --------------------------------------------------------*/
0063 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
0064   * @ingroup RTEMSBSPsARMSTM32H7
0065   * @{
0066   */
0067
0068 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
0069   * @ingroup RTEMSBSPsARMSTM32H7
0070   * @{
0071   */
0072 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/
0073 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
0074 /**
0075   * @}
0076   */
0077
0078 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
0079   * @ingroup RTEMSBSPsARMSTM32H7
0080   * @{
0081   */
0082 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
0083 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
0084 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
0085 /**
0086   * @}
0087   */
0088
0089 #if __MPU_PRESENT
0090
0091 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
0092   * @ingroup RTEMSBSPsARMSTM32H7
0093   * @{
0094   */
0095 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */
0096 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
0097 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
0098 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
0099 /**
0100   * @}
0101   */
0102
0103 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
0104   * @ingroup RTEMSBSPsARMSTM32H7
0105   * @{
0106   */
0107 #define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */
0108 #define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */
0109 #define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */
0110 #define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */
0111 #define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */
0112 #define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */
0113 #define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */
0114 #define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */
0115 #if !defined(CORE_CM4)
0116 #define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */
0117 #define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */
0118 #define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */
0119 #define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */
0120 #define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */
0121 #define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */
0122 #define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */
0123 #define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */
0124 #endif /* !defined(CORE_CM4) */
0125 /**
0126   * @}
0127   */
0128
0129 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
0130   * @ingroup RTEMSBSPsARMSTM32H7
0131   * @{
0132   */
0133 #define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
0134 #define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
0135 #define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
0136 #define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
0137 #define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
0138 #define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
0139 #define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
0140 #define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
0141 #define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
0142 #define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
0143 #define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
0144 #define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
0145 #define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
0146 #define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
0147 #define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
0148 #define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
0149 #define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
0150 #define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
0151 #define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
0152 #define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
0153 #define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
0154 #define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
0155 #define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
0156 #define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
0157 #define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
0158 #define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
0159 #define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
0160 #define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
0161 /**
0162   * @}
0163   */
0164
0165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
0166   * @ingroup RTEMSBSPsARMSTM32H7
0167   * @{
0168   */
0169 #define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
0170 #define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
0171 #define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
0172 #define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
0173 #define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
0174 #define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
0175 /**
0176   * @}
0177   */
0178
0179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
0180   * @ingroup RTEMSBSPsARMSTM32H7
0181   * @{
0182   */
0183 #define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
0184 #define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
0185 #define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
0186
0187 /* Legacy Define */
0188 #define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
0189 /**
0190   * @}
0191   */
0192
0193 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
0194   * @ingroup RTEMSBSPsARMSTM32H7
0195   * @{
0196   */
0197 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */
0198 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
0199 /**
0200   * @}
0201   */
0202
0203 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
0204   * @ingroup RTEMSBSPsARMSTM32H7
0205   * @{
0206   */
0207 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
0208 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */
0209 /**
0210   * @}
0211   */
0212
0213 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
0214   * @ingroup RTEMSBSPsARMSTM32H7
0215   * @{
0216   */
0217 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
0218 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */
0219 /**
0220   * @}
0221   */
0222
0223 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
0224   * @ingroup RTEMSBSPsARMSTM32H7
0225   * @{
0226   */
0227 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
0228 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */
0229 /**
0230   * @}
0231   */
0232 #endif /* __MPU_PRESENT */
0233 /**
0234   * @}
0235   */
0236
0237 /* Exported macro ------------------------------------------------------------*/
0238
0239 /* Exported functions --------------------------------------------------------*/
0240 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
0241   * @ingroup RTEMSBSPsARMSTM32H7
0242   * @{
0243   */
0244
0245 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
0246   * @ingroup RTEMSBSPsARMSTM32H7
0247   * @{
0248   */
0249
0250 /**
0251   * @brief  This function checks if the Systick counter flag is active or not.
0252   * @note   It can be used in timeout function on application side.
0253   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
0254   * @retval State of bit (1 or 0).
0255   */
0256 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
0257 {
0258   return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
0259 }
0260
0261 /**
0262   * @brief  Configures the SysTick clock source
0263   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
0264   * @param  Source This parameter can be one of the following values:
0265   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
0266   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
0267   * @retval None
0268   */
0269 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
0270 {
0271   MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
0272 }
0273
0274 /**
0275   * @brief  Get the SysTick clock source
0276   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
0277   * @retval Returned value can be one of the following values:
0278   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
0279   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
0280   */
0281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
0282 {
0283   return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
0284 }
0285
0286 /**
0287   * @brief  Enable SysTick exception request
0288   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
0289   * @retval None
0290   */
0291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
0292 {
0293   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
0294 }
0295
0296 /**
0297   * @brief  Disable SysTick exception request
0298   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
0299   * @retval None
0300   */
0301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
0302 {
0303   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
0304 }
0305
0306 /**
0307   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
0308   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
0309   * @retval State of bit (1 or 0).
0310   */
0311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
0312 {
0313   return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
0314 }
0315
0316 /**
0317   * @}
0318   */
0319
0320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
0321   * @ingroup RTEMSBSPsARMSTM32H7
0322   * @{
0323   */
0324
0325 /**
0326   * @brief  Processor uses sleep as its low power mode
0327   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
0328   * @retval None
0329   */
0330 __STATIC_INLINE void LL_LPM_EnableSleep(void)
0331 {
0332   /* Clear SLEEPDEEP bit of Cortex System Control Register */
0333   CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0334 }
0335
0336 /**
0337   * @brief  Processor uses deep sleep as its low power mode
0338   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
0339   * @retval None
0340   */
0341 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
0342 {
0343   /* Set SLEEPDEEP bit of Cortex System Control Register */
0344   SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
0345 }
0346
0347 /**
0348   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
0349   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
0350   *         empty main application.
0351   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
0352   * @retval None
0353   */
0354 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
0355 {
0356   /* Set SLEEPONEXIT bit of Cortex System Control Register */
0357   SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
0358 }
0359
0360 /**
0361   * @brief  Do not sleep when returning to Thread mode.
0362   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
0363   * @retval None
0364   */
0365 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
0366 {
0367   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
0368   CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
0369 }
0370
0371 /**
0372   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
0373   *         processor.
0374   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
0375   * @retval None
0376   */
0377 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
0378 {
0379   /* Set SEVEONPEND bit of Cortex System Control Register */
0380   SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
0381 }
0382
0383 /**
0384   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
0385   *         excluded
0386   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
0387   * @retval None
0388   */
0389 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
0390 {
0391   /* Clear SEVEONPEND bit of Cortex System Control Register */
0392   CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
0393 }
0394
0395 /**
0396   * @}
0397   */
0398
0399 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
0400   * @ingroup RTEMSBSPsARMSTM32H7
0401   * @{
0402   */
0403
0404 /**
0405   * @brief  Enable a fault in System handler control register (SHCSR)
0406   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
0407   * @param  Fault This parameter can be a combination of the following values:
0408   *         @arg @ref LL_HANDLER_FAULT_USG
0409   *         @arg @ref LL_HANDLER_FAULT_BUS
0410   *         @arg @ref LL_HANDLER_FAULT_MEM
0411   * @retval None
0412   */
0413 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
0414 {
0415   /* Enable the system handler fault */
0416   SET_BIT(SCB->SHCSR, Fault);
0417 }
0418
0419 /**
0420   * @brief  Disable a fault in System handler control register (SHCSR)
0421   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
0422   * @param  Fault This parameter can be a combination of the following values:
0423   *         @arg @ref LL_HANDLER_FAULT_USG
0424   *         @arg @ref LL_HANDLER_FAULT_BUS
0425   *         @arg @ref LL_HANDLER_FAULT_MEM
0426   * @retval None
0427   */
0428 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
0429 {
0430   /* Disable the system handler fault */
0431   CLEAR_BIT(SCB->SHCSR, Fault);
0432 }
0433
0434 /**
0435   * @}
0436   */
0437
0438 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
0439   * @ingroup RTEMSBSPsARMSTM32H7
0440   * @{
0441   */
0442
0443 /**
0444   * @brief  Get Implementer code
0445   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
0446   * @retval Value should be equal to 0x41 for ARM
0447   */
0448 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
0449 {
0450   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
0451 }
0452
0453 /**
0454   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
0455   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
0456   * @retval Value between 0 and 255 (0x0: revision 0)
0457   */
0458 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
0459 {
0460   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
0461 }
0462
0463 /**
0464   * @brief  Get Constant number
0465   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
0466   * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
0467   */
0468 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
0469 {
0470   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
0471 }
0472
0473 /**
0474   * @brief  Get Part number
0475   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
0476   * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
0477   */
0478 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
0479 {
0480   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
0481 }
0482
0483 /**
0484   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
0485   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
0486   * @retval Value between 0 and 255 (0x1: patch 1)
0487   */
0488 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
0489 {
0490   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
0491 }
0492
0493 /**
0494   * @}
0495   */
0496
0497 #if __MPU_PRESENT
0498 /** @defgroup CORTEX_LL_EF_MPU MPU
0499   * @ingroup RTEMSBSPsARMSTM32H7
0500   * @{
0501   */
0502
0503 /**
0504   * @brief  Enable MPU with input options
0505   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
0506   * @param  Options This parameter can be one of the following values:
0507   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
0508   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
0509   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
0510   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
0511   * @retval None
0512   */
0513 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
0514 {
0515   /* Enable the MPU*/
0516   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
0517   /* Ensure MPU settings take effects */
0518   __DSB();
0519   /* Sequence instruction fetches using update settings */
0520   __ISB();
0521 }
0522
0523 /**
0524   * @brief  Disable MPU
0525   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
0526   * @retval None
0527   */
0528 __STATIC_INLINE void LL_MPU_Disable(void)
0529 {
0530   /* Make sure outstanding transfers are done */
0531   __DMB();
0532   /* Disable MPU*/
0533   WRITE_REG(MPU->CTRL, 0U);
0534 }
0535
0536 /**
0537   * @brief  Check if MPU is enabled or not
0538   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
0539   * @retval State of bit (1 or 0).
0540   */
0541 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
0542 {
0543   return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
0544 }
0545
0546 /**
0547   * @brief  Enable a MPU region
0548   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
0549   * @param  Region This parameter can be one of the following values:
0550   *         @arg @ref LL_MPU_REGION_NUMBER0
0551   *         @arg @ref LL_MPU_REGION_NUMBER1
0552   *         @arg @ref LL_MPU_REGION_NUMBER2
0553   *         @arg @ref LL_MPU_REGION_NUMBER3
0554   *         @arg @ref LL_MPU_REGION_NUMBER4
0555   *         @arg @ref LL_MPU_REGION_NUMBER5
0556   *         @arg @ref LL_MPU_REGION_NUMBER6
0557   *         @arg @ref LL_MPU_REGION_NUMBER7
0558   *         @arg @ref LL_MPU_REGION_NUMBER8
0559   *         @arg @ref LL_MPU_REGION_NUMBER9
0560   *         @arg @ref LL_MPU_REGION_NUMBER10
0561   *         @arg @ref LL_MPU_REGION_NUMBER11
0562   *         @arg @ref LL_MPU_REGION_NUMBER12
0563   *         @arg @ref LL_MPU_REGION_NUMBER13
0564   *         @arg @ref LL_MPU_REGION_NUMBER14
0565   *         @arg @ref LL_MPU_REGION_NUMBER15
0566   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
0567   * @retval None
0568   */
0569 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
0570 {
0571   /* Set Region number */
0572   WRITE_REG(MPU->RNR, Region);
0573   /* Enable the MPU region */
0574   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
0575 }
0576
0577 /**
0578   * @brief  Configure and enable a region
0579   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
0580   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
0581   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
0582   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
0583   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
0584   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
0585   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
0586   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
0587   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
0588   * @param  Region This parameter can be one of the following values:
0589   *         @arg @ref LL_MPU_REGION_NUMBER0
0590   *         @arg @ref LL_MPU_REGION_NUMBER1
0591   *         @arg @ref LL_MPU_REGION_NUMBER2
0592   *         @arg @ref LL_MPU_REGION_NUMBER3
0593   *         @arg @ref LL_MPU_REGION_NUMBER4
0594   *         @arg @ref LL_MPU_REGION_NUMBER5
0595   *         @arg @ref LL_MPU_REGION_NUMBER6
0596   *         @arg @ref LL_MPU_REGION_NUMBER7
0597   *         @arg @ref LL_MPU_REGION_NUMBER8
0598   *         @arg @ref LL_MPU_REGION_NUMBER9
0599   *         @arg @ref LL_MPU_REGION_NUMBER10
0600   *         @arg @ref LL_MPU_REGION_NUMBER11
0601   *         @arg @ref LL_MPU_REGION_NUMBER12
0602   *         @arg @ref LL_MPU_REGION_NUMBER13
0603   *         @arg @ref LL_MPU_REGION_NUMBER14
0604   *         @arg @ref LL_MPU_REGION_NUMBER15
0605   * @param  Address Value of region base address
0606   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
0607   * @param  Attributes This parameter can be a combination of the following values:
0608   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
0609   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
0610   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
0611   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
0612   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
0613   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
0614   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
0615   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
0616   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
0617   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
0618   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
0619   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
0620   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
0621   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
0622   * @retval None
0623   */
0624 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
0625 {
0626   /* Set Region number */
0627   WRITE_REG(MPU->RNR, Region);
0628   /* Set base address */
0629   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
0630   /* Configure MPU */
0631   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
0632 }
0633
0634 /**
0635   * @brief  Disable a region
0636   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
0637   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
0638   * @param  Region This parameter can be one of the following values:
0639   *         @arg @ref LL_MPU_REGION_NUMBER0
0640   *         @arg @ref LL_MPU_REGION_NUMBER1
0641   *         @arg @ref LL_MPU_REGION_NUMBER2
0642   *         @arg @ref LL_MPU_REGION_NUMBER3
0643   *         @arg @ref LL_MPU_REGION_NUMBER4
0644   *         @arg @ref LL_MPU_REGION_NUMBER5
0645   *         @arg @ref LL_MPU_REGION_NUMBER6
0646   *         @arg @ref LL_MPU_REGION_NUMBER7
0647   *         @arg @ref LL_MPU_REGION_NUMBER8
0648   *         @arg @ref LL_MPU_REGION_NUMBER9
0649   *         @arg @ref LL_MPU_REGION_NUMBER10
0650   *         @arg @ref LL_MPU_REGION_NUMBER11
0651   *         @arg @ref LL_MPU_REGION_NUMBER12
0652   *         @arg @ref LL_MPU_REGION_NUMBER13
0653   *         @arg @ref LL_MPU_REGION_NUMBER14
0654   *         @arg @ref LL_MPU_REGION_NUMBER15
0655   * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
0656   * @retval None
0657   */
0658 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
0659 {
0660   /* Set Region number */
0661   WRITE_REG(MPU->RNR, Region);
0662   /* Disable the MPU region */
0663   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
0664 }
0665
0666 /**
0667   * @}
0668   */
0669
0670 #endif /* __MPU_PRESENT */
0671 /**
0672   * @}
0673   */
0674
0675 /**
0676   * @}
0677   */
0678
0679 /**
0680   * @}
0681   */
0682
0683 #ifdef __cplusplus
0684 }
0685 #endif
0686
0687 #endif /* STM32H7xx_LL_CORTEX_H */
0688