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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_bus.h 0004 * @author MCD Application Team 0005 * @brief Header file of BUS LL module. 0006 0007 @verbatim 0008 ##### RCC Limitations ##### 0009 ============================================================================== 0010 [..] 0011 A delay between an RCC peripheral clock enable and the effective peripheral 0012 enabling should be taken into account in order to manage the peripheral read/write 0013 from/to registers. 0014 (+) This delay depends on the peripheral mapping. 0015 (++) AHB & APB peripherals, 1 dummy read is necessary 0016 0017 [..] 0018 Workarounds: 0019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 0020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 0021 0022 @endverbatim 0023 ****************************************************************************** 0024 * @attention 0025 * 0026 * Copyright (c) 2017 STMicroelectronics. 0027 * All rights reserved. 0028 * 0029 * This software is licensed under terms that can be found in the LICENSE file in 0030 * the root directory of this software component. 0031 * If no LICENSE file comes with this software, it is provided AS-IS. 0032 ****************************************************************************** 0033 */ 0034 0035 /* Define to prevent recursive inclusion -------------------------------------*/ 0036 #ifndef STM32H7xx_LL_BUS_H 0037 #define STM32H7xx_LL_BUS_H 0038 0039 #ifdef __cplusplus 0040 extern "C" { 0041 #endif 0042 0043 /* Includes ------------------------------------------------------------------*/ 0044 #include "stm32h7xx.h" 0045 0046 /** @addtogroup STM32H7xx_LL_Driver 0047 * @{ 0048 */ 0049 0050 #if defined(RCC) 0051 0052 /** @defgroup BUS_LL BUS 0053 * @ingroup RTEMSBSPsARMSTM32H7 0054 * @{ 0055 */ 0056 0057 /* Private variables ---------------------------------------------------------*/ 0058 0059 /* Private constants ---------------------------------------------------------*/ 0060 0061 /* Private macros ------------------------------------------------------------*/ 0062 0063 /* Exported types ------------------------------------------------------------*/ 0064 0065 /* Exported constants --------------------------------------------------------*/ 0066 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 0067 * @ingroup RTEMSBSPsARMSTM32H7 0068 * @{ 0069 */ 0070 0071 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 0072 * @ingroup RTEMSBSPsARMSTM32H7 0073 * @{ 0074 */ 0075 #define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN 0076 #define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN 0077 0078 #if defined(JPEG) 0079 #define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN 0080 #endif /* JPEG */ 0081 0082 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 0083 #if defined(QUADSPI) 0084 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 0085 #endif /* QUADSPI */ 0086 #if defined(OCTOSPI1) || defined(OCTOSPI2) 0087 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN 0088 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN 0089 #endif /*(OCTOSPI1) || (OCTOSPI2)*/ 0090 #if defined(OCTOSPIM) 0091 #define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN 0092 #endif /* OCTOSPIM */ 0093 #if defined(OTFDEC1) || defined(OTFDEC2) 0094 #define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN 0095 #define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN 0096 #endif /* (OTFDEC1) || (OTFDEC2) */ 0097 #if defined(GFXMMU) 0098 #define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN 0099 #endif /* GFXMMU */ 0100 #define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN 0101 #define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN 0102 #define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN 0103 #define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN 0104 #define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN 0105 #if defined(RCC_AHB3LPENR_AXISRAMLPEN) 0106 #define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN 0107 #else 0108 #define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN 0109 #define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/ 0110 #endif /* RCC_AHB3LPENR_AXISRAMLPEN */ 0111 #if defined(CD_AXISRAM2_BASE) 0112 #define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN 0113 #endif /* CD_AXISRAM2_BASE */ 0114 #if defined(CD_AXISRAM3_BASE) 0115 #define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN 0116 #endif /* CD_AXISRAM3_BASE */ 0117 /** 0118 * @} 0119 */ 0120 0121 0122 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 0123 * @ingroup RTEMSBSPsARMSTM32H7 0124 * @{ 0125 */ 0126 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 0127 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 0128 #define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN 0129 #if defined(DUAL_CORE) 0130 #define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN 0131 #endif /* DUAL_CORE */ 0132 #if defined(RCC_AHB1ENR_CRCEN) 0133 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 0134 #endif /* RCC_AHB1ENR_CRCEN */ 0135 #if defined(ETH) 0136 #define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN 0137 #define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN 0138 #define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN 0139 #endif /* ETH */ 0140 #define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN 0141 #define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN 0142 #if defined(USB2_OTG_FS) 0143 #define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN 0144 #define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN 0145 #endif /* USB2_OTG_FS */ 0146 /** 0147 * @} 0148 */ 0149 0150 0151 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 0152 * @ingroup RTEMSBSPsARMSTM32H7 0153 * @{ 0154 */ 0155 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 0156 #if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN) 0157 #define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN 0158 #endif /* HSEM && RCC_AHB2ENR_HSEMEN */ 0159 #if defined(CRYP) 0160 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN 0161 #endif /* CRYP */ 0162 #if defined(HASH) 0163 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 0164 #endif /* HASH */ 0165 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 0166 #define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN 0167 #if defined(FMAC) 0168 #define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN 0169 #endif /* FMAC */ 0170 #if defined(CORDIC) 0171 #define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN 0172 #endif /* CORDIC */ 0173 #if defined(BDMA1) 0174 #define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN 0175 #endif /* BDMA1 */ 0176 #if defined(RCC_AHB2ENR_D2SRAM1EN) 0177 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN 0178 #else 0179 #define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN 0180 #define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/ 0181 #endif /* RCC_AHB2ENR_D2SRAM1EN */ 0182 #if defined(RCC_AHB2ENR_D2SRAM2EN) 0183 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN 0184 #else 0185 #define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN 0186 #define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/ 0187 #endif /* RCC_AHB2ENR_D2SRAM2EN */ 0188 #if defined(RCC_AHB2ENR_D2SRAM3EN) 0189 #define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN 0190 #endif /* RCC_AHB2ENR_D2SRAM3EN */ 0191 /** 0192 * @} 0193 */ 0194 0195 0196 /** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH 0197 * @ingroup RTEMSBSPsARMSTM32H7 0198 * @{ 0199 */ 0200 #define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN 0201 #define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN 0202 #define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN 0203 #define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN 0204 #define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN 0205 #define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN 0206 #define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN 0207 #define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN 0208 #if defined(GPIOI) 0209 #define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN 0210 #endif /* GPIOI */ 0211 #define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN 0212 #define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN 0213 #if defined(RCC_AHB4ENR_CRCEN) 0214 #define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN 0215 #endif /* RCC_AHB4ENR_CRCEN */ 0216 #if defined(BDMA2) 0217 #define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN 0218 #define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/ 0219 #else 0220 #define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN 0221 #endif /* BDMA2 */ 0222 #if defined(ADC3) 0223 #define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN 0224 #endif /* ADC3 */ 0225 #if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN) 0226 #define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN 0227 #endif /* HSEM && RCC_AHB4ENR_HSEMEN*/ 0228 #define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN 0229 #if defined(RCC_AHB4LPENR_SRAM4LPEN) 0230 #define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN 0231 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4 0232 #else 0233 #define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN 0234 #define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ 0235 #define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ 0236 #endif /* RCC_AHB4ENR_D3SRAM1EN */ 0237 /** 0238 * @} 0239 */ 0240 0241 0242 /** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH 0243 * @ingroup RTEMSBSPsARMSTM32H7 0244 * @{ 0245 */ 0246 #if defined(LTDC) 0247 #define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN 0248 #endif /* LTDC */ 0249 #if defined(DSI) 0250 #define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN 0251 #endif /* DSI */ 0252 #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN 0253 #if defined(RCC_APB3ENR_WWDGEN) 0254 #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ 0255 #endif /* RCC_APB3ENR_WWDGEN */ 0256 /** 0257 * @} 0258 */ 0259 0260 0261 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 0262 * @ingroup RTEMSBSPsARMSTM32H7 0263 * @{ 0264 */ 0265 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN 0266 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN 0267 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN 0268 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN 0269 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN 0270 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN 0271 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN 0272 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN 0273 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN 0274 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN 0275 #if defined(DUAL_CORE) 0276 #define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN 0277 #endif /*DUAL_CORE*/ 0278 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN 0279 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN 0280 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN 0281 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN 0282 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN 0283 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN 0284 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN 0285 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN 0286 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN 0287 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN 0288 #if defined(I2C5) 0289 #define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN 0290 #endif /* I2C5 */ 0291 #if defined(RCC_APB1LENR_CECEN) 0292 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN 0293 #else 0294 #define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN 0295 #define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/ 0296 #endif /* RCC_APB1LENR_CECEN */ 0297 #define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN 0298 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN 0299 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN 0300 /** 0301 * @} 0302 */ 0303 0304 0305 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 0306 * @ingroup RTEMSBSPsARMSTM32H7 0307 * @{ 0308 */ 0309 #define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN 0310 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN 0311 #define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN 0312 #define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN 0313 #define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN 0314 #if defined(TIM23) 0315 #define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN 0316 #endif /* TIM23 */ 0317 #if defined(TIM24) 0318 #define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN 0319 #endif /* TIM24 */ 0320 /** 0321 * @} 0322 */ 0323 0324 0325 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 0326 * @ingroup RTEMSBSPsARMSTM32H7 0327 * @{ 0328 */ 0329 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 0330 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 0331 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 0332 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN 0333 #if defined(UART9) 0334 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN 0335 #endif /* UART9 */ 0336 #if defined(USART10) 0337 #define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN 0338 #endif /* USART10 */ 0339 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 0340 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN 0341 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 0342 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 0343 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 0344 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN 0345 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 0346 #if defined(SAI2) 0347 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 0348 #endif /* SAI2 */ 0349 #if defined(SAI3) 0350 #define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN 0351 #endif /* SAI3 */ 0352 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 0353 #if defined(HRTIM1) 0354 #define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN 0355 #endif /* HRTIM1 */ 0356 /** 0357 * @} 0358 */ 0359 0360 0361 /** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH 0362 * @ingroup RTEMSBSPsARMSTM32H7 0363 * @{ 0364 */ 0365 #define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN 0366 #define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN 0367 #define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN 0368 #define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN 0369 #define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN 0370 #define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN 0371 #if defined(LPTIM4) 0372 #define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN 0373 #endif /* LPTIM4 */ 0374 #if defined(LPTIM5) 0375 #define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN 0376 #endif /* LPTIM5 */ 0377 #if defined(DAC2) 0378 #define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN 0379 #endif /* DAC2 */ 0380 #define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN 0381 #define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN 0382 #define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN 0383 #if defined(SAI4) 0384 #define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN 0385 #endif /* SAI4 */ 0386 #if defined(DTS) 0387 #define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN 0388 #endif /*DTS*/ 0389 #if defined(DFSDM2_BASE) 0390 #define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN 0391 #endif /* DFSDM2_BASE */ 0392 /** 0393 * @} 0394 */ 0395 0396 /** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH 0397 * @ingroup RTEMSBSPsARMSTM32H7 0398 * @{ 0399 */ 0400 #if defined(RCC_D3AMR_BDMAAMEN) 0401 #define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN 0402 #else 0403 #define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN 0404 #define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/ 0405 #endif /* RCC_D3AMR_BDMAAMEN */ 0406 #if defined(RCC_SRDAMR_GPIOAMEN) 0407 #define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN 0408 #endif /* RCC_SRDAMR_GPIOAMEN */ 0409 #if defined(RCC_D3AMR_LPUART1AMEN) 0410 #define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN 0411 #else 0412 #define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN 0413 #endif /* RCC_D3AMR_LPUART1AMEN */ 0414 #if defined(RCC_D3AMR_SPI6AMEN) 0415 #define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN 0416 #else 0417 #define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN 0418 #endif /* RCC_D3AMR_SPI6AMEN */ 0419 #if defined(RCC_D3AMR_I2C4AMEN) 0420 #define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN 0421 #else 0422 #define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN 0423 #endif /* RCC_D3AMR_I2C4AMEN */ 0424 #if defined(RCC_D3AMR_LPTIM2AMEN) 0425 #define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN 0426 #else 0427 #define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN 0428 #endif /* RCC_D3AMR_LPTIM2AMEN */ 0429 #if defined(RCC_D3AMR_LPTIM3AMEN) 0430 #define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN 0431 #else 0432 #define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN 0433 #endif /* RCC_D3AMR_LPTIM3AMEN */ 0434 #if defined(RCC_D3AMR_LPTIM4AMEN) 0435 #define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN 0436 #endif /* RCC_D3AMR_LPTIM4AMEN */ 0437 #if defined(RCC_D3AMR_LPTIM5AMEN) 0438 #define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN 0439 #endif /* RCC_D3AMR_LPTIM5AMEN */ 0440 #if defined(DAC2) 0441 #define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN 0442 #endif /* DAC2 */ 0443 #if defined(RCC_D3AMR_COMP12AMEN) 0444 #define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN 0445 #else 0446 #define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN 0447 #endif /* RCC_D3AMR_COMP12AMEN */ 0448 #if defined(RCC_D3AMR_VREFAMEN) 0449 #define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN 0450 #else 0451 #define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN 0452 #endif /* RCC_D3AMR_VREFAMEN */ 0453 #if defined(RCC_D3AMR_RTCAMEN) 0454 #define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN 0455 #else 0456 #define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN 0457 #endif /* RCC_D3AMR_RTCAMEN */ 0458 #if defined(RCC_D3AMR_CRCAMEN) 0459 #define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN 0460 #endif /* RCC_D3AMR_CRCAMEN */ 0461 #if defined(SAI4) 0462 #define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN 0463 #endif /* SAI4 */ 0464 #if defined(ADC3) 0465 #define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN 0466 #endif /* ADC3 */ 0467 #if defined(RCC_SRDAMR_DTSAMEN) 0468 #define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN 0469 #endif /* RCC_SRDAMR_DTSAMEN */ 0470 #if defined(RCC_D3AMR_DTSAMEN) 0471 #define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN 0472 #endif /* RCC_D3AMR_DTSAMEN */ 0473 #if defined(DFSDM2_BASE) 0474 #define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN 0475 #endif /* DFSDM2_BASE */ 0476 #if defined(RCC_D3AMR_BKPRAMAMEN) 0477 #define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN 0478 #else 0479 #define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN 0480 #endif /* RCC_D3AMR_BKPRAMAMEN */ 0481 #if defined(RCC_D3AMR_SRAM4AMEN) 0482 #define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN 0483 #else 0484 #define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN 0485 #define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM 0486 #endif /* RCC_D3AMR_SRAM4AMEN */ 0487 /** 0488 * @} 0489 */ 0490 0491 #if defined(RCC_CKGAENR_AXICKG) 0492 /** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH 0493 * @ingroup RTEMSBSPsARMSTM32H7 0494 * @{ 0495 */ 0496 #define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG 0497 #define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG 0498 #define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG 0499 #define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG 0500 #define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG 0501 #define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG 0502 #define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG 0503 #define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG 0504 #define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG 0505 #define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG 0506 #define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG 0507 #define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG 0508 #define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG 0509 #define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG 0510 #define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG 0511 #define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG 0512 #define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG 0513 #define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG 0514 #define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG 0515 #define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG 0516 #define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG 0517 /** 0518 * @} 0519 */ 0520 #endif /* RCC_CKGAENR_AXICKG */ 0521 0522 /** 0523 * @} 0524 */ 0525 0526 /* Exported macro ------------------------------------------------------------*/ 0527 0528 /* Exported functions --------------------------------------------------------*/ 0529 0530 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 0531 * @ingroup RTEMSBSPsARMSTM32H7 0532 * @{ 0533 */ 0534 0535 /** @defgroup BUS_LL_EF_AHB3 AHB3 0536 * @ingroup RTEMSBSPsARMSTM32H7 0537 * @{ 0538 */ 0539 0540 /** 0541 * @brief Enable AHB3 peripherals clock. 0542 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n 0543 * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n 0544 * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n 0545 * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 0546 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*) 0547 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*) 0548 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*) 0549 * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) 0550 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) 0551 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) 0552 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*) 0553 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n 0554 * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) 0555 * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) 0556 * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*) 0557 * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*) 0558 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*) 0559 * @param Periphs This parameter can be a combination of the following values: 0560 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 0561 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0562 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0563 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0564 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0565 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0566 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0567 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0568 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0569 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0570 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0571 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0572 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 0573 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 0574 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 0575 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 0576 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 0577 * 0578 * (*) value not defined in all devices. 0579 * @retval None 0580 */ 0581 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 0582 { 0583 __IO uint32_t tmpreg; 0584 SET_BIT(RCC->AHB3ENR, Periphs); 0585 /* Delay after an RCC peripheral clock enabling */ 0586 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 0587 (void)tmpreg; 0588 } 0589 0590 /** 0591 * @brief Check if AHB3 peripheral clock is enabled or not 0592 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n 0593 * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n 0594 * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n 0595 * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 0596 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*) 0597 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0598 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0599 * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) 0600 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0601 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0602 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*) 0603 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n 0604 * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) 0605 * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0606 * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*) 0607 * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*) 0608 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*) 0609 * @param Periphs This parameter can be a combination of the following values: 0610 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 0611 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0612 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0613 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0614 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0615 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0616 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0617 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0618 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0619 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0620 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0621 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0622 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 0623 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 0624 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 0625 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 0626 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 0627 * 0628 * (*) value not defined in all devices. 0629 * @retval uint32_t 0630 */ 0631 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 0632 { 0633 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); 0634 } 0635 0636 /** 0637 * @brief Disable AHB3 peripherals clock. 0638 * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n 0639 * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n 0640 * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n 0641 * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 0642 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*) 0643 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*) 0644 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*) 0645 * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) 0646 * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) 0647 * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) 0648 * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*) 0649 * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) 0650 * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) 0651 * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) 0652 * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*) 0653 * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*) 0654 * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock 0655 * @param Periphs This parameter can be a combination of the following values: 0656 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 0657 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0658 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0659 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0660 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0661 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0662 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0663 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0664 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0665 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0666 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0667 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0668 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) 0669 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) 0670 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) 0671 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) 0672 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 0673 * 0674 * (*) value not defined in all devices. 0675 * @retval None 0676 */ 0677 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 0678 { 0679 CLEAR_BIT(RCC->AHB3ENR, Periphs); 0680 } 0681 0682 /** 0683 * @brief Force AHB3 peripherals reset. 0684 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n 0685 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n 0686 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n 0687 * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 0688 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*) 0689 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*) 0690 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*) 0691 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*) 0692 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*) 0693 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*) 0694 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*) 0695 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset 0696 * @param Periphs This parameter can be a combination of the following values: 0697 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 0698 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0699 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0700 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0701 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0702 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0703 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0704 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0705 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0706 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0707 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0708 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0709 * 0710 * (*) value not defined in all devices. 0711 * @retval None 0712 */ 0713 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 0714 { 0715 SET_BIT(RCC->AHB3RSTR, Periphs); 0716 } 0717 0718 /** 0719 * @brief Release AHB3 peripherals reset. 0720 * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n 0721 * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n 0722 * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n 0723 * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 0724 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n 0725 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*) 0726 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*) 0727 * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*) 0728 * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*) 0729 * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*) 0730 * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*) 0731 * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset 0732 * @param Periphs This parameter can be a combination of the following values: 0733 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 0734 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0735 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0736 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0737 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0738 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0739 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0740 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0741 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0742 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0743 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0744 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0745 * 0746 * (*) value not defined in all devices. 0747 * @retval None 0748 */ 0749 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 0750 { 0751 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 0752 } 0753 0754 /** 0755 * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. 0756 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n 0757 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n 0758 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n 0759 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n 0760 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0761 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0762 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0763 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0764 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0765 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0766 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*) 0767 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n 0768 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n 0769 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n 0770 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n 0771 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n 0772 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep 0773 * @param Periphs This parameter can be a combination of the following values: 0774 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0775 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0776 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0777 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0778 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0779 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0780 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0781 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0782 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0783 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0784 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0785 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 0786 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 0787 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 0788 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 0789 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 0790 * 0791 * (*) value not defined in all devices. 0792 * @retval None 0793 */ 0794 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 0795 { 0796 __IO uint32_t tmpreg; 0797 SET_BIT(RCC->AHB3LPENR, Periphs); 0798 /* Delay after an RCC peripheral clock enabling */ 0799 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); 0800 (void)tmpreg; 0801 } 0802 0803 /** 0804 * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. 0805 * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n 0806 * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n 0807 * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n 0808 * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n 0809 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n 0810 * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0811 * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0812 * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0813 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0814 * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0815 * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*) 0816 * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n 0817 * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n 0818 * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n 0819 * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n 0820 * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n 0821 * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep 0822 * @param Periphs This parameter can be a combination of the following values: 0823 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 0824 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 0825 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 0826 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 0827 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 0828 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 0829 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 0830 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 0831 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 0832 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 0833 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 0834 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 0835 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 0836 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 0837 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 0838 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 0839 * 0840 * (*) value not defined in all devices. 0841 * @retval None 0842 */ 0843 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 0844 { 0845 CLEAR_BIT(RCC->AHB3LPENR, Periphs); 0846 } 0847 0848 /** 0849 * @} 0850 */ 0851 0852 /** @defgroup BUS_LL_EF_AHB1 AHB1 0853 * @ingroup RTEMSBSPsARMSTM32H7 0854 * @{ 0855 */ 0856 0857 /** 0858 * @brief Enable AHB1 peripherals clock. 0859 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 0860 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 0861 * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n 0862 * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n 0863 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*) 0864 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) 0865 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) 0866 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) 0867 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n 0868 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n 0869 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*) 0870 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*) 0871 * @param Periphs This parameter can be a combination of the following values: 0872 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 0873 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 0874 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 0875 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 0876 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 0877 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 0878 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 0879 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 0880 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 0881 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 0882 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 0883 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 0884 * 0885 * (*) value not defined in all devices. 0886 * @retval None 0887 */ 0888 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 0889 { 0890 __IO uint32_t tmpreg; 0891 SET_BIT(RCC->AHB1ENR, Periphs); 0892 /* Delay after an RCC peripheral clock enabling */ 0893 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 0894 (void)tmpreg; 0895 } 0896 0897 /** 0898 * @brief Check if AHB1 peripheral clock is enabled or not 0899 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 0900 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 0901 * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n 0902 * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0903 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0904 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0905 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0906 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0907 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n 0908 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n 0909 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*) 0910 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*) 0911 * @param Periphs This parameter can be a combination of the following values: 0912 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 0913 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 0914 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 0915 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 0916 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 0917 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 0918 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 0919 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 0920 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 0921 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 0922 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 0923 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 0924 * 0925 * (*) value not defined in all devices. 0926 * @retval uint32_t 0927 */ 0928 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 0929 { 0930 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); 0931 } 0932 0933 /** 0934 * @brief Disable AHB1 peripherals clock. 0935 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 0936 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 0937 * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n 0938 * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) 0939 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*) 0940 * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) 0941 * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) 0942 * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) 0943 * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n 0944 * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n 0945 * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*) 0946 * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*) 0947 * @param Periphs This parameter can be a combination of the following values: 0948 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 0949 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 0950 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 0951 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 0952 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 0953 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 0954 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 0955 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 0956 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 0957 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 0958 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 0959 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 0960 * 0961 * (*) value not defined in all devices. 0962 * @retval None 0963 */ 0964 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 0965 { 0966 CLEAR_BIT(RCC->AHB1ENR, Periphs); 0967 } 0968 0969 /** 0970 * @brief Force AHB1 peripherals reset. 0971 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 0972 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 0973 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n 0974 * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*) 0975 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*) 0976 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*) 0977 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n 0978 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*) 0979 * @param Periphs This parameter can be a combination of the following values: 0980 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 0981 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 0982 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 0983 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 0984 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 0985 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 0986 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 0987 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 0988 * 0989 * (*) value not defined in all devices. 0990 * @retval None 0991 */ 0992 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 0993 { 0994 SET_BIT(RCC->AHB1RSTR, Periphs); 0995 } 0996 0997 /** 0998 * @brief Release AHB1 peripherals reset. 0999 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 1000 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 1001 * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n 1002 * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*) 1003 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*) 1004 * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*) 1005 * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n 1006 * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*) 1007 * @param Periphs This parameter can be a combination of the following values: 1008 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 1009 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 1010 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 1011 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 1012 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 1013 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 1014 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 1015 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 1016 * 1017 * (*) value not defined in all devices. 1018 * @retval None 1019 */ 1020 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 1021 { 1022 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 1023 } 1024 1025 /** 1026 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. 1027 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n 1028 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n 1029 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n 1030 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 1031 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 1032 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 1033 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 1034 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n 1035 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n 1036 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n 1037 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) 1038 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*) 1039 * @param Periphs This parameter can be a combination of the following values: 1040 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 1041 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 1042 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 1043 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 1044 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 1045 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 1046 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 1047 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 1048 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 1049 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 1050 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 1051 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 1052 * 1053 * (*) value not defined in all devices. 1054 * @retval None 1055 */ 1056 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 1057 { 1058 __IO uint32_t tmpreg; 1059 SET_BIT(RCC->AHB1LPENR, Periphs); 1060 /* Delay after an RCC peripheral clock enabling */ 1061 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); 1062 (void)tmpreg; 1063 } 1064 1065 /** 1066 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. 1067 * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n 1068 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n 1069 * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n 1070 * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1071 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1072 * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1073 * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1074 * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1075 * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n 1076 * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n 1077 * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) 1078 * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*) 1079 * @param Periphs This parameter can be a combination of the following values: 1080 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 1081 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 1082 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 1083 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 1084 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 1085 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 1086 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 1087 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 1088 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 1089 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 1090 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 1091 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 1092 * 1093 * (*) value not defined in all devices. 1094 * @retval None 1095 */ 1096 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 1097 { 1098 CLEAR_BIT(RCC->AHB1LPENR, Periphs); 1099 } 1100 1101 /** 1102 * @} 1103 */ 1104 1105 /** @defgroup BUS_LL_EF_AHB2 AHB2 1106 * @ingroup RTEMSBSPsARMSTM32H7 1107 * @{ 1108 */ 1109 1110 /** 1111 * @brief Enable AHB2 peripherals clock. 1112 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 1113 * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*) 1114 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*) 1115 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*) 1116 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 1117 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n 1118 * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*) 1119 * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n 1120 * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n 1121 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n 1122 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n 1123 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*) 1124 * @param Periphs This parameter can be a combination of the following values: 1125 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1126 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 1127 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1128 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1129 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1130 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1131 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1132 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1133 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1134 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 1135 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 1136 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 1137 * 1138 * (*) value not defined in all devices. 1139 * @retval None 1140 */ 1141 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 1142 { 1143 __IO uint32_t tmpreg; 1144 SET_BIT(RCC->AHB2ENR, Periphs); 1145 /* Delay after an RCC peripheral clock enabling */ 1146 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 1147 (void)tmpreg; 1148 } 1149 1150 /** 1151 * @brief Check if AHB2 peripheral clock is enabled or not 1152 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 1153 * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*) 1154 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*) 1155 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*) 1156 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 1157 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n 1158 * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*) 1159 * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n 1160 * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n 1161 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n 1162 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n 1163 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*) 1164 * @param Periphs This parameter can be a combination of the following values: 1165 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1166 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 1167 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1168 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1169 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1170 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1171 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1172 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1173 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1174 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 1175 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 1176 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 1177 * 1178 * (*) value not defined in all devices. 1179 * @retval uint32_t 1180 */ 1181 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 1182 { 1183 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); 1184 } 1185 1186 /** 1187 * @brief Disable AHB2 peripherals clock. 1188 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 1189 * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*) 1190 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*) 1191 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*) 1192 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 1193 * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n 1194 * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*) 1195 * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n 1196 * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n 1197 * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n 1198 * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n 1199 * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*) 1200 * @param Periphs This parameter can be a combination of the following values: 1201 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1202 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 1203 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1204 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1205 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1206 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1207 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1208 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1209 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1210 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 1211 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 1212 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 1213 * 1214 * (*) value not defined in all devices. 1215 * @retval None 1216 */ 1217 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 1218 { 1219 CLEAR_BIT(RCC->AHB2ENR, Periphs); 1220 } 1221 1222 /** 1223 * @brief Force AHB2 peripherals reset. 1224 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 1225 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*) 1226 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*) 1227 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) 1228 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 1229 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n 1230 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*) 1231 * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n 1232 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset 1233 * @param Periphs This parameter can be a combination of the following values: 1234 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1235 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 1236 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1237 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1238 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1239 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1240 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1241 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1242 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1243 * 1244 * (*) value not defined in all devices. 1245 * @retval None 1246 */ 1247 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 1248 { 1249 SET_BIT(RCC->AHB2RSTR, Periphs); 1250 } 1251 1252 /** 1253 * @brief Release AHB2 peripherals reset. 1254 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 1255 * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*) 1256 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*) 1257 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) 1258 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 1259 * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n 1260 * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*) 1261 * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n 1262 * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset 1263 * @param Periphs This parameter can be a combination of the following values: 1264 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1265 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 1266 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1267 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1268 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1269 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1270 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1271 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1272 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1273 * 1274 * (*) value not defined in all devices. 1275 * @retval None 1276 */ 1277 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 1278 { 1279 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 1280 } 1281 1282 /** 1283 * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. 1284 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n 1285 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 1286 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 1287 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n 1288 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n 1289 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*) 1290 * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n 1291 * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n 1292 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n 1293 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n 1294 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*) 1295 * @param Periphs This parameter can be a combination of the following values: 1296 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1297 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1298 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1299 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1300 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1301 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1302 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1303 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1304 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 1305 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 1306 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 1307 * 1308 * (*) value not defined in all devices. 1309 * @retval None 1310 */ 1311 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 1312 { 1313 __IO uint32_t tmpreg; 1314 SET_BIT(RCC->AHB2LPENR, Periphs); 1315 /* Delay after an RCC peripheral clock enabling */ 1316 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); 1317 (void)tmpreg; 1318 } 1319 1320 /** 1321 * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. 1322 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n 1323 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 1324 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 1325 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n 1326 * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n 1327 * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*) 1328 * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n 1329 * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n 1330 * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*) 1331 * @param Periphs This parameter can be a combination of the following values: 1332 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 1333 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 1334 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 1335 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 1336 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 1337 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 1338 * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) 1339 * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) 1340 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 1341 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 1342 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 1343 * 1344 * (*) value not defined in all devices. 1345 * @retval None 1346 */ 1347 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 1348 { 1349 CLEAR_BIT(RCC->AHB2LPENR, Periphs); 1350 } 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** @defgroup BUS_LL_EF_AHB4 AHB4 1357 * @ingroup RTEMSBSPsARMSTM32H7 1358 * @{ 1359 */ 1360 1361 /** 1362 * @brief Enable AHB4 peripherals clock. 1363 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n 1364 * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n 1365 * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n 1366 * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n 1367 * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n 1368 * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n 1369 * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n 1370 * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n 1371 * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*) 1372 * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n 1373 * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n 1374 * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*) 1375 * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n 1376 * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*) 1377 * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*) 1378 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n 1379 * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock 1380 * @param Periphs This parameter can be a combination of the following values: 1381 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1382 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1383 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1384 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1385 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1386 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1387 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1388 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1389 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1390 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1391 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1392 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1393 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1394 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1395 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 1396 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 1397 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 1398 * 1399 * (*) value not defined in all devices. 1400 * @retval None 1401 */ 1402 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) 1403 { 1404 __IO uint32_t tmpreg; 1405 SET_BIT(RCC->AHB4ENR, Periphs); 1406 /* Delay after an RCC peripheral clock enabling */ 1407 tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); 1408 (void)tmpreg; 1409 } 1410 1411 /** 1412 * @brief Check if AHB4 peripheral clock is enabled or not 1413 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n 1414 * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n 1415 * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n 1416 * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n 1417 * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n 1418 * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n 1419 * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n 1420 * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n 1421 * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*) 1422 * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n 1423 * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n 1424 * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*) 1425 * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n 1426 * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*) 1427 * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*) 1428 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n 1429 * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock 1430 * @param Periphs This parameter can be a combination of the following values: 1431 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1432 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1433 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1434 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1435 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1436 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1437 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1438 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1439 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1440 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1441 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1442 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1443 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1444 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1445 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 1446 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 1447 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 1448 * 1449 * (*) value not defined in all devices. 1450 * @retval uint32_t 1451 */ 1452 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 1453 { 1454 return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); 1455 } 1456 1457 /** 1458 * @brief Disable AHB4 peripherals clock. 1459 * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n 1460 * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n 1461 * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n 1462 * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n 1463 * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n 1464 * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n 1465 * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n 1466 * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n 1467 * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*) 1468 * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n 1469 * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n 1470 * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*) 1471 * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n 1472 * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*) 1473 * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*) 1474 * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n 1475 * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock 1476 * @param Periphs This parameter can be a combination of the following values: 1477 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1478 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1479 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1480 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1481 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1482 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1483 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1484 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1485 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1486 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1487 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1488 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1489 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1490 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1491 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 1492 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 1493 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 1494 * 1495 * (*) value not defined in all devices. 1496 * @retval None 1497 */ 1498 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) 1499 { 1500 CLEAR_BIT(RCC->AHB4ENR, Periphs); 1501 } 1502 1503 /** 1504 * @brief Force AHB4 peripherals reset. 1505 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n 1506 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n 1507 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n 1508 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n 1509 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n 1510 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n 1511 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n 1512 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n 1513 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*) 1514 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n 1515 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n 1516 * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*) 1517 * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n 1518 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*) 1519 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*) 1520 * @param Periphs This parameter can be a combination of the following values: 1521 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1522 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1523 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1524 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1525 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1526 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1527 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1528 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1529 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1530 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1531 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1532 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1533 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1534 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1535 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 1536 * 1537 * (*) value not defined in all devices. 1538 * @retval None 1539 */ 1540 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) 1541 { 1542 SET_BIT(RCC->AHB4RSTR, Periphs); 1543 } 1544 1545 /** 1546 * @brief Release AHB4 peripherals reset. 1547 * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n 1548 * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n 1549 * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n 1550 * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n 1551 * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n 1552 * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n 1553 * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n 1554 * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n 1555 * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*) 1556 * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n 1557 * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n 1558 * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*) 1559 * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n 1560 * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*) 1561 * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*) 1562 * @param Periphs This parameter can be a combination of the following values: 1563 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1564 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1565 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1566 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1567 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1568 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1569 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1570 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1571 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1572 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1573 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1574 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1575 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1576 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1577 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 1578 * 1579 * (*) value not defined in all devices. 1580 * @retval None 1581 */ 1582 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) 1583 { 1584 CLEAR_BIT(RCC->AHB4RSTR, Periphs); 1585 } 1586 1587 /** 1588 * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. 1589 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n 1590 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n 1591 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n 1592 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n 1593 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n 1594 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n 1595 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n 1596 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n 1597 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 1598 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n 1599 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n 1600 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 1601 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n 1602 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*) 1603 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n 1604 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep 1605 * @param Periphs This parameter can be a combination of the following values: 1606 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1607 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1608 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1609 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1610 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1611 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1612 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1613 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1614 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1615 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1616 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1617 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1618 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1619 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1620 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 1621 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 1622 * @retval None 1623 */ 1624 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 1625 { 1626 __IO uint32_t tmpreg; 1627 SET_BIT(RCC->AHB4LPENR, Periphs); 1628 /* Delay after an RCC peripheral clock enabling */ 1629 tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); 1630 (void)tmpreg; 1631 } 1632 1633 /** 1634 * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. 1635 * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n 1636 * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n 1637 * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n 1638 * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n 1639 * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n 1640 * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n 1641 * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n 1642 * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n 1643 * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 1644 * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n 1645 * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n 1646 * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 1647 * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n 1648 * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*) 1649 * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n 1650 * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep 1651 * @param Periphs This parameter can be a combination of the following values: 1652 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 1653 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 1654 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 1655 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 1656 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 1657 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 1658 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 1659 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 1660 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 1661 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 1662 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 1663 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 1664 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 1665 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 1666 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 1667 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 1668 * @retval None 1669 */ 1670 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 1671 { 1672 CLEAR_BIT(RCC->AHB4LPENR, Periphs); 1673 } 1674 1675 /** 1676 * @} 1677 */ 1678 1679 /** @defgroup BUS_LL_EF_APB3 APB3 1680 * @ingroup RTEMSBSPsARMSTM32H7 1681 * @{ 1682 */ 1683 1684 /** 1685 * @brief Enable APB3 peripherals clock. 1686 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*) 1687 * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*) 1688 * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock 1689 * @param Periphs This parameter can be a combination of the following values: 1690 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1691 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1692 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 1693 * 1694 * (*) value not defined in all devices. 1695 * @retval None 1696 */ 1697 __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) 1698 { 1699 __IO uint32_t tmpreg; 1700 SET_BIT(RCC->APB3ENR, Periphs); 1701 /* Delay after an RCC peripheral clock enabling */ 1702 tmpreg = READ_BIT(RCC->APB3ENR, Periphs); 1703 (void)tmpreg; 1704 } 1705 1706 /** 1707 * @brief Check if APB3 peripheral clock is enabled or not 1708 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*) 1709 * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*) 1710 * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock 1711 * @param Periphs This parameter can be a combination of the following values: 1712 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1713 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1714 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 1715 * 1716 * (*) value not defined in all devices. 1717 * @retval uint32_t 1718 */ 1719 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 1720 { 1721 return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); 1722 } 1723 1724 /** 1725 * @brief Disable APB3 peripherals clock. 1726 * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n 1727 * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n 1728 * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock 1729 * @param Periphs This parameter can be a combination of the following values: 1730 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1731 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1732 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 1733 * 1734 * (*) value not defined in all devices. 1735 * @retval None 1736 */ 1737 __STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) 1738 { 1739 CLEAR_BIT(RCC->APB3ENR, Periphs); 1740 } 1741 1742 /** 1743 * @brief Force APB3 peripherals reset. 1744 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*) 1745 * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*) 1746 * @param Periphs This parameter can be a combination of the following values: 1747 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1748 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1749 * 1750 * (*) value not defined in all devices. 1751 * @retval None 1752 */ 1753 __STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) 1754 { 1755 SET_BIT(RCC->APB3RSTR, Periphs); 1756 } 1757 1758 /** 1759 * @brief Release APB3 peripherals reset. 1760 * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n 1761 * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset 1762 * @param Periphs This parameter can be a combination of the following values: 1763 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1764 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1765 * 1766 * (*) value not defined in all devices. 1767 * @retval None 1768 */ 1769 __STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) 1770 { 1771 CLEAR_BIT(RCC->APB3RSTR, Periphs); 1772 } 1773 1774 /** 1775 * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. 1776 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*) 1777 * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*) 1778 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep 1779 * @param Periphs This parameter can be a combination of the following values: 1780 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1781 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1782 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 1783 * 1784 * (*) value not defined in all devices. 1785 * @retval None 1786 */ 1787 __STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 1788 { 1789 __IO uint32_t tmpreg; 1790 SET_BIT(RCC->APB3LPENR, Periphs); 1791 /* Delay after an RCC peripheral clock enabling */ 1792 tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); 1793 (void)tmpreg; 1794 } 1795 1796 /** 1797 * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. 1798 * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*) 1799 * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*) 1800 * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep 1801 * @param Periphs This parameter can be a combination of the following values: 1802 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 1803 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 1804 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 1805 * 1806 * (*) value not defined in all devices. 1807 * @retval None 1808 */ 1809 __STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 1810 { 1811 CLEAR_BIT(RCC->APB3LPENR, Periphs); 1812 } 1813 1814 /** 1815 * @} 1816 */ 1817 1818 /** @defgroup BUS_LL_EF_APB1 APB1 1819 * @ingroup RTEMSBSPsARMSTM32H7 1820 * @{ 1821 */ 1822 1823 /** 1824 * @brief Enable APB1 peripherals clock. 1825 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n 1826 * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n 1827 * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n 1828 * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n 1829 * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n 1830 * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n 1831 * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n 1832 * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n 1833 * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n 1834 * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n 1835 * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*) 1836 * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n 1837 * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n 1838 * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n 1839 * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n 1840 * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n 1841 * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n 1842 * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n 1843 * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n 1844 * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n 1845 * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n 1846 * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*) 1847 * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n 1848 * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n 1849 * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n 1850 * APB1LENR UART8EN LL_APB1_GRP1_EnableClock 1851 * @param Periphs This parameter can be a combination of the following values: 1852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1856 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1857 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1858 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1859 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1860 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1861 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1862 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 1863 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1864 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1865 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 1866 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1867 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1868 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1869 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1870 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1871 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1872 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1873 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 1874 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 1875 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 1876 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1877 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1878 * 1879 * (*) value not defined in all devices. 1880 * @retval None 1881 */ 1882 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 1883 { 1884 __IO uint32_t tmpreg; 1885 SET_BIT(RCC->APB1LENR, Periphs); 1886 /* Delay after an RCC peripheral clock enabling */ 1887 tmpreg = READ_BIT(RCC->APB1LENR, Periphs); 1888 (void)tmpreg; 1889 } 1890 1891 /** 1892 * @brief Check if APB1 peripheral clock is enabled or not 1893 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 1894 * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 1895 * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 1896 * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 1897 * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 1898 * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 1899 * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 1900 * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 1901 * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 1902 * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n 1903 * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*) 1904 * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 1905 * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 1906 * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n 1907 * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 1908 * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 1909 * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 1910 * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 1911 * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 1912 * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 1913 * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n 1914 * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*) 1915 * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n 1916 * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n 1917 * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n 1918 * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock 1919 * @param Periphs This parameter can be a combination of the following values: 1920 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1921 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1922 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1923 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1924 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1925 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1926 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1927 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1928 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1929 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1930 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 1931 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1932 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1933 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 1934 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1935 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 1936 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 1937 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 1938 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 1939 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 1940 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 1941 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 1942 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 1943 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 1944 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 1945 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 1946 * 1947 * (*) value not defined in all devices. 1948 * @retval uint32_t 1949 */ 1950 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 1951 { 1952 return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); 1953 } 1954 1955 /** 1956 * @brief Disable APB1 peripherals clock. 1957 * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n 1958 * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n 1959 * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n 1960 * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n 1961 * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n 1962 * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n 1963 * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n 1964 * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n 1965 * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n 1966 * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n 1967 * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*) 1968 * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n 1969 * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n 1970 * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n 1971 * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n 1972 * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n 1973 * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n 1974 * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n 1975 * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n 1976 * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n 1977 * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n 1978 * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*) 1979 * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n 1980 * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n 1981 * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n 1982 * APB1LENR UART8EN LL_APB1_GRP1_DisableClock 1983 * @param Periphs This parameter can be a combination of the following values: 1984 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 1985 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 1986 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 1987 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 1988 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 1989 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 1990 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 1991 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 1992 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 1993 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 1994 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 1995 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 1996 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 1997 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 1998 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 1999 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 2000 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 2001 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 2002 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 2003 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 2004 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 2005 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 2006 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 2007 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 2008 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 2009 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 2010 * 2011 * (*) value not defined in all devices. 2012 * @retval None 2013 */ 2014 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 2015 { 2016 CLEAR_BIT(RCC->APB1LENR, Periphs); 2017 } 2018 2019 /** 2020 * @brief Force APB1 peripherals reset. 2021 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n 2022 * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n 2023 * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n 2024 * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n 2025 * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n 2026 * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n 2027 * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n 2028 * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n 2029 * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n 2030 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n 2031 * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n 2032 * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n 2033 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n 2034 * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n 2035 * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n 2036 * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n 2037 * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n 2038 * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n 2039 * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n 2040 * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n 2041 * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*) 2042 * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n 2043 * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n 2044 * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n 2045 * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset 2046 * @param Periphs This parameter can be a combination of the following values: 2047 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 2048 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 2049 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 2050 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 2051 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 2052 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 2053 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 2054 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 2055 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 2056 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 2057 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 2058 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 2059 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 2060 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 2061 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 2062 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 2063 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 2064 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 2065 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 2066 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 2067 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 2068 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 2069 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 2070 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 2071 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 2072 * 2073 * (*) value not defined in all devices. 2074 * @retval None 2075 */ 2076 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 2077 { 2078 SET_BIT(RCC->APB1LRSTR, Periphs); 2079 } 2080 2081 /** 2082 * @brief Release APB1 peripherals reset. 2083 * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 2084 * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 2085 * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 2086 * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 2087 * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 2088 * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 2089 * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 2090 * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 2091 * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 2092 * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n 2093 * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 2094 * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 2095 * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n 2096 * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 2097 * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 2098 * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 2099 * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 2100 * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 2101 * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 2102 * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n 2103 * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*) 2104 * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n 2105 * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n 2106 * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n 2107 * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset 2108 * @param Periphs This parameter can be a combination of the following values: 2109 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 2110 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 2111 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 2112 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 2113 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 2114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 2115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 2116 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 2117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 2118 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 2119 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 2120 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 2121 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 2122 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 2123 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 2124 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 2125 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 2126 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 2127 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 2128 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 2129 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 2130 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 2131 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 2132 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 2133 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 2134 * 2135 * (*) value not defined in all devices. 2136 * @retval None 2137 */ 2138 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 2139 { 2140 CLEAR_BIT(RCC->APB1LRSTR, Periphs); 2141 } 2142 2143 /** 2144 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. 2145 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n 2146 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n 2147 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n 2148 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n 2149 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n 2150 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n 2151 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n 2152 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n 2153 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n 2154 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n 2155 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*) 2156 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n 2157 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n 2158 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n 2159 * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n 2160 * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n 2161 * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n 2162 * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n 2163 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n 2164 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n 2165 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n 2166 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*) 2167 * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n 2168 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n 2169 * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n 2170 * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep 2171 * @param Periphs This parameter can be a combination of the following values: 2172 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 2173 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 2174 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 2175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 2176 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 2177 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 2178 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 2179 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 2180 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 2181 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 2182 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 2183 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 2184 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 2185 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 2186 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 2187 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 2188 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 2189 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 2190 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 2191 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 2192 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 2193 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 2194 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 2195 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 2196 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 2197 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 2198 * 2199 * (*) value not defined in all devices. 2200 * @retval None 2201 */ 2202 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 2203 { 2204 __IO uint32_t tmpreg; 2205 SET_BIT(RCC->APB1LLPENR, Periphs); 2206 /* Delay after an RCC peripheral clock enabling */ 2207 tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); 2208 (void)tmpreg; 2209 } 2210 2211 /** 2212 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. 2213 * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n 2214 * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n 2215 * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n 2216 * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n 2217 * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n 2218 * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n 2219 * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n 2220 * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n 2221 * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n 2222 * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n 2223 * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*) 2224 * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n 2225 * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n 2226 * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n 2227 * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n 2228 * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n 2229 * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n 2230 * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n 2231 * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n 2232 * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n 2233 * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n 2234 * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*) 2235 * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n 2236 * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n 2237 * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n 2238 * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep 2239 * @param Periphs This parameter can be a combination of the following values: 2240 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 2241 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 2242 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 2243 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 2244 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 2245 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 2246 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 2247 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 2248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 2249 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 2250 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 2251 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 2252 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 2253 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 2254 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 2255 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 2256 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 2257 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 2258 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 2259 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 2260 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 2261 * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) 2262 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 2263 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 2264 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 2265 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 2266 * 2267 * (*) value not defined in all devices. 2268 * @retval None 2269 */ 2270 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 2271 { 2272 CLEAR_BIT(RCC->APB1LLPENR, Periphs); 2273 } 2274 2275 /** 2276 * @brief Enable APB1 peripherals clock. 2277 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n 2278 * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n 2279 * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n 2280 * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n 2281 * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock 2282 * @param Periphs This parameter can be a combination of the following values: 2283 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2284 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2285 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2286 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2287 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2288 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2289 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2290 * 2291 * (*) value not defined in all devices. 2292 * @retval None 2293 */ 2294 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 2295 { 2296 __IO uint32_t tmpreg; 2297 SET_BIT(RCC->APB1HENR, Periphs); 2298 /* Delay after an RCC peripheral clock enabling */ 2299 tmpreg = READ_BIT(RCC->APB1HENR, Periphs); 2300 (void)tmpreg; 2301 } 2302 2303 /** 2304 * @brief Check if APB1 peripheral clock is enabled or not 2305 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n 2306 * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n 2307 * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n 2308 * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n 2309 * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock 2310 * @param Periphs This parameter can be a combination of the following values: 2311 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2312 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2313 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2314 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2315 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2316 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2317 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2318 * 2319 * (*) value not defined in all devices. 2320 * @retval uint32_t 2321 */ 2322 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 2323 { 2324 return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); 2325 } 2326 2327 /** 2328 * @brief Disable APB1 peripherals clock. 2329 * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n 2330 * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n 2331 * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n 2332 * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n 2333 * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock 2334 * @param Periphs This parameter can be a combination of the following values: 2335 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2336 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2337 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2338 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2339 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2340 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2341 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2342 * 2343 * (*) value not defined in all devices. 2344 * @retval None 2345 */ 2346 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 2347 { 2348 CLEAR_BIT(RCC->APB1HENR, Periphs); 2349 } 2350 2351 /** 2352 * @brief Force APB1 peripherals reset. 2353 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n 2354 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n 2355 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n 2356 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n 2357 * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset 2358 * @param Periphs This parameter can be a combination of the following values: 2359 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2360 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2361 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2362 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2363 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2364 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2365 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2366 * 2367 * (*) value not defined in all devices. 2368 * @retval None 2369 */ 2370 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 2371 { 2372 SET_BIT(RCC->APB1HRSTR, Periphs); 2373 } 2374 2375 /** 2376 * @brief Release APB1 peripherals reset. 2377 * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n 2378 * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n 2379 * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n 2380 * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n 2381 * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset 2382 * @param Periphs This parameter can be a combination of the following values: 2383 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2384 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2385 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2386 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2387 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2388 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2389 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2390 * 2391 * (*) value not defined in all devices. 2392 * @retval None 2393 */ 2394 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 2395 { 2396 CLEAR_BIT(RCC->APB1HRSTR, Periphs); 2397 } 2398 2399 /** 2400 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. 2401 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n 2402 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n 2403 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n 2404 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n 2405 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep 2406 * @param Periphs This parameter can be a combination of the following values: 2407 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2408 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2409 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2410 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2411 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2412 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2413 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2414 * 2415 * (*) value not defined in all devices. 2416 * @retval None 2417 */ 2418 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 2419 { 2420 __IO uint32_t tmpreg; 2421 SET_BIT(RCC->APB1HLPENR, Periphs); 2422 /* Delay after an RCC peripheral clock enabling */ 2423 tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); 2424 (void)tmpreg; 2425 } 2426 2427 /** 2428 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. 2429 * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n 2430 * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n 2431 * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n 2432 * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n 2433 * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep 2434 * @param Periphs This parameter can be a combination of the following values: 2435 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 2436 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 2437 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 2438 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 2439 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 2440 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 2441 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 2442 * 2443 * (*) value not defined in all devices. 2444 * @retval None 2445 */ 2446 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 2447 { 2448 CLEAR_BIT(RCC->APB1HLPENR, Periphs); 2449 } 2450 2451 /** 2452 * @} 2453 */ 2454 2455 /** @defgroup BUS_LL_EF_APB2 APB2 2456 * @ingroup RTEMSBSPsARMSTM32H7 2457 * @{ 2458 */ 2459 2460 /** 2461 * @brief Enable APB2 peripherals clock. 2462 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 2463 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 2464 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 2465 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n 2466 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*) 2467 * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*) 2468 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 2469 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n 2470 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 2471 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 2472 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 2473 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n 2474 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 2475 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 2476 * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*) 2477 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 2478 * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*) 2479 * @param Periphs This parameter can be a combination of the following values: 2480 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2481 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2482 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2483 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2484 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2485 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2486 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2487 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2488 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2489 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2490 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2491 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2492 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2493 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2494 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2495 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2496 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2497 * 2498 * (*) value not defined in all devices. 2499 * @retval None 2500 */ 2501 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 2502 { 2503 __IO uint32_t tmpreg; 2504 SET_BIT(RCC->APB2ENR, Periphs); 2505 /* Delay after an RCC peripheral clock enabling */ 2506 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 2507 (void)tmpreg; 2508 } 2509 2510 /** 2511 * @brief Check if APB2 peripheral clock is enabled or not 2512 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 2513 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 2514 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 2515 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n 2516 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*) 2517 * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*) 2518 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 2519 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n 2520 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 2521 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 2522 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 2523 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n 2524 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 2525 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 2526 * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n 2527 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 2528 * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock 2529 * @param Periphs This parameter can be a combination of the following values: 2530 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2531 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2532 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2533 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2534 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2535 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2536 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2537 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2538 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2539 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2540 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2541 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2542 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2543 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2544 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2545 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2546 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2547 * 2548 * (*) value not defined in all devices. 2549 * @retval uint32_t 2550 */ 2551 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 2552 { 2553 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); 2554 } 2555 2556 /** 2557 * @brief Disable APB2 peripherals clock. 2558 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 2559 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 2560 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 2561 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n 2562 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*) 2563 * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*) 2564 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 2565 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n 2566 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 2567 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 2568 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 2569 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n 2570 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 2571 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 2572 * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*) 2573 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 2574 * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*) 2575 * @param Periphs This parameter can be a combination of the following values: 2576 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2577 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2578 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2579 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2580 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2581 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2582 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2583 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2584 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2585 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2586 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2587 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2588 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2589 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2590 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2591 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2592 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2593 * 2594 * (*) value not defined in all devices. 2595 * @retval None 2596 */ 2597 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 2598 { 2599 CLEAR_BIT(RCC->APB2ENR, Periphs); 2600 } 2601 2602 /** 2603 * @brief Force APB2 peripherals reset. 2604 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 2605 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 2606 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 2607 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n 2608 * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*) 2609 * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*) 2610 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 2611 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n 2612 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 2613 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 2614 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 2615 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n 2616 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 2617 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 2618 * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*) 2619 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 2620 * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*) 2621 * @param Periphs This parameter can be a combination of the following values: 2622 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2623 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2624 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2625 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2626 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2627 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2628 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2629 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2630 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2631 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2632 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2633 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2634 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2635 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2636 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2637 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2638 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2639 * 2640 * (*) value not defined in all devices. 2641 * @retval None 2642 */ 2643 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 2644 { 2645 SET_BIT(RCC->APB2RSTR, Periphs); 2646 } 2647 2648 /** 2649 * @brief Release APB2 peripherals reset. 2650 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 2651 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 2652 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 2653 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n 2654 * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*) 2655 * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*) 2656 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 2657 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n 2658 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 2659 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 2660 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 2661 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n 2662 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 2663 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 2664 * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*) 2665 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 2666 * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*) 2667 * @param Periphs This parameter can be a combination of the following values: 2668 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2669 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2670 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2671 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2672 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2673 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2674 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2675 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2677 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2678 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2679 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2680 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2681 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2682 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2683 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2684 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2685 * 2686 * (*) value not defined in all devices. 2687 * @retval None 2688 */ 2689 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 2690 { 2691 CLEAR_BIT(RCC->APB2RSTR, Periphs); 2692 } 2693 2694 /** 2695 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. 2696 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n 2697 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n 2698 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n 2699 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n 2700 * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 2701 * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 2702 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n 2703 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n 2704 * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n 2705 * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n 2706 * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n 2707 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n 2708 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n 2709 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n 2710 * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*) 2711 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n 2712 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*) 2713 * @param Periphs This parameter can be a combination of the following values: 2714 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2715 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2716 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2717 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2718 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2719 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2720 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2721 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2722 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2723 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2724 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2725 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2726 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2727 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2728 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2729 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2730 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2731 * 2732 * (*) value not defined in all devices. 2733 * @retval None 2734 */ 2735 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 2736 { 2737 __IO uint32_t tmpreg; 2738 SET_BIT(RCC->APB2LPENR, Periphs); 2739 /* Delay after an RCC peripheral clock enabling */ 2740 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); 2741 (void)tmpreg; 2742 } 2743 2744 /** 2745 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. 2746 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n 2747 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n 2748 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n 2749 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n 2750 * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 2751 * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 2752 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n 2753 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n 2754 * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n 2755 * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n 2756 * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n 2757 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n 2758 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n 2759 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n 2760 * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*) 2761 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n 2762 * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*) 2763 * @param Periphs This parameter can be a combination of the following values: 2764 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 2765 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 2766 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 2767 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 2768 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 2769 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 2770 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 2771 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 2772 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 2773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 2774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 2775 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 2776 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 2777 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 2778 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 2779 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 2780 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 2781 * 2782 * (*) value not defined in all devices. 2783 * @retval None 2784 */ 2785 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 2786 { 2787 CLEAR_BIT(RCC->APB2LPENR, Periphs); 2788 } 2789 2790 /** 2791 * @} 2792 */ 2793 2794 /** @defgroup BUS_LL_EF_APB4 APB4 2795 * @ingroup RTEMSBSPsARMSTM32H7 2796 * @{ 2797 */ 2798 2799 /** 2800 * @brief Enable APB4 peripherals clock. 2801 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n 2802 * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n 2803 * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n 2804 * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n 2805 * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n 2806 * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n 2807 * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*) 2808 * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*) 2809 * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*) 2810 * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n 2811 * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n 2812 * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n 2813 * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*) 2814 * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*) 2815 * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*) 2816 * @param Periphs This parameter can be a combination of the following values: 2817 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 2818 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 2819 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 2820 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 2821 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 2822 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 2823 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 2824 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 2825 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 2826 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 2827 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 2828 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 2829 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 2830 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 2831 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 2832 * 2833 * (*) value not defined in all devices. 2834 * @retval None 2835 */ 2836 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) 2837 { 2838 __IO uint32_t tmpreg; 2839 SET_BIT(RCC->APB4ENR, Periphs); 2840 /* Delay after an RCC peripheral clock enabling */ 2841 tmpreg = READ_BIT(RCC->APB4ENR, Periphs); 2842 (void)tmpreg; 2843 } 2844 2845 /** 2846 * @brief Check if APB4 peripheral clock is enabled or not 2847 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n 2848 * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n 2849 * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n 2850 * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n 2851 * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n 2852 * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n 2853 * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*) 2854 * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*) 2855 * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*) 2856 * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n 2857 * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n 2858 * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n 2859 * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*) 2860 * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*) 2861 * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*) 2862 * @param Periphs This parameter can be a combination of the following values: 2863 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 2864 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 2865 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 2866 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 2867 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 2868 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 2869 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 2870 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 2871 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 2872 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 2873 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 2874 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 2875 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 2876 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 2877 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 2878 * 2879 * (*) value not defined in all devices. 2880 * @retval uint32_t 2881 */ 2882 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 2883 { 2884 return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); 2885 } 2886 2887 /** 2888 * @brief Disable APB4 peripherals clock. 2889 * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n 2890 * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n 2891 * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n 2892 * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n 2893 * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n 2894 * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n 2895 * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*) 2896 * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*) 2897 * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*) 2898 * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n 2899 * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n 2900 * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n 2901 * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*) 2902 * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*) 2903 * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*) 2904 * @param Periphs This parameter can be a combination of the following values: 2905 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 2906 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 2907 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 2908 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 2909 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 2910 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 2911 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 2912 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 2913 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 2914 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 2915 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 2916 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 2917 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 2918 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 2919 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 2920 * 2921 * (*) value not defined in all devices. 2922 * @retval None 2923 */ 2924 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) 2925 { 2926 CLEAR_BIT(RCC->APB4ENR, Periphs); 2927 } 2928 2929 /** 2930 * @brief Force APB4 peripherals reset. 2931 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n 2932 * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n 2933 * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n 2934 * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n 2935 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n 2936 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n 2937 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*) 2938 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*) 2939 * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*) 2940 * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n 2941 * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n 2942 * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*) 2943 * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*) 2944 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*) 2945 * @param Periphs This parameter can be a combination of the following values: 2946 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 2947 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 2948 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 2949 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 2950 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 2951 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 2952 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 2953 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 2954 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 2955 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 2956 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 2957 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 2958 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 2959 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 2960 * 2961 * (*) value not defined in all devices. 2962 * @retval None 2963 */ 2964 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) 2965 { 2966 SET_BIT(RCC->APB4RSTR, Periphs); 2967 } 2968 2969 /** 2970 * @brief Release APB4 peripherals reset. 2971 * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n 2972 * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n 2973 * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n 2974 * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n 2975 * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n 2976 * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n 2977 * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*) 2978 * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*) 2979 * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*) 2980 * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n 2981 * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n 2982 * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n 2983 * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*) 2984 * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*) 2985 * @param Periphs This parameter can be a combination of the following values: 2986 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 2987 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 2988 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 2989 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 2990 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 2991 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 2992 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 2993 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 2994 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 2995 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 2996 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 2997 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 2998 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 2999 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 3000 * 3001 * (*) value not defined in all devices. 3002 * @retval None 3003 */ 3004 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) 3005 { 3006 CLEAR_BIT(RCC->APB4RSTR, Periphs); 3007 } 3008 3009 /** 3010 * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. 3011 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n 3012 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n 3013 * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n 3014 * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n 3015 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n 3016 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n 3017 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 3018 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 3019 * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 3020 * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n 3021 * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n 3022 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n 3023 * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) 3024 * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*) 3025 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*) 3026 * @param Periphs This parameter can be a combination of the following values: 3027 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 3028 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 3029 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 3030 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 3031 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 3032 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 3033 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 3034 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 3035 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 3036 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 3037 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 3038 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 3039 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 3040 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 3041 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 3042 * 3043 * (*) value not defined in all devices. 3044 * @retval None 3045 */ 3046 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 3047 { 3048 __IO uint32_t tmpreg; 3049 SET_BIT(RCC->APB4LPENR, Periphs); 3050 /* Delay after an RCC peripheral clock enabling */ 3051 tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); 3052 (void)tmpreg; 3053 } 3054 3055 /** 3056 * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. 3057 * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n 3058 * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n 3059 * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n 3060 * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n 3061 * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n 3062 * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n 3063 * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 3064 * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 3065 * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 3066 * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n 3067 * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n 3068 * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n 3069 * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) 3070 * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*) 3071 * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*) 3072 * @param Periphs This parameter can be a combination of the following values: 3073 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 3074 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 3075 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 3076 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 3077 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 3078 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 3079 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 3080 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 3081 * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) 3082 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 3083 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 3084 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 3085 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 3086 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 3087 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 3088 * 3089 * (*) value not defined in all devices. 3090 * @retval None 3091 */ 3092 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 3093 { 3094 CLEAR_BIT(RCC->APB4LPENR, Periphs); 3095 } 3096 3097 /** 3098 * @} 3099 */ 3100 3101 /** @defgroup BUS_LL_EF_CLKAM CLKAM 3102 * @ingroup RTEMSBSPsARMSTM32H7 3103 * @{ 3104 */ 3105 3106 /** 3107 * @brief Enable peripherals clock for CLKAM Mode. 3108 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n 3109 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n 3110 * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n 3111 * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n 3112 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n 3113 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n 3114 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*) 3115 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*) 3116 * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*) 3117 * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n 3118 * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n 3119 * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n 3120 * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n 3121 * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*) 3122 * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*) 3123 * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*) 3124 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*) 3125 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n 3126 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable 3127 * @param Periphs This parameter can be a combination of the following values: 3128 * @arg @ref LL_CLKAM_PERIPH_BDMA 3129 * @arg @ref LL_CLKAM_PERIPH_GPIO (*) 3130 * @arg @ref LL_CLKAM_PERIPH_LPUART1 3131 * @arg @ref LL_CLKAM_PERIPH_SPI6 3132 * @arg @ref LL_CLKAM_PERIPH_I2C4 3133 * @arg @ref LL_CLKAM_PERIPH_LPTIM2 3134 * @arg @ref LL_CLKAM_PERIPH_LPTIM3 3135 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) 3136 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) 3137 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) 3138 * @arg @ref LL_CLKAM_PERIPH_COMP12 3139 * @arg @ref LL_CLKAM_PERIPH_VREF 3140 * @arg @ref LL_CLKAM_PERIPH_RTC 3141 * @arg @ref LL_CLKAM_PERIPH_CRC (*) 3142 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) 3143 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) 3144 * @arg @ref LL_CLKAM_PERIPH_DTS (*) 3145 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) 3146 * @arg @ref LL_CLKAM_PERIPH_BKPRAM 3147 * @arg @ref LL_CLKAM_PERIPH_SRAM4 3148 * 3149 * (*) value not defined in all devices. 3150 * @retval None 3151 */ 3152 __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) 3153 { 3154 __IO uint32_t tmpreg; 3155 3156 #if defined(RCC_D3AMR_BDMAAMEN) 3157 SET_BIT(RCC->D3AMR, Periphs); 3158 /* Delay after an RCC peripheral clock enabling */ 3159 tmpreg = READ_BIT(RCC->D3AMR, Periphs); 3160 #else 3161 SET_BIT(RCC->SRDAMR, Periphs); 3162 /* Delay after an RCC peripheral clock enabling */ 3163 tmpreg = READ_BIT(RCC->SRDAMR, Periphs); 3164 #endif /* RCC_D3AMR_BDMAAMEN */ 3165 (void)tmpreg; 3166 } 3167 3168 /** 3169 * @brief Disable peripherals clock for CLKAM Mode. 3170 * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n 3171 * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n 3172 * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n 3173 * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n 3174 * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n 3175 * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n 3176 * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*) 3177 * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*) 3178 * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*) 3179 * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n 3180 * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n 3181 * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n 3182 * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n 3183 * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*) 3184 * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*) 3185 * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*) 3186 * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*) 3187 * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n 3188 * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable 3189 * @param Periphs This parameter can be a combination of the following values: 3190 * @arg @ref LL_CLKAM_PERIPH_BDMA 3191 * @arg @ref LL_CLKAM_PERIPH_GPIO (*) 3192 * @arg @ref LL_CLKAM_PERIPH_LPUART1 3193 * @arg @ref LL_CLKAM_PERIPH_SPI6 3194 * @arg @ref LL_CLKAM_PERIPH_I2C4 3195 * @arg @ref LL_CLKAM_PERIPH_LPTIM2 3196 * @arg @ref LL_CLKAM_PERIPH_LPTIM3 3197 * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) 3198 * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) 3199 * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) 3200 * @arg @ref LL_CLKAM_PERIPH_COMP12 3201 * @arg @ref LL_CLKAM_PERIPH_VREF 3202 * @arg @ref LL_CLKAM_PERIPH_RTC 3203 * @arg @ref LL_CLKAM_PERIPH_CRC (*) 3204 * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) 3205 * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) 3206 * @arg @ref LL_CLKAM_PERIPH_DTS (*) 3207 * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) 3208 * @arg @ref LL_CLKAM_PERIPH_BKPRAM 3209 * @arg @ref LL_CLKAM_PERIPH_SRAM4 3210 * 3211 * (*) value not defined in all devices. 3212 * @retval None 3213 */ 3214 __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) 3215 { 3216 #if defined(RCC_D3AMR_BDMAAMEN) 3217 CLEAR_BIT(RCC->D3AMR, Periphs); 3218 #else 3219 CLEAR_BIT(RCC->SRDAMR, Periphs); 3220 #endif /* RCC_D3AMR_BDMAAMEN */ 3221 } 3222 3223 /** 3224 * @} 3225 */ 3226 3227 /** @defgroup BUS_LL_EF_CKGA CKGA 3228 * @ingroup RTEMSBSPsARMSTM32H7 3229 * @{ 3230 */ 3231 3232 #if defined(RCC_CKGAENR_AXICKG) 3233 3234 3235 /** 3236 * @brief Enable clock gating for AXI bus peripherals. 3237 * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n 3238 * CKGAENR AHBCKG LL_CKGA_Enable\n 3239 * CKGAENR CPUCKG LL_CKGA_Enable\n 3240 * CKGAENR SDMMCCKG LL_CKGA_Enable\n 3241 * CKGAENR MDMACKG LL_CKGA_Enable\n 3242 * CKGAENR DMA2DCKG LL_CKGA_Enable\n 3243 * CKGAENR LTDCCKG LL_CKGA_Enable\n 3244 * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n 3245 * CKGAENR AHB12CKG LL_CKGA_Enable\n 3246 * CKGAENR AHB34CKG LL_CKGA_Enable\n 3247 * CKGAENR FLIFTCKG LL_CKGA_Enable\n 3248 * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n 3249 * CKGAENR FMCCKG LL_CKGA_Enable\n 3250 * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n 3251 * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n 3252 * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n 3253 * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n 3254 * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n 3255 * CKGAENR ECCRAMCKG LL_CKGA_Enable\n 3256 * CKGAENR EXTICKG LL_CKGA_Enable\n 3257 * CKGAENR JTAGCKG LL_CKGA_Enable 3258 * @param Periphs This parameter can be a combination of the following values: 3259 * @arg @ref LL_CKGA_PERIPH_AXI 3260 * @arg @ref LL_CKGA_PERIPH_AHB 3261 * @arg @ref LL_CKGA_PERIPH_CPU 3262 * @arg @ref LL_CKGA_PERIPH_SDMMC 3263 * @arg @ref LL_CKGA_PERIPH_MDMA 3264 * @arg @ref LL_CKGA_PERIPH_DMA2D 3265 * @arg @ref LL_CKGA_PERIPH_LTDC 3266 * @arg @ref LL_CKGA_PERIPH_GFXMMUM 3267 * @arg @ref LL_CKGA_PERIPH_AHB12 3268 * @arg @ref LL_CKGA_PERIPH_AHB34 3269 * @arg @ref LL_CKGA_PERIPH_FLIFT 3270 * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 3271 * @arg @ref LL_CKGA_PERIPH_FMC 3272 * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 3273 * @arg @ref LL_CKGA_PERIPH_AXIRAM1 3274 * @arg @ref LL_CKGA_PERIPH_AXIRAM2 3275 * @arg @ref LL_CKGA_PERIPH_AXIRAM3 3276 * @arg @ref LL_CKGA_PERIPH_GFXMMUS 3277 * @arg @ref LL_CKGA_PERIPH_ECCRAM 3278 * @arg @ref LL_CKGA_PERIPH_EXTI 3279 * @arg @ref LL_CKGA_PERIPH_JTAG 3280 * @retval None 3281 */ 3282 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) 3283 { 3284 __IO uint32_t tmpreg; 3285 SET_BIT(RCC->CKGAENR, Periphs); 3286 /* Delay after an RCC peripheral clock enabling */ 3287 tmpreg = READ_BIT(RCC->CKGAENR, Periphs); 3288 (void)tmpreg; 3289 } 3290 3291 #endif /* RCC_CKGAENR_AXICKG */ 3292 3293 #if defined(RCC_CKGAENR_AXICKG) 3294 3295 /** 3296 * @brief Disable clock gating for AXI bus peripherals. 3297 * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n 3298 * CKGAENR AHBCKG LL_CKGA_Enable\n 3299 * CKGAENR CPUCKG LL_CKGA_Enable\n 3300 * CKGAENR SDMMCCKG LL_CKGA_Enable\n 3301 * CKGAENR MDMACKG LL_CKGA_Enable\n 3302 * CKGAENR DMA2DCKG LL_CKGA_Enable\n 3303 * CKGAENR LTDCCKG LL_CKGA_Enable\n 3304 * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n 3305 * CKGAENR AHB12CKG LL_CKGA_Enable\n 3306 * CKGAENR AHB34CKG LL_CKGA_Enable\n 3307 * CKGAENR FLIFTCKG LL_CKGA_Enable\n 3308 * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n 3309 * CKGAENR FMCCKG LL_CKGA_Enable\n 3310 * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n 3311 * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n 3312 * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n 3313 * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n 3314 * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n 3315 * CKGAENR ECCRAMCKG LL_CKGA_Enable\n 3316 * CKGAENR EXTICKG LL_CKGA_Enable\n 3317 * CKGAENR JTAGCKG LL_CKGA_Enable 3318 * @param Periphs This parameter can be a combination of the following values: 3319 * @arg @ref LL_CKGA_PERIPH_AXI 3320 * @arg @ref LL_CKGA_PERIPH_AHB 3321 * @arg @ref LL_CKGA_PERIPH_CPU 3322 * @arg @ref LL_CKGA_PERIPH_SDMMC 3323 * @arg @ref LL_CKGA_PERIPH_MDMA 3324 * @arg @ref LL_CKGA_PERIPH_DMA2D 3325 * @arg @ref LL_CKGA_PERIPH_LTDC 3326 * @arg @ref LL_CKGA_PERIPH_GFXMMUM 3327 * @arg @ref LL_CKGA_PERIPH_AHB12 3328 * @arg @ref LL_CKGA_PERIPH_AHB34 3329 * @arg @ref LL_CKGA_PERIPH_FLIFT 3330 * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 3331 * @arg @ref LL_CKGA_PERIPH_FMC 3332 * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 3333 * @arg @ref LL_CKGA_PERIPH_AXIRAM1 3334 * @arg @ref LL_CKGA_PERIPH_AXIRAM2 3335 * @arg @ref LL_CKGA_PERIPH_AXIRAM3 3336 * @arg @ref LL_CKGA_PERIPH_GFXMMUS 3337 * @arg @ref LL_CKGA_PERIPH_ECCRAM 3338 * @arg @ref LL_CKGA_PERIPH_EXTI 3339 * @arg @ref LL_CKGA_PERIPH_JTAG 3340 * @retval None 3341 */ 3342 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) 3343 { 3344 CLEAR_BIT(RCC->CKGAENR, Periphs); 3345 } 3346 3347 #endif /* RCC_CKGAENR_AXICKG */ 3348 3349 /** 3350 * @} 3351 */ 3352 3353 #if defined(DUAL_CORE) 3354 /** @addtogroup BUS_LL_EF_AHB3 AHB3 3355 * @{ 3356 */ 3357 3358 /** 3359 * @brief Enable C1 AHB3 peripherals clock. 3360 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n 3361 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n 3362 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n 3363 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n 3364 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*) 3365 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*) 3366 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*) 3367 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) 3368 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) 3369 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) 3370 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*) 3371 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock 3372 * @param Periphs This parameter can be a combination of the following values: 3373 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 3374 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 3375 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC 3376 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 3377 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 3378 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 3379 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 3380 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 3381 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 3382 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 3383 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 3384 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 3385 * 3386 * (*) value not defined in all devices. 3387 * @retval None 3388 */ 3389 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) 3390 { 3391 __IO uint32_t tmpreg; 3392 SET_BIT(RCC_C1->AHB3ENR, Periphs); 3393 /* Delay after an RCC peripheral clock enabling */ 3394 tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); 3395 (void)tmpreg; 3396 } 3397 3398 /** 3399 * @brief Check if C1 AHB3 peripheral clock is enabled or not 3400 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n 3401 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n 3402 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n 3403 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n 3404 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3405 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3406 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3407 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3408 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3409 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3410 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) 3411 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock 3412 * @param Periphs This parameter can be a combination of the following values: 3413 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 3414 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 3415 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC 3416 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 3417 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 3418 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 3419 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 3420 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 3421 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 3422 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 3423 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 3424 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 3425 * 3426 * (*) value not defined in all devices. 3427 * @retval uint32_t 3428 */ 3429 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 3430 { 3431 return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); 3432 } 3433 3434 /** 3435 * @brief Disable C1 AHB3 peripherals clock. 3436 * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n 3437 * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n 3438 * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n 3439 * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n 3440 * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*) 3441 * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*) 3442 * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*) 3443 * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) 3444 * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) 3445 * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) 3446 * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*) 3447 * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock 3448 * @param Periphs This parameter can be a combination of the following values: 3449 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 3450 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 3451 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 3452 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 3453 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 3454 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 3455 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 3456 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 3457 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 3458 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 3459 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 3460 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 3461 * 3462 * (*) value not defined in all devices. 3463 * @retval None 3464 */ 3465 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) 3466 { 3467 CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); 3468 } 3469 3470 /** 3471 * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode. 3472 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3473 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3474 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3475 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3476 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3477 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3478 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3479 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3480 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3481 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3482 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) 3483 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3484 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3485 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3486 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3487 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n 3488 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep 3489 * @param Periphs This parameter can be a combination of the following values: 3490 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 3491 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 3492 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 3493 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 3494 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 3495 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 3496 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 3497 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 3498 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 3499 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 3500 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 3501 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 3502 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 3503 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 3504 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 3505 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 3506 * 3507 * (*) value not defined in all devices. 3508 * @retval None 3509 */ 3510 __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 3511 { 3512 __IO uint32_t tmpreg; 3513 SET_BIT(RCC_C1->AHB3LPENR, Periphs); 3514 /* Delay after an RCC peripheral clock enabling */ 3515 tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); 3516 (void)tmpreg; 3517 } 3518 3519 /** 3520 * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode. 3521 * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3522 * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3523 * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3524 * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3525 * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3526 * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3527 * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3528 * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3529 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3530 * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3531 * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) 3532 * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3533 * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3534 * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3535 * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3536 * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n 3537 * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep 3538 * @param Periphs This parameter can be a combination of the following values: 3539 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 3540 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 3541 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 3542 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 3543 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 3544 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 3545 * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) 3546 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) 3547 * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) 3548 * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) 3549 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 3550 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 3551 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 3552 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 3553 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 3554 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 3555 * 3556 * (*) value not defined in all devices. 3557 * @retval None 3558 */ 3559 __STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 3560 { 3561 CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); 3562 } 3563 3564 /** 3565 * @} 3566 */ 3567 3568 /** @addtogroup BUS_LL_EF_AHB1 AHB1 3569 * @{ 3570 */ 3571 3572 /** 3573 * @brief Enable C1 AHB1 peripherals clock. 3574 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n 3575 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n 3576 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n 3577 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3578 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3579 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3580 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3581 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3582 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n 3583 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n 3584 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*) 3585 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*) 3586 * @param Periphs This parameter can be a combination of the following values: 3587 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 3588 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 3589 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 3590 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 3591 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 3592 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 3593 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 3594 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 3595 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 3596 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 3597 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 3598 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 3599 * 3600 * (*) value not defined in all devices. 3601 * @retval None 3602 */ 3603 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) 3604 { 3605 __IO uint32_t tmpreg; 3606 SET_BIT(RCC_C1->AHB1ENR, Periphs); 3607 /* Delay after an RCC peripheral clock enabling */ 3608 tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); 3609 (void)tmpreg; 3610 } 3611 3612 /** 3613 * @brief Check if C1 AHB1 peripheral clock is enabled or not 3614 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n 3615 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n 3616 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n 3617 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3618 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3619 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3620 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3621 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3622 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n 3623 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n 3624 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) 3625 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*) 3626 * @param Periphs This parameter can be a combination of the following values: 3627 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 3628 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 3629 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 3630 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 3631 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 3632 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 3633 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 3634 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 3635 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 3636 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 3637 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 3638 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 3639 * 3640 * (*) value not defined in all devices. 3641 * @retval uint32_t 3642 */ 3643 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 3644 { 3645 return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); 3646 } 3647 3648 /** 3649 * @brief Disable C1 AHB1 peripherals clock. 3650 * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n 3651 * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n 3652 * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n 3653 * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3654 * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3655 * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3656 * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3657 * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3658 * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n 3659 * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n 3660 * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*) 3661 * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*) 3662 * @param Periphs This parameter can be a combination of the following values: 3663 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 3664 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 3665 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 3666 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 3667 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 3668 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 3669 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 3670 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 3671 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 3672 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 3673 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 3674 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 3675 * 3676 * (*) value not defined in all devices. 3677 * @retval None 3678 */ 3679 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) 3680 { 3681 CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); 3682 } 3683 3684 /** 3685 * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode. 3686 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 3687 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 3688 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 3689 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3690 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3691 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3692 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3693 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3694 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 3695 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n 3696 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) 3697 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*) 3698 * @param Periphs This parameter can be a combination of the following values: 3699 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 3700 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 3701 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 3702 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 3703 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 3704 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 3705 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 3706 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 3707 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 3708 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 3709 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 3710 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 3711 * 3712 * (*) value not defined in all devices. 3713 * @retval None 3714 */ 3715 __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 3716 { 3717 __IO uint32_t tmpreg; 3718 SET_BIT(RCC_C1->AHB1LPENR, Periphs); 3719 /* Delay after an RCC peripheral clock enabling */ 3720 tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); 3721 (void)tmpreg; 3722 } 3723 3724 /** 3725 * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode. 3726 * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 3727 * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 3728 * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 3729 * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3730 * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3731 * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3732 * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3733 * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3734 * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 3735 * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n 3736 * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) 3737 * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*) 3738 * @param Periphs This parameter can be a combination of the following values: 3739 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 3740 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 3741 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 3742 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) 3743 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 3744 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 3745 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 3746 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 3747 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 3748 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 3749 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 3750 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 3751 * 3752 * (*) value not defined in all devices. 3753 * @retval None 3754 */ 3755 __STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 3756 { 3757 CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); 3758 } 3759 3760 /** 3761 * @} 3762 */ 3763 3764 /** @addtogroup BUS_LL_EF_AHB2 AHB2 3765 * @{ 3766 */ 3767 3768 /** 3769 * @brief Enable C1 AHB2 peripherals clock. 3770 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n 3771 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*) 3772 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*) 3773 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*) 3774 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n 3775 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n 3776 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*) 3777 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n 3778 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n 3779 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*) 3780 * @param Periphs This parameter can be a combination of the following values: 3781 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 3782 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 3783 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 3784 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 3785 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 3786 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 3787 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 3788 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 3789 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 3790 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 3791 * 3792 * (*) value not defined in all devices. 3793 * @retval None 3794 */ 3795 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) 3796 { 3797 __IO uint32_t tmpreg; 3798 SET_BIT(RCC_C1->AHB2ENR, Periphs); 3799 /* Delay after an RCC peripheral clock enabling */ 3800 tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); 3801 (void)tmpreg; 3802 } 3803 3804 /** 3805 * @brief Check if C1 AHB2 peripheral clock is enabled or not 3806 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n 3807 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 3808 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 3809 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 3810 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n 3811 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n 3812 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) 3813 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n 3814 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n 3815 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*) 3816 * @param Periphs This parameter can be a combination of the following values: 3817 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 3818 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 3819 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 3820 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 3821 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 3822 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 3823 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 3824 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 3825 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 3826 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 3827 * 3828 * (*) value not defined in all devices. 3829 * @retval uint32_t 3830 */ 3831 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 3832 { 3833 return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); 3834 } 3835 3836 /** 3837 * @brief Disable C1 AHB2 peripherals clock. 3838 * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n 3839 * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*) 3840 * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*) 3841 * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*) 3842 * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n 3843 * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n 3844 * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*) 3845 * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n 3846 * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n 3847 * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*) 3848 * @param Periphs This parameter can be a combination of the following values: 3849 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 3850 * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) 3851 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 3852 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 3853 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 3854 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 3855 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 3856 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 3857 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 3858 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 3859 * 3860 * (*) value not defined in all devices. 3861 * @retval None 3862 */ 3863 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) 3864 { 3865 CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); 3866 } 3867 3868 /** 3869 * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode. 3870 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 3871 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 3872 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 3873 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 3874 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 3875 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 3876 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) 3877 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n 3878 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*) 3879 * @param Periphs This parameter can be a combination of the following values: 3880 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 3881 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 3882 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 3883 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 3884 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 3885 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 3886 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 3887 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 3888 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 3889 * 3890 * (*) value not defined in all devices. 3891 * @retval None 3892 */ 3893 __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 3894 { 3895 __IO uint32_t tmpreg; 3896 SET_BIT(RCC_C1->AHB2LPENR, Periphs); 3897 /* Delay after an RCC peripheral clock enabling */ 3898 tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); 3899 (void)tmpreg; 3900 } 3901 3902 /** 3903 * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode. 3904 * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 3905 * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 3906 * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 3907 * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 3908 * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 3909 * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) 3910 * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 3911 * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n 3912 * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep 3913 * @param Periphs This parameter can be a combination of the following values: 3914 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 3915 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 3916 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 3917 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 3918 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 3919 * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) 3920 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 3921 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 3922 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 3923 * 3924 * (*) value not defined in all devices. 3925 * @retval None 3926 */ 3927 __STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 3928 { 3929 CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); 3930 } 3931 3932 /** 3933 * @} 3934 */ 3935 3936 /** @addtogroup BUS_LL_EF_AHB4 AHB4 3937 * @{ 3938 */ 3939 3940 /** 3941 * @brief Enable C1 AHB4 peripherals clock. 3942 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n 3943 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n 3944 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n 3945 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n 3946 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n 3947 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n 3948 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n 3949 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n 3950 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n 3951 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n 3952 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n 3953 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*) 3954 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n 3955 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*) 3956 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*) 3957 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n 3958 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock 3959 * @param Periphs This parameter can be a combination of the following values: 3960 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 3961 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 3962 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 3963 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 3964 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 3965 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 3966 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 3967 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 3968 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 3969 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 3970 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 3971 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 3972 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 3973 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 3974 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 3975 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 3976 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 3977 * 3978 * (*) value not defined in all devices. 3979 * @retval None 3980 */ 3981 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) 3982 { 3983 __IO uint32_t tmpreg; 3984 SET_BIT(RCC_C1->AHB4ENR, Periphs); 3985 /* Delay after an RCC peripheral clock enabling */ 3986 tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); 3987 (void)tmpreg; 3988 } 3989 3990 /** 3991 * @brief Check if C1 AHB4 peripheral clock is enabled or not 3992 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3993 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3994 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3995 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3996 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3997 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3998 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n 3999 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4000 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4001 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4002 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4003 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 4004 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4005 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 4006 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) 4007 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n 4008 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock 4009 * @param Periphs This parameter can be a combination of the following values: 4010 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 4011 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 4012 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 4013 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 4014 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 4015 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 4016 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 4017 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 4018 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 4019 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 4020 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 4021 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 4022 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 4023 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 4024 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 4025 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 4026 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 4027 * 4028 * (*) value not defined in all devices. 4029 * @retval uint32_t 4030 */ 4031 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 4032 { 4033 return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); 4034 } 4035 4036 /** 4037 * @brief Disable C1 AHB4 peripherals clock. 4038 * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n 4039 * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n 4040 * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n 4041 * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n 4042 * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n 4043 * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n 4044 * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n 4045 * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n 4046 * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n 4047 * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n 4048 * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n 4049 * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*) 4050 * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n 4051 * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*) 4052 * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*) 4053 * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n 4054 * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock 4055 * @param Periphs This parameter can be a combination of the following values: 4056 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 4057 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 4058 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 4059 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 4060 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 4061 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 4062 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 4063 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 4064 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 4065 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 4066 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 4067 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 4068 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 4069 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 4070 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 4071 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 4072 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 4073 * 4074 * (*) value not defined in all devices. 4075 * @retval None 4076 */ 4077 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) 4078 { 4079 CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); 4080 } 4081 4082 /** 4083 * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode. 4084 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4085 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4086 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4087 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4088 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4089 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4090 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4091 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4092 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4093 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4094 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4095 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) 4096 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4097 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) 4098 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n 4099 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep 4100 * @param Periphs This parameter can be a combination of the following values: 4101 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 4102 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 4103 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 4104 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 4105 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 4106 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 4107 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 4108 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 4109 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 4110 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 4111 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 4112 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 4113 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 4114 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 4115 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 4116 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 4117 * @retval None 4118 */ 4119 __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 4120 { 4121 __IO uint32_t tmpreg; 4122 SET_BIT(RCC_C1->AHB4LPENR, Periphs); 4123 /* Delay after an RCC peripheral clock enabling */ 4124 tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); 4125 (void)tmpreg; 4126 } 4127 4128 /** 4129 * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode. 4130 * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4131 * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4132 * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4133 * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4134 * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4135 * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4136 * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4137 * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4138 * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4139 * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4140 * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4141 * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) 4142 * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4143 * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) 4144 * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n 4145 * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep 4146 * @param Periphs This parameter can be a combination of the following values: 4147 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 4148 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 4149 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 4150 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 4151 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 4152 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 4153 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 4154 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 4155 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 4156 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 4157 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 4158 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 4159 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 4160 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 4161 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 4162 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 4163 * @retval None 4164 */ 4165 __STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 4166 { 4167 CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); 4168 } 4169 4170 /** 4171 * @} 4172 */ 4173 4174 /** @addtogroup BUS_LL_EF_APB3 APB3 4175 * @{ 4176 */ 4177 4178 /** 4179 * @brief Enable C1 APB3 peripherals clock. 4180 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*) 4181 * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*) 4182 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock 4183 * @param Periphs This parameter can be a combination of the following values: 4184 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 4185 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 4186 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 4187 * 4188 * (*) value not defined in all devices. 4189 * @retval None 4190 */ 4191 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) 4192 { 4193 __IO uint32_t tmpreg; 4194 SET_BIT(RCC_C1->APB3ENR, Periphs); 4195 /* Delay after an RCC peripheral clock enabling */ 4196 tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); 4197 (void)tmpreg; 4198 } 4199 4200 /** 4201 * @brief Check if C1 APB3 peripheral clock is enabled or not 4202 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) 4203 * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) 4204 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock 4205 * @param Periphs This parameter can be a combination of the following values: 4206 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 4207 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 4208 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 4209 * 4210 * (*) value not defined in all devices. 4211 * @retval uint32_t 4212 */ 4213 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 4214 { 4215 return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); 4216 } 4217 4218 /** 4219 * @brief Disable C1 APB3 peripherals clock. 4220 * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*) 4221 * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*) 4222 * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock 4223 * @param Periphs This parameter can be a combination of the following values: 4224 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 4225 4226 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 4227 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 4228 * 4229 * (*) value not defined in all devices. 4230 * @retval None 4231 */ 4232 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) 4233 { 4234 CLEAR_BIT(RCC_C1->APB3ENR, Periphs); 4235 } 4236 4237 /** 4238 * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode. 4239 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) 4240 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) 4241 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep 4242 * @param Periphs This parameter can be a combination of the following values: 4243 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 4244 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 4245 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 4246 * 4247 * (*) value not defined in all devices. 4248 * @retval None 4249 */ 4250 __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 4251 { 4252 __IO uint32_t tmpreg; 4253 SET_BIT(RCC_C1->APB3LPENR, Periphs); 4254 /* Delay after an RCC peripheral clock enabling */ 4255 tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); 4256 (void)tmpreg; 4257 } 4258 4259 /** 4260 * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode. 4261 * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) 4262 * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) 4263 * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep 4264 * @param Periphs This parameter can be a combination of the following values: 4265 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 4266 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 4267 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 4268 * 4269 * (*) value not defined in all devices. 4270 * @retval None 4271 */ 4272 __STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 4273 { 4274 CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); 4275 } 4276 4277 /** 4278 * @} 4279 */ 4280 4281 /** @addtogroup BUS_LL_EF_APB1 APB1 4282 * @{ 4283 */ 4284 4285 /** 4286 * @brief Enable C1 APB1 peripherals clock. 4287 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n 4288 * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n 4289 * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n 4290 * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n 4291 * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n 4292 * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n 4293 * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n 4294 * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n 4295 * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n 4296 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n 4297 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*) 4298 * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n 4299 * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n 4300 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n 4301 * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n 4302 * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n 4303 * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n 4304 * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n 4305 * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n 4306 * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n 4307 * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n 4308 * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n 4309 * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n 4310 * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n 4311 * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock 4312 * @param Periphs This parameter can be a combination of the following values: 4313 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 4314 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 4315 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 4316 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 4317 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 4318 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 4319 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 4320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 4321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 4322 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 4323 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 4324 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 4325 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 4326 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 4327 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 4328 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 4329 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 4330 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 4331 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 4332 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 4333 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 4334 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 4335 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 4336 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 4337 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 4338 * 4339 * (*) value not defined in all devices. 4340 * @retval None 4341 */ 4342 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) 4343 { 4344 __IO uint32_t tmpreg; 4345 SET_BIT(RCC_C1->APB1LENR, Periphs); 4346 /* Delay after an RCC peripheral clock enabling */ 4347 tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); 4348 (void)tmpreg; 4349 } 4350 4351 /** 4352 * @brief Check if C1 APB1 peripheral clock is enabled or not 4353 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n 4354 * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n 4355 * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n 4356 * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n 4357 * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n 4358 * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n 4359 * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n 4360 * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n 4361 * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n 4362 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n 4363 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*) 4364 * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n 4365 * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n 4366 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n 4367 * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n 4368 * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n 4369 * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n 4370 * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n 4371 * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n 4372 * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n 4373 * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n 4374 * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n 4375 * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n 4376 * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n 4377 * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock 4378 * @param Periphs This parameter can be a combination of the following values: 4379 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 4380 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 4381 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 4382 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 4383 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 4384 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 4385 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 4386 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 4387 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 4388 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 4389 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 4390 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 4391 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 4392 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 4393 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 4394 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 4395 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 4396 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 4397 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 4398 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 4399 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 4400 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 4401 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 4402 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 4403 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 4404 * 4405 * (*) value not defined in all devices. 4406 * @retval uint32_t 4407 */ 4408 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 4409 { 4410 return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); 4411 } 4412 4413 /** 4414 * @brief Disable C1 APB1 peripherals clock. 4415 * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n 4416 * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n 4417 * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n 4418 * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n 4419 * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n 4420 * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n 4421 * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n 4422 * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n 4423 * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n 4424 * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n 4425 * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*) 4426 * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n 4427 * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n 4428 * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n 4429 * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n 4430 * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n 4431 * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n 4432 * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n 4433 * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n 4434 * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n 4435 * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n 4436 * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n 4437 * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n 4438 * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n 4439 * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock 4440 * @param Periphs This parameter can be a combination of the following values: 4441 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 4442 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 4443 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 4444 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 4445 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 4446 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 4447 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 4448 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 4449 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 4450 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 4451 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 4452 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 4453 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 4454 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 4455 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 4456 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 4457 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 4458 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 4459 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 4460 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 4461 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 4462 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 4463 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 4464 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 4465 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 4466 * 4467 * (*) value not defined in all devices. 4468 * @retval uint32_t 4469 */ 4470 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) 4471 { 4472 CLEAR_BIT(RCC_C1->APB1LENR, Periphs); 4473 } 4474 4475 /** 4476 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. 4477 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4478 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4479 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4480 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4481 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4482 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4483 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4484 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4485 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4486 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4487 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*) 4488 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4489 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4490 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4491 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4492 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4493 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4494 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4495 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4496 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4497 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4498 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4499 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4500 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n 4501 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep 4502 * @param Periphs This parameter can be a combination of the following values: 4503 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 4504 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 4505 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 4506 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 4507 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 4508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 4509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 4510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 4511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 4512 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 4513 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 4514 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 4515 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 4516 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 4517 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 4518 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 4519 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 4520 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 4521 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 4522 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 4523 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 4524 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 4525 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 4526 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 4527 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 4528 * 4529 * (*) value not defined in all devices. 4530 * @retval None 4531 */ 4532 __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 4533 { 4534 __IO uint32_t tmpreg; 4535 SET_BIT(RCC_C1->APB1LLPENR, Periphs); 4536 /* Delay after an RCC peripheral clock enabling */ 4537 tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); 4538 (void)tmpreg; 4539 } 4540 4541 /** 4542 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. 4543 * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4544 * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4545 * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4546 * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4547 * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4548 * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4549 * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4550 * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4551 * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4552 * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4553 * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*) 4554 * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4555 * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4556 * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4557 * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4558 * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4559 * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4560 * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4561 * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4562 * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4563 * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4564 * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4565 * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4566 * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n 4567 * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep 4568 * @param Periphs This parameter can be a combination of the following values: 4569 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 4570 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 4571 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 4572 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 4573 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 4574 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 4575 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 4576 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 4577 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 4578 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 4579 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 4580 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 4581 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 4582 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 4583 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 4584 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 4585 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 4586 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 4587 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 4588 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 4589 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 4590 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 4591 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 4592 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 4593 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 4594 * 4595 * (*) value not defined in all devices. 4596 * @retval None 4597 */ 4598 __STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 4599 { 4600 CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); 4601 } 4602 4603 /** 4604 * @brief Enable C1 APB1 peripherals clock. 4605 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n 4606 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n 4607 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n 4608 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n 4609 * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock 4610 * @param Periphs This parameter can be a combination of the following values: 4611 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 4612 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 4613 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 4614 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 4615 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 4616 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 4617 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 4618 * 4619 * (*) value not defined in all devices. 4620 * @retval None 4621 */ 4622 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) 4623 { 4624 __IO uint32_t tmpreg; 4625 SET_BIT(RCC_C1->APB1HENR, Periphs); 4626 /* Delay after an RCC peripheral clock enabling */ 4627 tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); 4628 (void)tmpreg; 4629 } 4630 4631 /** 4632 * @brief Check if C1 APB1 peripheral clock is enabled or not 4633 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n 4634 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n 4635 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n 4636 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n 4637 * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock 4638 * @param Periphs This parameter can be a combination of the following values: 4639 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 4640 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 4641 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 4642 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 4643 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 4644 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 4645 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 4646 * 4647 * (*) value not defined in all devices. 4648 * @retval uint32_t 4649 */ 4650 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 4651 { 4652 return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); 4653 } 4654 4655 /** 4656 * @brief Disable C1 APB1 peripherals clock. 4657 * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n 4658 * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n 4659 * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n 4660 * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n 4661 * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock 4662 * @param Periphs This parameter can be a combination of the following values: 4663 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 4664 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 4665 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 4666 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 4667 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 4668 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 4669 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 4670 * 4671 * (*) value not defined in all devices. 4672 * @retval None 4673 */ 4674 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) 4675 { 4676 CLEAR_BIT(RCC_C1->APB1HENR, Periphs); 4677 } 4678 4679 /** 4680 * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. 4681 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 4682 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n 4683 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 4684 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n 4685 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep 4686 * @param Periphs This parameter can be a combination of the following values: 4687 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 4688 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 4689 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 4690 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 4691 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 4692 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 4693 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 4694 * 4695 * (*) value not defined in all devices. 4696 * @retval None 4697 */ 4698 __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 4699 { 4700 __IO uint32_t tmpreg; 4701 SET_BIT(RCC_C1->APB1HLPENR, Periphs); 4702 /* Delay after an RCC peripheral clock enabling */ 4703 tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); 4704 (void)tmpreg; 4705 } 4706 4707 /** 4708 * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. 4709 * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 4710 * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n 4711 * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 4712 * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n 4713 * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep 4714 * @param Periphs This parameter can be a combination of the following values: 4715 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 4716 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 4717 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 4718 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 4719 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 4720 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 4721 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 4722 * 4723 * (*) value not defined in all devices. 4724 * @retval None 4725 */ 4726 __STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 4727 { 4728 CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); 4729 } 4730 4731 /** 4732 * @} 4733 */ 4734 4735 /** @addtogroup BUS_LL_EF_APB2 APB2 4736 * @{ 4737 */ 4738 4739 /** 4740 * @brief Enable C1 APB2 peripherals clock. 4741 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n 4742 * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n 4743 * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n 4744 * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n 4745 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*) 4746 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*) 4747 * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n 4748 * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n 4749 * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n 4750 * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n 4751 * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n 4752 * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n 4753 * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n 4754 * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n 4755 * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*) 4756 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n 4757 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*) 4758 * @param Periphs This parameter can be a combination of the following values: 4759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 4760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 4761 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 4762 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 4763 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 4764 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 4765 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 4766 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 4767 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 4768 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 4769 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 4770 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 4771 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 4772 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 4773 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 4774 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 4775 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 4776 * 4777 * (*) value not defined in all devices. 4778 * @retval None 4779 */ 4780 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) 4781 { 4782 __IO uint32_t tmpreg; 4783 SET_BIT(RCC_C1->APB2ENR, Periphs); 4784 /* Delay after an RCC peripheral clock enabling */ 4785 tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); 4786 (void)tmpreg; 4787 } 4788 4789 /** 4790 * @brief Check if C1 APB2 peripheral clock is enabled or not 4791 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n 4792 * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n 4793 * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n 4794 * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n 4795 * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 4796 * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 4797 * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n 4798 * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n 4799 * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n 4800 * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n 4801 * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n 4802 * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n 4803 * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n 4804 * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n 4805 * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) 4806 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n 4807 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*) 4808 * @param Periphs This parameter can be a combination of the following values: 4809 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 4810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 4811 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 4812 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 4813 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 4814 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 4815 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 4816 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 4817 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 4818 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 4819 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 4820 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 4821 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 4822 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 4823 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 4824 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 4825 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 4826 * 4827 * (*) value not defined in all devices. 4828 * @retval None 4829 */ 4830 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 4831 { 4832 return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); 4833 } 4834 4835 /** 4836 * @brief Disable C1 APB2 peripherals clock. 4837 * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n 4838 * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n 4839 * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n 4840 * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n 4841 * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*) 4842 * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*) 4843 * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n 4844 * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n 4845 * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n 4846 * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n 4847 * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n 4848 * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n 4849 * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n 4850 * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n 4851 * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*) 4852 * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n 4853 * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*) 4854 * @param Periphs This parameter can be a combination of the following values: 4855 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 4856 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 4857 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 4858 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 4859 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 4860 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 4861 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 4862 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 4863 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 4864 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 4865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 4866 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 4867 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 4868 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 4869 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 4870 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 4871 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 4872 * 4873 * (*) value not defined in all devices. 4874 * @retval None 4875 */ 4876 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) 4877 { 4878 CLEAR_BIT(RCC_C1->APB2ENR, Periphs); 4879 } 4880 4881 /** 4882 * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode. 4883 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4884 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4885 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4886 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4887 * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 4888 * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 4889 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4890 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4891 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4892 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4893 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4894 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4895 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4896 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4897 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*) 4898 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n 4899 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*) 4900 * @param Periphs This parameter can be a combination of the following values: 4901 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 4902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 4903 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 4904 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 4905 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 4906 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 4907 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 4908 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 4909 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 4910 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 4911 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 4912 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 4913 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 4914 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 4915 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 4916 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 4917 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 4918 * 4919 * (*) value not defined in all devices. 4920 * @retval None 4921 */ 4922 __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 4923 { 4924 __IO uint32_t tmpreg; 4925 SET_BIT(RCC_C1->APB2LPENR, Periphs); 4926 /* Delay after an RCC peripheral clock enabling */ 4927 tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); 4928 (void)tmpreg; 4929 } 4930 4931 /** 4932 * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode. 4933 * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4934 * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4935 * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4936 * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 4937 * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 4938 * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4939 * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4940 * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4941 * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4942 * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4943 * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4944 * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4945 * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4946 * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4947 * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) 4948 * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n 4949 * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*) 4950 * @param Periphs This parameter can be a combination of the following values: 4951 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 4952 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 4953 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 4954 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 4955 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) 4956 * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) 4957 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 4958 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 4959 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 4960 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 4961 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 4962 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 4963 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 4964 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 4965 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 4966 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 4967 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 4968 * 4969 * (*) value not defined in all devices. 4970 * @retval None 4971 */ 4972 __STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 4973 { 4974 CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); 4975 } 4976 4977 /** 4978 * @} 4979 */ 4980 4981 /** @addtogroup BUS_LL_EF_APB4 APB4 4982 * @{ 4983 */ 4984 4985 /** 4986 * @brief Enable C1 APB4 peripherals clock. 4987 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n 4988 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n 4989 * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n 4990 * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n 4991 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n 4992 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n 4993 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*) 4994 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*) 4995 * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*) 4996 * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n 4997 * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n 4998 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n 4999 * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*) 5000 * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*) 5001 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*) 5002 * @param Periphs This parameter can be a combination of the following values: 5003 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 5004 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 5005 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 5006 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 5007 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 5008 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 5009 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 5010 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 5011 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 5012 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 5013 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 5014 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 5015 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 5016 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 5017 * 5018 * (*) value not defined in all devices. 5019 * @retval None 5020 */ 5021 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) 5022 { 5023 __IO uint32_t tmpreg; 5024 SET_BIT(RCC_C1->APB4ENR, Periphs); 5025 /* Delay after an RCC peripheral clock enabling */ 5026 tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); 5027 (void)tmpreg; 5028 } 5029 5030 /** 5031 * @brief Check if C1 APB4 peripheral clock is enabled or not 5032 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n 5033 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n 5034 * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n 5035 * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n 5036 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n 5037 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n 5038 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 5039 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 5040 * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n 5041 * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n 5042 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n 5043 * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 5044 * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*) 5045 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*) 5046 * @param Periphs This parameter can be a combination of the following values: 5047 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 5048 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 5049 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 5050 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 5051 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 5052 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 5053 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 5054 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 5055 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 5056 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 5057 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 5058 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 5059 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 5060 * 5061 * (*) value not defined in all devices. 5062 * @retval uint32_t 5063 */ 5064 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 5065 { 5066 return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); 5067 } 5068 5069 /** 5070 * @brief Disable C1 APB4 peripherals clock. 5071 * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n 5072 * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n 5073 * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n 5074 * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n 5075 * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n 5076 * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n 5077 * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*) 5078 * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*) 5079 * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n 5080 * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n 5081 * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n 5082 * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*) 5083 * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*) 5084 * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*) 5085 * @param Periphs This parameter can be a combination of the following values: 5086 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 5087 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 5088 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 5089 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 5090 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 5091 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 5092 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 5093 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 5094 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 5095 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 5096 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 5097 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 5098 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 5099 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 5100 * 5101 * (*) value not defined in all devices. 5102 * @retval None 5103 */ 5104 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) 5105 { 5106 CLEAR_BIT(RCC_C1->APB4ENR, Periphs); 5107 } 5108 5109 /** 5110 * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode. 5111 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5112 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5113 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5114 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5115 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5116 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 5117 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 5118 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5119 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5120 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5121 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n 5122 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 5123 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) 5124 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*) 5125 * @param Periphs This parameter can be a combination of the following values: 5126 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 5127 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 5128 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 5129 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 5130 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 5131 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 5132 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 5133 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 5134 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 5135 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 5136 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 5137 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 5138 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 5139 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 5140 * 5141 * (*) value not defined in all devices. 5142 * @retval None 5143 */ 5144 __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 5145 { 5146 __IO uint32_t tmpreg; 5147 SET_BIT(RCC_C1->APB4LPENR, Periphs); 5148 /* Delay after an RCC peripheral clock enabling */ 5149 tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); 5150 (void)tmpreg; 5151 } 5152 5153 /** 5154 * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode. 5155 * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5156 * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5157 * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5158 * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5159 * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5160 * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5161 * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5162 * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5163 * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5164 * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5165 * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n 5166 * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) 5167 * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) 5168 * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*) 5169 * @param Periphs This parameter can be a combination of the following values: 5170 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 5171 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 5172 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 5173 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 5174 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 5175 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 5176 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 5177 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 5178 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 5179 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 5180 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 5181 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 5182 * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) 5183 * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) 5184 * 5185 * (*) value not defined in all devices. 5186 * @retval None 5187 */ 5188 __STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 5189 { 5190 CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); 5191 } 5192 5193 /** 5194 * @} 5195 */ 5196 5197 /** @addtogroup BUS_LL_EF_AHB3 AHB3 5198 * @{ 5199 */ 5200 5201 /** 5202 * @brief Enable C2 AHB3 peripherals clock. 5203 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n 5204 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n 5205 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n 5206 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n 5207 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n 5208 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n 5209 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n 5210 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n 5211 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n 5212 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n 5213 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock 5214 * @param Periphs This parameter can be a combination of the following values: 5215 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 5216 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 5217 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 5218 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 5219 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 5220 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 5221 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 5222 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 5223 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 5224 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 5225 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 5226 * @retval None 5227 */ 5228 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) 5229 { 5230 __IO uint32_t tmpreg; 5231 SET_BIT(RCC_C2->AHB3ENR, Periphs); 5232 /* Delay after an RCC peripheral clock enabling */ 5233 tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); 5234 (void)tmpreg; 5235 } 5236 5237 /** 5238 * @brief Check if C2 AHB3 peripheral clock is enabled or not 5239 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5240 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5241 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5242 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5243 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5244 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n 5245 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5246 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n 5247 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n 5248 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n 5249 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock 5250 * @param Periphs This parameter can be a combination of the following values: 5251 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 5252 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 5253 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 5254 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 5255 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 5256 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 5257 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 5258 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 5259 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 5260 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 5261 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 5262 * @retval uint32_t 5263 */ 5264 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 5265 { 5266 return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); 5267 } 5268 5269 /** 5270 * @brief Disable C2 AHB3 peripherals clock. 5271 * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n 5272 * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n 5273 * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n 5274 * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n 5275 * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n 5276 * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n 5277 * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n 5278 * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n 5279 * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n 5280 * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n 5281 * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock 5282 * @param Periphs This parameter can be a combination of the following values: 5283 * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA 5284 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 5285 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 5286 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 5287 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 5288 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 5289 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 5290 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 5291 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 5292 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 5293 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 5294 * @retval None 5295 */ 5296 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) 5297 { 5298 CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); 5299 } 5300 5301 /** 5302 * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode. 5303 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5304 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5305 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5306 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5307 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5308 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5309 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5310 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5311 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5312 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n 5313 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep 5314 * @param Periphs This parameter can be a combination of the following values: 5315 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 5316 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 5317 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 5318 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 5319 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 5320 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 5321 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 5322 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 5323 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 5324 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 5325 * @retval None 5326 */ 5327 __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) 5328 { 5329 __IO uint32_t tmpreg; 5330 SET_BIT(RCC_C2->AHB3LPENR, Periphs); 5331 /* Delay after an RCC peripheral clock enabling */ 5332 tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); 5333 (void)tmpreg; 5334 } 5335 5336 /** 5337 * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode. 5338 * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5339 * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5340 * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5341 * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5342 * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5343 * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5344 * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5345 * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5346 * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5347 * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n 5348 * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep 5349 * @param Periphs This parameter can be a combination of the following values: 5350 * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D 5351 * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) 5352 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC 5353 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 5354 * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 5355 * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH 5356 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 5357 * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 5358 * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM 5359 * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM 5360 * @retval None 5361 */ 5362 __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) 5363 { 5364 CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); 5365 } 5366 5367 /** 5368 * @} 5369 */ 5370 5371 /** @addtogroup BUS_LL_EF_AHB1 AHB1 5372 * @{ 5373 */ 5374 5375 /** 5376 * @brief Enable C2 AHB1 peripherals clock. 5377 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n 5378 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n 5379 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n 5380 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n 5381 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n 5382 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n 5383 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n 5384 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n 5385 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n 5386 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n 5387 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock 5388 * @param Periphs This parameter can be a combination of the following values: 5389 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 5390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 5391 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 5392 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 5393 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 5394 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 5395 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 5396 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 5397 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 5398 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 5399 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 5400 * 5401 * (*) value not defined in all devices. 5402 * @retval None 5403 */ 5404 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) 5405 { 5406 __IO uint32_t tmpreg; 5407 SET_BIT(RCC_C2->AHB1ENR, Periphs); 5408 /* Delay after an RCC peripheral clock enabling */ 5409 tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); 5410 (void)tmpreg; 5411 } 5412 5413 /** 5414 * @brief Check if C2 AHB1 peripheral clock is enabled or not 5415 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n 5416 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n 5417 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n 5418 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5419 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5420 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5421 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5422 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5423 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5424 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n 5425 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock 5426 * @param Periphs This parameter can be a combination of the following values: 5427 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 5428 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 5429 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 5430 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 5431 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 5432 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 5433 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 5434 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 5435 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 5436 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 5437 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 5438 * 5439 * (*) value not defined in all devices. 5440 * @retval uint32_t 5441 */ 5442 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 5443 { 5444 return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); 5445 } 5446 5447 /** 5448 * @brief Disable C2 AHB1 peripherals clock. 5449 * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n 5450 * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n 5451 * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n 5452 * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n 5453 * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n 5454 * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n 5455 * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n 5456 * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n 5457 * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n 5458 * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n 5459 * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock 5460 * @param Periphs This parameter can be a combination of the following values: 5461 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 5462 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 5463 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 5464 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 5465 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 5466 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 5467 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 5468 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 5469 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 5470 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 5471 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 5472 * 5473 * (*) value not defined in all devices. 5474 * @retval None 5475 */ 5476 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) 5477 { 5478 CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); 5479 } 5480 5481 /** 5482 * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode. 5483 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5484 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5485 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5486 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5487 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5488 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5489 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5490 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5491 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5492 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n 5493 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep 5494 * @param Periphs This parameter can be a combination of the following values: 5495 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 5496 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 5497 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 5498 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 5499 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 5500 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 5501 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 5502 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 5503 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 5504 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 5505 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 5506 * 5507 * (*) value not defined in all devices. 5508 * @retval None 5509 */ 5510 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) 5511 { 5512 __IO uint32_t tmpreg; 5513 SET_BIT(RCC_C2->AHB1LPENR, Periphs); 5514 /* Delay after an RCC peripheral clock enabling */ 5515 tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); 5516 (void)tmpreg; 5517 } 5518 5519 /** 5520 * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode. 5521 * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5522 * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5523 * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5524 * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5525 * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5526 * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5527 * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5528 * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5529 * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5530 * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n 5531 * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep 5532 * @param Periphs This parameter can be a combination of the following values: 5533 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 5534 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 5535 * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 5536 * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) 5537 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) 5538 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) 5539 * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) 5540 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS 5541 * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI 5542 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) 5543 * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) 5544 * 5545 * (*) value not defined in all devices. 5546 * @retval None 5547 */ 5548 __STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) 5549 { 5550 CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); 5551 } 5552 5553 /** 5554 * @} 5555 */ 5556 5557 /** @addtogroup BUS_LL_EF_AHB2 AHB2 5558 * @{ 5559 */ 5560 5561 /** 5562 * @brief Enable C2 AHB2 peripherals clock. 5563 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n 5564 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n 5565 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n 5566 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n 5567 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock 5568 * @param Periphs This parameter can be a combination of the following values: 5569 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 5570 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 5571 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 5572 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 5573 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 5574 * 5575 * (*) value not defined in all devices. 5576 * @retval None 5577 */ 5578 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) 5579 { 5580 __IO uint32_t tmpreg; 5581 SET_BIT(RCC_C2->AHB2ENR, Periphs); 5582 /* Delay after an RCC peripheral clock enabling */ 5583 tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); 5584 (void)tmpreg; 5585 } 5586 5587 /** 5588 * @brief Check if C2 AHB2 peripheral clock is enabled or not 5589 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n 5590 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n 5591 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n 5592 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n 5593 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock 5594 * @param Periphs This parameter can be a combination of the following values: 5595 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 5596 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 5597 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 5598 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 5599 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 5600 * 5601 * (*) value not defined in all devices. 5602 * @retval uint32_t 5603 */ 5604 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 5605 { 5606 return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); 5607 } 5608 5609 /** 5610 * @brief Disable C2 AHB2 peripherals clock. 5611 * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n 5612 * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n 5613 * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n 5614 * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n 5615 * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock 5616 * @param Periphs This parameter can be a combination of the following values: 5617 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 5618 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 5619 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 5620 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 5621 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 5622 * 5623 * (*) value not defined in all devices. 5624 * @retval None 5625 */ 5626 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) 5627 { 5628 CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); 5629 } 5630 5631 /** 5632 * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode. 5633 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5634 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5635 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5636 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5637 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5638 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5639 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n 5640 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep 5641 * @param Periphs This parameter can be a combination of the following values: 5642 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 5643 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 5644 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 5645 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 5646 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 5647 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 5648 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 5649 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 5650 * 5651 * (*) value not defined in all devices. 5652 * @retval None 5653 */ 5654 __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) 5655 { 5656 __IO uint32_t tmpreg; 5657 SET_BIT(RCC_C2->AHB2LPENR, Periphs); 5658 /* Delay after an RCC peripheral clock enabling */ 5659 tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); 5660 (void)tmpreg; 5661 } 5662 5663 /** 5664 * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode. 5665 * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5666 * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5667 * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5668 * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5669 * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5670 * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5671 * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n 5672 * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep 5673 * @param Periphs This parameter can be a combination of the following values: 5674 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI 5675 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) 5676 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 5677 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 5678 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 5679 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 5680 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 5681 * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) 5682 * 5683 * (*) value not defined in all devices. 5684 * @retval None 5685 */ 5686 __STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) 5687 { 5688 CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); 5689 } 5690 5691 /** 5692 * @} 5693 */ 5694 5695 /** @addtogroup BUS_LL_EF_AHB4 AHB4 5696 * @{ 5697 */ 5698 5699 /** 5700 * @brief Enable C2 AHB4 peripherals clock. 5701 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n 5702 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n 5703 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n 5704 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n 5705 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n 5706 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n 5707 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n 5708 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n 5709 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n 5710 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n 5711 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n 5712 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n 5713 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n 5714 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n 5715 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n 5716 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n 5717 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock 5718 * @param Periphs This parameter can be a combination of the following values: 5719 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 5720 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 5721 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 5722 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 5723 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 5724 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 5725 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 5726 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 5727 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 5728 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 5729 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 5730 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 5731 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 5732 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 5733 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 5734 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 5735 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 5736 * 5737 * (*) value not defined in all devices. 5738 * @retval None 5739 */ 5740 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) 5741 { 5742 __IO uint32_t tmpreg; 5743 SET_BIT(RCC_C2->AHB4ENR, Periphs); 5744 /* Delay after an RCC peripheral clock enabling */ 5745 tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); 5746 (void)tmpreg; 5747 } 5748 5749 /** 5750 * @brief Check if C2 AHB4 peripheral clock is enabled or not 5751 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5752 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5753 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5754 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5755 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5756 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5757 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5758 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5759 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5760 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5761 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5762 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5763 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5764 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n 5765 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5766 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n 5767 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock 5768 * @param Periphs This parameter can be a combination of the following values: 5769 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 5770 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 5771 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 5772 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 5773 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 5774 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 5775 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 5776 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 5777 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 5778 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 5779 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 5780 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 5781 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 5782 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 5783 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 5784 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 5785 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 5786 * 5787 * (*) value not defined in all devices. 5788 * @retval uint32_t 5789 */ 5790 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) 5791 { 5792 return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); 5793 } 5794 5795 /** 5796 * @brief Disable C2 AHB4 peripherals clock. 5797 * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n 5798 * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n 5799 * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n 5800 * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n 5801 * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n 5802 * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n 5803 * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n 5804 * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n 5805 * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n 5806 * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n 5807 * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n 5808 * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n 5809 * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n 5810 * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n 5811 * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n 5812 * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n 5813 * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock 5814 * @param Periphs This parameter can be a combination of the following values: 5815 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 5816 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 5817 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 5818 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 5819 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 5820 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 5821 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 5822 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 5823 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 5824 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 5825 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 5826 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 5827 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 5828 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 5829 * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) 5830 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 5831 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 5832 * 5833 * (*) value not defined in all devices. 5834 * @retval None 5835 */ 5836 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) 5837 { 5838 CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); 5839 } 5840 5841 /** 5842 * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode. 5843 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5844 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5845 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5846 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5847 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5848 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5849 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5850 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5851 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5852 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5853 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5854 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5855 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5856 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5857 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n 5858 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep 5859 * @param Periphs This parameter can be a combination of the following values: 5860 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 5861 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 5862 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 5863 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 5864 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 5865 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 5866 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 5867 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 5868 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 5869 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 5870 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 5871 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 5872 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 5873 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 5874 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 5875 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 5876 * @retval None 5877 */ 5878 __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) 5879 { 5880 __IO uint32_t tmpreg; 5881 SET_BIT(RCC_C2->AHB4LPENR, Periphs); 5882 /* Delay after an RCC peripheral clock enabling */ 5883 tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); 5884 (void)tmpreg; 5885 } 5886 5887 /** 5888 * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode. 5889 * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5890 * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5891 * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5892 * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5893 * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5894 * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5895 * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5896 * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5897 * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5898 * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5899 * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5900 * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5901 * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5902 * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5903 * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n 5904 * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep 5905 * @param Periphs This parameter can be a combination of the following values: 5906 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA 5907 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB 5908 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC 5909 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD 5910 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE 5911 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF 5912 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG 5913 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH 5914 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) 5915 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ 5916 * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK 5917 * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) 5918 * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA 5919 * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) 5920 * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM 5921 * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 5922 * @retval None 5923 */ 5924 __STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) 5925 { 5926 CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); 5927 } 5928 5929 /** 5930 * @} 5931 */ 5932 5933 /** @addtogroup BUS_LL_EF_APB3 APB3 5934 * @{ 5935 */ 5936 5937 /** 5938 * @brief Enable C2 APB3 peripherals clock. 5939 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n 5940 * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n 5941 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock 5942 * @param Periphs This parameter can be a combination of the following values: 5943 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 5944 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 5945 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 5946 * 5947 * (*) value not defined in all devices. 5948 * @retval None 5949 */ 5950 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) 5951 { 5952 __IO uint32_t tmpreg; 5953 SET_BIT(RCC_C2->APB3ENR, Periphs); 5954 /* Delay after an RCC peripheral clock enabling */ 5955 tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); 5956 (void)tmpreg; 5957 } 5958 5959 /** 5960 * @brief Check if C2 APB3 peripheral clock is enabled or not 5961 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n 5962 * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n 5963 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock 5964 * @param Periphs This parameter can be a combination of the following values: 5965 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 5966 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 5967 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 5968 * 5969 * (*) value not defined in all devices. 5970 * @retval uint32_t 5971 */ 5972 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) 5973 { 5974 return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); 5975 } 5976 5977 /** 5978 * @brief Disable C2 APB3 peripherals clock. 5979 * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n 5980 * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n 5981 * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock 5982 * @param Periphs This parameter can be a combination of the following values: 5983 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 5984 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 5985 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 5986 * 5987 * (*) value not defined in all devices. 5988 * @retval None 5989 */ 5990 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) 5991 { 5992 CLEAR_BIT(RCC_C2->APB3ENR, Periphs); 5993 } 5994 5995 /** 5996 * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode. 5997 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n 5998 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n 5999 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep 6000 * @param Periphs This parameter can be a combination of the following values: 6001 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 6002 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 6003 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 6004 * 6005 * (*) value not defined in all devices. 6006 * @retval None 6007 */ 6008 __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) 6009 { 6010 __IO uint32_t tmpreg; 6011 SET_BIT(RCC_C2->APB3LPENR, Periphs); 6012 /* Delay after an RCC peripheral clock enabling */ 6013 tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); 6014 (void)tmpreg; 6015 } 6016 6017 /** 6018 * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode. 6019 * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n 6020 * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n 6021 * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep 6022 * @param Periphs This parameter can be a combination of the following values: 6023 * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) 6024 * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) 6025 * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 6026 * 6027 * (*) value not defined in all devices. 6028 * @retval None 6029 */ 6030 __STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) 6031 { 6032 CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); 6033 } 6034 6035 /** 6036 * @} 6037 */ 6038 6039 /** @addtogroup BUS_LL_EF_APB1 APB1 6040 * @{ 6041 */ 6042 6043 /** 6044 * @brief Enable C2 APB1 peripherals clock. 6045 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n 6046 * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n 6047 * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n 6048 * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n 6049 * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n 6050 * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n 6051 * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n 6052 * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n 6053 * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n 6054 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n 6055 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n 6056 * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n 6057 * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n 6058 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n 6059 * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n 6060 * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n 6061 * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n 6062 * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n 6063 * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n 6064 * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n 6065 * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n 6066 * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n 6067 * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n 6068 * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n 6069 * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock 6070 * @param Periphs This parameter can be a combination of the following values: 6071 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 6072 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 6073 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 6074 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 6075 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 6076 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 6077 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 6078 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 6079 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 6080 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 6081 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 6082 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 6083 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 6084 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 6085 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 6086 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 6087 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 6088 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 6089 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 6090 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 6091 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 6092 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 6093 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 6094 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 6095 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 6096 * 6097 * (*) value not defined in all devices. 6098 * @retval None 6099 */ 6100 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) 6101 { 6102 __IO uint32_t tmpreg; 6103 SET_BIT(RCC_C2->APB1LENR, Periphs); 6104 /* Delay after an RCC peripheral clock enabling */ 6105 tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); 6106 (void)tmpreg; 6107 } 6108 6109 /** 6110 * @brief Check if C2 APB1 peripheral clock is enabled or not 6111 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n 6112 * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n 6113 * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n 6114 * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n 6115 * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n 6116 * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n 6117 * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n 6118 * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n 6119 * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n 6120 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n 6121 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n 6122 * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n 6123 * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n 6124 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n 6125 * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n 6126 * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n 6127 * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n 6128 * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n 6129 * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n 6130 * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n 6131 * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n 6132 * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n 6133 * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n 6134 * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n 6135 * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock 6136 * @param Periphs This parameter can be a combination of the following values: 6137 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 6138 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 6139 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 6140 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 6141 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 6142 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 6143 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 6144 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 6145 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 6146 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 6147 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 6148 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 6149 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 6150 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 6151 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 6152 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 6153 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 6154 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 6155 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 6156 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 6157 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 6158 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 6159 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 6160 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 6161 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 6162 * 6163 * (*) value not defined in all devices. 6164 * @retval uint32_t 6165 */ 6166 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 6167 { 6168 return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); 6169 } 6170 6171 /** 6172 * @brief Disable C2 APB1 peripherals clock. 6173 * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n 6174 * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n 6175 * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n 6176 * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n 6177 * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n 6178 * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n 6179 * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n 6180 * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n 6181 * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n 6182 * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n 6183 * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n 6184 * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n 6185 * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n 6186 * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n 6187 * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n 6188 * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n 6189 * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n 6190 * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n 6191 * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n 6192 * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n 6193 * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n 6194 * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n 6195 * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n 6196 * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n 6197 * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock 6198 * @param Periphs This parameter can be a combination of the following values: 6199 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 6200 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 6201 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 6202 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 6203 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 6204 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 6205 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 6206 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 6207 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 6208 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 6209 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 6210 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 6211 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 6212 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 6213 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 6214 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 6215 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 6216 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 6217 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 6218 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 6219 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 6220 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 6221 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 6222 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 6223 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 6224 * 6225 * (*) value not defined in all devices. 6226 * @retval None 6227 */ 6228 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) 6229 { 6230 CLEAR_BIT(RCC_C2->APB1LENR, Periphs); 6231 } 6232 6233 /** 6234 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. 6235 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6236 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6237 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6238 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6239 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6240 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6241 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6242 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6243 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6244 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6245 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6246 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6247 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6248 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6249 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6250 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6251 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6252 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6253 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6254 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6255 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6256 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6257 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6258 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n 6259 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep 6260 * @param Periphs This parameter can be a combination of the following values: 6261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 6262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 6263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 6264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 6265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 6266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 6267 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 6268 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 6269 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 6270 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 6271 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 6272 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 6273 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 6274 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 6275 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 6276 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 6277 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 6278 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 6279 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 6280 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 6281 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 6282 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 6283 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 6284 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 6285 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 6286 * 6287 * (*) value not defined in all devices. 6288 * @retval None 6289 */ 6290 __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) 6291 { 6292 __IO uint32_t tmpreg; 6293 SET_BIT(RCC_C2->APB1LLPENR, Periphs); 6294 /* Delay after an RCC peripheral clock enabling */ 6295 tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); 6296 (void)tmpreg; 6297 } 6298 6299 /** 6300 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. 6301 * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6302 * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6303 * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6304 * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6305 * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6306 * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6307 * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6308 * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6309 * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6310 * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6311 * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6312 * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6313 * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6314 * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6315 * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6316 * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6317 * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6318 * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6319 * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6320 * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6321 * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6322 * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6323 * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6324 * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n 6325 * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep 6326 * @param Periphs This parameter can be a combination of the following values: 6327 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 6328 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 6329 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 6330 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 6331 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 6332 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 6333 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 6334 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 6335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 6336 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 6337 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) 6338 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 6339 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 6340 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX 6341 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 6342 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 6343 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 6344 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 6345 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 6346 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 6347 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 6348 * @arg @ref LL_APB1_GRP1_PERIPH_CEC 6349 * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 6350 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 6351 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 6352 * 6353 * (*) value not defined in all devices. 6354 * @retval None 6355 */ 6356 __STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) 6357 { 6358 CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); 6359 } 6360 6361 /** 6362 * @brief Enable C2 APB1 peripherals clock. 6363 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n 6364 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n 6365 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n 6366 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n 6367 * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock 6368 * @param Periphs This parameter can be a combination of the following values: 6369 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 6370 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 6371 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 6372 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 6373 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 6374 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 6375 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 6376 * 6377 * (*) value not defined in all devices. 6378 * @retval None 6379 */ 6380 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) 6381 { 6382 __IO uint32_t tmpreg; 6383 SET_BIT(RCC_C2->APB1HENR, Periphs); 6384 /* Delay after an RCC peripheral clock enabling */ 6385 tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); 6386 (void)tmpreg; 6387 } 6388 6389 /** 6390 * @brief Check if C2 APB1 peripheral clock is enabled or not 6391 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n 6392 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n 6393 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n 6394 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n 6395 * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock 6396 * @param Periphs This parameter can be a combination of the following values: 6397 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 6398 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 6399 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 6400 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 6401 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 6402 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 6403 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 6404 * 6405 * (*) value not defined in all devices. 6406 * @retval uint32_t 6407 */ 6408 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 6409 { 6410 return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); 6411 } 6412 6413 /** 6414 * @brief Disable C2 APB1 peripherals clock. 6415 * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n 6416 * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n 6417 * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n 6418 * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n 6419 * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock 6420 * @param Periphs This parameter can be a combination of the following values: 6421 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 6422 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 6423 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 6424 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 6425 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 6426 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 6427 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 6428 * 6429 * (*) value not defined in all devices. 6430 * @retval None 6431 */ 6432 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) 6433 { 6434 CLEAR_BIT(RCC_C2->APB1HENR, Periphs); 6435 } 6436 6437 /** 6438 * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. 6439 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 6440 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n 6441 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 6442 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n 6443 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep 6444 * @param Periphs This parameter can be a combination of the following values: 6445 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 6446 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 6447 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 6448 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 6449 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 6450 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 6451 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 6452 * 6453 * (*) value not defined in all devices. 6454 * @retval None 6455 */ 6456 __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) 6457 { 6458 __IO uint32_t tmpreg; 6459 SET_BIT(RCC_C2->APB1HLPENR, Periphs); 6460 /* Delay after an RCC peripheral clock enabling */ 6461 tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); 6462 (void)tmpreg; 6463 } 6464 6465 /** 6466 * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. 6467 * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 6468 * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n 6469 * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 6470 * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n 6471 * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep 6472 * @param Periphs This parameter can be a combination of the following values: 6473 * @arg @ref LL_APB1_GRP2_PERIPH_CRS 6474 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 6475 * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP 6476 * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS 6477 * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN 6478 * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) 6479 * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) 6480 * 6481 * (*) value not defined in all devices. 6482 * @retval None 6483 */ 6484 __STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) 6485 { 6486 CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); 6487 } 6488 6489 /** 6490 * @} 6491 */ 6492 6493 /** @addtogroup BUS_LL_EF_APB2 APB2 6494 * @{ 6495 */ 6496 6497 /** 6498 * @brief Enable C2 APB2 peripherals clock. 6499 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n 6500 * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n 6501 * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n 6502 * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n 6503 * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n 6504 * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n 6505 * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n 6506 * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n 6507 * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n 6508 * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n 6509 * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n 6510 * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n 6511 * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n 6512 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n 6513 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock 6514 * @param Periphs This parameter can be a combination of the following values: 6515 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 6516 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 6517 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 6518 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 6519 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 6520 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 6521 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 6522 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 6523 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 6524 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 6525 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 6526 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 6527 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 6528 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 6529 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 6530 * 6531 * (*) value not defined in all devices. 6532 6533 * @retval None 6534 */ 6535 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) 6536 { 6537 __IO uint32_t tmpreg; 6538 SET_BIT(RCC_C2->APB2ENR, Periphs); 6539 /* Delay after an RCC peripheral clock enabling */ 6540 tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); 6541 (void)tmpreg; 6542 } 6543 6544 /** 6545 * @brief Check if C2 APB2 peripheral clock is enabled or not 6546 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n 6547 * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n 6548 * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n 6549 * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n 6550 * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n 6551 * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n 6552 * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n 6553 * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n 6554 * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n 6555 * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n 6556 * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n 6557 * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n 6558 * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n 6559 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n 6560 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock 6561 * @param Periphs This parameter can be a combination of the following values: 6562 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 6563 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 6564 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 6565 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 6566 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 6567 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 6568 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 6569 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 6570 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 6571 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 6572 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 6573 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 6574 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 6575 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 6576 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 6577 * 6578 * (*) value not defined in all devices. 6579 * @retval uint32_t 6580 */ 6581 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 6582 { 6583 return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); 6584 } 6585 6586 /** 6587 * @brief Disable C2 APB2 peripherals clock. 6588 * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n 6589 * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n 6590 * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n 6591 * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n 6592 * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n 6593 * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n 6594 * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n 6595 * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n 6596 * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n 6597 * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n 6598 * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n 6599 * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n 6600 * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n 6601 * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n 6602 * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock 6603 * @param Periphs This parameter can be a combination of the following values: 6604 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 6605 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 6606 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 6607 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 6608 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 6609 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 6610 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 6611 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 6612 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 6613 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 6614 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 6615 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 6616 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 6617 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 6618 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 6619 * 6620 * (*) value not defined in all devices. 6621 * @retval None 6622 */ 6623 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) 6624 { 6625 CLEAR_BIT(RCC_C2->APB2ENR, Periphs); 6626 } 6627 6628 /** 6629 * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode. 6630 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6631 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6632 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6633 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6634 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6635 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6636 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6637 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6638 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6639 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6640 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6641 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6642 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6643 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n 6644 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep 6645 * @param Periphs This parameter can be a combination of the following values: 6646 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 6647 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 6648 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 6649 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 6650 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 6651 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 6652 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 6653 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 6654 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 6655 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 6656 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 6657 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 6658 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 6659 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 6660 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 6661 * 6662 * (*) value not defined in all devices. 6663 * @retval None 6664 */ 6665 __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) 6666 { 6667 __IO uint32_t tmpreg; 6668 SET_BIT(RCC_C2->APB2LPENR, Periphs); 6669 /* Delay after an RCC peripheral clock enabling */ 6670 tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); 6671 (void)tmpreg; 6672 } 6673 6674 /** 6675 * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode. 6676 * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6677 * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6678 * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6679 * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6680 * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6681 * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6682 * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6683 * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6684 * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6685 * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6686 * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6687 * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6688 * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6689 * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n 6690 * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep 6691 * @param Periphs This parameter can be a combination of the following values: 6692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 6693 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 6694 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 6695 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 6696 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 6697 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 6698 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 6699 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 6700 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 6701 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 6702 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 6703 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 6704 * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) 6705 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 6706 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) 6707 * 6708 * (*) value not defined in all devices. 6709 * @retval None 6710 */ 6711 __STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) 6712 { 6713 CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); 6714 } 6715 6716 /** 6717 * @} 6718 */ 6719 6720 /** @addtogroup BUS_LL_EF_APB4 APB4 6721 * @{ 6722 */ 6723 6724 /** 6725 * @brief Enable C2 APB4 peripherals clock. 6726 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n 6727 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n 6728 * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n 6729 * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n 6730 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n 6731 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n 6732 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n 6733 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n 6734 * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n 6735 * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n 6736 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n 6737 * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock 6738 * @param Periphs This parameter can be a combination of the following values: 6739 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 6740 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 6741 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 6742 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 6743 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 6744 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 6745 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 6746 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 6747 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 6748 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 6749 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 6750 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 6751 * 6752 * (*) value not defined in all devices 6753 * @retval None 6754 */ 6755 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) 6756 { 6757 __IO uint32_t tmpreg; 6758 SET_BIT(RCC_C2->APB4ENR, Periphs); 6759 /* Delay after an RCC peripheral clock enabling */ 6760 tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); 6761 (void)tmpreg; 6762 } 6763 6764 /** 6765 * @brief Check if C2 APB4 peripheral clock is enabled or not 6766 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n 6767 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n 6768 * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n 6769 * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n 6770 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n 6771 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n 6772 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n 6773 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n 6774 * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n 6775 * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n 6776 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n 6777 * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock 6778 * @param Periphs This parameter can be a combination of the following values: 6779 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 6780 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 6781 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 6782 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 6783 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 6784 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 6785 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 6786 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 6787 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 6788 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 6789 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 6790 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 6791 * 6792 * (*) value not defined in all devices 6793 * @retval uint32_t 6794 */ 6795 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) 6796 { 6797 return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); 6798 } 6799 6800 /** 6801 * @brief Disable C2 APB4 peripherals clock. 6802 * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n 6803 * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n 6804 * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n 6805 * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n 6806 * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n 6807 * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n 6808 * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n 6809 * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n 6810 * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n 6811 * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n 6812 * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n 6813 * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock 6814 * @param Periphs This parameter can be a combination of the following values: 6815 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 6816 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 6817 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 6818 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 6819 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 6820 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 6821 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 6822 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 6823 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 6824 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 6825 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 6826 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 6827 * 6828 * (*) value not defined in all devices 6829 * @retval None 6830 */ 6831 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) 6832 { 6833 CLEAR_BIT(RCC_C2->APB4ENR, Periphs); 6834 } 6835 6836 /** 6837 * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode. 6838 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6839 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6840 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6841 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6842 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6843 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6844 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6845 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6846 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6847 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6848 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n 6849 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep 6850 * @param Periphs This parameter can be a combination of the following values: 6851 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 6852 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 6853 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 6854 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 6855 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 6856 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 6857 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 6858 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 6859 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 6860 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 6861 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 6862 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 6863 * 6864 * (*) value not defined in all devices 6865 * @retval None 6866 */ 6867 __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) 6868 { 6869 __IO uint32_t tmpreg; 6870 SET_BIT(RCC_C2->APB4LPENR, Periphs); 6871 /* Delay after an RCC peripheral clock enabling */ 6872 tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); 6873 (void)tmpreg; 6874 } 6875 6876 /** 6877 * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode. 6878 * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6879 * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6880 * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6881 * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6882 * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6883 * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6884 * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6885 * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6886 * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6887 * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6888 * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n 6889 * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep 6890 * @param Periphs This parameter can be a combination of the following values: 6891 * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG 6892 * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 6893 * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 6894 * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 6895 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 6896 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 6897 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) 6898 * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) 6899 * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 6900 * @arg @ref LL_APB4_GRP1_PERIPH_VREF 6901 * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB 6902 * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) 6903 * 6904 * (*) value not defined in all devices 6905 * @retval None 6906 */ 6907 __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) 6908 { 6909 CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); 6910 } 6911 6912 /** 6913 * @} 6914 */ 6915 6916 #endif /*DUAL_CORE*/ 6917 6918 /** 6919 * @} 6920 */ 6921 6922 /** 6923 * @} 6924 */ 6925 6926 #endif /* defined(RCC) */ 6927 6928 /** 6929 * @} 6930 */ 6931 6932 #ifdef __cplusplus 6933 } 6934 #endif 6935 6936 #endif /* STM32H7xx_LL_BUS_H */ 6937 6938
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