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File indexing completed on 2025-05-11 08:23:37
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_ll_bdma.h 0004 * @author MCD Application Team 0005 * @brief Header file of BDMA LL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_LL_BDMA_H 0021 #define STM32H7xx_LL_BDMA_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx.h" 0029 #include "stm32h7xx_ll_dmamux.h" 0030 0031 /** @addtogroup STM32H7xx_LL_Driver 0032 * @{ 0033 */ 0034 0035 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2) 0036 0037 /** @defgroup BDMA_LL BDMA 0038 * @ingroup RTEMSBSPsARMSTM32H7 0039 * @{ 0040 */ 0041 0042 /* Private types -------------------------------------------------------------*/ 0043 /* Private variables ---------------------------------------------------------*/ 0044 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables 0045 * @ingroup RTEMSBSPsARMSTM32H7 0046 * @{ 0047 */ 0048 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */ 0049 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] = 0050 { 0051 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE), 0052 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE), 0053 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE), 0054 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE), 0055 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE), 0056 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE), 0057 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE), 0058 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE) 0059 }; 0060 /** 0061 * @} 0062 */ 0063 0064 /* Private constants ---------------------------------------------------------*/ 0065 /* Private macros ------------------------------------------------------------*/ 0066 /** @defgroup BDMA_LL_Private_Macros BDMA Private Macros 0067 * @ingroup RTEMSBSPsARMSTM32H7 0068 * @{ 0069 */ 0070 #if !defined(UNUSED) 0071 #define UNUSED(x) ((void)(x)) 0072 #endif 0073 /** 0074 * @} 0075 */ 0076 /* Exported types ------------------------------------------------------------*/ 0077 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0078 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure 0079 * @ingroup RTEMSBSPsARMSTM32H7 0080 * @{ 0081 */ 0082 typedef struct 0083 { 0084 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer 0085 or as Source base address in case of memory to memory transfer direction. 0086 0087 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 0088 0089 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 0090 or as Destination base address in case of memory to memory transfer direction. 0091 0092 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 0093 0094 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 0095 from memory to memory or from peripheral to memory. 0096 This parameter can be a value of @ref BDMA_LL_EC_DIRECTION 0097 0098 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */ 0099 0100 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 0101 This parameter can be a value of @ref BDMA_LL_EC_MODE 0102 @note: The circular buffer mode cannot be used if the memory to memory 0103 data transfer direction is configured on the selected Channel 0104 0105 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */ 0106 0107 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 0108 is incremented or not. 0109 This parameter can be a value of @ref BDMA_LL_EC_PERIPH 0110 0111 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */ 0112 0113 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 0114 is incremented or not. 0115 This parameter can be a value of @ref BDMA_LL_EC_MEMORY 0116 0117 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */ 0118 0119 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 0120 in case of memory to memory transfer direction. 0121 This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN 0122 0123 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */ 0124 0125 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 0126 in case of memory to memory transfer direction. 0127 This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN 0128 0129 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */ 0130 0131 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 0132 The data unit is equal to the source buffer configuration set in PeripheralSize 0133 or MemorySize parameters depending in the transfer direction. 0134 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 0135 0136 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ 0137 0138 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 0139 This parameter can be a value of @ref DMAMUX2_Request_selection 0140 0141 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ 0142 0143 uint32_t Priority; /*!< Specifies the channel priority level. 0144 This parameter can be a value of @ref BDMA_LL_EC_PRIORITY 0145 0146 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */ 0147 0148 uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode. 0149 This parameter can be a value of @ref BDMA_LL_EC_DOUBLEBUFFER_MODE 0150 0151 This feature can be modified afterwards using unitary function @ref LL_BDMA_EnableDoubleBufferMode() & LL_BDMA_DisableDoubleBufferMode(). */ 0152 0153 uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode. 0154 This parameter can be a value of @ref BDMA_LL_EC_CURRENTTARGETMEM 0155 0156 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetCurrentTargetMem(). */ 0157 } LL_BDMA_InitTypeDef; 0158 /** 0159 * @} 0160 */ 0161 #endif /* USE_FULL_LL_DRIVER */ 0162 0163 /* Exported constants --------------------------------------------------------*/ 0164 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants 0165 * @ingroup RTEMSBSPsARMSTM32H7 0166 * @{ 0167 */ 0168 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines 0169 * @ingroup RTEMSBSPsARMSTM32H7 0170 * @brief Flags defines which can be used with LL_BDMA_WriteReg function 0171 * @{ 0172 */ 0173 #define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 0174 #define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 0175 #define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 0176 #define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 0177 #define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 0178 #define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 0179 #define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 0180 #define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 0181 #define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 0182 #define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 0183 #define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 0184 #define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 0185 #define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 0186 #define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 0187 #define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 0188 #define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 0189 #define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 0190 #define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 0191 #define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 0192 #define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 0193 #define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 0194 #define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 0195 #define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 0196 #define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 0197 #define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 0198 #define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 0199 #define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 0200 #define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 0201 /** 0202 * @} 0203 */ 0204 0205 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines 0206 * @ingroup RTEMSBSPsARMSTM32H7 0207 * @brief Flags defines which can be used with LL_BDMA_ReadReg function 0208 * @{ 0209 */ 0210 #define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */ 0211 #define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */ 0212 #define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */ 0213 #define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */ 0214 #define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */ 0215 #define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 0216 #define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 0217 #define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 0218 #define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */ 0219 #define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 0220 #define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 0221 #define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 0222 #define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */ 0223 #define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 0224 #define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 0225 #define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 0226 #define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */ 0227 #define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 0228 #define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 0229 #define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 0230 #define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */ 0231 #define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 0232 #define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 0233 #define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 0234 #define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */ 0235 #define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 0236 #define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 0237 #define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 0238 #define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */ 0239 #define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 0240 #define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 0241 #define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 0242 /** 0243 * @} 0244 */ 0245 0246 /** @defgroup BDMA_LL_EC_IT IT Defines 0247 * @ingroup RTEMSBSPsARMSTM32H7 0248 * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions 0249 * @{ 0250 */ 0251 #define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */ 0252 #define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */ 0253 #define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */ 0254 /** 0255 * @} 0256 */ 0257 0258 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL 0259 * @ingroup RTEMSBSPsARMSTM32H7 0260 * @{ 0261 */ 0262 #define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 0263 #define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */ 0264 #define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */ 0265 #define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */ 0266 #define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */ 0267 #define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */ 0268 #define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */ 0269 #define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */ 0270 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 0271 #define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */ 0272 #endif /*USE_FULL_LL_DRIVER*/ 0273 /** 0274 * @} 0275 */ 0276 0277 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction 0278 * @ingroup RTEMSBSPsARMSTM32H7 0279 * @{ 0280 */ 0281 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 0282 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */ 0283 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */ 0284 /** 0285 * @} 0286 */ 0287 0288 /** @defgroup BDMA_LL_EC_MODE Transfer mode 0289 * @ingroup RTEMSBSPsARMSTM32H7 0290 * @{ 0291 */ 0292 #define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 0293 #define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */ 0294 /** 0295 * @} 0296 */ 0297 0298 /** @defgroup BDMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 0299 * @ingroup RTEMSBSPsARMSTM32H7 0300 * @{ 0301 */ 0302 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 0303 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */ 0304 /** 0305 * @} 0306 */ 0307 0308 /** @defgroup BDMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 0309 * @{ 0310 */ 0311 #define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 0312 #define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 0313 /** 0314 * @} 0315 */ 0316 0317 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode 0318 * @ingroup RTEMSBSPsARMSTM32H7 0319 * @{ 0320 */ 0321 #define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */ 0322 #define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 0323 /** 0324 * @} 0325 */ 0326 0327 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode 0328 * @ingroup RTEMSBSPsARMSTM32H7 0329 * @{ 0330 */ 0331 #define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */ 0332 #define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 0333 /** 0334 * @} 0335 */ 0336 0337 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment 0338 * @ingroup RTEMSBSPsARMSTM32H7 0339 * @{ 0340 */ 0341 #define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 0342 #define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 0343 #define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 0344 /** 0345 * @} 0346 */ 0347 0348 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment 0349 * @ingroup RTEMSBSPsARMSTM32H7 0350 * @{ 0351 */ 0352 #define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 0353 #define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 0354 #define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 0355 /** 0356 * @} 0357 */ 0358 0359 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level 0360 * @ingroup RTEMSBSPsARMSTM32H7 0361 * @{ 0362 */ 0363 #define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 0364 #define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */ 0365 #define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */ 0366 #define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */ 0367 /** 0368 * @} 0369 */ 0370 0371 0372 /** 0373 * @} 0374 */ 0375 /* Exported macro ------------------------------------------------------------*/ 0376 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros 0377 * @ingroup RTEMSBSPsARMSTM32H7 0378 * @{ 0379 */ 0380 0381 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros 0382 * @ingroup RTEMSBSPsARMSTM32H7 0383 * @{ 0384 */ 0385 /** 0386 * @brief Write a value in BDMA register 0387 * @param __INSTANCE__ BDMA Instance 0388 * @param __REG__ Register to be written 0389 * @param __VALUE__ Value to be written in the register 0390 * @retval None 0391 */ 0392 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 0393 0394 /** 0395 * @brief Read a value in BDMA register 0396 * @param __INSTANCE__ BDMA Instance 0397 * @param __REG__ Register to be read 0398 * @retval Register value 0399 */ 0400 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 0401 /** 0402 * @} 0403 */ 0404 0405 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely 0406 * @ingroup RTEMSBSPsARMSTM32H7 0407 * @{ 0408 */ 0409 /** 0410 * @brief Convert BDMAx_Channely into BDMAx 0411 * @param __CHANNEL_INSTANCE__ BDMAx_Channely 0412 * @retval BDMAx 0413 */ 0414 #if defined (BDMA1) 0415 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 0416 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA) 0417 #else 0418 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA) 0419 #endif /* BDMA1 */ 0420 0421 /** 0422 * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y 0423 * @param __CHANNEL_INSTANCE__ BDMAx_Channely 0424 * @retval LL_BDMA_CHANNEL_y 0425 */ 0426 #if defined (BDMA1) 0427 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 0428 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 0429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 0430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 0431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 0432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 0433 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 0434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 0435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 0436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 0437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 0438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 0439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 0440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 0441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 0442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \ 0443 LL_BDMA_CHANNEL_7) 0444 #else 0445 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 0446 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 0447 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 0448 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 0449 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 0450 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 0451 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 0452 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 0453 LL_BDMA_CHANNEL_7) 0454 #endif /* BDMA1 */ 0455 0456 /** 0457 * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely 0458 * @param __BDMA_INSTANCE__ BDMAx 0459 * @param __CHANNEL__ LL_BDMA_CHANNEL_y 0460 * @retval BDMAx_Channely 0461 */ 0462 #if defined (BDMA1) 0463 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ 0464 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ 0465 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \ 0466 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ 0467 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \ 0468 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ 0469 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \ 0470 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ 0471 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \ 0472 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ 0473 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \ 0474 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ 0475 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \ 0476 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ 0477 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \ 0478 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \ 0479 BDMA1_Channel7) 0480 #else 0481 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ 0482 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ 0483 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ 0484 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ 0485 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ 0486 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ 0487 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ 0488 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ 0489 BDMA_Channel7) 0490 #endif /* BDMA1 */ 0491 /** 0492 * @} 0493 */ 0494 0495 /** 0496 * @} 0497 */ 0498 0499 /* Exported functions --------------------------------------------------------*/ 0500 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions 0501 * @ingroup RTEMSBSPsARMSTM32H7 0502 * @{ 0503 */ 0504 0505 /** @defgroup BDMA_LL_EF_Configuration Configuration 0506 * @ingroup RTEMSBSPsARMSTM32H7 0507 * @{ 0508 */ 0509 /** 0510 * @brief Enable BDMA channel. 0511 * @rmtoll CCR EN LL_BDMA_EnableChannel 0512 * @param BDMAx BDMA Instance 0513 * @param Channel This parameter can be one of the following values: 0514 * @arg @ref LL_BDMA_CHANNEL_0 0515 * @arg @ref LL_BDMA_CHANNEL_1 0516 * @arg @ref LL_BDMA_CHANNEL_2 0517 * @arg @ref LL_BDMA_CHANNEL_3 0518 * @arg @ref LL_BDMA_CHANNEL_4 0519 * @arg @ref LL_BDMA_CHANNEL_5 0520 * @arg @ref LL_BDMA_CHANNEL_6 0521 * @arg @ref LL_BDMA_CHANNEL_7 0522 * @retval None 0523 */ 0524 __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 0525 { 0526 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0527 0528 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); 0529 } 0530 0531 /** 0532 * @brief Disable BDMA channel. 0533 * @rmtoll CCR EN LL_BDMA_DisableChannel 0534 * @param BDMAx BDMA Instance 0535 * @param Channel This parameter can be one of the following values: 0536 * @arg @ref LL_BDMA_CHANNEL_0 0537 * @arg @ref LL_BDMA_CHANNEL_1 0538 * @arg @ref LL_BDMA_CHANNEL_2 0539 * @arg @ref LL_BDMA_CHANNEL_3 0540 * @arg @ref LL_BDMA_CHANNEL_4 0541 * @arg @ref LL_BDMA_CHANNEL_5 0542 * @arg @ref LL_BDMA_CHANNEL_6 0543 * @arg @ref LL_BDMA_CHANNEL_7 0544 * @retval None 0545 */ 0546 __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 0547 { 0548 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0549 0550 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); 0551 } 0552 0553 /** 0554 * @brief Check if BDMA channel is enabled or disabled. 0555 * @rmtoll CCR EN LL_BDMA_IsEnabledChannel 0556 * @param BDMAx BDMA Instance 0557 * @param Channel This parameter can be one of the following values: 0558 * @arg @ref LL_BDMA_CHANNEL_0 0559 * @arg @ref LL_BDMA_CHANNEL_1 0560 * @arg @ref LL_BDMA_CHANNEL_2 0561 * @arg @ref LL_BDMA_CHANNEL_3 0562 * @arg @ref LL_BDMA_CHANNEL_4 0563 * @arg @ref LL_BDMA_CHANNEL_5 0564 * @arg @ref LL_BDMA_CHANNEL_6 0565 * @arg @ref LL_BDMA_CHANNEL_7 0566 * @retval State of bit (1 or 0). 0567 */ 0568 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 0569 { 0570 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0571 0572 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL); 0573 } 0574 0575 /** 0576 * @brief Configure all parameters link to BDMA transfer. 0577 * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n 0578 * CCR MEM2MEM LL_BDMA_ConfigTransfer\n 0579 * CCR CIRC LL_BDMA_ConfigTransfer\n 0580 * CCR PINC LL_BDMA_ConfigTransfer\n 0581 * CCR MINC LL_BDMA_ConfigTransfer\n 0582 * CCR PSIZE LL_BDMA_ConfigTransfer\n 0583 * CCR MSIZE LL_BDMA_ConfigTransfer\n 0584 * CCR PL LL_BDMA_ConfigTransfer\n 0585 * CCR DBM LL_BDMA_ConfigTransfer\n 0586 * CCR CT LL_BDMA_ConfigTransfer 0587 * @param BDMAx BDMA Instance 0588 * @param Channel This parameter can be one of the following values: 0589 * @arg @ref LL_BDMA_CHANNEL_0 0590 * @arg @ref LL_BDMA_CHANNEL_1 0591 * @arg @ref LL_BDMA_CHANNEL_2 0592 * @arg @ref LL_BDMA_CHANNEL_3 0593 * @arg @ref LL_BDMA_CHANNEL_4 0594 * @arg @ref LL_BDMA_CHANNEL_5 0595 * @arg @ref LL_BDMA_CHANNEL_6 0596 * @arg @ref LL_BDMA_CHANNEL_7 0597 * @param Configuration This parameter must be a combination of all the following values: 0598 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 0599 * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR 0600 * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT 0601 * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT 0602 * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD 0603 * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD 0604 * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH 0605 * @arg @ref LL_BDMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_BDMA_DOUBLEBUFFER_MODE_ENABLE 0606 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1 0607 * @retval None 0608 */ 0609 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) 0610 { 0611 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0612 0613 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0614 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \ 0615 BDMA_CCR_DBM | BDMA_CCR_CT, Configuration); 0616 } 0617 0618 /** 0619 * @brief Set Data transfer direction (read from peripheral or from memory). 0620 * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n 0621 * CCR MEM2MEM LL_BDMA_SetDataTransferDirection 0622 * @param BDMAx BDMA Instance 0623 * @param Channel This parameter can be one of the following values: 0624 * @arg @ref LL_BDMA_CHANNEL_0 0625 * @arg @ref LL_BDMA_CHANNEL_1 0626 * @arg @ref LL_BDMA_CHANNEL_2 0627 * @arg @ref LL_BDMA_CHANNEL_3 0628 * @arg @ref LL_BDMA_CHANNEL_4 0629 * @arg @ref LL_BDMA_CHANNEL_5 0630 * @arg @ref LL_BDMA_CHANNEL_6 0631 * @arg @ref LL_BDMA_CHANNEL_7 0632 * @param Direction This parameter can be one of the following values: 0633 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0634 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 0635 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 0636 * @retval None 0637 */ 0638 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) 0639 { 0640 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0641 0642 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0643 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction); 0644 } 0645 0646 /** 0647 * @brief Get Data transfer direction (read from peripheral or from memory). 0648 * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n 0649 * CCR MEM2MEM LL_BDMA_GetDataTransferDirection 0650 * @param BDMAx BDMA Instance 0651 * @param Channel This parameter can be one of the following values: 0652 * @arg @ref LL_BDMA_CHANNEL_0 0653 * @arg @ref LL_BDMA_CHANNEL_1 0654 * @arg @ref LL_BDMA_CHANNEL_2 0655 * @arg @ref LL_BDMA_CHANNEL_3 0656 * @arg @ref LL_BDMA_CHANNEL_4 0657 * @arg @ref LL_BDMA_CHANNEL_5 0658 * @arg @ref LL_BDMA_CHANNEL_6 0659 * @arg @ref LL_BDMA_CHANNEL_7 0660 * @retval Returned value can be one of the following values: 0661 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0662 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 0663 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 0664 */ 0665 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) 0666 { 0667 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0668 0669 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0670 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)); 0671 } 0672 0673 /** 0674 * @brief Set BDMA mode circular or normal. 0675 * @note The circular buffer mode cannot be used if the memory-to-memory 0676 * data transfer is configured on the selected Channel. 0677 * @rmtoll CCR CIRC LL_BDMA_SetMode 0678 * @param BDMAx BDMA Instance 0679 * @param Channel This parameter can be one of the following values: 0680 * @arg @ref LL_BDMA_CHANNEL_0 0681 * @arg @ref LL_BDMA_CHANNEL_1 0682 * @arg @ref LL_BDMA_CHANNEL_2 0683 * @arg @ref LL_BDMA_CHANNEL_3 0684 * @arg @ref LL_BDMA_CHANNEL_4 0685 * @arg @ref LL_BDMA_CHANNEL_5 0686 * @arg @ref LL_BDMA_CHANNEL_6 0687 * @arg @ref LL_BDMA_CHANNEL_7 0688 * @param Mode This parameter can be one of the following values: 0689 * @arg @ref LL_BDMA_MODE_NORMAL 0690 * @arg @ref LL_BDMA_MODE_CIRCULAR 0691 * @retval None 0692 */ 0693 __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) 0694 { 0695 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0696 0697 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC, 0698 Mode); 0699 } 0700 0701 /** 0702 * @brief Get BDMA mode circular or normal. 0703 * @rmtoll CCR CIRC LL_BDMA_GetMode 0704 * @param BDMAx BDMA Instance 0705 * @param Channel This parameter can be one of the following values: 0706 * @arg @ref LL_BDMA_CHANNEL_0 0707 * @arg @ref LL_BDMA_CHANNEL_1 0708 * @arg @ref LL_BDMA_CHANNEL_2 0709 * @arg @ref LL_BDMA_CHANNEL_3 0710 * @arg @ref LL_BDMA_CHANNEL_4 0711 * @arg @ref LL_BDMA_CHANNEL_5 0712 * @arg @ref LL_BDMA_CHANNEL_6 0713 * @arg @ref LL_BDMA_CHANNEL_7 0714 * @retval Returned value can be one of the following values: 0715 * @arg @ref LL_BDMA_MODE_NORMAL 0716 * @arg @ref LL_BDMA_MODE_CIRCULAR 0717 */ 0718 __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 0719 { 0720 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0721 0722 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0723 BDMA_CCR_CIRC)); 0724 } 0725 0726 /** 0727 * @brief Set Peripheral increment mode. 0728 * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode 0729 * @param BDMAx BDMA Instance 0730 * @param Channel This parameter can be one of the following values: 0731 * @arg @ref LL_BDMA_CHANNEL_0 0732 * @arg @ref LL_BDMA_CHANNEL_1 0733 * @arg @ref LL_BDMA_CHANNEL_2 0734 * @arg @ref LL_BDMA_CHANNEL_3 0735 * @arg @ref LL_BDMA_CHANNEL_4 0736 * @arg @ref LL_BDMA_CHANNEL_5 0737 * @arg @ref LL_BDMA_CHANNEL_6 0738 * @arg @ref LL_BDMA_CHANNEL_7 0739 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 0740 * @arg @ref LL_BDMA_PERIPH_INCREMENT 0741 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT 0742 * @retval None 0743 */ 0744 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 0745 { 0746 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0747 0748 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC, 0749 PeriphOrM2MSrcIncMode); 0750 } 0751 0752 /** 0753 * @brief Get Peripheral increment mode. 0754 * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode 0755 * @param BDMAx BDMA Instance 0756 * @param Channel This parameter can be one of the following values: 0757 * @arg @ref LL_BDMA_CHANNEL_0 0758 * @arg @ref LL_BDMA_CHANNEL_1 0759 * @arg @ref LL_BDMA_CHANNEL_2 0760 * @arg @ref LL_BDMA_CHANNEL_3 0761 * @arg @ref LL_BDMA_CHANNEL_4 0762 * @arg @ref LL_BDMA_CHANNEL_5 0763 * @arg @ref LL_BDMA_CHANNEL_6 0764 * @arg @ref LL_BDMA_CHANNEL_7 0765 * @retval Returned value can be one of the following values: 0766 * @arg @ref LL_BDMA_PERIPH_INCREMENT 0767 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT 0768 */ 0769 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 0770 { 0771 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0772 0773 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0774 BDMA_CCR_PINC)); 0775 } 0776 0777 /** 0778 * @brief Set Memory increment mode. 0779 * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode 0780 * @param BDMAx BDMA Instance 0781 * @param Channel This parameter can be one of the following values: 0782 * @arg @ref LL_BDMA_CHANNEL_0 0783 * @arg @ref LL_BDMA_CHANNEL_1 0784 * @arg @ref LL_BDMA_CHANNEL_2 0785 * @arg @ref LL_BDMA_CHANNEL_3 0786 * @arg @ref LL_BDMA_CHANNEL_4 0787 * @arg @ref LL_BDMA_CHANNEL_5 0788 * @arg @ref LL_BDMA_CHANNEL_6 0789 * @arg @ref LL_BDMA_CHANNEL_7 0790 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 0791 * @arg @ref LL_BDMA_MEMORY_INCREMENT 0792 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT 0793 * @retval None 0794 */ 0795 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 0796 { 0797 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0798 0799 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC, 0800 MemoryOrM2MDstIncMode); 0801 } 0802 0803 /** 0804 * @brief Get Memory increment mode. 0805 * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode 0806 * @param BDMAx BDMA Instance 0807 * @param Channel This parameter can be one of the following values: 0808 * @arg @ref LL_BDMA_CHANNEL_0 0809 * @arg @ref LL_BDMA_CHANNEL_1 0810 * @arg @ref LL_BDMA_CHANNEL_2 0811 * @arg @ref LL_BDMA_CHANNEL_3 0812 * @arg @ref LL_BDMA_CHANNEL_4 0813 * @arg @ref LL_BDMA_CHANNEL_5 0814 * @arg @ref LL_BDMA_CHANNEL_6 0815 * @arg @ref LL_BDMA_CHANNEL_7 0816 * @retval Returned value can be one of the following values: 0817 * @arg @ref LL_BDMA_MEMORY_INCREMENT 0818 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT 0819 */ 0820 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 0821 { 0822 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0823 0824 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0825 BDMA_CCR_MINC)); 0826 } 0827 0828 /** 0829 * @brief Set Peripheral size. 0830 * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize 0831 * @param BDMAx BDMA Instance 0832 * @param Channel This parameter can be one of the following values: 0833 * @arg @ref LL_BDMA_CHANNEL_0 0834 * @arg @ref LL_BDMA_CHANNEL_1 0835 * @arg @ref LL_BDMA_CHANNEL_2 0836 * @arg @ref LL_BDMA_CHANNEL_3 0837 * @arg @ref LL_BDMA_CHANNEL_4 0838 * @arg @ref LL_BDMA_CHANNEL_5 0839 * @arg @ref LL_BDMA_CHANNEL_6 0840 * @arg @ref LL_BDMA_CHANNEL_7 0841 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 0842 * @arg @ref LL_BDMA_PDATAALIGN_BYTE 0843 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD 0844 * @arg @ref LL_BDMA_PDATAALIGN_WORD 0845 * @retval None 0846 */ 0847 __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) 0848 { 0849 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0850 0851 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE, 0852 PeriphOrM2MSrcDataSize); 0853 } 0854 0855 /** 0856 * @brief Get Peripheral size. 0857 * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize 0858 * @param BDMAx BDMA Instance 0859 * @param Channel This parameter can be one of the following values: 0860 * @arg @ref LL_BDMA_CHANNEL_0 0861 * @arg @ref LL_BDMA_CHANNEL_1 0862 * @arg @ref LL_BDMA_CHANNEL_2 0863 * @arg @ref LL_BDMA_CHANNEL_3 0864 * @arg @ref LL_BDMA_CHANNEL_4 0865 * @arg @ref LL_BDMA_CHANNEL_5 0866 * @arg @ref LL_BDMA_CHANNEL_6 0867 * @arg @ref LL_BDMA_CHANNEL_7 0868 * @retval Returned value can be one of the following values: 0869 * @arg @ref LL_BDMA_PDATAALIGN_BYTE 0870 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD 0871 * @arg @ref LL_BDMA_PDATAALIGN_WORD 0872 */ 0873 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) 0874 { 0875 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0876 0877 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0878 BDMA_CCR_PSIZE)); 0879 } 0880 0881 /** 0882 * @brief Set Memory size. 0883 * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize 0884 * @param BDMAx BDMA Instance 0885 * @param Channel This parameter can be one of the following values: 0886 * @arg @ref LL_BDMA_CHANNEL_0 0887 * @arg @ref LL_BDMA_CHANNEL_1 0888 * @arg @ref LL_BDMA_CHANNEL_2 0889 * @arg @ref LL_BDMA_CHANNEL_3 0890 * @arg @ref LL_BDMA_CHANNEL_4 0891 * @arg @ref LL_BDMA_CHANNEL_5 0892 * @arg @ref LL_BDMA_CHANNEL_6 0893 * @arg @ref LL_BDMA_CHANNEL_7 0894 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 0895 * @arg @ref LL_BDMA_MDATAALIGN_BYTE 0896 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD 0897 * @arg @ref LL_BDMA_MDATAALIGN_WORD 0898 * @retval None 0899 */ 0900 __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) 0901 { 0902 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0903 0904 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE, 0905 MemoryOrM2MDstDataSize); 0906 } 0907 0908 /** 0909 * @brief Get Memory size. 0910 * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize 0911 * @param BDMAx BDMA Instance 0912 * @param Channel This parameter can be one of the following values: 0913 * @arg @ref LL_BDMA_CHANNEL_0 0914 * @arg @ref LL_BDMA_CHANNEL_1 0915 * @arg @ref LL_BDMA_CHANNEL_2 0916 * @arg @ref LL_BDMA_CHANNEL_3 0917 * @arg @ref LL_BDMA_CHANNEL_4 0918 * @arg @ref LL_BDMA_CHANNEL_5 0919 * @arg @ref LL_BDMA_CHANNEL_6 0920 * @arg @ref LL_BDMA_CHANNEL_7 0921 * @retval Returned value can be one of the following values: 0922 * @arg @ref LL_BDMA_MDATAALIGN_BYTE 0923 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD 0924 * @arg @ref LL_BDMA_MDATAALIGN_WORD 0925 */ 0926 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) 0927 { 0928 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0929 0930 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0931 BDMA_CCR_MSIZE)); 0932 } 0933 0934 /** 0935 * @brief Set Channel priority level. 0936 * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel 0937 * @param BDMAx BDMA Instance 0938 * @param Channel This parameter can be one of the following values: 0939 * @arg @ref LL_BDMA_CHANNEL_0 0940 * @arg @ref LL_BDMA_CHANNEL_1 0941 * @arg @ref LL_BDMA_CHANNEL_2 0942 * @arg @ref LL_BDMA_CHANNEL_3 0943 * @arg @ref LL_BDMA_CHANNEL_4 0944 * @arg @ref LL_BDMA_CHANNEL_5 0945 * @arg @ref LL_BDMA_CHANNEL_6 0946 * @arg @ref LL_BDMA_CHANNEL_7 0947 * @param Priority This parameter can be one of the following values: 0948 * @arg @ref LL_BDMA_PRIORITY_LOW 0949 * @arg @ref LL_BDMA_PRIORITY_MEDIUM 0950 * @arg @ref LL_BDMA_PRIORITY_HIGH 0951 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH 0952 * @retval None 0953 */ 0954 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) 0955 { 0956 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0957 0958 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL, 0959 Priority); 0960 } 0961 0962 /** 0963 * @brief Get Channel priority level. 0964 * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel 0965 * @param BDMAx BDMA Instance 0966 * @param Channel This parameter can be one of the following values: 0967 * @arg @ref LL_BDMA_CHANNEL_0 0968 * @arg @ref LL_BDMA_CHANNEL_1 0969 * @arg @ref LL_BDMA_CHANNEL_2 0970 * @arg @ref LL_BDMA_CHANNEL_3 0971 * @arg @ref LL_BDMA_CHANNEL_4 0972 * @arg @ref LL_BDMA_CHANNEL_5 0973 * @arg @ref LL_BDMA_CHANNEL_6 0974 * @arg @ref LL_BDMA_CHANNEL_7 0975 * @retval Returned value can be one of the following values: 0976 * @arg @ref LL_BDMA_PRIORITY_LOW 0977 * @arg @ref LL_BDMA_PRIORITY_MEDIUM 0978 * @arg @ref LL_BDMA_PRIORITY_HIGH 0979 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH 0980 */ 0981 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) 0982 { 0983 uint32_t bdma_base_addr = (uint32_t)BDMAx; 0984 0985 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 0986 BDMA_CCR_PL)); 0987 } 0988 0989 /** 0990 * @brief Set Number of data to transfer. 0991 * @note This action has no effect if 0992 * channel is enabled. 0993 * @rmtoll CNDTR NDT LL_BDMA_SetDataLength 0994 * @param BDMAx BDMA Instance 0995 * @param Channel This parameter can be one of the following values: 0996 * @arg @ref LL_BDMA_CHANNEL_0 0997 * @arg @ref LL_BDMA_CHANNEL_1 0998 * @arg @ref LL_BDMA_CHANNEL_2 0999 * @arg @ref LL_BDMA_CHANNEL_3 1000 * @arg @ref LL_BDMA_CHANNEL_4 1001 * @arg @ref LL_BDMA_CHANNEL_5 1002 * @arg @ref LL_BDMA_CHANNEL_6 1003 * @arg @ref LL_BDMA_CHANNEL_7 1004 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 1005 * @retval None 1006 */ 1007 __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) 1008 { 1009 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1010 1011 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, 1012 BDMA_CNDTR_NDT, NbData); 1013 } 1014 1015 /** 1016 * @brief Get Number of data to transfer. 1017 * @note Once the channel is enabled, the return value indicate the 1018 * remaining bytes to be transmitted. 1019 * @rmtoll CNDTR NDT LL_BDMA_GetDataLength 1020 * @param BDMAx BDMA Instance 1021 * @param Channel This parameter can be one of the following values: 1022 * @arg @ref LL_BDMA_CHANNEL_0 1023 * @arg @ref LL_BDMA_CHANNEL_1 1024 * @arg @ref LL_BDMA_CHANNEL_2 1025 * @arg @ref LL_BDMA_CHANNEL_3 1026 * @arg @ref LL_BDMA_CHANNEL_4 1027 * @arg @ref LL_BDMA_CHANNEL_5 1028 * @arg @ref LL_BDMA_CHANNEL_6 1029 * @arg @ref LL_BDMA_CHANNEL_7 1030 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1031 */ 1032 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) 1033 { 1034 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1035 1036 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, 1037 BDMA_CNDTR_NDT)); 1038 } 1039 1040 /** 1041 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1042 * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem 1043 * @param BDMAx BDMAx Instance 1044 * @param Channel This parameter can be one of the following values: 1045 * @arg @ref LL_BDMA_CHANNEL_0 1046 * @arg @ref LL_BDMA_CHANNEL_1 1047 * @arg @ref LL_BDMA_CHANNEL_2 1048 * @arg @ref LL_BDMA_CHANNEL_3 1049 * @arg @ref LL_BDMA_CHANNEL_4 1050 * @arg @ref LL_BDMA_CHANNEL_5 1051 * @arg @ref LL_BDMA_CHANNEL_6 1052 * @arg @ref LL_BDMA_CHANNEL_7 1053 * @param CurrentMemory This parameter can be one of the following values: 1054 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 1055 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 1056 * @retval None 1057 */ 1058 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) 1059 { 1060 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1061 1062 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory); 1063 } 1064 1065 /** 1066 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 1067 * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem 1068 * @param BDMAx BDMAx Instance 1069 * @param Channel This parameter can be one of the following values: 1070 * @arg @ref LL_BDMA_CHANNEL_0 1071 * @arg @ref LL_BDMA_CHANNEL_1 1072 * @arg @ref LL_BDMA_CHANNEL_2 1073 * @arg @ref LL_BDMA_CHANNEL_3 1074 * @arg @ref LL_BDMA_CHANNEL_4 1075 * @arg @ref LL_BDMA_CHANNEL_5 1076 * @arg @ref LL_BDMA_CHANNEL_6 1077 * @arg @ref LL_BDMA_CHANNEL_7 1078 * @retval Returned value can be one of the following values: 1079 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 1080 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 1081 */ 1082 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) 1083 { 1084 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1085 1086 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT)); 1087 } 1088 1089 /** 1090 * @brief Enable the double buffer mode. 1091 * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode 1092 * @param BDMAx BDMAx Instance 1093 * @param Channel This parameter can be one of the following values: 1094 * @arg @ref LL_BDMA_CHANNEL_0 1095 * @arg @ref LL_BDMA_CHANNEL_1 1096 * @arg @ref LL_BDMA_CHANNEL_2 1097 * @arg @ref LL_BDMA_CHANNEL_3 1098 * @arg @ref LL_BDMA_CHANNEL_4 1099 * @arg @ref LL_BDMA_CHANNEL_5 1100 * @arg @ref LL_BDMA_CHANNEL_6 1101 * @arg @ref LL_BDMA_CHANNEL_7 1102 * @retval None 1103 */ 1104 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 1105 { 1106 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1107 1108 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); 1109 } 1110 1111 /** 1112 * @brief Disable the double buffer mode. 1113 * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode 1114 * @param BDMAx BDMAx Instance 1115 * @param Channel This parameter can be one of the following values: 1116 * @arg @ref LL_BDMA_CHANNEL_0 1117 * @arg @ref LL_BDMA_CHANNEL_1 1118 * @arg @ref LL_BDMA_CHANNEL_2 1119 * @arg @ref LL_BDMA_CHANNEL_3 1120 * @arg @ref LL_BDMA_CHANNEL_4 1121 * @arg @ref LL_BDMA_CHANNEL_5 1122 * @arg @ref LL_BDMA_CHANNEL_6 1123 * @arg @ref LL_BDMA_CHANNEL_7 1124 * @retval None 1125 */ 1126 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 1127 { 1128 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1129 1130 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); 1131 } 1132 1133 /** 1134 * @brief Check if double buffer mode is enabled or not. 1135 * @rmtoll CCR DBM LL_BDMA_IsEnabledDoubleBufferMode 1136 * @param BDMAx BDMAx Instance 1137 * @param Channel This parameter can be one of the following values: 1138 * @arg @ref LL_BDMA_CHANNEL_0 1139 * @arg @ref LL_BDMA_CHANNEL_1 1140 * @arg @ref LL_BDMA_CHANNEL_2 1141 * @arg @ref LL_BDMA_CHANNEL_3 1142 * @arg @ref LL_BDMA_CHANNEL_4 1143 * @arg @ref LL_BDMA_CHANNEL_5 1144 * @arg @ref LL_BDMA_CHANNEL_6 1145 * @arg @ref LL_BDMA_CHANNEL_7 1146 * @retval State of bit (1 or 0). 1147 */ 1148 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 1149 { 1150 register uint32_t bdma_base_addr = (uint32_t)BDMAx; 1151 1152 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL); 1153 } 1154 1155 /** 1156 * @brief Configure the Source and Destination addresses. 1157 * @note This API must not be called when the BDMA channel is enabled. 1158 * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr). 1159 * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n 1160 * CMAR MA LL_BDMA_ConfigAddresses 1161 * @param BDMAx BDMA Instance 1162 * @param Channel This parameter can be one of the following values: 1163 * @arg @ref LL_BDMA_CHANNEL_0 1164 * @arg @ref LL_BDMA_CHANNEL_1 1165 * @arg @ref LL_BDMA_CHANNEL_2 1166 * @arg @ref LL_BDMA_CHANNEL_3 1167 * @arg @ref LL_BDMA_CHANNEL_4 1168 * @arg @ref LL_BDMA_CHANNEL_5 1169 * @arg @ref LL_BDMA_CHANNEL_6 1170 * @arg @ref LL_BDMA_CHANNEL_7 1171 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1172 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1173 * @param Direction This parameter can be one of the following values: 1174 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 1175 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 1176 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 1177 * @retval None 1178 */ 1179 __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, 1180 uint32_t DstAddress, uint32_t Direction) 1181 { 1182 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1183 1184 /* Direction Memory to Periph */ 1185 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) 1186 { 1187 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress); 1188 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress); 1189 } 1190 /* Direction Periph to Memory and Memory to Memory */ 1191 else 1192 { 1193 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress); 1194 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress); 1195 } 1196 } 1197 1198 /** 1199 * @brief Set the Memory address. 1200 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 1201 * @note This API must not be called when the BDMA channel is enabled. 1202 * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress 1203 * @param BDMAx BDMA Instance 1204 * @param Channel This parameter can be one of the following values: 1205 * @arg @ref LL_BDMA_CHANNEL_0 1206 * @arg @ref LL_BDMA_CHANNEL_1 1207 * @arg @ref LL_BDMA_CHANNEL_2 1208 * @arg @ref LL_BDMA_CHANNEL_3 1209 * @arg @ref LL_BDMA_CHANNEL_4 1210 * @arg @ref LL_BDMA_CHANNEL_5 1211 * @arg @ref LL_BDMA_CHANNEL_6 1212 * @arg @ref LL_BDMA_CHANNEL_7 1213 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1214 * @retval None 1215 */ 1216 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 1217 { 1218 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1219 1220 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); 1221 } 1222 1223 /** 1224 * @brief Set the Peripheral address. 1225 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 1226 * @note This API must not be called when the BDMA channel is enabled. 1227 * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress 1228 * @param BDMAx BDMA Instance 1229 * @param Channel This parameter can be one of the following values: 1230 * @arg @ref LL_BDMA_CHANNEL_0 1231 * @arg @ref LL_BDMA_CHANNEL_1 1232 * @arg @ref LL_BDMA_CHANNEL_2 1233 * @arg @ref LL_BDMA_CHANNEL_3 1234 * @arg @ref LL_BDMA_CHANNEL_4 1235 * @arg @ref LL_BDMA_CHANNEL_5 1236 * @arg @ref LL_BDMA_CHANNEL_6 1237 * @arg @ref LL_BDMA_CHANNEL_7 1238 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1239 * @retval None 1240 */ 1241 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) 1242 { 1243 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1244 1245 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); 1246 } 1247 1248 /** 1249 * @brief Get Memory address. 1250 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 1251 * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress 1252 * @param BDMAx BDMA Instance 1253 * @param Channel This parameter can be one of the following values: 1254 * @arg @ref LL_BDMA_CHANNEL_0 1255 * @arg @ref LL_BDMA_CHANNEL_1 1256 * @arg @ref LL_BDMA_CHANNEL_2 1257 * @arg @ref LL_BDMA_CHANNEL_3 1258 * @arg @ref LL_BDMA_CHANNEL_4 1259 * @arg @ref LL_BDMA_CHANNEL_5 1260 * @arg @ref LL_BDMA_CHANNEL_6 1261 * @arg @ref LL_BDMA_CHANNEL_7 1262 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1263 */ 1264 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 1265 { 1266 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1267 1268 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); 1269 } 1270 1271 /** 1272 * @brief Get Peripheral address. 1273 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 1274 * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress 1275 * @param BDMAx BDMA Instance 1276 * @param Channel This parameter can be one of the following values: 1277 * @arg @ref LL_BDMA_CHANNEL_0 1278 * @arg @ref LL_BDMA_CHANNEL_1 1279 * @arg @ref LL_BDMA_CHANNEL_2 1280 * @arg @ref LL_BDMA_CHANNEL_3 1281 * @arg @ref LL_BDMA_CHANNEL_4 1282 * @arg @ref LL_BDMA_CHANNEL_5 1283 * @arg @ref LL_BDMA_CHANNEL_6 1284 * @arg @ref LL_BDMA_CHANNEL_7 1285 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1286 */ 1287 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 1288 { 1289 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1290 1291 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); 1292 } 1293 1294 /** 1295 * @brief Set the Memory to Memory Source address. 1296 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 1297 * @note This API must not be called when the BDMA channel is enabled. 1298 * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress 1299 * @param BDMAx BDMA Instance 1300 * @param Channel This parameter can be one of the following values: 1301 * @arg @ref LL_BDMA_CHANNEL_0 1302 * @arg @ref LL_BDMA_CHANNEL_1 1303 * @arg @ref LL_BDMA_CHANNEL_2 1304 * @arg @ref LL_BDMA_CHANNEL_3 1305 * @arg @ref LL_BDMA_CHANNEL_4 1306 * @arg @ref LL_BDMA_CHANNEL_5 1307 * @arg @ref LL_BDMA_CHANNEL_6 1308 * @arg @ref LL_BDMA_CHANNEL_7 1309 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1310 * @retval None 1311 */ 1312 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 1313 { 1314 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1315 1316 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); 1317 } 1318 1319 /** 1320 * @brief Set the Memory to Memory Destination address. 1321 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 1322 * @note This API must not be called when the BDMA channel is enabled. 1323 * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress 1324 * @param BDMAx BDMA Instance 1325 * @param Channel This parameter can be one of the following values: 1326 * @arg @ref LL_BDMA_CHANNEL_0 1327 * @arg @ref LL_BDMA_CHANNEL_1 1328 * @arg @ref LL_BDMA_CHANNEL_2 1329 * @arg @ref LL_BDMA_CHANNEL_3 1330 * @arg @ref LL_BDMA_CHANNEL_4 1331 * @arg @ref LL_BDMA_CHANNEL_5 1332 * @arg @ref LL_BDMA_CHANNEL_6 1333 * @arg @ref LL_BDMA_CHANNEL_7 1334 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1335 * @retval None 1336 */ 1337 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 1338 { 1339 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1340 1341 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); 1342 } 1343 1344 /** 1345 * @brief Get the Memory to Memory Source address. 1346 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 1347 * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress 1348 * @param BDMAx BDMA Instance 1349 * @param Channel This parameter can be one of the following values: 1350 * @arg @ref LL_BDMA_CHANNEL_0 1351 * @arg @ref LL_BDMA_CHANNEL_1 1352 * @arg @ref LL_BDMA_CHANNEL_2 1353 * @arg @ref LL_BDMA_CHANNEL_3 1354 * @arg @ref LL_BDMA_CHANNEL_4 1355 * @arg @ref LL_BDMA_CHANNEL_5 1356 * @arg @ref LL_BDMA_CHANNEL_6 1357 * @arg @ref LL_BDMA_CHANNEL_7 1358 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1359 */ 1360 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 1361 { 1362 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1363 1364 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); 1365 } 1366 1367 /** 1368 * @brief Get the Memory to Memory Destination address. 1369 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 1370 * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress 1371 * @param BDMAx BDMA Instance 1372 * @param Channel This parameter can be one of the following values: 1373 * @arg @ref LL_BDMA_CHANNEL_0 1374 * @arg @ref LL_BDMA_CHANNEL_1 1375 * @arg @ref LL_BDMA_CHANNEL_2 1376 * @arg @ref LL_BDMA_CHANNEL_3 1377 * @arg @ref LL_BDMA_CHANNEL_4 1378 * @arg @ref LL_BDMA_CHANNEL_5 1379 * @arg @ref LL_BDMA_CHANNEL_6 1380 * @arg @ref LL_BDMA_CHANNEL_7 1381 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1382 */ 1383 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 1384 { 1385 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1386 1387 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); 1388 } 1389 1390 /** 1391 * @brief Set Memory 1 address (used in case of Double buffer mode). 1392 * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address 1393 * @param BDMAx BDMAx Instance 1394 * @param Channel This parameter can be one of the following values: 1395 * @arg @ref LL_BDMA_CHANNEL_0 1396 * @arg @ref LL_BDMA_CHANNEL_1 1397 * @arg @ref LL_BDMA_CHANNEL_2 1398 * @arg @ref LL_BDMA_CHANNEL_3 1399 * @arg @ref LL_BDMA_CHANNEL_4 1400 * @arg @ref LL_BDMA_CHANNEL_5 1401 * @arg @ref LL_BDMA_CHANNEL_6 1402 * @arg @ref LL_BDMA_CHANNEL_7 1403 * @param Address Between 0 to 0xFFFFFFFF 1404 * @retval None 1405 */ 1406 __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) 1407 { 1408 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1409 1410 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address); 1411 } 1412 1413 /** 1414 * @brief Get Memory 1 address (used in case of Double buffer mode). 1415 * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address 1416 * @param BDMAx BDMAx Instance 1417 * @param Channel This parameter can be one of the following values: 1418 * @arg @ref LL_BDMA_CHANNEL_0 1419 * @arg @ref LL_BDMA_CHANNEL_1 1420 * @arg @ref LL_BDMA_CHANNEL_2 1421 * @arg @ref LL_BDMA_CHANNEL_3 1422 * @arg @ref LL_BDMA_CHANNEL_4 1423 * @arg @ref LL_BDMA_CHANNEL_5 1424 * @arg @ref LL_BDMA_CHANNEL_6 1425 * @arg @ref LL_BDMA_CHANNEL_7 1426 * @retval Between 0 to 0xFFFFFFFF 1427 */ 1428 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) 1429 { 1430 uint32_t bdma_base_addr = (uint32_t)BDMAx; 1431 1432 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR); 1433 } 1434 1435 /** 1436 * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x. 1437 * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. 1438 * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest 1439 * @param BDMAx BDMAx Instance 1440 * @param Channel This parameter can be one of the following values: 1441 * @arg @ref LL_BDMA_CHANNEL_0 1442 * @arg @ref LL_BDMA_CHANNEL_1 1443 * @arg @ref LL_BDMA_CHANNEL_2 1444 * @arg @ref LL_BDMA_CHANNEL_3 1445 * @arg @ref LL_BDMA_CHANNEL_4 1446 * @arg @ref LL_BDMA_CHANNEL_5 1447 * @arg @ref LL_BDMA_CHANNEL_6 1448 * @arg @ref LL_BDMA_CHANNEL_7 1449 * @param Request This parameter can be one of the following values: 1450 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM 1451 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 1452 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 1453 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 1454 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 1455 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 1456 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 1457 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 1458 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 1459 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX 1460 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX 1461 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX 1462 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX 1463 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX 1464 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX 1465 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) 1466 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) 1467 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) 1468 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) 1469 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) 1470 * 1471 * @note (*) Availability depends on devices. 1472 * @retval None 1473 */ 1474 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) 1475 { 1476 UNUSED(BDMAx); 1477 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); 1478 } 1479 1480 /** 1481 * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x. 1482 * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7. 1483 * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest 1484 * @param BDMAx BDMAx Instance 1485 * @param Channel This parameter can be one of the following values: 1486 * @arg @ref LL_BDMA_CHANNEL_0 1487 * @arg @ref LL_BDMA_CHANNEL_1 1488 * @arg @ref LL_BDMA_CHANNEL_2 1489 * @arg @ref LL_BDMA_CHANNEL_3 1490 * @arg @ref LL_BDMA_CHANNEL_4 1491 * @arg @ref LL_BDMA_CHANNEL_5 1492 * @arg @ref LL_BDMA_CHANNEL_6 1493 * @arg @ref LL_BDMA_CHANNEL_7 1494 * @retval Returned value can be one of the following values: 1495 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM 1496 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 1497 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 1498 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 1499 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 1500 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 1501 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 1502 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 1503 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 1504 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX 1505 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX 1506 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX 1507 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX 1508 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX 1509 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX 1510 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) 1511 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) 1512 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) 1513 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) 1514 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) 1515 * 1516 * @note (*) Availability depends on devices. 1517 */ 1518 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) 1519 { 1520 UNUSED(BDMAx); 1521 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); 1522 } 1523 1524 /** 1525 * @} 1526 */ 1527 1528 1529 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management 1530 * @ingroup RTEMSBSPsARMSTM32H7 1531 * @{ 1532 */ 1533 /** 1534 * @brief Get Channel 0 global interrupt flag. 1535 * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0 1536 * @param BDMAx BDMA Instance 1537 * @retval State of bit (1 or 0). 1538 */ 1539 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) 1540 { 1541 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); 1542 } 1543 1544 /** 1545 * @brief Get Channel 1 global interrupt flag. 1546 * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1 1547 * @param BDMAx BDMA Instance 1548 * @retval State of bit (1 or 0). 1549 */ 1550 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) 1551 { 1552 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); 1553 } 1554 1555 /** 1556 * @brief Get Channel 2 global interrupt flag. 1557 * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2 1558 * @param BDMAx BDMA Instance 1559 * @retval State of bit (1 or 0). 1560 */ 1561 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) 1562 { 1563 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); 1564 } 1565 1566 /** 1567 * @brief Get Channel 3 global interrupt flag. 1568 * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3 1569 * @param BDMAx BDMA Instance 1570 * @retval State of bit (1 or 0). 1571 */ 1572 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) 1573 { 1574 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); 1575 } 1576 1577 /** 1578 * @brief Get Channel 4 global interrupt flag. 1579 * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4 1580 * @param BDMAx BDMA Instance 1581 * @retval State of bit (1 or 0). 1582 */ 1583 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) 1584 { 1585 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); 1586 } 1587 1588 /** 1589 * @brief Get Channel 5 global interrupt flag. 1590 * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5 1591 * @param BDMAx BDMA Instance 1592 * @retval State of bit (1 or 0). 1593 */ 1594 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) 1595 { 1596 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); 1597 } 1598 1599 /** 1600 * @brief Get Channel 6 global interrupt flag. 1601 * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6 1602 * @param BDMAx BDMA Instance 1603 * @retval State of bit (1 or 0). 1604 */ 1605 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) 1606 { 1607 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); 1608 } 1609 1610 /** 1611 * @brief Get Channel 7 global interrupt flag. 1612 * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7 1613 * @param BDMAx BDMA Instance 1614 * @retval State of bit (1 or 0). 1615 */ 1616 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) 1617 { 1618 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); 1619 } 1620 1621 /** 1622 * @brief Get Channel 0 transfer complete flag. 1623 * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0 1624 * @param BDMAx BDMA Instance 1625 * @retval State of bit (1 or 0). 1626 */ 1627 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) 1628 { 1629 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); 1630 } 1631 /** 1632 * @brief Get Channel 1 transfer complete flag. 1633 * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1 1634 * @param BDMAx BDMA Instance 1635 * @retval State of bit (1 or 0). 1636 */ 1637 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) 1638 { 1639 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); 1640 } 1641 1642 /** 1643 * @brief Get Channel 2 transfer complete flag. 1644 * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2 1645 * @param BDMAx BDMA Instance 1646 * @retval State of bit (1 or 0). 1647 */ 1648 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) 1649 { 1650 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); 1651 } 1652 1653 /** 1654 * @brief Get Channel 3 transfer complete flag. 1655 * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3 1656 * @param BDMAx BDMA Instance 1657 * @retval State of bit (1 or 0). 1658 */ 1659 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) 1660 { 1661 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); 1662 } 1663 1664 /** 1665 * @brief Get Channel 4 transfer complete flag. 1666 * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4 1667 * @param BDMAx BDMA Instance 1668 * @retval State of bit (1 or 0). 1669 */ 1670 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) 1671 { 1672 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); 1673 } 1674 1675 /** 1676 * @brief Get Channel 5 transfer complete flag. 1677 * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5 1678 * @param BDMAx BDMA Instance 1679 * @retval State of bit (1 or 0). 1680 */ 1681 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) 1682 { 1683 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); 1684 } 1685 1686 /** 1687 * @brief Get Channel 6 transfer complete flag. 1688 * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6 1689 * @param BDMAx BDMA Instance 1690 * @retval State of bit (1 or 0). 1691 */ 1692 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) 1693 { 1694 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); 1695 } 1696 1697 /** 1698 * @brief Get Channel 7 transfer complete flag. 1699 * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7 1700 * @param BDMAx BDMA Instance 1701 * @retval State of bit (1 or 0). 1702 */ 1703 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) 1704 { 1705 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); 1706 } 1707 1708 /** 1709 * @brief Get Channel 0 half transfer flag. 1710 * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0 1711 * @param BDMAx BDMA Instance 1712 * @retval State of bit (1 or 0). 1713 */ 1714 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) 1715 { 1716 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); 1717 } 1718 1719 /** 1720 * @brief Get Channel 1 half transfer flag. 1721 * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1 1722 * @param BDMAx BDMA Instance 1723 * @retval State of bit (1 or 0). 1724 */ 1725 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) 1726 { 1727 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); 1728 } 1729 1730 /** 1731 * @brief Get Channel 2 half transfer flag. 1732 * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2 1733 * @param BDMAx BDMA Instance 1734 * @retval State of bit (1 or 0). 1735 */ 1736 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) 1737 { 1738 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); 1739 } 1740 1741 /** 1742 * @brief Get Channel 3 half transfer flag. 1743 * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3 1744 * @param BDMAx BDMA Instance 1745 * @retval State of bit (1 or 0). 1746 */ 1747 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) 1748 { 1749 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); 1750 } 1751 1752 /** 1753 * @brief Get Channel 4 half transfer flag. 1754 * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4 1755 * @param BDMAx BDMA Instance 1756 * @retval State of bit (1 or 0). 1757 */ 1758 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) 1759 { 1760 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); 1761 } 1762 1763 /** 1764 * @brief Get Channel 5 half transfer flag. 1765 * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5 1766 * @param BDMAx BDMA Instance 1767 * @retval State of bit (1 or 0). 1768 */ 1769 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) 1770 { 1771 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); 1772 } 1773 1774 /** 1775 * @brief Get Channel 6 half transfer flag. 1776 * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6 1777 * @param BDMAx BDMA Instance 1778 * @retval State of bit (1 or 0). 1779 */ 1780 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) 1781 { 1782 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); 1783 } 1784 1785 /** 1786 * @brief Get Channel 7 half transfer flag. 1787 * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7 1788 * @param BDMAx BDMA Instance 1789 * @retval State of bit (1 or 0). 1790 */ 1791 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) 1792 { 1793 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); 1794 } 1795 1796 /** 1797 * @brief Get Channel 0 transfer error flag. 1798 * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0 1799 * @param BDMAx BDMA Instance 1800 * @retval State of bit (1 or 0). 1801 */ 1802 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) 1803 { 1804 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); 1805 } 1806 1807 /** 1808 * @brief Get Channel 1 transfer error flag. 1809 * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1 1810 * @param BDMAx BDMA Instance 1811 * @retval State of bit (1 or 0). 1812 */ 1813 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) 1814 { 1815 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); 1816 } 1817 1818 /** 1819 * @brief Get Channel 2 transfer error flag. 1820 * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2 1821 * @param BDMAx BDMA Instance 1822 * @retval State of bit (1 or 0). 1823 */ 1824 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) 1825 { 1826 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); 1827 } 1828 1829 /** 1830 * @brief Get Channel 3 transfer error flag. 1831 * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3 1832 * @param BDMAx BDMA Instance 1833 * @retval State of bit (1 or 0). 1834 */ 1835 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) 1836 { 1837 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); 1838 } 1839 1840 /** 1841 * @brief Get Channel 4 transfer error flag. 1842 * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4 1843 * @param BDMAx BDMA Instance 1844 * @retval State of bit (1 or 0). 1845 */ 1846 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) 1847 { 1848 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); 1849 } 1850 1851 /** 1852 * @brief Get Channel 5 transfer error flag. 1853 * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5 1854 * @param BDMAx BDMA Instance 1855 * @retval State of bit (1 or 0). 1856 */ 1857 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) 1858 { 1859 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); 1860 } 1861 1862 /** 1863 * @brief Get Channel 6 transfer error flag. 1864 * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6 1865 * @param BDMAx BDMA Instance 1866 * @retval State of bit (1 or 0). 1867 */ 1868 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) 1869 { 1870 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); 1871 } 1872 1873 /** 1874 * @brief Get Channel 7 transfer error flag. 1875 * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7 1876 * @param BDMAx BDMA Instance 1877 * @retval State of bit (1 or 0). 1878 */ 1879 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) 1880 { 1881 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); 1882 } 1883 1884 /** 1885 * @brief Clear Channel 0 global interrupt flag. 1886 * @note Do not Clear Channel 0 global interrupt flag when the channel in ON. 1887 Instead clear specific flags transfer complete, half transfer & transfer 1888 error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0, 1889 LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet. 1890 * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0 1891 * @param BDMAx BDMA Instance 1892 * @retval None 1893 */ 1894 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx) 1895 { 1896 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0); 1897 } 1898 1899 /** 1900 * @brief Clear Channel 1 global interrupt flag. 1901 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. 1902 Instead clear specific flags transfer complete, half transfer & transfer 1903 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, 1904 LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. 1905 * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1 1906 * @param BDMAx BDMA Instance 1907 * @retval None 1908 */ 1909 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx) 1910 { 1911 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1); 1912 } 1913 1914 /** 1915 * @brief Clear Channel 2 global interrupt flag. 1916 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. 1917 Instead clear specific flags transfer complete, half transfer & transfer 1918 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, 1919 LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. 1920 * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2 1921 * @param BDMAx BDMA Instance 1922 * @retval None 1923 */ 1924 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx) 1925 { 1926 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2); 1927 } 1928 1929 /** 1930 * @brief Clear Channel 3 global interrupt flag. 1931 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. 1932 Instead clear specific flags transfer complete, half transfer & transfer 1933 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, 1934 LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. 1935 * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3 1936 * @param BDMAx BDMA Instance 1937 * @retval None 1938 */ 1939 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx) 1940 { 1941 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3); 1942 } 1943 1944 /** 1945 * @brief Clear Channel 4 global interrupt flag. 1946 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. 1947 Instead clear specific flags transfer complete, half transfer & transfer 1948 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, 1949 LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. 1950 * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4 1951 * @param BDMAx BDMA Instance 1952 * @retval None 1953 */ 1954 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx) 1955 { 1956 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4); 1957 } 1958 1959 /** 1960 * @brief Clear Channel 5 global interrupt flag. 1961 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. 1962 Instead clear specific flags transfer complete, half transfer & transfer 1963 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, 1964 LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. 1965 * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5 1966 * @param BDMAx BDMA Instance 1967 * @retval None 1968 */ 1969 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx) 1970 { 1971 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5); 1972 } 1973 1974 /** 1975 * @brief Clear Channel 6 global interrupt flag. 1976 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. 1977 Instead clear specific flags transfer complete, half transfer & transfer 1978 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, 1979 LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. 1980 * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6 1981 * @param BDMAx BDMA Instance 1982 * @retval None 1983 */ 1984 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx) 1985 { 1986 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6); 1987 } 1988 1989 /** 1990 * @brief Clear Channel 7 global interrupt flag. 1991 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. 1992 Instead clear specific flags transfer complete, half transfer & transfer 1993 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, 1994 LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. 1995 * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7 1996 * @param BDMAx BDMA Instance 1997 * @retval None 1998 */ 1999 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx) 2000 { 2001 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7); 2002 } 2003 2004 /** 2005 * @brief Clear Channel 0 transfer complete flag. 2006 * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0 2007 * @param BDMAx BDMA Instance 2008 * @retval None 2009 */ 2010 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx) 2011 { 2012 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0); 2013 } 2014 2015 /** 2016 * @brief Clear Channel 1 transfer complete flag. 2017 * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1 2018 * @param BDMAx BDMA Instance 2019 * @retval None 2020 */ 2021 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx) 2022 { 2023 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1); 2024 } 2025 2026 /** 2027 * @brief Clear Channel 2 transfer complete flag. 2028 * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2 2029 * @param BDMAx BDMA Instance 2030 * @retval None 2031 */ 2032 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx) 2033 { 2034 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2); 2035 } 2036 2037 /** 2038 * @brief Clear Channel 3 transfer complete flag. 2039 * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3 2040 * @param BDMAx BDMA Instance 2041 * @retval None 2042 */ 2043 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx) 2044 { 2045 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3); 2046 } 2047 2048 /** 2049 * @brief Clear Channel 4 transfer complete flag. 2050 * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4 2051 * @param BDMAx BDMA Instance 2052 * @retval None 2053 */ 2054 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx) 2055 { 2056 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4); 2057 } 2058 2059 /** 2060 * @brief Clear Channel 5 transfer complete flag. 2061 * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5 2062 * @param BDMAx BDMA Instance 2063 * @retval None 2064 */ 2065 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx) 2066 { 2067 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5); 2068 } 2069 2070 /** 2071 * @brief Clear Channel 6 transfer complete flag. 2072 * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6 2073 * @param BDMAx BDMA Instance 2074 * @retval None 2075 */ 2076 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx) 2077 { 2078 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6); 2079 } 2080 2081 /** 2082 * @brief Clear Channel 7 transfer complete flag. 2083 * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7 2084 * @param BDMAx BDMA Instance 2085 * @retval None 2086 */ 2087 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx) 2088 { 2089 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7); 2090 } 2091 2092 /** 2093 * @brief Clear Channel 0 half transfer flag. 2094 * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0 2095 * @param BDMAx BDMA Instance 2096 * @retval None 2097 */ 2098 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx) 2099 { 2100 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0); 2101 } 2102 2103 /** 2104 * @brief Clear Channel 1 half transfer flag. 2105 * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1 2106 * @param BDMAx BDMA Instance 2107 * @retval None 2108 */ 2109 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx) 2110 { 2111 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1); 2112 } 2113 2114 /** 2115 * @brief Clear Channel 2 half transfer flag. 2116 * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2 2117 * @param BDMAx BDMA Instance 2118 * @retval None 2119 */ 2120 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx) 2121 { 2122 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2); 2123 } 2124 2125 /** 2126 * @brief Clear Channel 3 half transfer flag. 2127 * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3 2128 * @param BDMAx BDMA Instance 2129 * @retval None 2130 */ 2131 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx) 2132 { 2133 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3); 2134 } 2135 2136 /** 2137 * @brief Clear Channel 4 half transfer flag. 2138 * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4 2139 * @param BDMAx BDMA Instance 2140 * @retval None 2141 */ 2142 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx) 2143 { 2144 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4); 2145 } 2146 2147 /** 2148 * @brief Clear Channel 5 half transfer flag. 2149 * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5 2150 * @param BDMAx BDMA Instance 2151 * @retval None 2152 */ 2153 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx) 2154 { 2155 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5); 2156 } 2157 2158 /** 2159 * @brief Clear Channel 6 half transfer flag. 2160 * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6 2161 * @param BDMAx BDMA Instance 2162 * @retval None 2163 */ 2164 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx) 2165 { 2166 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6); 2167 } 2168 2169 /** 2170 * @brief Clear Channel 7 half transfer flag. 2171 * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7 2172 * @param BDMAx BDMA Instance 2173 * @retval None 2174 */ 2175 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx) 2176 { 2177 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7); 2178 } 2179 2180 /** 2181 * @brief Clear Channel 0 transfer error flag. 2182 * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0 2183 * @param BDMAx BDMA Instance 2184 * @retval None 2185 */ 2186 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx) 2187 { 2188 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0); 2189 } 2190 2191 /** 2192 * @brief Clear Channel 1 transfer error flag. 2193 * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1 2194 * @param BDMAx BDMA Instance 2195 * @retval None 2196 */ 2197 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx) 2198 { 2199 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1); 2200 } 2201 2202 /** 2203 * @brief Clear Channel 2 transfer error flag. 2204 * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2 2205 * @param BDMAx BDMA Instance 2206 * @retval None 2207 */ 2208 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx) 2209 { 2210 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2); 2211 } 2212 2213 /** 2214 * @brief Clear Channel 3 transfer error flag. 2215 * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3 2216 * @param BDMAx BDMA Instance 2217 * @retval None 2218 */ 2219 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx) 2220 { 2221 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3); 2222 } 2223 2224 /** 2225 * @brief Clear Channel 4 transfer error flag. 2226 * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4 2227 * @param BDMAx BDMA Instance 2228 * @retval None 2229 */ 2230 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx) 2231 { 2232 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4); 2233 } 2234 2235 /** 2236 * @brief Clear Channel 5 transfer error flag. 2237 * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5 2238 * @param BDMAx BDMA Instance 2239 * @retval None 2240 */ 2241 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx) 2242 { 2243 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5); 2244 } 2245 2246 /** 2247 * @brief Clear Channel 6 transfer error flag. 2248 * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6 2249 * @param BDMAx BDMA Instance 2250 * @retval None 2251 */ 2252 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx) 2253 { 2254 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6); 2255 } 2256 2257 /** 2258 * @brief Clear Channel 7 transfer error flag. 2259 * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7 2260 * @param BDMAx BDMA Instance 2261 * @retval None 2262 */ 2263 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) 2264 { 2265 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7); 2266 } 2267 2268 /** 2269 * @} 2270 */ 2271 2272 /** @defgroup BDMA_LL_EF_IT_Management IT_Management 2273 * @ingroup RTEMSBSPsARMSTM32H7 2274 * @{ 2275 */ 2276 /** 2277 * @brief Enable Transfer complete interrupt. 2278 * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC 2279 * @param BDMAx BDMA Instance 2280 * @param Channel This parameter can be one of the following values: 2281 * @arg @ref LL_BDMA_CHANNEL_0 2282 * @arg @ref LL_BDMA_CHANNEL_1 2283 * @arg @ref LL_BDMA_CHANNEL_2 2284 * @arg @ref LL_BDMA_CHANNEL_3 2285 * @arg @ref LL_BDMA_CHANNEL_4 2286 * @arg @ref LL_BDMA_CHANNEL_5 2287 * @arg @ref LL_BDMA_CHANNEL_6 2288 * @arg @ref LL_BDMA_CHANNEL_7 2289 * @retval None 2290 */ 2291 __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 2292 { 2293 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2294 2295 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); 2296 } 2297 2298 /** 2299 * @brief Enable Half transfer interrupt. 2300 * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT 2301 * @param BDMAx BDMA Instance 2302 * @param Channel This parameter can be one of the following values: 2303 * @arg @ref LL_BDMA_CHANNEL_0 2304 * @arg @ref LL_BDMA_CHANNEL_1 2305 * @arg @ref LL_BDMA_CHANNEL_2 2306 * @arg @ref LL_BDMA_CHANNEL_3 2307 * @arg @ref LL_BDMA_CHANNEL_4 2308 * @arg @ref LL_BDMA_CHANNEL_5 2309 * @arg @ref LL_BDMA_CHANNEL_6 2310 * @arg @ref LL_BDMA_CHANNEL_7 2311 * @retval None 2312 */ 2313 __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 2314 { 2315 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2316 2317 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); 2318 } 2319 2320 /** 2321 * @brief Enable Transfer error interrupt. 2322 * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE 2323 * @param BDMAx BDMA Instance 2324 * @param Channel This parameter can be one of the following values: 2325 * @arg @ref LL_BDMA_CHANNEL_0 2326 * @arg @ref LL_BDMA_CHANNEL_1 2327 * @arg @ref LL_BDMA_CHANNEL_2 2328 * @arg @ref LL_BDMA_CHANNEL_3 2329 * @arg @ref LL_BDMA_CHANNEL_4 2330 * @arg @ref LL_BDMA_CHANNEL_5 2331 * @arg @ref LL_BDMA_CHANNEL_6 2332 * @arg @ref LL_BDMA_CHANNEL_7 2333 * @retval None 2334 */ 2335 __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 2336 { 2337 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2338 2339 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); 2340 } 2341 2342 /** 2343 * @brief Disable Transfer complete interrupt. 2344 * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC 2345 * @param BDMAx BDMA Instance 2346 * @param Channel This parameter can be one of the following values: 2347 * @arg @ref LL_BDMA_CHANNEL_0 2348 * @arg @ref LL_BDMA_CHANNEL_1 2349 * @arg @ref LL_BDMA_CHANNEL_2 2350 * @arg @ref LL_BDMA_CHANNEL_3 2351 * @arg @ref LL_BDMA_CHANNEL_4 2352 * @arg @ref LL_BDMA_CHANNEL_5 2353 * @arg @ref LL_BDMA_CHANNEL_6 2354 * @arg @ref LL_BDMA_CHANNEL_7 2355 * @retval None 2356 */ 2357 __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 2358 { 2359 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2360 2361 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); 2362 } 2363 2364 /** 2365 * @brief Disable Half transfer interrupt. 2366 * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT 2367 * @param BDMAx BDMA Instance 2368 * @param Channel This parameter can be one of the following values: 2369 * @arg @ref LL_BDMA_CHANNEL_0 2370 * @arg @ref LL_BDMA_CHANNEL_1 2371 * @arg @ref LL_BDMA_CHANNEL_2 2372 * @arg @ref LL_BDMA_CHANNEL_3 2373 * @arg @ref LL_BDMA_CHANNEL_4 2374 * @arg @ref LL_BDMA_CHANNEL_5 2375 * @arg @ref LL_BDMA_CHANNEL_6 2376 * @arg @ref LL_BDMA_CHANNEL_7 2377 * @retval None 2378 */ 2379 __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 2380 { 2381 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2382 2383 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); 2384 } 2385 2386 /** 2387 * @brief Disable Transfer error interrupt. 2388 * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE 2389 * @param BDMAx BDMA Instance 2390 * @param Channel This parameter can be one of the following values: 2391 * @arg @ref LL_BDMA_CHANNEL_0 2392 * @arg @ref LL_BDMA_CHANNEL_1 2393 * @arg @ref LL_BDMA_CHANNEL_2 2394 * @arg @ref LL_BDMA_CHANNEL_3 2395 * @arg @ref LL_BDMA_CHANNEL_4 2396 * @arg @ref LL_BDMA_CHANNEL_5 2397 * @arg @ref LL_BDMA_CHANNEL_6 2398 * @arg @ref LL_BDMA_CHANNEL_7 2399 * @retval None 2400 */ 2401 __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 2402 { 2403 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2404 2405 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); 2406 } 2407 2408 /** 2409 * @brief Check if Transfer complete Interrupt is enabled. 2410 * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC 2411 * @param BDMAx BDMA Instance 2412 * @param Channel This parameter can be one of the following values: 2413 * @arg @ref LL_BDMA_CHANNEL_0 2414 * @arg @ref LL_BDMA_CHANNEL_1 2415 * @arg @ref LL_BDMA_CHANNEL_2 2416 * @arg @ref LL_BDMA_CHANNEL_3 2417 * @arg @ref LL_BDMA_CHANNEL_4 2418 * @arg @ref LL_BDMA_CHANNEL_5 2419 * @arg @ref LL_BDMA_CHANNEL_6 2420 * @arg @ref LL_BDMA_CHANNEL_7 2421 * @retval State of bit (1 or 0). 2422 */ 2423 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 2424 { 2425 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2426 2427 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL); 2428 } 2429 2430 /** 2431 * @brief Check if Half transfer Interrupt is enabled. 2432 * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT 2433 * @param BDMAx BDMA Instance 2434 * @param Channel This parameter can be one of the following values: 2435 * @arg @ref LL_BDMA_CHANNEL_0 2436 * @arg @ref LL_BDMA_CHANNEL_1 2437 * @arg @ref LL_BDMA_CHANNEL_2 2438 * @arg @ref LL_BDMA_CHANNEL_3 2439 * @arg @ref LL_BDMA_CHANNEL_4 2440 * @arg @ref LL_BDMA_CHANNEL_5 2441 * @arg @ref LL_BDMA_CHANNEL_6 2442 * @arg @ref LL_BDMA_CHANNEL_7 2443 * @retval State of bit (1 or 0). 2444 */ 2445 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 2446 { 2447 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2448 2449 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL); 2450 } 2451 2452 /** 2453 * @brief Check if Transfer error Interrupt is enabled. 2454 * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE 2455 * @param BDMAx BDMA Instance 2456 * @param Channel This parameter can be one of the following values: 2457 * @arg @ref LL_BDMA_CHANNEL_0 2458 * @arg @ref LL_BDMA_CHANNEL_1 2459 * @arg @ref LL_BDMA_CHANNEL_2 2460 * @arg @ref LL_BDMA_CHANNEL_3 2461 * @arg @ref LL_BDMA_CHANNEL_4 2462 * @arg @ref LL_BDMA_CHANNEL_5 2463 * @arg @ref LL_BDMA_CHANNEL_6 2464 * @arg @ref LL_BDMA_CHANNEL_7 2465 * @retval State of bit (1 or 0). 2466 */ 2467 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 2468 { 2469 uint32_t bdma_base_addr = (uint32_t)BDMAx; 2470 2471 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL); 2472 } 2473 2474 /** 2475 * @} 2476 */ 2477 2478 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__) 2479 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions 2480 * @ingroup RTEMSBSPsARMSTM32H7 2481 * @{ 2482 */ 2483 2484 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct); 2485 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel); 2486 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct); 2487 2488 /** 2489 * @} 2490 */ 2491 #endif /* USE_FULL_LL_DRIVER */ 2492 2493 /** 2494 * @} 2495 */ 2496 2497 /** 2498 * @} 2499 */ 2500 2501 #endif /* BDMA || BDMA1 || BDMA2 */ 2502 /** 2503 * @} 2504 */ 2505 2506 #ifdef __cplusplus 2507 } 2508 #endif 2509 2510 #endif /* STM32H7xx_LL_BDMA_H */ 2511
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