Back to home page

LXR
 
 

    

File indexing completed on 2025-05-11 08:23:36 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_tim.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of TIM HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_TIM_H
0021 #define STM32H7xx_HAL_TIM_H
0022 
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026 
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029 
0030 /** @addtogroup STM32H7xx_HAL_Driver
0031   * @{
0032   */
0033 
0034 /** @addtogroup TIM
0035   * @{
0036   */
0037 
0038 /* Exported types ------------------------------------------------------------*/
0039 /** @defgroup TIM_Exported_Types TIM Exported Types
0040   * @ingroup RTEMSBSPsARMSTM32H7
0041   * @{
0042   */
0043 
0044 /**
0045   * @brief  TIM Time base Configuration Structure definition
0046   */
0047 typedef struct
0048 {
0049   uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
0050                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
0051 
0052   uint32_t CounterMode;       /*!< Specifies the counter mode.
0053                                    This parameter can be a value of @ref TIM_Counter_Mode */
0054 
0055   uint32_t Period;            /*!< Specifies the period value to be loaded into the active
0056                                    Auto-Reload Register at the next update event.
0057                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
0058 
0059   uint32_t ClockDivision;     /*!< Specifies the clock division.
0060                                    This parameter can be a value of @ref TIM_ClockDivision */
0061 
0062   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
0063                                     reaches zero, an update event is generated and counting restarts
0064                                     from the RCR value (N).
0065                                     This means in PWM mode that (N+1) corresponds to:
0066                                         - the number of PWM periods in edge-aligned mode
0067                                         - the number of half PWM period in center-aligned mode
0068                                      GP timers: this parameter must be a number between Min_Data = 0x00 and
0069                                      Max_Data = 0xFF.
0070                                      Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
0071                                      Max_Data = 0xFFFF. */
0072 
0073   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
0074                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
0075 } TIM_Base_InitTypeDef;
0076 
0077 /**
0078   * @brief  TIM Output Compare Configuration Structure definition
0079   */
0080 typedef struct
0081 {
0082   uint32_t OCMode;        /*!< Specifies the TIM mode.
0083                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
0084 
0085   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
0086                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
0087 
0088   uint32_t OCPolarity;    /*!< Specifies the output polarity.
0089                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
0090 
0091   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
0092                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
0093                                @note This parameter is valid only for timer instances supporting break feature. */
0094 
0095   uint32_t OCFastMode;    /*!< Specifies the Fast mode state.
0096                                This parameter can be a value of @ref TIM_Output_Fast_State
0097                                @note This parameter is valid only in PWM1 and PWM2 mode. */
0098 
0099 
0100   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
0101                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
0102                                @note This parameter is valid only for timer instances supporting break feature. */
0103 
0104   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
0105                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
0106                                @note This parameter is valid only for timer instances supporting break feature. */
0107 } TIM_OC_InitTypeDef;
0108 
0109 /**
0110   * @brief  TIM One Pulse Mode Configuration Structure definition
0111   */
0112 typedef struct
0113 {
0114   uint32_t OCMode;        /*!< Specifies the TIM mode.
0115                                This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
0116 
0117   uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
0118                                This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
0119 
0120   uint32_t OCPolarity;    /*!< Specifies the output polarity.
0121                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
0122 
0123   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
0124                                This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
0125                                @note This parameter is valid only for timer instances supporting break feature. */
0126 
0127   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
0128                                This parameter can be a value of @ref TIM_Output_Compare_Idle_State
0129                                @note This parameter is valid only for timer instances supporting break feature. */
0130 
0131   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
0132                                This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
0133                                @note This parameter is valid only for timer instances supporting break feature. */
0134 
0135   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
0136                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
0137 
0138   uint32_t ICSelection;   /*!< Specifies the input.
0139                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
0140 
0141   uint32_t ICFilter;      /*!< Specifies the input capture filter.
0142                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0143 } TIM_OnePulse_InitTypeDef;
0144 
0145 /**
0146   * @brief  TIM Input Capture Configuration Structure definition
0147   */
0148 typedef struct
0149 {
0150   uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
0151                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
0152 
0153   uint32_t ICSelection;  /*!< Specifies the input.
0154                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
0155 
0156   uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
0157                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
0158 
0159   uint32_t ICFilter;     /*!< Specifies the input capture filter.
0160                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0161 } TIM_IC_InitTypeDef;
0162 
0163 /**
0164   * @brief  TIM Encoder Configuration Structure definition
0165   */
0166 typedef struct
0167 {
0168   uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
0169                                This parameter can be a value of @ref TIM_Encoder_Mode */
0170 
0171   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
0172                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
0173 
0174   uint32_t IC1Selection;  /*!< Specifies the input.
0175                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
0176 
0177   uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
0178                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
0179 
0180   uint32_t IC1Filter;     /*!< Specifies the input capture filter.
0181                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0182 
0183   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
0184                                This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
0185 
0186   uint32_t IC2Selection;  /*!< Specifies the input.
0187                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
0188 
0189   uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
0190                                This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
0191 
0192   uint32_t IC2Filter;     /*!< Specifies the input capture filter.
0193                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0194 } TIM_Encoder_InitTypeDef;
0195 
0196 /**
0197   * @brief  Clock Configuration Handle Structure definition
0198   */
0199 typedef struct
0200 {
0201   uint32_t ClockSource;     /*!< TIM clock sources
0202                                  This parameter can be a value of @ref TIM_Clock_Source */
0203   uint32_t ClockPolarity;   /*!< TIM clock polarity
0204                                  This parameter can be a value of @ref TIM_Clock_Polarity */
0205   uint32_t ClockPrescaler;  /*!< TIM clock prescaler
0206                                  This parameter can be a value of @ref TIM_Clock_Prescaler */
0207   uint32_t ClockFilter;     /*!< TIM clock filter
0208                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0209 } TIM_ClockConfigTypeDef;
0210 
0211 /**
0212   * @brief  TIM Clear Input Configuration Handle Structure definition
0213   */
0214 typedef struct
0215 {
0216   uint32_t ClearInputState;      /*!< TIM clear Input state
0217                                       This parameter can be ENABLE or DISABLE */
0218   uint32_t ClearInputSource;     /*!< TIM clear Input sources
0219                                       This parameter can be a value of @ref TIM_ClearInput_Source */
0220   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
0221                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
0222   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
0223                                       This parameter must be 0: When OCRef clear feature is used with ETR source,
0224                                       ETR prescaler must be off */
0225   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
0226                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0227 } TIM_ClearInputConfigTypeDef;
0228 
0229 /**
0230   * @brief  TIM Master configuration Structure definition
0231   * @note   Advanced timers provide TRGO2 internal line which is redirected
0232   *         to the ADC
0233   */
0234 typedef struct
0235 {
0236   uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection
0237                                         This parameter can be a value of @ref TIM_Master_Mode_Selection */
0238   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
0239                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
0240   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
0241                                         This parameter can be a value of @ref TIM_Master_Slave_Mode
0242                                         @note When the Master/slave mode is enabled, the effect of
0243                                         an event on the trigger input (TRGI) is delayed to allow a
0244                                         perfect synchronization between the current timer and its
0245                                         slaves (through TRGO). It is not mandatory in case of timer
0246                                         synchronization mode. */
0247 } TIM_MasterConfigTypeDef;
0248 
0249 /**
0250   * @brief  TIM Slave configuration Structure definition
0251   */
0252 typedef struct
0253 {
0254   uint32_t  SlaveMode;         /*!< Slave mode selection
0255                                     This parameter can be a value of @ref TIM_Slave_Mode */
0256   uint32_t  InputTrigger;      /*!< Input Trigger source
0257                                     This parameter can be a value of @ref TIM_Trigger_Selection */
0258   uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
0259                                     This parameter can be a value of @ref TIM_Trigger_Polarity */
0260   uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
0261                                     This parameter can be a value of @ref TIM_Trigger_Prescaler */
0262   uint32_t  TriggerFilter;     /*!< Input trigger filter
0263                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */
0264 
0265 } TIM_SlaveConfigTypeDef;
0266 
0267 /**
0268   * @brief  TIM Break input(s) and Dead time configuration Structure definition
0269   * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable
0270   *        filter and polarity.
0271   */
0272 typedef struct
0273 {
0274   uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
0275 
0276   uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
0277 
0278   uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
0279 
0280   uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
0281 
0282   uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
0283 
0284   uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
0285 
0286   uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0287 
0288 #if defined(TIM_BDTR_BKBID)
0289   uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
0290 
0291 #endif /* TIM_BDTR_BKBID */
0292   uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
0293 
0294   uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
0295 
0296   uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
0297 
0298 #if defined(TIM_BDTR_BKBID)
0299   uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
0300 
0301 #endif /* TIM_BDTR_BKBID */
0302   uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
0303 
0304 } TIM_BreakDeadTimeConfigTypeDef;
0305 
0306 /**
0307   * @brief  HAL State structures definition
0308   */
0309 typedef enum
0310 {
0311   HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
0312   HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
0313   HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
0314   HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
0315   HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */
0316 } HAL_TIM_StateTypeDef;
0317 
0318 /**
0319   * @brief  TIM Channel States definition
0320   */
0321 typedef enum
0322 {
0323   HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */
0324   HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */
0325   HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */
0326 } HAL_TIM_ChannelStateTypeDef;
0327 
0328 /**
0329   * @brief  DMA Burst States definition
0330   */
0331 typedef enum
0332 {
0333   HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */
0334   HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */
0335   HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */
0336 } HAL_TIM_DMABurstStateTypeDef;
0337 
0338 /**
0339   * @brief  HAL Active channel structures definition
0340   */
0341 typedef enum
0342 {
0343   HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */
0344   HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */
0345   HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */
0346   HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */
0347   HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */
0348   HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */
0349   HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */
0350 } HAL_TIM_ActiveChannel;
0351 
0352 /**
0353   * @brief  TIM Time Base Handle Structure definition
0354   */
0355 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0356 typedef struct __TIM_HandleTypeDef
0357 #else
0358 typedef struct
0359 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0360 {
0361   TIM_TypeDef                        *Instance;         /*!< Register base address                             */
0362   TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */
0363   HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */
0364   DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array
0365                                                              This array is accessed by a @ref DMA_Handle_index */
0366   HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */
0367   __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */
0368   __IO HAL_TIM_ChannelStateTypeDef   ChannelState[6];   /*!< TIM channel operation state                       */
0369   __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */
0370   __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */
0371 
0372 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0373   void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */
0374   void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */
0375   void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */
0376   void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */
0377   void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */
0378   void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */
0379   void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */
0380   void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */
0381   void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */
0382   void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */
0383   void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */
0384   void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */
0385   void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */
0386   void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */
0387   void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */
0388   void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */
0389   void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */
0390   void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */
0391   void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */
0392   void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */
0393   void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */
0394   void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */
0395   void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */
0396   void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */
0397   void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */
0398   void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */
0399   void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */
0400   void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */
0401 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0402 } TIM_HandleTypeDef;
0403 
0404 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
0405 /**
0406   * @brief  HAL TIM Callback ID enumeration definition
0407   */
0408 typedef enum
0409 {
0410   HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
0411   , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
0412   , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
0413   , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
0414   , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
0415   , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
0416   , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
0417   , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
0418   , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
0419   , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
0420   , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
0421   , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
0422   , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
0423   , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
0424   , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
0425   , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
0426   , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
0427   , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
0428   , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
0429   , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
0430   , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
0431   , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
0432   , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
0433   , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
0434   , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
0435   , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */
0436   , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */
0437   , HAL_TIM_BREAK2_CB_ID                  = 0x1BU   /*!< TIM Break2 Callback ID                                     */
0438 } HAL_TIM_CallbackIDTypeDef;
0439 
0440 /**
0441   * @brief  HAL TIM Callback pointer definition
0442   */
0443 typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */
0444 
0445 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
0446 
0447 /**
0448   * @}
0449   */
0450 /* End of exported types -----------------------------------------------------*/
0451 
0452 /* Exported constants --------------------------------------------------------*/
0453 /** @defgroup TIM_Exported_Constants TIM Exported Constants
0454   * @ingroup RTEMSBSPsARMSTM32H7
0455   * @{
0456   */
0457 
0458 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
0459   * @ingroup RTEMSBSPsARMSTM32H7
0460   * @{
0461   */
0462 #define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */
0463 #define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */
0464 /**
0465   * @}
0466   */
0467 
0468 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
0469   * @ingroup RTEMSBSPsARMSTM32H7
0470   * @{
0471   */
0472 #define TIM_DMABASE_CR1                    0x00000000U
0473 #define TIM_DMABASE_CR2                    0x00000001U
0474 #define TIM_DMABASE_SMCR                   0x00000002U
0475 #define TIM_DMABASE_DIER                   0x00000003U
0476 #define TIM_DMABASE_SR                     0x00000004U
0477 #define TIM_DMABASE_EGR                    0x00000005U
0478 #define TIM_DMABASE_CCMR1                  0x00000006U
0479 #define TIM_DMABASE_CCMR2                  0x00000007U
0480 #define TIM_DMABASE_CCER                   0x00000008U
0481 #define TIM_DMABASE_CNT                    0x00000009U
0482 #define TIM_DMABASE_PSC                    0x0000000AU
0483 #define TIM_DMABASE_ARR                    0x0000000BU
0484 #define TIM_DMABASE_RCR                    0x0000000CU
0485 #define TIM_DMABASE_CCR1                   0x0000000DU
0486 #define TIM_DMABASE_CCR2                   0x0000000EU
0487 #define TIM_DMABASE_CCR3                   0x0000000FU
0488 #define TIM_DMABASE_CCR4                   0x00000010U
0489 #define TIM_DMABASE_BDTR                   0x00000011U
0490 #define TIM_DMABASE_DCR                    0x00000012U
0491 #define TIM_DMABASE_DMAR                   0x00000013U
0492 #define TIM_DMABASE_CCMR3                  0x00000015U
0493 #define TIM_DMABASE_CCR5                   0x00000016U
0494 #define TIM_DMABASE_CCR6                   0x00000017U
0495 #if   defined(TIM_BREAK_INPUT_SUPPORT)
0496 #define TIM_DMABASE_AF1                    0x00000018U
0497 #define TIM_DMABASE_AF2                    0x00000019U
0498 #endif /* TIM_BREAK_INPUT_SUPPORT */
0499 #define TIM_DMABASE_TISEL                  0x0000001AU
0500 /**
0501   * @}
0502   */
0503 
0504 /** @defgroup TIM_Event_Source TIM Event Source
0505   * @ingroup RTEMSBSPsARMSTM32H7
0506   * @{
0507   */
0508 #define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */
0509 #define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */
0510 #define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */
0511 #define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */
0512 #define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */
0513 #define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */
0514 #define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */
0515 #define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */
0516 #define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */
0517 /**
0518   * @}
0519   */
0520 
0521 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
0522   * @ingroup RTEMSBSPsARMSTM32H7
0523   * @{
0524   */
0525 #define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */
0526 #define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */
0527 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
0528 /**
0529   * @}
0530   */
0531 
0532 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
0533   * @ingroup RTEMSBSPsARMSTM32H7
0534   * @{
0535   */
0536 #define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */
0537 #define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */
0538 /**
0539   * @}
0540   */
0541 
0542 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
0543   * @ingroup RTEMSBSPsARMSTM32H7
0544   * @{
0545   */
0546 #define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */
0547 #define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */
0548 #define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */
0549 #define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */
0550 /**
0551   * @}
0552   */
0553 
0554 /** @defgroup TIM_Counter_Mode TIM Counter Mode
0555   * @ingroup RTEMSBSPsARMSTM32H7
0556   * @{
0557   */
0558 #define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */
0559 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */
0560 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */
0561 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */
0562 #define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */
0563 /**
0564   * @}
0565   */
0566 
0567 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
0568   * @ingroup RTEMSBSPsARMSTM32H7
0569   * @{
0570   */
0571 #define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
0572 #define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
0573 /**
0574   * @}
0575   */
0576 
0577 /** @defgroup TIM_ClockDivision TIM Clock Division
0578   * @ingroup RTEMSBSPsARMSTM32H7
0579   * @{
0580   */
0581 #define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
0582 #define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */
0583 #define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */
0584 /**
0585   * @}
0586   */
0587 
0588 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
0589   * @ingroup RTEMSBSPsARMSTM32H7
0590   * @{
0591   */
0592 #define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */
0593 #define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */
0594 /**
0595   * @}
0596   */
0597 
0598 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
0599   * @ingroup RTEMSBSPsARMSTM32H7
0600   * @{
0601   */
0602 #define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */
0603 #define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */
0604 
0605 /**
0606   * @}
0607   */
0608 
0609 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
0610   * @ingroup RTEMSBSPsARMSTM32H7
0611   * @{
0612   */
0613 #define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */
0614 #define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */
0615 /**
0616   * @}
0617   */
0618 
0619 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
0620   * @ingroup RTEMSBSPsARMSTM32H7
0621   * @{
0622   */
0623 #define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */
0624 #define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */
0625 /**
0626   * @}
0627   */
0628 
0629 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
0630   * @ingroup RTEMSBSPsARMSTM32H7
0631   * @{
0632   */
0633 #define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */
0634 #define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */
0635 /**
0636   * @}
0637   */
0638 
0639 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
0640   * @ingroup RTEMSBSPsARMSTM32H7
0641   * @{
0642   */
0643 #define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */
0644 #define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */
0645 /**
0646   * @}
0647   */
0648 
0649 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
0650   * @ingroup RTEMSBSPsARMSTM32H7
0651   * @{
0652   */
0653 #define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */
0654 #define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */
0655 /**
0656   * @}
0657   */
0658 
0659 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
0660   * @ingroup RTEMSBSPsARMSTM32H7
0661   * @{
0662   */
0663 #define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
0664 #define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
0665 /**
0666   * @}
0667   */
0668 
0669 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
0670   * @ingroup RTEMSBSPsARMSTM32H7
0671   * @{
0672   */
0673 #define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */
0674 #define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */
0675 #define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/
0676 /**
0677   * @}
0678   */
0679 
0680 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
0681   * @ingroup RTEMSBSPsARMSTM32H7
0682   * @{
0683   */
0684 #define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
0685 #define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
0686 /**
0687   * @}
0688   */
0689 
0690 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
0691   * @ingroup RTEMSBSPsARMSTM32H7
0692   * @{
0693   */
0694 #define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
0695 #define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
0696 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
0697 /**
0698   * @}
0699   */
0700 
0701 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
0702   * @ingroup RTEMSBSPsARMSTM32H7
0703   * @{
0704   */
0705 #define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */
0706 #define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */
0707 #define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */
0708 #define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */
0709 /**
0710   * @}
0711   */
0712 
0713 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
0714   * @ingroup RTEMSBSPsARMSTM32H7
0715   * @{
0716   */
0717 #define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */
0718 #define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */
0719 /**
0720   * @}
0721   */
0722 
0723 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
0724   * @ingroup RTEMSBSPsARMSTM32H7
0725   * @{
0726   */
0727 #define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */
0728 #define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
0729 #define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
0730 /**
0731   * @}
0732   */
0733 
0734 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
0735   * @ingroup RTEMSBSPsARMSTM32H7
0736   * @{
0737   */
0738 #define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */
0739 #define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */
0740 #define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */
0741 #define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */
0742 #define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */
0743 #define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */
0744 #define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */
0745 #define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */
0746 /**
0747   * @}
0748   */
0749 
0750 /** @defgroup TIM_Commutation_Source  TIM Commutation Source
0751   * @ingroup RTEMSBSPsARMSTM32H7
0752   * @{
0753   */
0754 #define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
0755 #define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
0756 /**
0757   * @}
0758   */
0759 
0760 /** @defgroup TIM_DMA_sources TIM DMA Sources
0761   * @ingroup RTEMSBSPsARMSTM32H7
0762   * @{
0763   */
0764 #define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */
0765 #define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */
0766 #define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */
0767 #define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */
0768 #define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */
0769 #define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */
0770 #define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */
0771 /**
0772   * @}
0773   */
0774 
0775 /** @defgroup TIM_CC_DMA_Request CCx DMA request selection
0776   * @ingroup RTEMSBSPsARMSTM32H7
0777   * @{
0778   */
0779 #define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
0780 #define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
0781 /**
0782   * @}
0783   */
0784 
0785 /** @defgroup TIM_Flag_definition TIM Flag Definition
0786   * @ingroup RTEMSBSPsARMSTM32H7
0787   * @{
0788   */
0789 #define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */
0790 #define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */
0791 #define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */
0792 #define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */
0793 #define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */
0794 #define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */
0795 #define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */
0796 #define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */
0797 #define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */
0798 #define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */
0799 #define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */
0800 #define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */
0801 #define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */
0802 #define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */
0803 #define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */
0804 #define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */
0805 /**
0806   * @}
0807   */
0808 
0809 /** @defgroup TIM_Channel TIM Channel
0810   * @ingroup RTEMSBSPsARMSTM32H7
0811   * @{
0812   */
0813 #define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */
0814 #define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */
0815 #define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */
0816 #define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */
0817 #define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */
0818 #define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */
0819 #define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */
0820 /**
0821   * @}
0822   */
0823 
0824 /** @defgroup TIM_Clock_Source TIM Clock Source
0825   * @ingroup RTEMSBSPsARMSTM32H7
0826   * @{
0827   */
0828 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
0829 #define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
0830 #define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
0831 #define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
0832 #define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
0833 #define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
0834 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
0835 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
0836 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
0837 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
0838 #define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
0839 #define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
0840 #define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
0841 #define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */
0842 #define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */
0843 /**
0844   * @}
0845   */
0846 
0847 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
0848   * @ingroup RTEMSBSPsARMSTM32H7
0849   * @{
0850   */
0851 #define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
0852 #define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
0853 #define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
0854 #define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
0855 #define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
0856 /**
0857   * @}
0858   */
0859 
0860 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
0861   * @ingroup RTEMSBSPsARMSTM32H7
0862   * @{
0863   */
0864 #define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */
0865 #define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
0866 #define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
0867 #define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
0868 /**
0869   * @}
0870   */
0871 
0872 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
0873   * @ingroup RTEMSBSPsARMSTM32H7
0874   * @{
0875   */
0876 #define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */
0877 #define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */
0878 /**
0879   * @}
0880   */
0881 
0882 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
0883   * @ingroup RTEMSBSPsARMSTM32H7
0884   * @{
0885   */
0886 #define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */
0887 #define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
0888 #define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
0889 #define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
0890 /**
0891   * @}
0892   */
0893 
0894 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
0895   * @ingroup RTEMSBSPsARMSTM32H7
0896   * @{
0897   */
0898 #define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
0899 #define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
0900 /**
0901   * @}
0902   */
0903 
0904 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
0905   * @ingroup RTEMSBSPsARMSTM32H7
0906   * @{
0907   */
0908 #define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */
0909 #define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
0910 /**
0911   * @}
0912   */
0913 /** @defgroup TIM_Lock_level  TIM Lock level
0914   * @ingroup RTEMSBSPsARMSTM32H7
0915   * @{
0916   */
0917 #define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */
0918 #define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */
0919 #define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */
0920 #define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */
0921 /**
0922   * @}
0923   */
0924 
0925 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
0926   * @ingroup RTEMSBSPsARMSTM32H7
0927   * @{
0928   */
0929 #define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */
0930 #define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */
0931 /**
0932   * @}
0933   */
0934 
0935 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
0936   * @ingroup RTEMSBSPsARMSTM32H7
0937   * @{
0938   */
0939 #define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */
0940 #define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */
0941 /**
0942   * @}
0943   */
0944 #if  defined(TIM_BDTR_BKBID)
0945 
0946 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
0947   * @ingroup RTEMSBSPsARMSTM32H7
0948   * @{
0949   */
0950 #define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
0951 #define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
0952 /**
0953   * @}
0954   */
0955 #endif /*TIM_BDTR_BKBID */
0956 
0957 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
0958   * @ingroup RTEMSBSPsARMSTM32H7
0959   * @{
0960   */
0961 #define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */
0962 #define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */
0963 /**
0964   * @}
0965   */
0966 
0967 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
0968   * @ingroup RTEMSBSPsARMSTM32H7
0969   * @{
0970   */
0971 #define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */
0972 #define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */
0973 /**
0974   * @}
0975   */
0976 #if defined(TIM_BDTR_BKBID)
0977 
0978 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
0979   * @ingroup RTEMSBSPsARMSTM32H7
0980   * @{
0981   */
0982 #define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
0983 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
0984 /**
0985   * @}
0986   */
0987 #endif /* TIM_BDTR_BKBID */
0988 
0989 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
0990   * @ingroup RTEMSBSPsARMSTM32H7
0991   * @{
0992   */
0993 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
0994 #define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
0995 /**
0996   * @}
0997   */
0998 
0999 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
1000   * @ingroup RTEMSBSPsARMSTM32H7
1001   * @{
1002   */
1003 #define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
1004 #define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
1005 #define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
1006 #define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
1007 /**
1008   * @}
1009   */
1010 
1011 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
1012   * @ingroup RTEMSBSPsARMSTM32H7
1013   * @{
1014   */
1015 #define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */
1016 #define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */
1017 #define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */
1018 #define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
1019 #define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */
1020 #define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */
1021 #define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */
1022 #define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */
1023 /**
1024   * @}
1025   */
1026 
1027 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
1028   * @ingroup RTEMSBSPsARMSTM32H7
1029   * @{
1030   */
1031 #define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */
1032 #define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */
1033 #define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */
1034 #define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
1035 #define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */
1036 #define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */
1037 #define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */
1038 #define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */
1039 #define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */
1040 #define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */
1041 #define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */
1042 #define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */
1043 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */
1044 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
1045 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
1046 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */
1047 /**
1048   * @}
1049   */
1050 
1051 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
1052   * @ingroup RTEMSBSPsARMSTM32H7
1053   * @{
1054   */
1055 #define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */
1056 #define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */
1057 /**
1058   * @}
1059   */
1060 
1061 /** @defgroup TIM_Slave_Mode TIM Slave mode
1062   * @ingroup RTEMSBSPsARMSTM32H7
1063   * @{
1064   */
1065 #define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */
1066 #define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */
1067 #define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */
1068 #define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */
1069 #define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */
1070 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */
1071 /**
1072   * @}
1073   */
1074 
1075 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
1076   * @ingroup RTEMSBSPsARMSTM32H7
1077   * @{
1078   */
1079 #define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */
1080 #define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */
1081 #define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */
1082 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */
1083 #define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */
1084 #define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */
1085 #define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */
1086 #define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */
1087 #define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */
1088 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
1089 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
1090 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
1091 #define TIM_OCMODE_ASYMMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
1092 #define TIM_OCMODE_ASYMMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
1093 /**
1094   * @}
1095   */
1096 
1097 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1098   * @ingroup RTEMSBSPsARMSTM32H7
1099   * @{
1100   */
1101 #define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */
1102 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
1103 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
1104 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
1105 #define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
1106 #define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
1107 #define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
1108 #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
1109 #define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
1110 #define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
1111 #define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
1112 #define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
1113 #define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
1114 #define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
1115 #define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
1116 #define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
1117 #define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
1118 #define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
1119 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
1120 /**
1121   * @}
1122   */
1123 
1124 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1125   * @ingroup RTEMSBSPsARMSTM32H7
1126   * @{
1127   */
1128 #define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */
1129 #define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */
1130 #define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1131 #define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1132 #define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1133 /**
1134   * @}
1135   */
1136 
1137 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1138   * @ingroup RTEMSBSPsARMSTM32H7
1139   * @{
1140   */
1141 #define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */
1142 #define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
1143 #define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
1144 #define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
1145 /**
1146   * @}
1147   */
1148 
1149 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1150   * @ingroup RTEMSBSPsARMSTM32H7
1151   * @{
1152   */
1153 #define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */
1154 #define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1155 /**
1156   * @}
1157   */
1158 
1159 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1160   * @ingroup RTEMSBSPsARMSTM32H7
1161   * @{
1162   */
1163 #define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */
1164 #define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1165 #define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1166 #define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1167 #define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1168 #define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1169 #define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1170 #define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1171 #define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */
1172 #define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1173 #define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1174 #define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1175 #define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1176 #define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1177 #define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1178 #define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1179 #define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1180 #define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
1181 /**
1182   * @}
1183   */
1184 
1185 /** @defgroup DMA_Handle_index TIM DMA Handle Index
1186   * @ingroup RTEMSBSPsARMSTM32H7
1187   * @{
1188   */
1189 #define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */
1190 #define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1191 #define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1192 #define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1193 #define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1194 #define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */
1195 #define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */
1196 /**
1197   * @}
1198   */
1199 
1200 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1201   * @ingroup RTEMSBSPsARMSTM32H7
1202   * @{
1203   */
1204 #define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */
1205 #define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */
1206 #define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */
1207 #define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */
1208 /**
1209   * @}
1210   */
1211 
1212 /** @defgroup TIM_Break_System TIM Break System
1213   * @ingroup RTEMSBSPsARMSTM32H7
1214   * @{
1215   */
1216 #define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */
1217 #define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1218 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
1219 #define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */
1220 /**
1221   * @}
1222   */
1223 
1224 /**
1225   * @}
1226   */
1227 /* End of exported constants -------------------------------------------------*/
1228 
1229 /* Exported macros -----------------------------------------------------------*/
1230 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1231   * @ingroup RTEMSBSPsARMSTM32H7
1232   * @{
1233   */
1234 
1235 /** @brief  Reset TIM handle state.
1236   * @param  __HANDLE__ TIM handle.
1237   * @retval None
1238   */
1239 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1240 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
1241                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
1242                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
1243                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
1244                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
1245                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
1246                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
1247                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
1248                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1249                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1250                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1251                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1252                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
1253                                                       (__HANDLE__)->Base_MspInitCallback         = NULL;            \
1254                                                       (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \
1255                                                       (__HANDLE__)->IC_MspInitCallback           = NULL;            \
1256                                                       (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \
1257                                                       (__HANDLE__)->OC_MspInitCallback           = NULL;            \
1258                                                       (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \
1259                                                       (__HANDLE__)->PWM_MspInitCallback          = NULL;            \
1260                                                       (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \
1261                                                       (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \
1262                                                       (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \
1263                                                       (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \
1264                                                       (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \
1265                                                       (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \
1266                                                       (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \
1267                                                      } while(0)
1268 #else
1269 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \
1270                                                       (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \
1271                                                       (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \
1272                                                       (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \
1273                                                       (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \
1274                                                       (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \
1275                                                       (__HANDLE__)->ChannelState[4]  = HAL_TIM_CHANNEL_STATE_RESET; \
1276                                                       (__HANDLE__)->ChannelState[5]  = HAL_TIM_CHANNEL_STATE_RESET; \
1277                                                       (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1278                                                       (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1279                                                       (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1280                                                       (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1281                                                       (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \
1282                                                      } while(0)
1283 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1284 
1285 /**
1286   * @brief  Enable the TIM peripheral.
1287   * @param  __HANDLE__ TIM handle
1288   * @retval None
1289   */
1290 #define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1291 
1292 /**
1293   * @brief  Enable the TIM main Output.
1294   * @param  __HANDLE__ TIM handle
1295   * @retval None
1296   */
1297 #define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1298 
1299 /**
1300   * @brief  Disable the TIM peripheral.
1301   * @param  __HANDLE__ TIM handle
1302   * @retval None
1303   */
1304 #define __HAL_TIM_DISABLE(__HANDLE__) \
1305   do { \
1306     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1307     { \
1308       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1309       { \
1310         (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1311       } \
1312     } \
1313   } while(0)
1314 
1315 /**
1316   * @brief  Disable the TIM main Output.
1317   * @param  __HANDLE__ TIM handle
1318   * @retval None
1319   * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
1320   *       disabled
1321   */
1322 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1323   do { \
1324     if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1325     { \
1326       if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1327       { \
1328         (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1329       } \
1330     } \
1331   } while(0)
1332 
1333 /**
1334   * @brief  Disable the TIM main Output.
1335   * @param  __HANDLE__ TIM handle
1336   * @retval None
1337   * @note The Main Output Enable of a timer instance is disabled unconditionally
1338   */
1339 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1340 
1341 /** @brief  Enable the specified TIM interrupt.
1342   * @param  __HANDLE__ specifies the TIM Handle.
1343   * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.
1344   *          This parameter can be one of the following values:
1345   *            @arg TIM_IT_UPDATE: Update interrupt
1346   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1347   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1348   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1349   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1350   *            @arg TIM_IT_COM:   Commutation interrupt
1351   *            @arg TIM_IT_TRIGGER: Trigger interrupt
1352   *            @arg TIM_IT_BREAK: Break interrupt
1353   * @retval None
1354   */
1355 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1356 
1357 /** @brief  Disable the specified TIM interrupt.
1358   * @param  __HANDLE__ specifies the TIM Handle.
1359   * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.
1360   *          This parameter can be one of the following values:
1361   *            @arg TIM_IT_UPDATE: Update interrupt
1362   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1363   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1364   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1365   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1366   *            @arg TIM_IT_COM:   Commutation interrupt
1367   *            @arg TIM_IT_TRIGGER: Trigger interrupt
1368   *            @arg TIM_IT_BREAK: Break interrupt
1369   * @retval None
1370   */
1371 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1372 
1373 /** @brief  Enable the specified DMA request.
1374   * @param  __HANDLE__ specifies the TIM Handle.
1375   * @param  __DMA__ specifies the TIM DMA request to enable.
1376   *          This parameter can be one of the following values:
1377   *            @arg TIM_DMA_UPDATE: Update DMA request
1378   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
1379   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
1380   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
1381   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
1382   *            @arg TIM_DMA_COM:   Commutation DMA request
1383   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
1384   * @retval None
1385   */
1386 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
1387 
1388 /** @brief  Disable the specified DMA request.
1389   * @param  __HANDLE__ specifies the TIM Handle.
1390   * @param  __DMA__ specifies the TIM DMA request to disable.
1391   *          This parameter can be one of the following values:
1392   *            @arg TIM_DMA_UPDATE: Update DMA request
1393   *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request
1394   *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request
1395   *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request
1396   *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request
1397   *            @arg TIM_DMA_COM:   Commutation DMA request
1398   *            @arg TIM_DMA_TRIGGER: Trigger DMA request
1399   * @retval None
1400   */
1401 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1402 
1403 /** @brief  Check whether the specified TIM interrupt flag is set or not.
1404   * @param  __HANDLE__ specifies the TIM Handle.
1405   * @param  __FLAG__ specifies the TIM interrupt flag to check.
1406   *        This parameter can be one of the following values:
1407   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
1408   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1409   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1410   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1411   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1412   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1413   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1414   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
1415   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1416   *            @arg TIM_FLAG_BREAK: Break interrupt flag
1417   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1418   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1419   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1420   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1421   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1422   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1423   * @retval The new state of __FLAG__ (TRUE or FALSE).
1424   */
1425 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1426 
1427 /** @brief  Clear the specified TIM interrupt flag.
1428   * @param  __HANDLE__ specifies the TIM Handle.
1429   * @param  __FLAG__ specifies the TIM interrupt flag to clear.
1430   *        This parameter can be one of the following values:
1431   *            @arg TIM_FLAG_UPDATE: Update interrupt flag
1432   *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1433   *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1434   *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1435   *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1436   *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1437   *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1438   *            @arg TIM_FLAG_COM:  Commutation interrupt flag
1439   *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1440   *            @arg TIM_FLAG_BREAK: Break interrupt flag
1441   *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1442   *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1443   *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1444   *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1445   *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1446   *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1447   * @retval The new state of __FLAG__ (TRUE or FALSE).
1448   */
1449 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1450 
1451 /**
1452   * @brief  Check whether the specified TIM interrupt source is enabled or not.
1453   * @param  __HANDLE__ TIM handle
1454   * @param  __INTERRUPT__ specifies the TIM interrupt source to check.
1455   *          This parameter can be one of the following values:
1456   *            @arg TIM_IT_UPDATE: Update interrupt
1457   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1458   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1459   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1460   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1461   *            @arg TIM_IT_COM:   Commutation interrupt
1462   *            @arg TIM_IT_TRIGGER: Trigger interrupt
1463   *            @arg TIM_IT_BREAK: Break interrupt
1464   * @retval The state of TIM_IT (SET or RESET).
1465   */
1466 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1467                                                              == (__INTERRUPT__)) ? SET : RESET)
1468 
1469 /** @brief Clear the TIM interrupt pending bits.
1470   * @param  __HANDLE__ TIM handle
1471   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
1472   *          This parameter can be one of the following values:
1473   *            @arg TIM_IT_UPDATE: Update interrupt
1474   *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt
1475   *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt
1476   *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt
1477   *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt
1478   *            @arg TIM_IT_COM:   Commutation interrupt
1479   *            @arg TIM_IT_TRIGGER: Trigger interrupt
1480   *            @arg TIM_IT_BREAK: Break interrupt
1481   * @retval None
1482   */
1483 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1484 
1485 /**
1486   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1487   * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
1488   *       in an atomic way.
1489   * @param  __HANDLE__ TIM handle.
1490   * @retval None
1491 mode.
1492   */
1493 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
1494 
1495 /**
1496   * @brief  Disable update interrupt flag (UIF) remapping.
1497   * @param  __HANDLE__ TIM handle.
1498   * @retval None
1499 mode.
1500   */
1501 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
1502 
1503 /**
1504   * @brief  Get update interrupt flag (UIF) copy status.
1505   * @param  __COUNTER__ Counter value.
1506   * @retval The state of UIFCPY (TRUE or FALSE).
1507 mode.
1508   */
1509 #define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
1510 
1511 /**
1512   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
1513   * @param  __HANDLE__ TIM handle.
1514   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1515   * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
1516   *       or Encoder mode.
1517   */
1518 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1519 
1520 /**
1521   * @brief  Set the TIM Prescaler on runtime.
1522   * @param  __HANDLE__ TIM handle.
1523   * @param  __PRESC__ specifies the Prescaler new value.
1524   * @retval None
1525   */
1526 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))
1527 
1528 /**
1529   * @brief  Set the TIM Counter Register value on runtime.
1530   * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
1531   *      case of 32 bits counter TIM instance.
1532   *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
1533   * @param  __HANDLE__ TIM handle.
1534   * @param  __COUNTER__ specifies the Counter register new value.
1535   * @retval None
1536   */
1537 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1538 
1539 /**
1540   * @brief  Get the TIM Counter Register value on runtime.
1541   * @param  __HANDLE__ TIM handle.
1542   * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1543   */
1544 #define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)
1545 
1546 /**
1547   * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1548   * @param  __HANDLE__ TIM handle.
1549   * @param  __AUTORELOAD__ specifies the Counter register new value.
1550   * @retval None
1551   */
1552 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1553   do{                                                    \
1554     (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
1555     (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
1556   } while(0)
1557 
1558 /**
1559   * @brief  Get the TIM Autoreload Register value on runtime.
1560   * @param  __HANDLE__ TIM handle.
1561   * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1562   */
1563 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)
1564 
1565 /**
1566   * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.
1567   * @param  __HANDLE__ TIM handle.
1568   * @param  __CKD__ specifies the clock division value.
1569   *          This parameter can be one of the following value:
1570   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1571   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1572   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1573   * @retval None
1574   */
1575 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1576   do{                                                   \
1577     (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \
1578     (__HANDLE__)->Instance->CR1 |= (__CKD__);       \
1579     (__HANDLE__)->Init.ClockDivision = (__CKD__);   \
1580   } while(0)
1581 
1582 /**
1583   * @brief  Get the TIM Clock Division value on runtime.
1584   * @param  __HANDLE__ TIM handle.
1585   * @retval The clock division can be one of the following values:
1586   *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1587   *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1588   *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1589   */
1590 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1591 
1592 /**
1593   * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
1594   *         function.
1595   * @param  __HANDLE__ TIM handle.
1596   * @param  __CHANNEL__ TIM Channels to be configured.
1597   *          This parameter can be one of the following values:
1598   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1599   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1600   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1601   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1602   * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.
1603   *          This parameter can be one of the following values:
1604   *            @arg TIM_ICPSC_DIV1: no prescaler
1605   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1606   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1607   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1608   * @retval None
1609   */
1610 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1611   do{                                                    \
1612     TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \
1613     TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1614   } while(0)
1615 
1616 /**
1617   * @brief  Get the TIM Input Capture prescaler on runtime.
1618   * @param  __HANDLE__ TIM handle.
1619   * @param  __CHANNEL__ TIM Channels to be configured.
1620   *          This parameter can be one of the following values:
1621   *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1622   *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1623   *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1624   *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1625   * @retval The input capture prescaler can be one of the following values:
1626   *            @arg TIM_ICPSC_DIV1: no prescaler
1627   *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1628   *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1629   *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1630   */
1631 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \
1632   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1633    ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1634    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1635    (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1636 
1637 /**
1638   * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1639   * @param  __HANDLE__ TIM handle.
1640   * @param  __CHANNEL__ TIM Channels to be configured.
1641   *          This parameter can be one of the following values:
1642   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1643   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1644   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1645   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1646   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1647   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1648   * @param  __COMPARE__ specifies the Capture Compare register new value.
1649   * @retval None
1650   */
1651 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1652   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1653    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1654    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1655    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1656    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1657    ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1658 
1659 /**
1660   * @brief  Get the TIM Capture Compare Register value on runtime.
1661   * @param  __HANDLE__ TIM handle.
1662   * @param  __CHANNEL__ TIM Channel associated with the capture compare register
1663   *          This parameter can be one of the following values:
1664   *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
1665   *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
1666   *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
1667   *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
1668   *            @arg TIM_CHANNEL_5: get capture/compare 5 register value
1669   *            @arg TIM_CHANNEL_6: get capture/compare 6 register value
1670   * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1671   */
1672 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1673   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1674    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1675    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1676    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1677    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1678    ((__HANDLE__)->Instance->CCR6))
1679 
1680 /**
1681   * @brief  Set the TIM Output compare preload.
1682   * @param  __HANDLE__ TIM handle.
1683   * @param  __CHANNEL__ TIM Channels to be configured.
1684   *          This parameter can be one of the following values:
1685   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1686   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1687   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1688   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1689   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1690   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1691   * @retval None
1692   */
1693 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1694   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1695    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1696    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1697    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1698    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1699    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1700 
1701 /**
1702   * @brief  Reset the TIM Output compare preload.
1703   * @param  __HANDLE__ TIM handle.
1704   * @param  __CHANNEL__ TIM Channels to be configured.
1705   *          This parameter can be one of the following values:
1706   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1707   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1708   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1709   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1710   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1711   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1712   * @retval None
1713   */
1714 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
1715   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1716    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1717    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1718    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
1719    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
1720    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
1721 
1722 /**
1723   * @brief  Enable fast mode for a given channel.
1724   * @param  __HANDLE__ TIM handle.
1725   * @param  __CHANNEL__ TIM Channels to be configured.
1726   *          This parameter can be one of the following values:
1727   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1728   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1729   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1730   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1731   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1732   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1733   * @note  When fast mode is enabled an active edge on the trigger input acts
1734   *        like a compare match on CCx output. Delay to sample the trigger
1735   *        input and to activate CCx output is reduced to 3 clock cycles.
1736   * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
1737   * @retval None
1738   */
1739 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
1740   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1741    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1742    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1743    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
1744    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
1745    ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
1746 
1747 /**
1748   * @brief  Disable fast mode for a given channel.
1749   * @param  __HANDLE__ TIM handle.
1750   * @param  __CHANNEL__ TIM Channels to be configured.
1751   *          This parameter can be one of the following values:
1752   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1753   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1754   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1755   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1756   *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
1757   *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
1758   * @note  When fast mode is disabled CCx output behaves normally depending
1759   *        on counter and CCRx values even when the trigger is ON. The minimum
1760   *        delay to activate CCx output when an active edge occurs on the
1761   *        trigger input is 5 clock cycles.
1762   * @retval None
1763   */
1764 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
1765   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1766    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1767    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1768    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
1769    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
1770    ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
1771 
1772 /**
1773   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1774   * @param  __HANDLE__ TIM handle.
1775   * @note  When the URS bit of the TIMx_CR1 register is set, only counter
1776   *        overflow/underflow generates an update interrupt or DMA request (if
1777   *        enabled)
1778   * @retval None
1779   */
1780 #define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1781 
1782 /**
1783   * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1784   * @param  __HANDLE__ TIM handle.
1785   * @note  When the URS bit of the TIMx_CR1 register is reset, any of the
1786   *        following events generate an update interrupt or DMA request (if
1787   *        enabled):
1788   *           _ Counter overflow underflow
1789   *           _ Setting the UG bit
1790   *           _ Update generation through the slave mode controller
1791   * @retval None
1792   */
1793 #define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1794 
1795 /**
1796   * @brief  Set the TIM Capture x input polarity on runtime.
1797   * @param  __HANDLE__ TIM handle.
1798   * @param  __CHANNEL__ TIM Channels to be configured.
1799   *          This parameter can be one of the following values:
1800   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1801   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1802   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1803   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
1804   * @param  __POLARITY__ Polarity for TIx source
1805   *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1806   *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1807   *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1808   * @retval None
1809   */
1810 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \
1811   do{                                                                     \
1812     TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \
1813     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1814   }while(0)
1815 
1816 /** @brief  Select the Capture/compare DMA request source.
1817   * @param  __HANDLE__ specifies the TIM Handle.
1818   * @param  __CCDMA__ specifies Capture/compare DMA request source
1819   *          This parameter can be one of the following values:
1820   *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
1821   *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
1822   * @retval None
1823   */
1824 #define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
1825   MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
1826 
1827 /**
1828   * @}
1829   */
1830 /* End of exported macros ----------------------------------------------------*/
1831 
1832 /* Private constants ---------------------------------------------------------*/
1833 /** @defgroup TIM_Private_Constants TIM Private Constants
1834   * @ingroup RTEMSBSPsARMSTM32H7
1835   * @{
1836   */
1837 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1838    channels have been disabled */
1839 #define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1840 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1841 /**
1842   * @}
1843   */
1844 /* End of private constants --------------------------------------------------*/
1845 
1846 /* Private macros ------------------------------------------------------------*/
1847 /** @defgroup TIM_Private_Macros TIM Private Macros
1848   * @ingroup RTEMSBSPsARMSTM32H7
1849   * @{
1850   */
1851 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \
1852                                              ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1853 
1854 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \
1855                                    ((__BASE__) == TIM_DMABASE_CR2)   || \
1856                                    ((__BASE__) == TIM_DMABASE_SMCR)  || \
1857                                    ((__BASE__) == TIM_DMABASE_DIER)  || \
1858                                    ((__BASE__) == TIM_DMABASE_SR)    || \
1859                                    ((__BASE__) == TIM_DMABASE_EGR)   || \
1860                                    ((__BASE__) == TIM_DMABASE_CCMR1) || \
1861                                    ((__BASE__) == TIM_DMABASE_CCMR2) || \
1862                                    ((__BASE__) == TIM_DMABASE_CCER)  || \
1863                                    ((__BASE__) == TIM_DMABASE_CNT)   || \
1864                                    ((__BASE__) == TIM_DMABASE_PSC)   || \
1865                                    ((__BASE__) == TIM_DMABASE_ARR)   || \
1866                                    ((__BASE__) == TIM_DMABASE_RCR)   || \
1867                                    ((__BASE__) == TIM_DMABASE_CCR1)  || \
1868                                    ((__BASE__) == TIM_DMABASE_CCR2)  || \
1869                                    ((__BASE__) == TIM_DMABASE_CCR3)  || \
1870                                    ((__BASE__) == TIM_DMABASE_CCR4)  || \
1871                                    ((__BASE__) == TIM_DMABASE_BDTR)  || \
1872                                    ((__BASE__) == TIM_DMABASE_CCMR3) || \
1873                                    ((__BASE__) == TIM_DMABASE_CCR5)  || \
1874                                    ((__BASE__) == TIM_DMABASE_CCR6)  || \
1875                                    ((__BASE__) == TIM_DMABASE_AF1)   || \
1876                                    ((__BASE__) == TIM_DMABASE_AF2)   || \
1877                                    ((__BASE__) == TIM_DMABASE_TISEL))
1878 
1879 
1880 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1881 
1882 #define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \
1883                                             ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \
1884                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
1885                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
1886                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1887 
1888 #define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
1889                                             ((__MODE__) == TIM_UIFREMAP_ENABLE))
1890 
1891 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1892                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1893                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1894 
1895 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1896                                             ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1897 
1898 #define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \
1899                                             ((__STATE__) == TIM_OCFAST_ENABLE))
1900 
1901 #define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1902                                             ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1903 
1904 #define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1905                                             ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1906 
1907 #define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1908                                             ((__STATE__) == TIM_OCIDLESTATE_RESET))
1909 
1910 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1911                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1912 
1913 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
1914                                                       ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1915 
1916 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
1917                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
1918                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1919 
1920 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1921                                             ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1922                                             ((__SELECTION__) == TIM_ICSELECTION_TRC))
1923 
1924 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1925                                             ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1926                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1927                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
1928 
1929 #define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
1930                                                        ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
1931                                                        ((__CHANNEL__) != (TIM_CHANNEL_6)))
1932 
1933 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
1934                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
1935 
1936 #define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1937                                             ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1938                                             ((__MODE__) == TIM_ENCODERMODE_TI12))
1939 
1940 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1941 
1942 #define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \
1943                                             ((__CHANNEL__) == TIM_CHANNEL_2) || \
1944                                             ((__CHANNEL__) == TIM_CHANNEL_3) || \
1945                                             ((__CHANNEL__) == TIM_CHANNEL_4) || \
1946                                             ((__CHANNEL__) == TIM_CHANNEL_5) || \
1947                                             ((__CHANNEL__) == TIM_CHANNEL_6) || \
1948                                             ((__CHANNEL__) == TIM_CHANNEL_ALL))
1949 
1950 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
1951                                             ((__CHANNEL__) == TIM_CHANNEL_2))
1952 
1953 #define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
1954                                                (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
1955                                                ((__PERIOD__) > 0U))
1956 
1957 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1958                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
1959                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
1960 
1961 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1962                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1963                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1964                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
1965                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
1966                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
1967                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
1968                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
1969                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
1970                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
1971 
1972 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
1973                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1974                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \
1975                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \
1976                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1977 
1978 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1979                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1980                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1981                                               ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1982 
1983 #define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)
1984 
1985 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1986                                                   ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1987 
1988 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1989                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1990                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1991                                                     ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1992 
1993 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1994 
1995 #define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \
1996                                             ((__STATE__) == TIM_OSSR_DISABLE))
1997 
1998 #define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \
1999                                             ((__STATE__) == TIM_OSSI_DISABLE))
2000 
2001 #define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
2002                                             ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \
2003                                             ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \
2004                                             ((__LEVEL__) == TIM_LOCKLEVEL_3))
2005 
2006 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
2007 
2008 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
2009                                             ((__STATE__) == TIM_BREAK_DISABLE))
2010 
2011 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
2012                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
2013 #if  defined(TIM_BDTR_BKBID)
2014 
2015 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
2016                                          ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
2017 
2018 #endif /* TIM_BDTR_BKBID */
2019 
2020 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
2021                                             ((__STATE__) == TIM_BREAK2_DISABLE))
2022 
2023 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
2024                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
2025 #if  defined(TIM_BDTR_BKBID)
2026 
2027 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
2028                                           ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
2029 
2030 #endif /* TIM_BDTR_BKBID */
2031 
2032 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
2033                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
2034 
2035 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
2036 
2037 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \
2038                                         ((__SOURCE__) == TIM_TRGO_ENABLE) || \
2039                                         ((__SOURCE__) == TIM_TRGO_UPDATE) || \
2040                                         ((__SOURCE__) == TIM_TRGO_OC1)    || \
2041                                         ((__SOURCE__) == TIM_TRGO_OC1REF) || \
2042                                         ((__SOURCE__) == TIM_TRGO_OC2REF) || \
2043                                         ((__SOURCE__) == TIM_TRGO_OC3REF) || \
2044                                         ((__SOURCE__) == TIM_TRGO_OC4REF))
2045 
2046 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \
2047                                          ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \
2048                                          ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \
2049                                          ((__SOURCE__) == TIM_TRGO2_OC1)                          || \
2050                                          ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \
2051                                          ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \
2052                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
2053                                          ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \
2054                                          ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \
2055                                          ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \
2056                                          ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \
2057                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \
2058                                          ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \
2059                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \
2060                                          ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
2061                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \
2062                                          ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
2063 
2064 #define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
2065                                           ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
2066 
2067 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \
2068                                      ((__MODE__) == TIM_SLAVEMODE_RESET)     || \
2069                                      ((__MODE__) == TIM_SLAVEMODE_GATED)     || \
2070                                      ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \
2071                                      ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
2072                                      ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2073 
2074 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \
2075                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
2076                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
2077                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
2078                                    ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
2079                                    ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
2080 
2081 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
2082                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
2083                                    ((__MODE__) == TIM_OCMODE_INACTIVE)           || \
2084                                    ((__MODE__) == TIM_OCMODE_TOGGLE)             || \
2085                                    ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \
2086                                    ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \
2087                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
2088                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
2089 
2090 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
2091                                                  ((__SELECTION__) == TIM_TS_ITR1)    || \
2092                                                  ((__SELECTION__) == TIM_TS_ITR2)    || \
2093                                                  ((__SELECTION__) == TIM_TS_ITR3)    || \
2094                                                  ((__SELECTION__) == TIM_TS_ITR4)    || \
2095                                                  ((__SELECTION__) == TIM_TS_ITR5)    || \
2096                                                  ((__SELECTION__) == TIM_TS_ITR6)    || \
2097                                                  ((__SELECTION__) == TIM_TS_ITR7)    || \
2098                                                  ((__SELECTION__) == TIM_TS_ITR8)    || \
2099                                                  ((__SELECTION__) == TIM_TS_ITR12)   || \
2100                                                  ((__SELECTION__) == TIM_TS_ITR13)   || \
2101                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2102                                                  ((__SELECTION__) == TIM_TS_TI1FP1)  || \
2103                                                  ((__SELECTION__) == TIM_TS_TI2FP2)  || \
2104                                                  ((__SELECTION__) == TIM_TS_ETRF))
2105 
2106 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)  || \
2107                                                                ((__SELECTION__) == TIM_TS_ITR1)  || \
2108                                                                ((__SELECTION__) == TIM_TS_ITR2)  || \
2109                                                                ((__SELECTION__) == TIM_TS_ITR3)  || \
2110                                                                ((__SELECTION__) == TIM_TS_ITR4)  || \
2111                                                                ((__SELECTION__) == TIM_TS_ITR5)  || \
2112                                                                ((__SELECTION__) == TIM_TS_ITR6)  || \
2113                                                                ((__SELECTION__) == TIM_TS_ITR7)  || \
2114                                                                ((__SELECTION__) == TIM_TS_ITR8)  || \
2115                                                                ((__SELECTION__) == TIM_TS_ITR12) || \
2116                                                                ((__SELECTION__) == TIM_TS_ITR13) || \
2117                                                                ((__SELECTION__) == TIM_TS_NONE))
2118 
2119 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
2120                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
2121                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \
2122                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \
2123                                                 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
2124 
2125 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
2126                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
2127                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
2128                                                 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
2129 
2130 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2131 
2132 #define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
2133                                                 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2134 
2135 #define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \
2136                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \
2137                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \
2138                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \
2139                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \
2140                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \
2141                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \
2142                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \
2143                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \
2144                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2145                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2146                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2147                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2148                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2149                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2150                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2151                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2152                                             ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
2153 
2154 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2155 
2156 #define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
2157 
2158 #define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)
2159 
2160 #define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \
2161                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \
2162                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \
2163                                             ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2164 
2165 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2166                                                        ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2167 
2168 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2169   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2170    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2171    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2172    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2173 
2174 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2175   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
2176    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
2177    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
2178    ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
2179 
2180 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2181   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2182    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2183    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2184    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2185 
2186 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2187   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2188    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2189    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2190    ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2191 
2192 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
2193   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
2194    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
2195    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
2196    ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
2197    ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
2198    (__HANDLE__)->ChannelState[5])
2199 
2200 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2201   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
2202    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
2203    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
2204    ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
2205    ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
2206    ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
2207 
2208 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
2209                                                                        (__HANDLE__)->ChannelState[0]  = \
2210                                                                        (__CHANNEL_STATE__);  \
2211                                                                        (__HANDLE__)->ChannelState[1]  = \
2212                                                                        (__CHANNEL_STATE__);  \
2213                                                                        (__HANDLE__)->ChannelState[2]  = \
2214                                                                        (__CHANNEL_STATE__);  \
2215                                                                        (__HANDLE__)->ChannelState[3]  = \
2216                                                                        (__CHANNEL_STATE__);  \
2217                                                                        (__HANDLE__)->ChannelState[4]  = \
2218                                                                        (__CHANNEL_STATE__);  \
2219                                                                        (__HANDLE__)->ChannelState[5]  = \
2220                                                                        (__CHANNEL_STATE__);  \
2221                                                                      } while(0)
2222 
2223 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
2224   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
2225    ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
2226    ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
2227    (__HANDLE__)->ChannelNState[3])
2228 
2229 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
2230   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
2231    ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
2232    ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
2233    ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
2234 
2235 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
2236                                                                          (__HANDLE__)->ChannelNState[0] = \
2237                                                                          (__CHANNEL_STATE__);  \
2238                                                                          (__HANDLE__)->ChannelNState[1] = \
2239                                                                          (__CHANNEL_STATE__);  \
2240                                                                          (__HANDLE__)->ChannelNState[2] = \
2241                                                                          (__CHANNEL_STATE__);  \
2242                                                                          (__HANDLE__)->ChannelNState[3] = \
2243                                                                          (__CHANNEL_STATE__);  \
2244                                                                        } while(0)
2245 
2246 /**
2247   * @}
2248   */
2249 /* End of private macros -----------------------------------------------------*/
2250 
2251 /* Include TIM HAL Extended module */
2252 #include "stm32h7xx_hal_tim_ex.h"
2253 
2254 /* Exported functions --------------------------------------------------------*/
2255 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
2256   * @{
2257   */
2258 
2259 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2260   *  @brief   Time Base functions
2261   * @{
2262   */
2263 /* Time Base functions ********************************************************/
2264 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2265 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2266 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2267 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2268 /* Blocking mode: Polling */
2269 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2270 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2271 /* Non-Blocking mode: Interrupt */
2272 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2273 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2274 /* Non-Blocking mode: DMA */
2275 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
2276 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2277 /**
2278   * @}
2279   */
2280 
2281 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2282   *  @brief   TIM Output Compare functions
2283   * @{
2284   */
2285 /* Timer Output Compare functions *********************************************/
2286 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2287 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2288 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2289 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2290 /* Blocking mode: Polling */
2291 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2292 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2293 /* Non-Blocking mode: Interrupt */
2294 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2295 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2296 /* Non-Blocking mode: DMA */
2297 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2298                                        uint16_t Length);
2299 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2300 /**
2301   * @}
2302   */
2303 
2304 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2305   *  @brief   TIM PWM functions
2306   * @{
2307   */
2308 /* Timer PWM functions ********************************************************/
2309 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2310 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2311 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2312 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2313 /* Blocking mode: Polling */
2314 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2315 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2316 /* Non-Blocking mode: Interrupt */
2317 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2318 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2319 /* Non-Blocking mode: DMA */
2320 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
2321                                         uint16_t Length);
2322 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2323 /**
2324   * @}
2325   */
2326 
2327 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2328   *  @brief   TIM Input Capture functions
2329   * @{
2330   */
2331 /* Timer Input Capture functions **********************************************/
2332 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2333 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2334 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2335 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2336 /* Blocking mode: Polling */
2337 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2338 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2339 /* Non-Blocking mode: Interrupt */
2340 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2341 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2342 /* Non-Blocking mode: DMA */
2343 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2344 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2345 /**
2346   * @}
2347   */
2348 
2349 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2350   *  @brief   TIM One Pulse functions
2351   * @{
2352   */
2353 /* Timer One Pulse functions **************************************************/
2354 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2355 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2356 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2357 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2358 /* Blocking mode: Polling */
2359 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2360 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2361 /* Non-Blocking mode: Interrupt */
2362 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2363 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2364 /**
2365   * @}
2366   */
2367 
2368 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2369   *  @brief   TIM Encoder functions
2370   * @{
2371   */
2372 /* Timer Encoder functions ****************************************************/
2373 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
2374 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2375 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2376 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2377 /* Blocking mode: Polling */
2378 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2379 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2380 /* Non-Blocking mode: Interrupt */
2381 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2382 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2383 /* Non-Blocking mode: DMA */
2384 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2385                                             uint32_t *pData2, uint16_t Length);
2386 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2387 /**
2388   * @}
2389   */
2390 
2391 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2392   *  @brief   IRQ handler management
2393   * @{
2394   */
2395 /* Interrupt Handler functions  ***********************************************/
2396 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2397 /**
2398   * @}
2399   */
2400 
2401 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2402   * @ingroup RTEMSBSPsARMSTM32H7
2403   *  @brief   Peripheral Control functions
2404   * @{
2405   */
2406 /* Control functions  *********************************************************/
2407 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2408                                            uint32_t Channel);
2409 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
2410                                             uint32_t Channel);
2411 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
2412                                            uint32_t Channel);
2413 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2414                                                  uint32_t OutputChannel,  uint32_t InputChannel);
2415 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
2416                                            const TIM_ClearInputConfigTypeDef *sClearInputConfig,
2417                                            uint32_t Channel);
2418 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
2419 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2420 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2421 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
2422 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2423                                               uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
2424                                               uint32_t  BurstLength);
2425 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2426                                                    uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
2427                                                    uint32_t BurstLength,  uint32_t DataLength);
2428 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2429 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2430                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
2431 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2432                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
2433                                                   uint32_t  BurstLength, uint32_t  DataLength);
2434 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2435 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2436 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
2437 /**
2438   * @}
2439   */
2440 
2441 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2442   * @ingroup RTEMSBSPsARMSTM32H7
2443   *  @brief   TIM Callbacks functions
2444   * @{
2445   */
2446 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2447 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2448 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2449 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2450 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2451 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2452 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2453 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2454 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2455 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2456 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2457 
2458 /* Callbacks Register/UnRegister functions  ***********************************/
2459 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2460 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2461                                            pTIM_CallbackTypeDef pCallback);
2462 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2463 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2464 
2465 /**
2466   * @}
2467   */
2468 
2469 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2470   * @ingroup RTEMSBSPsARMSTM32H7
2471   *  @brief  Peripheral State functions
2472   * @{
2473   */
2474 /* Peripheral State functions  ************************************************/
2475 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
2476 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
2477 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
2478 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
2479 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
2480 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
2481 
2482 /* Peripheral Channel state functions  ************************************************/
2483 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
2484 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
2485 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
2486 /**
2487   * @}
2488   */
2489 
2490 /**
2491   * @}
2492   */
2493 /* End of exported functions -------------------------------------------------*/
2494 
2495 /* Private functions----------------------------------------------------------*/
2496 /** @defgroup TIM_Private_Functions TIM Private Functions
2497   * @ingroup RTEMSBSPsARMSTM32H7
2498   * @{
2499   */
2500 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
2501 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2502 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
2503 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2504                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2505 
2506 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2507 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2508 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2509 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2510 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2511 
2512 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2513 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2514 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2515 
2516 /**
2517   * @}
2518   */
2519 /* End of private functions --------------------------------------------------*/
2520 
2521 /**
2522   * @}
2523   */
2524 
2525 /**
2526   * @}
2527   */
2528 
2529 #ifdef __cplusplus
2530 }
2531 #endif
2532 
2533 #endif /* STM32H7xx_HAL_TIM_H */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.3.7 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!