stm32h7/include/stm32h7xx_hal_sram.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_sram.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of SRAM HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_SRAM_H
0021 #define STM32H7xx_HAL_SRAM_H
0022
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026
0027
0028 /* Includes ------------------------------------------------------------------*/
0029 #include "stm32h7xx_ll_fmc.h"
0030
0031 /** @addtogroup STM32H7xx_HAL_Driver
0032   * @{
0033   */
0034 /** @addtogroup SRAM
0035   * @{
0036   */
0037
0038 /* Exported typedef ----------------------------------------------------------*/
0039
0040 /** @defgroup SRAM_Exported_Types SRAM Exported Types
0041   * @ingroup RTEMSBSPsARMSTM32H7
0042   * @{
0043   */
0044 /**
0045   * @brief  HAL SRAM State structures definition
0046   */
0047 typedef enum
0048 {
0049   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
0050   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
0051   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
0052   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
0053   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
0054
0055 } HAL_SRAM_StateTypeDef;
0056
0057 /**
0058   * @brief  SRAM handle Structure definition
0059   */
0060 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
0061 typedef struct __SRAM_HandleTypeDef
0062 #else
0063 typedef struct
0064 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
0065 {
0066   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
0067
0068   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
0069
0070   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
0071
0072   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
0073
0074   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
0075
0076   MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                          */
0077
0078 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
0079   void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
0080   void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
0081   void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma);                      /*!< SRAM DMA Xfer Complete callback     */
0082   void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma);                     /*!< SRAM DMA Xfer Error callback        */
0083 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
0084 } SRAM_HandleTypeDef;
0085
0086 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
0087 /**
0088   * @brief  HAL SRAM Callback ID enumeration definition
0089   */
0090 typedef enum
0091 {
0092   HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
0093   HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
0094   HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
0095   HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
0096 } HAL_SRAM_CallbackIDTypeDef;
0097
0098 /**
0099   * @brief  HAL SRAM Callback pointer definition
0100   */
0101 typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
0102 typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);
0103 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
0104 /**
0105   * @}
0106   */
0107
0108 /* Exported constants --------------------------------------------------------*/
0109 /* Exported macro ------------------------------------------------------------*/
0110
0111 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
0112   * @ingroup RTEMSBSPsARMSTM32H7
0113   * @{
0114   */
0115
0116 /** @brief Reset SRAM handle state
0117   * @param  __HANDLE__ SRAM handle
0118   * @retval None
0119   */
0120 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
0121 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
0122                                                                (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
0123                                                                (__HANDLE__)->MspInitCallback = NULL;       \
0124                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
0125                                                              } while(0)
0126 #else
0127 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
0128 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
0129
0130 /**
0131   * @}
0132   */
0133
0134 /* Exported functions --------------------------------------------------------*/
0135 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
0136   * @{
0137   */
0138
0139 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
0140   * @{
0141   */
0142
0143 /* Initialization/de-initialization functions  ********************************/
0144 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
0145                                 FMC_NORSRAM_TimingTypeDef *ExtTiming);
0146 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
0147 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
0148 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
0149
0150 /**
0151   * @}
0152   */
0153
0154 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
0155   * @{
0156   */
0157
0158 /* I/O operation functions  ***************************************************/
0159 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
0160                                    uint32_t BufferSize);
0161 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
0162                                     uint32_t BufferSize);
0163 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
0164                                     uint32_t BufferSize);
0165 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
0166                                      uint32_t BufferSize);
0167 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
0168                                     uint32_t BufferSize);
0169 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0170                                      uint32_t BufferSize);
0171 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
0172                                     uint32_t BufferSize);
0173 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
0174                                      uint32_t BufferSize);
0175
0176 void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
0177 void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
0178
0179 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
0180 /* SRAM callback registering/unregistering */
0181 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
0182                                             pSRAM_CallbackTypeDef pCallback);
0183 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
0184 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
0185                                                pSRAM_DmaCallbackTypeDef pCallback);
0186 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
0187
0188 /**
0189   * @}
0190   */
0191
0192 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
0193   * @{
0194   */
0195
0196 /* SRAM Control functions  ****************************************************/
0197 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
0198 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
0199
0200 /**
0201   * @}
0202   */
0203
0204 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
0205   * @{
0206   */
0207
0208 /* SRAM  State functions ******************************************************/
0209 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
0210
0211 /**
0212   * @}
0213   */
0214
0215 /**
0216   * @}
0217   */
0218
0219 /**
0220   * @}
0221   */
0222
0223 /**
0224   * @}
0225   */
0226
0227
0228 #ifdef __cplusplus
0229 }
0230 #endif
0231
0232 #endif /* STM32H7xx_HAL_SRAM_H */