Back to home page

LXR
 
 

    

File indexing completed on 2025-05-11 08:23:36 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_pwr_ex.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of PWR HAL Extension module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_PWR_EX_H
0021 #define STM32H7xx_HAL_PWR_EX_H
0022 
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif /* __cplusplus */
0026 
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029 
0030 /** @addtogroup STM32H7xx_HAL_Driver
0031   * @{
0032   */
0033 
0034 /** @addtogroup PWREx
0035   * @{
0036   */
0037 
0038 /* Exported types ------------------------------------------------------------*/
0039 /** @defgroup PWREx_Exported_Types PWREx Exported Types
0040   * @ingroup RTEMSBSPsARMSTM32H7
0041   * @{
0042   */
0043 /**
0044   * @brief  PWREx AVD configuration structure definition
0045   */
0046 typedef struct
0047 {
0048   uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
0049                                      parameter can be a value of @ref
0050                                      PWREx_AVD_detection_level
0051                      */
0052 
0053   uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
0054                                  event. This parameter can be a value of @ref
0055                                  PWREx_AVD_Mode.
0056                      */
0057 }PWREx_AVDTypeDef;
0058 
0059 /**
0060   * @brief  PWREx Wakeup pin configuration structure definition
0061   */
0062 typedef struct
0063 {
0064   uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
0065                                         This parameter can be a value of @ref
0066                                         PWREx_WakeUp_Pins
0067                         */
0068 
0069   uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
0070                                           This parameter can be a value of @ref
0071                                           PWREx_PIN_Polarity
0072                         */
0073 
0074   uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
0075                                       parameter can be a value of @ref
0076                                       PWREx_PIN_Pull
0077                         */
0078 }PWREx_WakeupPinTypeDef;
0079 
0080 #if defined (PWR_CSR1_MMCVDO)
0081 /**
0082   * @brief  PWR VDDMMC voltage level enum definition
0083   */
0084 typedef enum
0085 {
0086   PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
0087   PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
0088 } PWREx_MMC_VoltageLevel;
0089 #endif /* defined (PWR_CSR1_MMCVDO) */
0090 
0091 /**
0092   * @}
0093   */
0094 
0095 /* Exported constants --------------------------------------------------------*/
0096 
0097 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
0098   * @ingroup RTEMSBSPsARMSTM32H7
0099   * @{
0100   */
0101 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
0102   * @ingroup RTEMSBSPsARMSTM32H7
0103   * @{
0104   */
0105 /* High level and No pull (default configuration) */
0106 #define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
0107 #if defined (PWR_WKUPEPR_WKUPEN5)
0108 #define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
0109 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */
0110 #define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
0111 #if defined (PWR_WKUPEPR_WKUPEN3)
0112 #define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
0113 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
0114 #define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
0115 #define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
0116 
0117 /* High level and No pull */
0118 #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
0119 #if defined (PWR_WKUPEPR_WKUPEN5)
0120 #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
0121 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */
0122 #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
0123 #if defined (PWR_WKUPEPR_WKUPEN3)
0124 #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
0125 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
0126 #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
0127 #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
0128 
0129 /* Low level and No pull */
0130 #define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
0131 #if defined (PWR_WKUPEPR_WKUPP5)
0132 #define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
0133 #endif /* defined (PWR_WKUPEPR_WKUPP5) */
0134 #define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
0135 #if defined (PWR_WKUPEPR_WKUPP3)
0136 #define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
0137 #endif /* defined (PWR_WKUPEPR_WKUPP3) */
0138 #define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
0139 #define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
0140 /**
0141   * @}
0142   */
0143 
0144 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
0145   * @ingroup RTEMSBSPsARMSTM32H7
0146   * @{
0147   */
0148 #define PWR_PIN_POLARITY_HIGH (0x00000000U)
0149 #define PWR_PIN_POLARITY_LOW  (0x00000001U)
0150 /**
0151   * @}
0152   */
0153 
0154 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
0155   * @ingroup RTEMSBSPsARMSTM32H7
0156   * @{
0157   */
0158 #define PWR_PIN_NO_PULL   (0x00000000U)
0159 #define PWR_PIN_PULL_UP   (0x00000001U)
0160 #define PWR_PIN_PULL_DOWN (0x00000002U)
0161 /**
0162   * @}
0163   */
0164 
0165 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
0166   * @ingroup RTEMSBSPsARMSTM32H7
0167   * @{
0168   */
0169 #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
0170 #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
0171 #if defined (PWR_WKUPFR_WKUPF3)
0172 #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
0173 #endif /* defined (PWR_WKUPFR_WKUPF3) */
0174 #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
0175 #if defined (PWR_WKUPFR_WKUPF5)
0176 #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
0177 #endif /* defined (PWR_WKUPFR_WKUPF5) */
0178 #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
0179 #if defined (PWR_WKUPFR_WKUPF3)
0180 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
0181                              PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
0182                              PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
0183 #else
0184 #define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
0185                              PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6)
0186 #endif /* defined (PWR_WKUPFR_WKUPF3) */
0187 /**
0188   * @}
0189   */
0190 
0191 #if defined (DUAL_CORE)
0192 /** @defgroup PWREx_Core_Select PWREx Core definition
0193   * @ingroup RTEMSBSPsARMSTM32H7
0194   * @{
0195   */
0196 #define PWR_CORE_CPU1 (0x00000000U)
0197 #define PWR_CORE_CPU2 (0x00000001U)
0198 /**
0199   * @}
0200   */
0201 #endif /* defined (DUAL_CORE) */
0202 
0203 /** @defgroup PWREx_Domains PWREx Domains definition
0204   * @ingroup RTEMSBSPsARMSTM32H7
0205   * @{
0206   */
0207 #define PWR_D1_DOMAIN (0x00000000U)
0208 #if defined (PWR_CPUCR_PDDS_D2)
0209 #define PWR_D2_DOMAIN (0x00000001U)
0210 #endif /* defined (PWR_CPUCR_PDDS_D2) */
0211 #define PWR_D3_DOMAIN (0x00000002U)
0212 /**
0213   * @}
0214   */
0215 
0216 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
0217   * @ingroup RTEMSBSPsARMSTM32H7
0218   * @{
0219   */
0220 #if defined (DUAL_CORE)
0221 #define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
0222 #define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
0223 #define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
0224 #else
0225 #define PWR_CPU_FLAGS       (0x00000000U)
0226 #endif /* defined (DUAL_CORE) */
0227 /**
0228   * @}
0229   */
0230 
0231 /** @defgroup PWREx_D3_State PWREx D3 Domain State
0232   * @ingroup RTEMSBSPsARMSTM32H7
0233   * @{
0234   */
0235 #define PWR_D3_DOMAIN_STOP (0x00000000U)
0236 #define PWR_D3_DOMAIN_RUN  (0x00000800U)
0237 
0238 /**
0239   * @}
0240   */
0241 
0242 /** @defgroup PWREx_Supply_configuration PWREx Supply configuration
0243   * @ingroup RTEMSBSPsARMSTM32H7
0244   * @{
0245   */
0246 #define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are supplied from the LDO                                                                     */
0247 #if defined (SMPS)
0248 #define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are supplied from the SMPS only                                                               */
0249 #define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
0250 #define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
0251 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
0252 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */
0253 #define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
0254 #define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
0255 #endif /* defined (SMPS) */
0256 #define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
0257 
0258 #if defined (SMPS)
0259 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
0260                                 PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
0261 #else
0262 #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
0263 #endif /* defined (SMPS) */
0264 /**
0265   * @}
0266   */
0267 
0268 
0269 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
0270   * @ingroup RTEMSBSPsARMSTM32H7
0271   * @{
0272   */
0273 #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
0274                                              selection : 1V7                 */
0275 #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
0276                                              selection : 2V1                 */
0277 #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
0278                                              selection : 2V5                 */
0279 #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
0280                                              selection : 2V8                 */
0281 /**
0282   * @}
0283   */
0284 
0285 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode
0286   * @ingroup RTEMSBSPsARMSTM32H7
0287   * @{
0288   */
0289 #define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
0290 #define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
0291 #define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
0292 #define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
0293 #define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
0294 #define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
0295 #define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
0296 /**
0297   * @}
0298   */
0299 
0300 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
0301   * @ingroup RTEMSBSPsARMSTM32H7
0302   * @{
0303   */
0304 #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
0305 #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
0306 #define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
0307 /**
0308   * @}
0309   */
0310 
0311 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
0312   * @ingroup RTEMSBSPsARMSTM32H7
0313   * @{
0314   */
0315 #define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
0316 #define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
0317 /**
0318   * @}
0319   */
0320 
0321 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
0322   * @ingroup RTEMSBSPsARMSTM32H7
0323   * @{
0324   */
0325 #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
0326 #define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
0327 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
0328 /**
0329   * @}
0330   */
0331 
0332 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
0333   * @ingroup RTEMSBSPsARMSTM32H7
0334   * @{
0335   */
0336 #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
0337 #define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
0338 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
0339 /**
0340   * @}
0341   */
0342 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
0343   * @ingroup RTEMSBSPsARMSTM32H7
0344   * @{
0345   */
0346 #define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
0347                                               Connected to the AVD EXTI Line */
0348 /**
0349   * @}
0350   */
0351 
0352 #if defined (PWR_CR1_SRDRAMSO)
0353 /** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
0354   * @ingroup RTEMSBSPsARMSTM32H7
0355   * @{
0356   */
0357 #define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
0358 #define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
0359 #define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
0360 #define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
0361 #define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
0362 #define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
0363 #define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
0364 #define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
0365 #define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
0366 #define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
0367 #define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
0368 /**
0369   * @}
0370   */
0371 #endif /* defined (PWR_CR1_SRDRAMSO) */
0372 /**
0373   * @}
0374   */
0375 
0376 /* Exported macro ------------------------------------------------------------*/
0377 
0378 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
0379   * @ingroup RTEMSBSPsARMSTM32H7
0380   *  @{
0381   */
0382 
0383 /**
0384   * @brief Enable the AVD EXTI Line 16.
0385   * @retval None.
0386   */
0387 #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
0388 
0389 #if defined (DUAL_CORE)
0390 /**
0391   * @brief Enable the AVD EXTI D2 Line 16.
0392   * @retval None.
0393   */
0394 #define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
0395 #endif /* defined (DUAL_CORE) */
0396 
0397 /**
0398   * @brief Disable the AVD EXTI Line 16
0399   * @retval None.
0400   */
0401 #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
0402 
0403 #if defined (DUAL_CORE)
0404 /**
0405   * @brief Disable the AVD EXTI D2 Line 16.
0406   * @retval None.
0407   */
0408 #define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
0409 #endif /* defined (DUAL_CORE) */
0410 
0411 /**
0412   * @brief Enable event on AVD EXTI Line 16.
0413   * @retval None.
0414   */
0415 #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
0416 
0417 #if defined (DUAL_CORE)
0418 /**
0419   * @brief Enable event on AVD EXTI D2 Line 16.
0420   * @retval None.
0421   */
0422 #define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
0423 #endif /* defined (DUAL_CORE) */
0424 
0425 /**
0426   * @brief Disable event on AVD EXTI Line 16.
0427   * @retval None.
0428   */
0429 #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
0430 
0431 #if defined (DUAL_CORE)
0432 /**
0433   * @brief Disable event on AVD EXTI D2 Line 16.
0434   * @retval None.
0435   */
0436 #define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
0437 #endif /* defined (DUAL_CORE) */
0438 
0439 /**
0440   * @brief Enable the AVD Extended Interrupt Rising Trigger.
0441   * @retval None.
0442   */
0443 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
0444 
0445 /**
0446   * @brief Disable the AVD Extended Interrupt Rising Trigger.
0447   * @retval None.
0448   */
0449 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
0450 
0451 /**
0452   * @brief Enable the AVD Extended Interrupt Falling Trigger.
0453   * @retval None.
0454   */
0455 #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
0456 
0457 /**
0458   * @brief Disable the AVD Extended Interrupt Falling Trigger.
0459   * @retval None.
0460   */
0461 #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
0462 
0463 /**
0464   * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
0465   * @retval None.
0466   */
0467 #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
0468 do {                                                    \
0469      __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
0470      __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
0471 } while(0);
0472 
0473 /**
0474   * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
0475   * @retval None.
0476   */
0477 #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
0478 do {                                                     \
0479      __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
0480      __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
0481 } while(0);
0482 
0483 /**
0484   * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
0485   * @retval EXTI AVD Line Status.
0486   */
0487 #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
0488 
0489 #if defined (DUAL_CORE)
0490 /**
0491   * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
0492   * @retval EXTI D2 AVD Line Status.
0493   */
0494 #define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
0495 #endif /* defined (DUAL_CORE) */
0496 
0497 /**
0498   * @brief  Clear the AVD EXTI flag.
0499   * @retval None.
0500   */
0501 #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
0502 
0503 #if defined (DUAL_CORE)
0504 /**
0505   * @brief  Clear the AVD EXTI D2 flag.
0506   * @retval None.
0507   */
0508 #define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
0509 #endif /* defined (DUAL_CORE) */
0510 
0511 /**
0512   * @brief  Generates a Software interrupt on AVD EXTI line.
0513   * @retval None.
0514   */
0515 #define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
0516 /**
0517   * @}
0518   */
0519 
0520 /* Exported functions --------------------------------------------------------*/
0521 
0522 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
0523   * @{
0524   */
0525 
0526 /** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
0527   * @{
0528   */
0529 HAL_StatusTypeDef HAL_PWREx_ConfigSupply                  (uint32_t SupplySource);
0530 uint32_t          HAL_PWREx_GetSupplyConfig               (void);
0531 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling         (uint32_t VoltageScaling);
0532 uint32_t          HAL_PWREx_GetVoltageRange               (void);
0533 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling);
0534 uint32_t          HAL_PWREx_GetStopModeVoltageRange       (void);
0535 /**
0536   * @}
0537   */
0538 
0539 /** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
0540   * @{
0541   */
0542 /* System low power control functions */
0543 #if defined (PWR_CPUCR_RETDS_CD)
0544 void HAL_PWREx_EnterSTOP2Mode    (uint32_t Regulator, uint8_t STOPEntry);
0545 #endif /* defined (PWR_CPUCR_RETDS_CD) */
0546 void HAL_PWREx_EnterSTOPMode     (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
0547 void HAL_PWREx_EnterSTANDBYMode  (uint32_t Domain);
0548 void HAL_PWREx_ConfigD3Domain    (uint32_t D3State);
0549 /* Clear Cortex-Mx pending flag */
0550 void HAL_PWREx_ClearPendingEvent (void);
0551 #if defined (DUAL_CORE)
0552 /* Clear domain flags */
0553 void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags);
0554 /* Core Hold/Release functions */
0555 HAL_StatusTypeDef HAL_PWREx_HoldCore    (uint32_t CPU);
0556 void              HAL_PWREx_ReleaseCore (uint32_t CPU);
0557 #endif /* defined (DUAL_CORE) */
0558 /* Flash low power control functions */
0559 void HAL_PWREx_EnableFlashPowerDown  (void);
0560 void HAL_PWREx_DisableFlashPowerDown (void);
0561 #if defined (PWR_CR1_SRDRAMSO)
0562 /* Memory shut-off functions */
0563 void HAL_PWREx_EnableMemoryShutOff  (uint32_t MemoryBlock);
0564 void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock);
0565 #endif /* defined(PWR_CR1_SRDRAMSO) */
0566 /* Wakeup Pins control functions */
0567 void HAL_PWREx_EnableWakeUpPin              (PWREx_WakeupPinTypeDef *sPinParams);
0568 void HAL_PWREx_DisableWakeUpPin             (uint32_t WakeUpPin);
0569 uint32_t HAL_PWREx_GetWakeupFlag            (uint32_t WakeUpFlag);
0570 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag);
0571 /* Power Wakeup PIN IRQ Handler */
0572 void HAL_PWREx_WAKEUP_PIN_IRQHandler (void);
0573 void HAL_PWREx_WKUP1_Callback        (void);
0574 void HAL_PWREx_WKUP2_Callback        (void);
0575 #if defined (PWR_WKUPEPR_WKUPEN3)
0576 void HAL_PWREx_WKUP3_Callback        (void);
0577 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
0578 void HAL_PWREx_WKUP4_Callback        (void);
0579 #if defined (PWR_WKUPEPR_WKUPEN5)
0580 void HAL_PWREx_WKUP5_Callback        (void);
0581 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */
0582 void HAL_PWREx_WKUP6_Callback        (void);
0583 /**
0584   * @}
0585   */
0586 
0587 /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
0588   * @{
0589   */
0590 /* Backup regulator control functions */
0591 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg  (void);
0592 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void);
0593 /* USB regulator control functions */
0594 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg  (void);
0595 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void);
0596 void HAL_PWREx_EnableUSBVoltageDetector   (void);
0597 void HAL_PWREx_DisableUSBVoltageDetector  (void);
0598 /* Battery control functions */
0599 void HAL_PWREx_EnableBatteryCharging  (uint32_t ResistorValue);
0600 void HAL_PWREx_DisableBatteryCharging (void);
0601 #if defined (PWR_CR1_BOOSTE)
0602 /* Analog Booster functions */
0603 void HAL_PWREx_EnableAnalogBooster  (void);
0604 void HAL_PWREx_DisableAnalogBooster (void);
0605 #endif /* PWR_CR1_BOOSTE */
0606 /**
0607   * @}
0608   */
0609 
0610 /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
0611   * @{
0612   */
0613 /* Power VBAT/Temperature monitoring functions */
0614 void HAL_PWREx_EnableMonitoring        (void);
0615 void HAL_PWREx_DisableMonitoring       (void);
0616 uint32_t HAL_PWREx_GetTemperatureLevel (void);
0617 uint32_t HAL_PWREx_GetVBATLevel        (void);
0618 #if defined (PWR_CSR1_MMCVDO)
0619 PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void);
0620 #endif /* PWR_CSR1_MMCVDO */
0621 /* Power AVD configuration functions */
0622 void HAL_PWREx_ConfigAVD  (PWREx_AVDTypeDef *sConfigAVD);
0623 void HAL_PWREx_EnableAVD  (void);
0624 void HAL_PWREx_DisableAVD (void);
0625 /* Power PVD/AVD IRQ Handler */
0626 void HAL_PWREx_PVD_AVD_IRQHandler (void);
0627 void HAL_PWREx_AVDCallback        (void);
0628 /**
0629   * @}
0630   */
0631 
0632 /**
0633   * @}
0634   */
0635 /* Private types -------------------------------------------------------------*/
0636 /* Private variables ---------------------------------------------------------*/
0637 /* Private constants ---------------------------------------------------------*/
0638 /* Private macros ------------------------------------------------------------*/
0639 /** @defgroup PWREx_Private_Macros PWREx Private Macros
0640   * @ingroup RTEMSBSPsARMSTM32H7
0641   * @{
0642   */
0643 
0644 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
0645   * @ingroup RTEMSBSPsARMSTM32H7
0646   * @{
0647   */
0648 /* Check PWR regulator configuration parameter */
0649 #if defined (SMPS)
0650 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
0651                                    ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
0652                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
0653                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
0654                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
0655                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
0656                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
0657                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
0658                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
0659 
0660 #else
0661 #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
0662                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
0663 #endif /* defined (SMPS) */
0664 
0665 /* Check PWR regulator configuration in STOP mode parameter */
0666 #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
0667                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
0668                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
0669 
0670 /* Check PWR domain parameter */
0671 #if defined (PWR_CPUCR_PDDS_D2)
0672 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
0673                                ((DOMAIN) == PWR_D2_DOMAIN) ||\
0674                                ((DOMAIN) == PWR_D3_DOMAIN))
0675 #else
0676 #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
0677                                ((DOMAIN) == PWR_D3_DOMAIN))
0678 #endif /* defined (PWR_CPUCR_PDDS_D2) */
0679 
0680 /* Check D3/SRD domain state parameter */
0681 #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
0682                             ((STATE) == PWR_D3_DOMAIN_RUN))
0683 
0684 /* Check wake up pin parameter */
0685 #if defined (PWR_WKUPEPR_WKUPEN3)
0686 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
0687                                 ((PIN) == PWR_WAKEUP_PIN2)      ||\
0688                                 ((PIN) == PWR_WAKEUP_PIN3)      ||\
0689                                 ((PIN) == PWR_WAKEUP_PIN4)      ||\
0690                                 ((PIN) == PWR_WAKEUP_PIN5)      ||\
0691                                 ((PIN) == PWR_WAKEUP_PIN6)      ||\
0692                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
0693                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
0694                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
0695                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
0696                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
0697                                 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
0698                                 ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
0699                                 ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
0700                                 ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
0701                                 ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
0702                                 ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
0703                                 ((PIN) == PWR_WAKEUP_PIN6_LOW))
0704 #else
0705 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
0706                                 ((PIN) == PWR_WAKEUP_PIN2)      ||\
0707                                 ((PIN) == PWR_WAKEUP_PIN4)      ||\
0708                                 ((PIN) == PWR_WAKEUP_PIN6)      ||\
0709                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
0710                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
0711                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
0712                                 ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
0713                                 ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
0714                                 ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
0715                                 ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
0716                                 ((PIN) == PWR_WAKEUP_PIN6_LOW))
0717 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
0718 
0719 /* Check wake up pin polarity parameter */
0720 #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
0721                                               ((POLARITY) == PWR_PIN_POLARITY_LOW))
0722 
0723 /* Check wake up pin pull configuration parameter */
0724 #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
0725                                       ((PULL) == PWR_PIN_PULL_UP) ||\
0726                                       ((PULL) == PWR_PIN_PULL_DOWN))
0727 
0728 /* Check wake up flag parameter */
0729 #if defined (PWR_WKUPEPR_WKUPEN3)
0730 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
0731                                   ((FLAG) == PWR_WAKEUP_FLAG2) ||\
0732                                   ((FLAG) == PWR_WAKEUP_FLAG3) ||\
0733                                   ((FLAG) == PWR_WAKEUP_FLAG4) ||\
0734                                   ((FLAG) == PWR_WAKEUP_FLAG5) ||\
0735                                   ((FLAG) == PWR_WAKEUP_FLAG6) ||\
0736                                   ((FLAG) == PWR_WAKEUP_FLAG_ALL))
0737 #else
0738 #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
0739                                   ((FLAG) == PWR_WAKEUP_FLAG2) ||\
0740                                   ((FLAG) == PWR_WAKEUP_FLAG4) ||\
0741                                   ((FLAG) == PWR_WAKEUP_FLAG6) ||\
0742                                   ((FLAG) == PWR_WAKEUP_FLAG_ALL))
0743 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */
0744 
0745 /* Check wake up flag parameter */
0746 #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
0747                                  ((LEVEL) == PWR_AVDLEVEL_1) ||\
0748                                  ((LEVEL) == PWR_AVDLEVEL_2) ||\
0749                                  ((LEVEL) == PWR_AVDLEVEL_3))
0750 
0751 /* Check AVD mode parameter */
0752 #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
0753                                ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
0754                                ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
0755                                ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
0756                                ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
0757                                ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
0758                                ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
0759 
0760 /* Check resistor battery parameter */
0761 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
0762                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
0763 /* Check D1/CD CPU ID parameter */
0764 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
0765 
0766 #if defined (DUAL_CORE)
0767 /* Check CPU parameter */
0768 #define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
0769 
0770 /* Check D2 CPU ID parameter */
0771 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
0772 
0773 /* Check PWR domain flag parameter */
0774 #define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
0775                                    ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
0776                                    ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
0777 #endif /* defined (DUAL_CORE) */
0778 
0779 #if defined (PWR_CR1_SRDRAMSO)
0780 /* Check memory block parameter */
0781 #define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
0782                                     ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
0783                                     ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
0784                                     ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
0785                                     ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
0786                                     ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
0787                                     ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
0788                                     ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
0789                                     ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
0790 #endif /* defined (PWR_CR1_SRDRAMSO) */
0791 /**
0792   * @}
0793   */
0794 /**
0795   * @}
0796   */
0797 
0798 /**
0799   * @}
0800   */
0801 
0802 /**
0803   * @}
0804   */
0805 #ifdef __cplusplus
0806 }
0807 #endif /* __cplusplus */
0808 
0809 
0810 #endif /* STM32H7xx_HAL_PWR_EX_H */
0811
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.3.7 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!