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File indexing completed on 2025-05-11 08:23:36 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_pwr.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of PWR HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_PWR_H
0021 #define STM32H7xx_HAL_PWR_H
0022 
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif /* __cplusplus */
0026 
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029 
0030 /** @addtogroup STM32H7xx_HAL_Driver
0031   * @{
0032   */
0033 
0034 /** @addtogroup PWR
0035   * @{
0036   */
0037 
0038 /* Exported types ------------------------------------------------------------*/
0039 
0040 /** @defgroup PWR_Exported_Types PWR Exported Types
0041   * @ingroup RTEMSBSPsARMSTM32H7
0042   * @{
0043   */
0044 
0045 /**
0046   * @brief  PWR PVD configuration structure definition
0047   */
0048 typedef struct
0049 {
0050   uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
0051                                     parameter can be a value of @ref
0052                                     PWR_PVD_detection_level.
0053                      */
0054 
0055   uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
0056                                 event. This parameter can be a value of @ref
0057                                 PWR_PVD_Mode.
0058                      */
0059 }PWR_PVDTypeDef;
0060 
0061 /**
0062   * @}
0063   */
0064 
0065 /* Exported constants --------------------------------------------------------*/
0066 /** @defgroup PWR_Exported_Constants PWR Exported Constants
0067   * @ingroup RTEMSBSPsARMSTM32H7
0068   * @{
0069   */
0070 
0071 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
0072   * @ingroup RTEMSBSPsARMSTM32H7
0073   * @{
0074   */
0075 #define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
0076                                                level 0 selection : 1V95       */
0077 #define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
0078                                                level 1 selection : 2V1        */
0079 #define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
0080                                                level 2 selection : 2V25       */
0081 #define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
0082                                                level 3 selection : 2V4        */
0083 #define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
0084                                                level 4 selection : 2V55       */
0085 #define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
0086                                                level 5 selection : 2V7        */
0087 #define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
0088                                                level 6 selection : 2V85       */
0089 #define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
0090                                                (Compare internally to VREF)   */
0091 /**
0092   * @}
0093   */
0094 
0095 /** @defgroup PWR_PVD_Mode PWR PVD Mode
0096   * @ingroup RTEMSBSPsARMSTM32H7
0097   * @{
0098   */
0099 #define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
0100 #define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
0101 #define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
0102 #define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
0103 #define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
0104 #define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
0105 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
0106 /**
0107   * @}
0108   */
0109 
0110 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
0111   * @ingroup RTEMSBSPsARMSTM32H7
0112   * @{
0113   */
0114 #define PWR_MAINREGULATOR_ON      (0U)
0115 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
0116 /**
0117   * @}
0118   */
0119 
0120 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
0121   * @ingroup RTEMSBSPsARMSTM32H7
0122   * @{
0123   */
0124 #define PWR_SLEEPENTRY_WFI  (0x01U)
0125 #define PWR_SLEEPENTRY_WFE  (0x02U)
0126 /**
0127   * @}
0128   */
0129 
0130 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
0131   * @ingroup RTEMSBSPsARMSTM32H7
0132   * @{
0133   */
0134 #define PWR_STOPENTRY_WFI  (0x01U)
0135 #define PWR_STOPENTRY_WFE  (0x02U)
0136 /**
0137   * @}
0138   */
0139 
0140 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
0141   * @ingroup RTEMSBSPsARMSTM32H7
0142   * @{
0143   */
0144 #if defined(PWR_SRDCR_VOS)
0145 #define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
0146 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
0147 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
0148 #define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
0149 #else
0150 #define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
0151 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
0152 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
0153 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
0154 #endif /* PWR_SRDCR_VOS */
0155 /**
0156   * @}
0157   */
0158 
0159 /** @defgroup PWR_Flag PWR Flag
0160   * @ingroup RTEMSBSPsARMSTM32H7
0161   * @{
0162   */
0163 /* PWR CPU flag */
0164 #define PWR_FLAG_STOP       (0x01U)
0165 #if defined (PWR_CPUCR_SBF_D2)
0166 #define PWR_FLAG_SB_D1      (0x02U)
0167 #define PWR_FLAG_SB_D2      (0x03U)
0168 #endif /* defined (PWR_CPUCR_SBF_D2) */
0169 #define PWR_FLAG_SB         (0x04U)
0170 #if defined (DUAL_CORE)
0171 #define PWR_FLAG_CPU_HOLD   (0x05U)
0172 #define PWR_FLAG_CPU2_HOLD  (0x06U)
0173 #define PWR_FLAG2_STOP      (0x07U)
0174 #define PWR_FLAG2_SB_D1     (0x08U)
0175 #define PWR_FLAG2_SB_D2     (0x09U)
0176 #define PWR_FLAG2_SB        (0x0AU)
0177 #endif /* defined (DUAL_CORE) */
0178 #define PWR_FLAG_PVDO       (0x0BU)
0179 #define PWR_FLAG_AVDO       (0x0CU)
0180 #define PWR_FLAG_ACTVOSRDY  (0x0DU)
0181 #define PWR_FLAG_ACTVOS     (0x0EU)
0182 #define PWR_FLAG_BRR        (0x0FU)
0183 #define PWR_FLAG_VOSRDY     (0x10U)
0184 #if defined (SMPS)
0185 #define PWR_FLAG_SMPSEXTRDY (0x11U)
0186 #else
0187 #define PWR_FLAG_SCUEN      (0x11U)
0188 #endif /* defined (SMPS) */
0189 #if defined (PWR_CSR1_MMCVDO)
0190 #define PWR_FLAG_MMCVDO     (0x12U)
0191 #endif /* defined (PWR_CSR1_MMCVDO) */
0192 #define PWR_FLAG_USB33RDY   (0x13U)
0193 #define PWR_FLAG_TEMPH      (0x14U)
0194 #define PWR_FLAG_TEMPL      (0x15U)
0195 #define PWR_FLAG_VBATH      (0x16U)
0196 #define PWR_FLAG_VBATL      (0x17U)
0197 
0198 /* PWR Wake up flag */
0199 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
0200 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
0201 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
0202 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
0203 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
0204 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
0205 /**
0206   * @}
0207   */
0208 
0209 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
0210   * @ingroup RTEMSBSPsARMSTM32H7
0211   * @{
0212   */
0213 #define  PWR_EWUP_MASK  (0x0FFF3F3FU)
0214 /**
0215   * @}
0216   */
0217 
0218 /**
0219   * @}
0220   */
0221 /* Exported macro ------------------------------------------------------------*/
0222 /** @defgroup PWR_Exported_Macro PWR Exported Macro
0223   * @ingroup RTEMSBSPsARMSTM32H7
0224   * @{
0225   */
0226 
0227 /** @brief  Configure the main internal regulator output voltage.
0228   * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
0229   *                         trade-off between performance and power consumption
0230   *                         when the device does not operate at the maximum
0231   *                         frequency (refer to the datasheet for more details).
0232   *          This parameter can be one of the following values:
0233   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
0234   *                                                Scale 0 mode.
0235   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
0236   *                                                Scale 1 mode.
0237   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
0238   *                                                Scale 2 mode.
0239   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
0240   *                                                Scale 3 mode.
0241   * @note   For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
0242   *         only possible when Vcore is supplied from LDO (Low DropOut). The
0243   *         SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
0244   *         macro before configuring Voltage Scale 0 using
0245   *         __HAL_PWR_VOLTAGESCALING_CONFIG().
0246   *         Transition to Voltage Scale 0 is only possible when the system is
0247   *         already in Voltage Scale 1.
0248   *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
0249   *         then once in Voltage Scale 1 it is possible to switch to another
0250   *         voltage scale.
0251   *         After each regulator voltage setting, wait on VOSRDY flag to be set
0252   *         using macro __HAL_PWR_GET_FLAG().
0253   *         To enter low power mode , and if current regulator voltage is
0254   *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
0255   *         low power mode.
0256   * @retval None.
0257   */
0258 #if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
0259 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
0260 do {                                                                           \
0261       __IO uint32_t tmpreg = 0x00;                                             \
0262       /* Configure the Voltage Scaling */                                      \
0263       MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
0264       /* Delay after setting the voltage scaling */                            \
0265       tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
0266       UNUSED(tmpreg);                                                          \
0267 } while(0)
0268 #else /* 3 power domains devices */
0269 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
0270 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
0271 do {                                                                           \
0272       __IO uint32_t tmpreg = 0x00;                                             \
0273       /* Check the voltage scaling to be configured */                         \
0274       if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
0275       {                                                                        \
0276         /* Configure the Voltage Scaling 1 */                                  \
0277         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
0278         /* Delay after setting the voltage scaling */                          \
0279         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
0280         /* Enable the PWR overdrive */                                         \
0281         SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
0282         /* Delay after setting the syscfg boost setting */                     \
0283         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
0284       }                                                                        \
0285       else                                                                     \
0286       {                                                                        \
0287         /* Disable the PWR overdrive */                                        \
0288         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
0289         /* Delay after setting the syscfg boost setting */                     \
0290         tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
0291         /* Configure the Voltage Scaling x */                                  \
0292         MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
0293         /* Delay after setting the voltage scaling */                          \
0294         tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
0295       }                                                                        \
0296       UNUSED(tmpreg);                                                          \
0297 } while(0)
0298 #else /* STM32H72xxx and STM32H73xxx lines */
0299 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
0300 do {                                                                           \
0301       __IO uint32_t tmpreg = 0x00;                                             \
0302       /* Configure the Voltage Scaling */                                      \
0303       MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                   \
0304       /* Delay after setting the voltage scaling */                            \
0305       tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                              \
0306       UNUSED(tmpreg);                                                          \
0307 } while(0)
0308 #endif /* defined(SYSCFG_PWRCR_ODEN) */
0309 #endif /* defined (PWR_SRDCR_VOS) */
0310 
0311 /** @brief  Check PWR flags are set or not.
0312   * @param  __FLAG__ : Specifies the flag to check.
0313   *           This parameter can be one of the following values:
0314   *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
0315   *                                 is enabled by the HAL_PWR_EnablePVD()
0316   *                                 function.
0317   *                                 The PVD is stopped by STANDBY mode. For this
0318   *                                 reason, this bit is equal to 0 after STANDBY
0319   *                                 or reset until the PVDE bit is set.
0320   *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
0321   *                                 is enabled by the HAL_PWREx_EnableAVD()
0322   *                                 function. The AVD is stopped by STANDBY mode.
0323   *                                 For this reason, this bit is equal to 0
0324   *                                 after STANDBY or reset until the AVDE bit
0325   *                                 is set.
0326   *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
0327   *                                      voltage scaling output selection is
0328   *                                      ready.
0329   *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
0330   *                                reset when the device wakes up from STANDBY
0331   *                                mode or by a system reset or power-on reset.
0332   *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
0333   *                                   voltage scaling output selection is ready.
0334   *                                mode or by a system reset or power-on reset.
0335   *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
0336   *                                     from regulator is ready.
0337   *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
0338   *                                  equal or above high threshold level.
0339   *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
0340   *                                  equal or below low threshold level.
0341   *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
0342   *                                  or above high threshold level.
0343   *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
0344   *                                  or below low threshold level.
0345   *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
0346   *                                 in STOP mode.
0347   *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
0348   *                               STANDBY mode.
0349   *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
0350   *                                  entered in STANDBY mode.
0351   *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
0352   *                                  entered in STANDBY mode.
0353   *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
0354   *                                 in STOP mode.
0355   *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
0356   *                                in STANDBY mode.
0357   *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
0358   *                                   entered in STANDBY mode.
0359   *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
0360   *                                   entered in STANDBY mode.
0361   *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
0362   *                                     up with hold.
0363   *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
0364   *                                      up with hold.
0365   *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
0366   *                                       External supply is sready.
0367   *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
0368   *                                  configuration update is enabled.
0369   *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
0370   *                                   above or equal to 1.2 V.
0371   * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
0372   *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
0373   *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
0374   *         are used for all H7 family lines.
0375   *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
0376   *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
0377   *         dual core lines.
0378   *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
0379   *         family except STM32H7Axxx and STM32H7Bxxx lines.
0380   *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
0381   *         STM32H7Bxxx lines.
0382   *         The PWR_FLAG_SCUEN flag is used for devices that support only LDO
0383   *         regulator.
0384   *         The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO
0385   *         and SMPS regulators.
0386   * @retval The (__FLAG__) state (TRUE or FALSE).
0387   */
0388 #if defined (DUAL_CORE) /* Dual core lines */
0389 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
0390 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
0391  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
0392  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
0393  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
0394  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
0395  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
0396  ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
0397  ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
0398  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
0399  ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
0400  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
0401  ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
0402  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
0403  ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
0404  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
0405  ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
0406  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
0407  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
0408  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
0409  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
0410  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
0411 #else /* Single core lines */
0412 #if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */
0413 #if defined (SMPS) /* STM32H725 and STM32H735 lines */
0414 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
0415 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)       :\
0416  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)       :\
0417  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY)  :\
0418  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)     :\
0419  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\
0420  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)       :\
0421  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)       :\
0422  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)     :\
0423  ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)    :\
0424  ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)    :\
0425  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)    :\
0426  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)       :\
0427  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)       :\
0428  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)       :\
0429  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
0430 #else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */
0431 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
0432 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
0433  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
0434  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
0435  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
0436  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
0437  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
0438  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
0439  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
0440  ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
0441  ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
0442  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
0443  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
0444  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
0445  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
0446  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
0447 #endif /* defined (SMPS) */
0448 #else /* STM32H7Axxx and STM32H7Bxxx lines */
0449 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */
0450 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                             \
0451 (((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
0452  ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
0453  ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
0454  ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
0455  ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
0456  ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
0457  ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
0458  ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
0459  ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
0460  ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
0461  ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
0462  ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
0463  ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
0464  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
0465 #else /* STM32H7Axx and STM32H7Bxx lines */
0466 #define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
0467 (((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
0468  ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
0469  ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
0470  ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
0471  ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
0472  ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
0473  ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
0474  ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
0475  ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
0476  ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
0477  ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
0478  ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
0479  ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
0480  ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
0481 #endif /* SMPS */
0482 #endif /* PWR_CPUCR_SBF_D2 */
0483 #endif /* DUAL_CORE */
0484 
0485 /** @brief  Check PWR wake up flags are set or not.
0486   * @param  __FLAG__: specifies the wake up flag to check.
0487   *           This parameter can be one of the following values:
0488   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
0489   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
0490   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
0491   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
0492   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
0493   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
0494   * @note   The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
0495   *         that support GPIOI port.
0496   * @retval The (__FLAG__) state (TRUE or FALSE).
0497   */
0498 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
0499 
0500 #if defined (DUAL_CORE)
0501 /** @brief  Clear CPU PWR flags.
0502   * @param  __FLAG__ : Specifies the flag to clear.
0503   * @note   This parameter is not used for the STM32H7 family and is kept as
0504   *         parameter just to maintain compatibility with other families.
0505   * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
0506   *           This parameter can be one of the following values :
0507   *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
0508   *                                 CPU flags.
0509   * @retval None.
0510   */
0511 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
0512 do {                                        \
0513      SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \
0514      SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
0515 } while(0)
0516 #else
0517 /** @brief  Clear CPU PWR flags.
0518   * @param  __FLAG__ : Specifies the flag to clear.
0519   * @note   This parameter is not used for the STM32H7 family and is kept as
0520   *         parameter just to maintain compatibility with other families.
0521   * @note   This macro clear all CPU flags.
0522   *         For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU
0523   *         flags are STOPF, SBF, SBF_D1 and SBF_D2.
0524   *         For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF.
0525   * @retval None.
0526   */
0527 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
0528 #endif /* defined (DUAL_CORE) */
0529 
0530 /** @brief  Clear PWR wake up flags.
0531   * @param  __FLAG__ : Specifies the wake up flag to be cleared.
0532   *           This parameter can be one of the following values :
0533   *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
0534   *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
0535   *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
0536   *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
0537   *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
0538   *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
0539   * @note   The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices
0540   *         that support GPIOI port.
0541   * @retval None.
0542   */
0543 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
0544 
0545 /**
0546   * @brief Enable the PVD EXTI Line 16.
0547   * @retval None.
0548   */
0549 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
0550 
0551 #if defined (DUAL_CORE)
0552 /**
0553   * @brief Enable the PVD EXTI D2 Line 16.
0554   * @retval None.
0555   */
0556 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
0557 #endif /* defined (DUAL_CORE) */
0558 
0559 /**
0560   * @brief Disable the PVD EXTI Line 16.
0561   * @retval None.
0562   */
0563 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
0564 
0565 #if defined (DUAL_CORE)
0566 /**
0567   * @brief Disable the PVD EXTI D2 Line 16.
0568   * @retval None.
0569   */
0570 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
0571 #endif /* defined (DUAL_CORE) */
0572 
0573 /**
0574   * @brief   Enable event on PVD EXTI Line 16.
0575   * @retval None.
0576   */
0577 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
0578 
0579 #if defined (DUAL_CORE)
0580 /**
0581   * @brief Enable event on PVD EXTI D2 Line.
0582   * @retval None.
0583   */
0584 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
0585 #endif /* defined (DUAL_CORE) */
0586 
0587 /**
0588   * @brief   Disable event on PVD EXTI Line 16.
0589   * @retval None.
0590   */
0591 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
0592 
0593 #if defined (DUAL_CORE)
0594 /**
0595   * @brief Disable event on PVD EXTI D2 Line.
0596   * @retval None.
0597   */
0598 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
0599 #endif /* defined (DUAL_CORE) */
0600 
0601 /**
0602   * @brief Enable the PVD Rising Interrupt Trigger.
0603   * @retval None.
0604   */
0605 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
0606 
0607 /**
0608   * @brief Disable the PVD Rising Interrupt Trigger.
0609   * @retval None.
0610   */
0611 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
0612 
0613 /**
0614   * @brief Enable the PVD Falling Interrupt Trigger.
0615   * @retval None.
0616   */
0617 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
0618 
0619 /**
0620   * @brief Disable the PVD Falling Interrupt Trigger.
0621   * @retval None.
0622   */
0623 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
0624 
0625 /**
0626   * @brief Enable the PVD Rising & Falling Interrupt Trigger.
0627   * @retval None.
0628   */
0629 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
0630 do {                                                    \
0631       __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
0632       __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
0633 } while(0);
0634 
0635 /**
0636   * @brief Disable the PVD Rising & Falling Interrupt Trigger.
0637   * @retval None.
0638   */
0639 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
0640 do {                                                     \
0641       __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
0642       __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
0643 } while(0);
0644 
0645 /**
0646   * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
0647   * @retval EXTI PVD Line Status.
0648   */
0649 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
0650 
0651 #if defined (DUAL_CORE)
0652 /**
0653   * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
0654   * @retval EXTI D2 PVD Line Status.
0655   */
0656 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
0657 #endif /* defined (DUAL_CORE) */
0658 
0659 /**
0660   * @brief Clear the PVD EXTI flag.
0661   * @retval None.
0662   */
0663 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
0664 
0665 #if defined (DUAL_CORE)
0666 /**
0667   * @brief Clear the PVD EXTI D2 flag.
0668   * @retval None.
0669   */
0670 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
0671 #endif /* defined (DUAL_CORE) */
0672 
0673 /**
0674   * @brief  Generates a Software interrupt on PVD EXTI line.
0675   * @retval None.
0676   */
0677 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
0678 /**
0679   * @}
0680   */
0681 
0682 /* Include PWR HAL Extension module */
0683 #include "stm32h7xx_hal_pwr_ex.h"
0684 
0685 /* Exported functions --------------------------------------------------------*/
0686 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
0687   * @{
0688   */
0689 
0690 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions
0691   * @{
0692   */
0693 /* Initialization and de-initialization functions *****************************/
0694 void HAL_PWR_DeInit            (void);
0695 void HAL_PWR_EnableBkUpAccess  (void);
0696 void HAL_PWR_DisableBkUpAccess (void);
0697 /**
0698   * @}
0699   */
0700 
0701 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions
0702   * @{
0703   */
0704 /* Peripheral Control functions  **********************************************/
0705 /* PVD configuration */
0706 void HAL_PWR_ConfigPVD  (PWR_PVDTypeDef *sConfigPVD);
0707 void HAL_PWR_EnablePVD  (void);
0708 void HAL_PWR_DisablePVD (void);
0709 
0710 /* WakeUp pins configuration */
0711 void HAL_PWR_EnableWakeUpPin  (uint32_t WakeUpPinPolarity);
0712 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx);
0713 
0714 /* Low Power modes entry */
0715 void HAL_PWR_EnterSTOPMode    (uint32_t Regulator, uint8_t STOPEntry);
0716 void HAL_PWR_EnterSLEEPMode   (uint32_t Regulator, uint8_t SLEEPEntry);
0717 void HAL_PWR_EnterSTANDBYMode (void);
0718 
0719 /* Power PVD IRQ Handler */
0720 void HAL_PWR_PVD_IRQHandler (void);
0721 void HAL_PWR_PVDCallback    (void);
0722 
0723 /* Cortex System Control functions  *******************************************/
0724 void HAL_PWR_EnableSleepOnExit  (void);
0725 void HAL_PWR_DisableSleepOnExit (void);
0726 void HAL_PWR_EnableSEVOnPend    (void);
0727 void HAL_PWR_DisableSEVOnPend   (void);
0728 /**
0729   * @}
0730   */
0731 
0732 /**
0733   * @}
0734   */
0735 
0736 /* Private types -------------------------------------------------------------*/
0737 /* Private variables ---------------------------------------------------------*/
0738 /* Private constants ---------------------------------------------------------*/
0739 /** @defgroup PWR_Private_Constants PWR Private Constants
0740   * @ingroup RTEMSBSPsARMSTM32H7
0741   * @{
0742   */
0743 
0744 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
0745   * @ingroup RTEMSBSPsARMSTM32H7
0746   * @{
0747   */
0748 #define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
0749                                                Connected to the PVD EXTI Line */
0750 /**
0751   * @}
0752   */
0753 
0754 /**
0755   * @}
0756   */
0757 /* Private macros ------------------------------------------------------------*/
0758 /** @defgroup PWR_Private_Macros PWR Private Macros
0759   * @ingroup RTEMSBSPsARMSTM32H7
0760   * @{
0761   */
0762 
0763 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
0764   * @ingroup RTEMSBSPsARMSTM32H7
0765   * @{
0766   */
0767 /* Check PVD level parameter */
0768 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
0769                                  ((LEVEL) == PWR_PVDLEVEL_1) ||\
0770                                  ((LEVEL) == PWR_PVDLEVEL_2) ||\
0771                                  ((LEVEL) == PWR_PVDLEVEL_3) ||\
0772                                  ((LEVEL) == PWR_PVDLEVEL_4) ||\
0773                                  ((LEVEL) == PWR_PVDLEVEL_5) ||\
0774                                  ((LEVEL) == PWR_PVDLEVEL_6) ||\
0775                                  ((LEVEL) == PWR_PVDLEVEL_7))
0776 
0777 /* Check PVD mode parameter */
0778 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
0779                                ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
0780                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
0781                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
0782                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
0783                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
0784                                ((MODE) == PWR_PVD_MODE_NORMAL))
0785 
0786 /* Check low power regulator parameter */
0787 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
0788                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
0789 
0790 /* Check low power mode entry parameter */
0791 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
0792                                    ((ENTRY) == PWR_SLEEPENTRY_WFE))
0793 
0794 /* Check low power mode entry parameter */
0795 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
0796                                   ((ENTRY) == PWR_STOPENTRY_WFE))
0797 
0798 /* Check voltage scale level parameter */
0799 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
0800                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
0801                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
0802                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
0803 /**
0804   * @}
0805   */
0806 
0807 /**
0808   * @}
0809   */
0810 
0811 /**
0812   * @}
0813   */
0814 
0815 /**
0816   * @}
0817   */
0818 
0819 #ifdef __cplusplus
0820 }
0821 #endif /* __cplusplus */
0822 
0823 #endif /* STM32H7xx_HAL_PWR_H */
0824
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