stm32h7/include/stm32h7xx_hal_nor.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_nor.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of NOR HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_NOR_H
0021 #define STM32H7xx_HAL_NOR_H
0022
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026
0027
0028 /* Includes ------------------------------------------------------------------*/
0029 #include "stm32h7xx_ll_fmc.h"
0030
0031 /** @addtogroup STM32H7xx_HAL_Driver
0032   * @{
0033   */
0034
0035 /** @addtogroup NOR
0036   * @{
0037   */
0038
0039 /* Exported typedef ----------------------------------------------------------*/
0040 /** @defgroup NOR_Exported_Types NOR Exported Types
0041   * @ingroup RTEMSBSPsARMSTM32H7
0042   * @{
0043   */
0044
0045 /**
0046   * @brief  HAL SRAM State structures definition
0047   */
0048 typedef enum
0049 {
0050   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
0051   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
0052   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
0053   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
0054   HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */
0055 } HAL_NOR_StateTypeDef;
0056
0057 /**
0058   * @brief  FMC NOR Status typedef
0059   */
0060 typedef enum
0061 {
0062   HAL_NOR_STATUS_SUCCESS  = 0U,
0063   HAL_NOR_STATUS_ONGOING,
0064   HAL_NOR_STATUS_ERROR,
0065   HAL_NOR_STATUS_TIMEOUT
0066 } HAL_NOR_StatusTypeDef;
0067
0068 /**
0069   * @brief  FMC NOR ID typedef
0070   */
0071 typedef struct
0072 {
0073   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
0074
0075   uint16_t Device_Code1;
0076
0077   uint16_t Device_Code2;
0078
0079   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
0080                                     These codes can be accessed by performing read operations with specific
0081                                     control signals and addresses set.They can also be accessed by issuing
0082                                     an Auto Select command                                                   */
0083 } NOR_IDTypeDef;
0084
0085 /**
0086   * @brief  FMC NOR CFI typedef
0087   */
0088 typedef struct
0089 {
0090   /*!< Defines the information stored in the memory's Common flash interface
0091        which contains a description of various electrical and timing parameters,
0092        density information and functions supported by the memory                   */
0093
0094   uint16_t CFI_1;
0095
0096   uint16_t CFI_2;
0097
0098   uint16_t CFI_3;
0099
0100   uint16_t CFI_4;
0101 } NOR_CFITypeDef;
0102
0103 /**
0104   * @brief  NOR handle Structure definition
0105   */
0106 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
0107 typedef struct __NOR_HandleTypeDef
0108 #else
0109 typedef struct
0110 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */
0111
0112 {
0113   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
0114
0115   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
0116
0117   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
0118
0119   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
0120
0121   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
0122
0123   uint32_t                      CommandSet;   /*!< NOR algorithm command set and control        */
0124
0125 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
0126   void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor);               /*!< NOR Msp Init callback              */
0127   void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor);             /*!< NOR Msp DeInit callback            */
0128 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
0129 } NOR_HandleTypeDef;
0130
0131 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
0132 /**
0133   * @brief  HAL NOR Callback ID enumeration definition
0134   */
0135 typedef enum
0136 {
0137   HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */
0138   HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */
0139 } HAL_NOR_CallbackIDTypeDef;
0140
0141 /**
0142   * @brief  HAL NOR Callback pointer definition
0143   */
0144 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
0145 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
0146 /**
0147   * @}
0148   */
0149
0150 /* Exported constants --------------------------------------------------------*/
0151 /* Exported macro ------------------------------------------------------------*/
0152 /** @defgroup NOR_Exported_Macros NOR Exported Macros
0153   * @ingroup RTEMSBSPsARMSTM32H7
0154   * @{
0155   */
0156 /** @brief Reset NOR handle state
0157   * @param  __HANDLE__ specifies the NOR handle.
0158   * @retval None
0159   */
0160 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
0161 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \
0162                                                                (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \
0163                                                                (__HANDLE__)->MspInitCallback = NULL;       \
0164                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
0165                                                              } while(0)
0166 #else
0167 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
0168 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
0169 /**
0170   * @}
0171   */
0172
0173 /* Exported functions --------------------------------------------------------*/
0174 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
0175   * @{
0176   */
0177
0178 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
0179   * @{
0180   */
0181
0182 /* Initialization/de-initialization functions  ********************************/
0183 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
0184                                FMC_NORSRAM_TimingTypeDef *ExtTiming);
0185 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
0186 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
0187 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
0188 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
0189 /**
0190   * @}
0191   */
0192
0193 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
0194   * @{
0195   */
0196
0197 /* I/O operation functions  ***************************************************/
0198 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
0199 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
0200 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
0201 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
0202
0203 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
0204                                      uint32_t uwBufferSize);
0205 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
0206                                         uint32_t uwBufferSize);
0207
0208 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
0209 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
0210 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
0211
0212 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
0213 /* NOR callback registering/unregistering */
0214 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
0215                                            pNOR_CallbackTypeDef pCallback);
0216 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
0217 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
0218 /**
0219   * @}
0220   */
0221
0222 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
0223   * @{
0224   */
0225
0226 /* NOR Control functions  *****************************************************/
0227 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
0228 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
0229 /**
0230   * @}
0231   */
0232
0233 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
0234   * @{
0235   */
0236
0237 /* NOR State functions ********************************************************/
0238 HAL_NOR_StateTypeDef  HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
0239 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
0240 /**
0241   * @}
0242   */
0243
0244 /**
0245   * @}
0246   */
0247
0248 /* Private types -------------------------------------------------------------*/
0249 /* Private variables ---------------------------------------------------------*/
0250 /* Private constants ---------------------------------------------------------*/
0251 /** @defgroup NOR_Private_Constants NOR Private Constants
0252   * @ingroup RTEMSBSPsARMSTM32H7
0253   * @{
0254   */
0255 /* NOR device IDs addresses */
0256 #define MC_ADDRESS               ((uint16_t)0x0000)
0257 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
0258 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
0259 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
0260
0261 /* NOR CFI IDs addresses */
0262 #define CFI1_ADDRESS             ((uint16_t)0x0061)
0263 #define CFI2_ADDRESS             ((uint16_t)0x0062)
0264 #define CFI3_ADDRESS             ((uint16_t)0x0063)
0265 #define CFI4_ADDRESS             ((uint16_t)0x0064)
0266
0267 /* NOR operation wait timeout */
0268 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
0269
0270 /* NOR memory data width */
0271 #define NOR_MEMORY_8B            ((uint8_t)0x00)
0272 #define NOR_MEMORY_16B           ((uint8_t)0x01)
0273
0274 /* NOR memory device read/write start address */
0275 #define NOR_MEMORY_ADRESS1       (0x60000000U)
0276 #define NOR_MEMORY_ADRESS2       (0x64000000U)
0277 #define NOR_MEMORY_ADRESS3       (0x68000000U)
0278 #define NOR_MEMORY_ADRESS4       (0x6C000000U)
0279 /**
0280   * @}
0281   */
0282
0283 /* Private macros ------------------------------------------------------------*/
0284 /** @defgroup NOR_Private_Macros NOR Private Macros
0285   * @ingroup RTEMSBSPsARMSTM32H7
0286   * @{
0287   */
0288 /**
0289   * @brief  NOR memory address shifting.
0290   * @param  __NOR_ADDRESS NOR base address
0291   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
0292   * @param  __ADDRESS__ NOR memory address
0293   * @retval NOR shifted address value
0294   */
0295 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \
0296   ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \
0297               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
0298               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
0299
0300 /**
0301   * @brief  NOR memory write data to specified address.
0302   * @param  __ADDRESS__ NOR memory address
0303   * @param  __DATA__ Data to write
0304   * @retval None
0305   */
0306 #define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \
0307                                                (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
0308                                                __DSB();                                                    \
0309                                              } while(0)
0310
0311 /**
0312   * @}
0313   */
0314
0315 /**
0316   * @}
0317   */
0318
0319 /**
0320   * @}
0321   */
0322
0323
0324 #ifdef __cplusplus
0325 }
0326 #endif
0327
0328 #endif /* STM32H7xx_HAL_NOR_H */