stm32h7/include/stm32h7xx_hal_nand.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_nand.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of NAND HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_NAND_H
0021 #define STM32H7xx_HAL_NAND_H
0022
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026
0027
0028 /* Includes ------------------------------------------------------------------*/
0029 #include "stm32h7xx_ll_fmc.h"
0030
0031 /** @addtogroup STM32H7xx_HAL_Driver
0032   * @{
0033   */
0034
0035 /** @addtogroup NAND
0036   * @{
0037   */
0038
0039 /* Exported typedef ----------------------------------------------------------*/
0040 /* Exported types ------------------------------------------------------------*/
0041 /** @defgroup NAND_Exported_Types NAND Exported Types
0042   * @ingroup RTEMSBSPsARMSTM32H7
0043   * @{
0044   */
0045
0046 /**
0047   * @brief  HAL NAND State structures definition
0048   */
0049 typedef enum
0050 {
0051   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
0052   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
0053   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
0054   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
0055 } HAL_NAND_StateTypeDef;
0056
0057 /**
0058   * @brief  NAND Memory electronic signature Structure definition
0059   */
0060 typedef struct
0061 {
0062   /*<! NAND memory electronic signature maker and device IDs */
0063
0064   uint8_t Maker_Id;
0065
0066   uint8_t Device_Id;
0067
0068   uint8_t Third_Id;
0069
0070   uint8_t Fourth_Id;
0071 } NAND_IDTypeDef;
0072
0073 /**
0074   * @brief  NAND Memory address Structure definition
0075   */
0076 typedef struct
0077 {
0078   uint16_t Page;   /*!< NAND memory Page address  */
0079
0080   uint16_t Plane;   /*!< NAND memory Zone address  */
0081
0082   uint16_t Block;  /*!< NAND memory Block address */
0083
0084 } NAND_AddressTypeDef;
0085
0086 /**
0087   * @brief  NAND Memory info Structure definition
0088   */
0089 typedef struct
0090 {
0091   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
0092                                               for 8 bits addressing or words for 16 bits addressing             */
0093
0094   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
0095                                               for 8 bits addressing or words for 16 bits addressing             */
0096
0097   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
0098
0099   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
0100
0101   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
0102
0103   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
0104
0105   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
0106                                               parameter is mandatory for some NAND parts after the read
0107                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
0108                                               This parameter could be ENABLE or DISABLE
0109                                               Please check the Read Mode sequence in the NAND device datasheet */
0110 } NAND_DeviceConfigTypeDef;
0111
0112 /**
0113   * @brief  NAND handle Structure definition
0114   */
0115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
0116 typedef struct __NAND_HandleTypeDef
0117 #else
0118 typedef struct
0119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
0120 {
0121   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
0122
0123   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
0124
0125   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
0126
0127   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
0128
0129   NAND_DeviceConfigTypeDef       Config;     /*!< NAND physical characteristic information structure    */
0130
0131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
0132   void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand);               /*!< NAND Msp Init callback              */
0133   void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand);             /*!< NAND Msp DeInit callback            */
0134   void (* ItCallback)(struct __NAND_HandleTypeDef *hnand);                    /*!< NAND IT callback                    */
0135 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
0136 } NAND_HandleTypeDef;
0137
0138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
0139 /**
0140   * @brief  HAL NAND Callback ID enumeration definition
0141   */
0142 typedef enum
0143 {
0144   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
0145   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
0146   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
0147 } HAL_NAND_CallbackIDTypeDef;
0148
0149 /**
0150   * @brief  HAL NAND Callback pointer definition
0151   */
0152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
0153 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
0154
0155 /**
0156   * @}
0157   */
0158
0159 /* Exported constants --------------------------------------------------------*/
0160 /* Exported macro ------------------------------------------------------------*/
0161 /** @defgroup NAND_Exported_Macros NAND Exported Macros
0162   * @ingroup RTEMSBSPsARMSTM32H7
0163   * @{
0164   */
0165
0166 /** @brief Reset NAND handle state
0167   * @param  __HANDLE__ specifies the NAND handle.
0168   * @retval None
0169   */
0170 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
0171 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
0172                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
0173                                                                (__HANDLE__)->MspInitCallback = NULL;       \
0174                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
0175                                                              } while(0)
0176 #else
0177 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
0178 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
0179
0180 /**
0181   * @}
0182   */
0183
0184 /* Exported functions --------------------------------------------------------*/
0185 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
0186   * @{
0187   */
0188
0189 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
0190   * @{
0191   */
0192
0193 /* Initialization/de-initialization functions  ********************************/
0194 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
0195                                  FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
0196 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
0197
0198 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
0199
0200 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
0201
0202 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
0203 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
0204 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
0205 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
0206
0207 /**
0208   * @}
0209   */
0210
0211 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
0212   * @{
0213   */
0214
0215 /* IO operation functions  ****************************************************/
0216 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
0217
0218 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0219                                          uint8_t *pBuffer, uint32_t NumPageToRead);
0220 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0221                                           const uint8_t *pBuffer, uint32_t NumPageToWrite);
0222 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0223                                               uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
0224 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0225                                                const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
0226
0227 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0228                                           uint16_t *pBuffer, uint32_t NumPageToRead);
0229 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0230                                            const uint16_t *pBuffer, uint32_t NumPageToWrite);
0231 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0232                                                uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
0233 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
0234                                                 const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
0235
0236 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
0237
0238 uint32_t           HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
0239
0240 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
0241 /* NAND callback registering/unregistering */
0242 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
0243                                              pNAND_CallbackTypeDef pCallback);
0244 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
0245 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
0246
0247 /**
0248   * @}
0249   */
0250
0251 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
0252   * @{
0253   */
0254
0255 /* NAND Control functions  ****************************************************/
0256 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
0257 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
0258 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
0259
0260 /**
0261   * @}
0262   */
0263
0264 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
0265   * @{
0266   */
0267 /* NAND State functions *******************************************************/
0268 HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
0269 uint32_t              HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
0270 /**
0271   * @}
0272   */
0273
0274 /**
0275   * @}
0276   */
0277
0278 /* Private types -------------------------------------------------------------*/
0279 /* Private variables ---------------------------------------------------------*/
0280 /* Private constants ---------------------------------------------------------*/
0281 /** @defgroup NAND_Private_Constants NAND Private Constants
0282   * @ingroup RTEMSBSPsARMSTM32H7
0283   * @{
0284   */
0285 #define NAND_DEVICE                0x80000000UL
0286 #define NAND_WRITE_TIMEOUT         0x01000000UL
0287
0288 #define CMD_AREA                   (1UL<<16U)  /* A16 = CLE high */
0289 #define ADDR_AREA                  (1UL<<17U)  /* A17 = ALE high */
0290
0291 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
0292 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
0293 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
0294 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
0295
0296 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
0297 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
0298 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
0299 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
0300 #define NAND_CMD_READID            ((uint8_t)0x90)
0301 #define NAND_CMD_STATUS            ((uint8_t)0x70)
0302 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
0303 #define NAND_CMD_RESET             ((uint8_t)0xFF)
0304
0305 /* NAND memory status */
0306 #define NAND_VALID_ADDRESS         0x00000100UL
0307 #define NAND_INVALID_ADDRESS       0x00000200UL
0308 #define NAND_TIMEOUT_ERROR         0x00000400UL
0309 #define NAND_BUSY                  0x00000000UL
0310 #define NAND_ERROR                 0x00000001UL
0311 #define NAND_READY                 0x00000040UL
0312 /**
0313   * @}
0314   */
0315
0316 /* Private macros ------------------------------------------------------------*/
0317 /** @defgroup NAND_Private_Macros NAND Private Macros
0318   * @ingroup RTEMSBSPsARMSTM32H7
0319   * @{
0320   */
0321
0322 /**
0323   * @brief  NAND memory address computation.
0324   * @param  __ADDRESS__ NAND memory address.
0325   * @param  __HANDLE__  NAND handle.
0326   * @retval NAND Raw address value
0327   */
0328 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
0329                                                  (((__ADDRESS__)->Block + \
0330                                                    (((__ADDRESS__)->Plane) * \
0331                                                     ((__HANDLE__)->Config.PlaneSize))) * \
0332                                                   ((__HANDLE__)->Config.BlockSize)))
0333
0334 /**
0335   * @brief  NAND memory Column address computation.
0336   * @param  __HANDLE__ NAND handle.
0337   * @retval NAND Raw address value
0338   */
0339 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
0340
0341 /**
0342   * @brief  NAND memory address cycling.
0343   * @param  __ADDRESS__ NAND memory address.
0344   * @retval NAND address cycling value.
0345   */
0346 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
0347 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
0348 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
0349 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
0350
0351 /**
0352   * @brief  NAND memory Columns cycling.
0353   * @param  __ADDRESS__ NAND memory address.
0354   * @retval NAND Column address cycling value.
0355   */
0356 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
0357 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
0358
0359 /**
0360   * @}
0361   */
0362
0363 /**
0364   * @}
0365   */
0366
0367 /**
0368   * @}
0369   */
0370
0371 /**
0372   * @}
0373   */
0374
0375
0376 #ifdef __cplusplus
0377 }
0378 #endif
0379
0380 #endif /* STM32H7xx_HAL_NAND_H */