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File indexing completed on 2025-05-11 08:23:35
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_hal_mdma.h 0004 * @author MCD Application Team 0005 * @brief Header file of DMA HAL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_HAL_MDMA_H 0021 #define STM32H7xx_HAL_MDMA_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx_hal_def.h" 0029 0030 /** @addtogroup STM32H7xx_HAL_Driver 0031 * @{ 0032 */ 0033 0034 /** @addtogroup MDMA 0035 * @{ 0036 */ 0037 0038 /* Exported types ------------------------------------------------------------*/ 0039 0040 /** @defgroup MDMA_Exported_Types MDMA Exported Types 0041 * @ingroup RTEMSBSPsARMSTM32H7 0042 * @brief MDMA Exported Types 0043 * @{ 0044 */ 0045 0046 /** 0047 * @brief MDMA Configuration Structure definition 0048 */ 0049 typedef struct 0050 { 0051 0052 uint32_t Request; /*!< Specifies the MDMA request. 0053 This parameter can be a value of @ref MDMA_Request_selection*/ 0054 0055 uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : 0056 a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer 0057 This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ 0058 0059 uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. 0060 This parameter can be a value of @ref MDMA_Priority_level */ 0061 0062 uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. 0063 This parameter can be a value of @ref MDMA_Endianness */ 0064 0065 uint32_t SourceInc; /*!< Specifies if the Source increment mode . 0066 This parameter can be a value of @ref MDMA_Source_increment_mode */ 0067 0068 uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . 0069 This parameter can be a value of @ref MDMA_Destination_increment_mode */ 0070 0071 uint32_t SourceDataSize; /*!< Specifies the source data size. 0072 This parameter can be a value of @ref MDMA_Source_data_size */ 0073 0074 uint32_t DestDataSize; /*!< Specifies the destination data size. 0075 This parameter can be a value of @ref MDMA_Destination_data_size */ 0076 0077 0078 uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. 0079 This parameter can be a value of @ref MDMA_data_Alignment */ 0080 0081 uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), 0082 this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ 0083 0084 uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. 0085 It specifies the amount of data to be transferred in a single non interruptible 0086 transaction. 0087 This parameter can be a value of @ref MDMA_Source_burst 0088 @note : the burst may be FIXED/INCR based on SourceInc value , 0089 the BURST must be programmed as to ensure that the burst size will be lower than than 0090 BufferTransferLength */ 0091 0092 uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. 0093 It specifies the amount of data to be transferred in a single non interruptible 0094 transaction. 0095 This parameter can be a value of @ref MDMA_Destination_burst 0096 @note : the burst may be FIXED/INCR based on DestinationInc value , 0097 the BURST must be programmed as to ensure that the burst size will be lower than than 0098 BufferTransferLength */ 0099 0100 int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset 0101 signed value : if > 0 then increment the next block source Address by offset from where the last block ends 0102 if < 0 then decrement the next block source Address by offset from where the last block ends 0103 if == 0, the next block source address starts from where the last block ends 0104 */ 0105 0106 0107 int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset 0108 signed value : if > 0 then increment the next block destination Address by offset from where the last block ends 0109 if < 0 then decrement the next block destination Address by offset from where the last block ends 0110 if == 0, the next block destination address starts from where the last block ends 0111 */ 0112 0113 }MDMA_InitTypeDef; 0114 0115 /** 0116 * @brief HAL MDMA linked list node structure definition 0117 * @note The Linked list node allows to define a new MDMA configuration 0118 * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). 0119 * When CLAR register is configured to a non NULL value , each time a transfer ends, 0120 * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. 0121 */ 0122 typedef struct 0123 { 0124 __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ 0125 __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ 0126 __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ 0127 __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ 0128 __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ 0129 __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ 0130 __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ 0131 __IO uint32_t Reserved; /*!< Reserved register */ 0132 __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ 0133 __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ 0134 0135 }MDMA_LinkNodeTypeDef; 0136 0137 /** 0138 * @brief HAL MDMA linked list node configuration structure definition 0139 * @note used with HAL_MDMA_LinkedList_CreateNode function 0140 */ 0141 typedef struct 0142 { 0143 MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ 0144 uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ 0145 uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ 0146 uint32_t BlockDataLength; /*!< The data length of a block in bytes */ 0147 uint32_t BlockCount; /*!< The number of blocks to be transferred */ 0148 0149 uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. 0150 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ 0151 0152 uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. 0153 PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ 0154 0155 0156 }MDMA_LinkNodeConfTypeDef; 0157 0158 0159 /** 0160 * @brief HAL MDMA State structure definition 0161 */ 0162 typedef enum 0163 { 0164 HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ 0165 HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ 0166 HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ 0167 HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ 0168 HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ 0169 0170 }HAL_MDMA_StateTypeDef; 0171 0172 /** 0173 * @brief HAL MDMA Level Complete structure definition 0174 */ 0175 typedef enum 0176 { 0177 HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 0178 HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ 0179 HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ 0180 HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ 0181 0182 }HAL_MDMA_LevelCompleteTypeDef; 0183 0184 /** 0185 * @brief HAL MDMA Callbacks IDs structure definition 0186 */ 0187 typedef enum 0188 { 0189 HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 0190 HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */ 0191 HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */ 0192 HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */ 0193 HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 0194 HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 0195 HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 0196 0197 }HAL_MDMA_CallbackIDTypeDef; 0198 0199 0200 /** 0201 * @brief MDMA handle Structure definition 0202 */ 0203 typedef struct __MDMA_HandleTypeDef 0204 { 0205 MDMA_Channel_TypeDef *Instance; /*!< Register base address */ 0206 0207 MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ 0208 0209 HAL_LockTypeDef Lock; /*!< MDMA locking object */ 0210 0211 __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ 0212 0213 void *Parent; /*!< Parent object state */ 0214 0215 void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ 0216 0217 void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ 0218 0219 void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ 0220 0221 void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ 0222 0223 void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ 0224 0225 void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ 0226 0227 0228 MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list 0229 (after the initial node defined by the Init struct) 0230 this parameter is used internally by the MDMA driver 0231 to construct the linked list node 0232 */ 0233 0234 MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list 0235 this parameter is used internally by the MDMA driver 0236 to construct the linked list node 0237 */ 0238 uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ 0239 0240 __IO uint32_t ErrorCode; /*!< MDMA Error code */ 0241 0242 } MDMA_HandleTypeDef; 0243 0244 /** 0245 * @} 0246 */ 0247 0248 /* Exported constants --------------------------------------------------------*/ 0249 0250 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants 0251 * @ingroup RTEMSBSPsARMSTM32H7 0252 * @brief MDMA Exported constants 0253 * @{ 0254 */ 0255 0256 /** @defgroup MDMA_Error_Codes MDMA Error Codes 0257 * @ingroup RTEMSBSPsARMSTM32H7 0258 * @brief MDMA Error Codes 0259 * @{ 0260 */ 0261 #define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 0262 #define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ 0263 #define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ 0264 #define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */ 0265 #define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */ 0266 #define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ 0267 #define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ 0268 #define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ 0269 #define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ 0270 #define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ 0271 0272 /** 0273 * @} 0274 */ 0275 0276 /** @defgroup MDMA_Request_selection MDMA Request selection 0277 * @ingroup RTEMSBSPsARMSTM32H7 0278 * @brief MDMA_Request_selection 0279 * @{ 0280 */ 0281 0282 #define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */ 0283 #define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */ 0284 #define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */ 0285 #define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */ 0286 #define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */ 0287 #define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */ 0288 #define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */ 0289 #define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */ 0290 #define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */ 0291 #define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */ 0292 #define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */ 0293 #define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */ 0294 #define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */ 0295 #define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ 0296 #define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ 0297 #define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ 0298 #if defined (LTDC) 0299 #define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */ 0300 #endif /* LTDC */ 0301 #if defined (JPEG) 0302 #define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */ 0303 #define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */ 0304 #define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */ 0305 #define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */ 0306 #define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */ 0307 #endif /* JPEG */ 0308 #if defined (OCTOSPI1) 0309 #define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */ 0310 #define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */ 0311 #endif /* OCTOSPI1 */ 0312 #if defined (QUADSPI) 0313 #define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ 0314 #define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ 0315 #endif /* QUADSPI */ 0316 #define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */ 0317 #define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */ 0318 #define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */ 0319 0320 #if defined (DSI) 0321 #define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */ 0322 #define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */ 0323 #endif /* DSI */ 0324 0325 #define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */ 0326 0327 #define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */ 0328 #define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */ 0329 0330 #if defined (OCTOSPI2) 0331 #define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */ 0332 #define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */ 0333 #endif /* OCTOSPI2 */ 0334 0335 #define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ 0336 0337 /** 0338 * @} 0339 */ 0340 0341 /** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode 0342 * @ingroup RTEMSBSPsARMSTM32H7 0343 * @brief MDMA Transfer Trigger Mode 0344 * @{ 0345 */ 0346 #define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ 0347 #define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ 0348 #define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ 0349 #define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ 0350 0351 /** 0352 * @} 0353 */ 0354 0355 /** @defgroup MDMA_Priority_level MDMA Priority level 0356 * @ingroup RTEMSBSPsARMSTM32H7 0357 * @brief MDMA Priority level 0358 * @{ 0359 */ 0360 #define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ 0361 #define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */ 0362 #define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */ 0363 #define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */ 0364 0365 /** 0366 * @} 0367 */ 0368 0369 0370 /** @defgroup MDMA_Endianness MDMA Endianness 0371 * @ingroup RTEMSBSPsARMSTM32H7 0372 * @brief MDMA Endianness 0373 * @{ 0374 */ 0375 #define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ 0376 #define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ 0377 #define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ 0378 #define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ 0379 0380 /** 0381 * @} 0382 */ 0383 0384 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode 0385 * @ingroup RTEMSBSPsARMSTM32H7 0386 * @brief MDMA Source increment mode 0387 * @{ 0388 */ 0389 #define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ 0390 #define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ 0391 #define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ 0392 #define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ 0393 #define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ 0394 #define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ 0395 #define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ 0396 #define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ 0397 #define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ 0398 0399 /** 0400 * @} 0401 */ 0402 0403 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode 0404 * @ingroup RTEMSBSPsARMSTM32H7 0405 * @brief MDMA Destination increment mode 0406 * @{ 0407 */ 0408 #define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ 0409 #define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ 0410 #define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ 0411 #define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ 0412 #define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ 0413 #define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ 0414 #define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ 0415 #define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ 0416 #define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ 0417 0418 /** 0419 * @} 0420 */ 0421 0422 /** @defgroup MDMA_Source_data_size MDMA Source data size 0423 * @ingroup RTEMSBSPsARMSTM32H7 0424 * @brief MDMA Source data size 0425 * @{ 0426 */ 0427 #define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ 0428 #define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ 0429 #define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ 0430 #define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ 0431 0432 /** 0433 * @} 0434 */ 0435 0436 /** @defgroup MDMA_Destination_data_size MDMA Destination data size 0437 * @ingroup RTEMSBSPsARMSTM32H7 0438 * @brief MDMA Destination data size 0439 * @{ 0440 */ 0441 #define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ 0442 #define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ 0443 #define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ 0444 #define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ 0445 0446 /** 0447 * @} 0448 */ 0449 0450 /** @defgroup MDMA_data_Alignment MDMA data alignment 0451 * @ingroup RTEMSBSPsARMSTM32H7 0452 * @brief MDMA data alignment 0453 * @{ 0454 */ 0455 #define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size 0456 All data are right aligned, in Little Endien mode. */ 0457 #define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ 0458 #define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , 0459 Note : this mode is allowed only if the Source data size is smaller than Destination data size */ 0460 #define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ 0461 0462 /** 0463 * @} 0464 */ 0465 0466 /** @defgroup MDMA_Source_burst MDMA Source burst 0467 * @ingroup RTEMSBSPsARMSTM32H7 0468 * @brief MDMA Source burst 0469 * @{ 0470 */ 0471 #define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ 0472 #define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ 0473 #define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ 0474 #define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ 0475 #define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ 0476 #define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ 0477 #define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ 0478 #define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ 0479 0480 /** 0481 * @} 0482 */ 0483 0484 /** @defgroup MDMA_Destination_burst MDMA Destination burst 0485 * @ingroup RTEMSBSPsARMSTM32H7 0486 * @brief MDMA Destination burst 0487 * @{ 0488 */ 0489 #define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ 0490 #define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ 0491 #define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ 0492 #define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ 0493 #define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ 0494 #define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ 0495 #define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ 0496 #define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ 0497 0498 /** 0499 * @} 0500 */ 0501 0502 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions 0503 * @ingroup RTEMSBSPsARMSTM32H7 0504 * @brief MDMA interrupt enable definitions 0505 * @{ 0506 */ 0507 #define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ 0508 #define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ 0509 #define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ 0510 #define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ 0511 #define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ 0512 0513 /** 0514 * @} 0515 */ 0516 0517 /** @defgroup MDMA_flag_definitions MDMA flag definitions 0518 * @ingroup RTEMSBSPsARMSTM32H7 0519 * @brief MDMA flag definitions 0520 * @{ 0521 */ 0522 #define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ 0523 #define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ 0524 #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ 0525 #define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ 0526 #define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ 0527 #define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */ 0528 0529 /** 0530 * @} 0531 */ 0532 0533 /** 0534 * @} 0535 */ 0536 0537 /* Exported macro ------------------------------------------------------------*/ 0538 0539 /** @defgroup MDMA_Exported_Macros MDMA Exported Macros 0540 * @ingroup RTEMSBSPsARMSTM32H7 0541 * @{ 0542 */ 0543 0544 /** 0545 * @brief Enable the specified MDMA Channel. 0546 * @param __HANDLE__: MDMA handle 0547 * @retval None 0548 */ 0549 #define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) 0550 0551 /** 0552 * @brief Disable the specified MDMA Channel. 0553 * @param __HANDLE__: MDMA handle 0554 * @retval None 0555 */ 0556 #define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) 0557 0558 /** 0559 * @brief Get the MDMA Channel pending flags. 0560 * @param __HANDLE__: MDMA handle 0561 * @param __FLAG__: Get the specified flag. 0562 * This parameter can be any combination of the following values: 0563 * @arg MDMA_FLAG_TE : Transfer Error flag. 0564 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. 0565 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. 0566 * @arg MDMA_FLAG_BT : Block Transfer complete flag. 0567 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. 0568 * @arg MDMA_FLAG_CRQA : Channel request Active flag. 0569 * @retval The state of FLAG (SET or RESET). 0570 */ 0571 #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) 0572 0573 /** 0574 * @brief Clear the MDMA Stream pending flags. 0575 * @param __HANDLE__: MDMA handle 0576 * @param __FLAG__: specifies the flag to clear. 0577 * This parameter can be any combination of the following values: 0578 * @arg MDMA_FLAG_TE : Transfer Error flag. 0579 * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. 0580 * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. 0581 * @arg MDMA_FLAG_BT : Block Transfer complete flag. 0582 * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. 0583 * @retval None 0584 */ 0585 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) 0586 0587 /** 0588 * @brief Enables the specified MDMA Channel interrupts. 0589 * @param __HANDLE__: MDMA handle 0590 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 0591 * This parameter can be any combination of the following values: 0592 * @arg MDMA_IT_TE : Transfer Error interrupt mask 0593 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 0594 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 0595 * @arg MDMA_IT_BT : Block Transfer interrupt mask 0596 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 0597 * @retval None 0598 */ 0599 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 0600 0601 /** 0602 * @brief Disables the specified MDMA Channel interrupts. 0603 * @param __HANDLE__: MDMA handle 0604 * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. 0605 * This parameter can be any combination of the following values: 0606 * @arg MDMA_IT_TE : Transfer Error interrupt mask 0607 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 0608 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 0609 * @arg MDMA_IT_BT : Block Transfer interrupt mask 0610 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 0611 * @retval None 0612 */ 0613 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 0614 0615 /** 0616 * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. 0617 * @param __HANDLE__: MDMA handle 0618 * @param __INTERRUPT__: specifies the MDMA interrupt source to check. 0619 * @arg MDMA_IT_TE : Transfer Error interrupt mask 0620 * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask 0621 * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask 0622 * @arg MDMA_IT_BT : Block Transfer interrupt mask 0623 * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask 0624 * @retval The state of MDMA_IT (SET or RESET). 0625 */ 0626 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 0627 0628 /** 0629 * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. 0630 * @param __HANDLE__ : MDMA handle 0631 * @param __COUNTER__: Number of data in bytes to be transferred. 0632 * @retval None 0633 */ 0634 #define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) 0635 0636 /** 0637 * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. 0638 * @param __HANDLE__ : MDMA handle 0639 * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. 0640 */ 0641 #define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) 0642 0643 /** 0644 * @} 0645 */ 0646 0647 /* Exported functions --------------------------------------------------------*/ 0648 /** @defgroup MDMA_Exported_Functions MDMA Exported Functions 0649 * @ingroup RTEMSBSPsARMSTM32H7 0650 * @{ 0651 */ 0652 0653 /* Initialization and de-initialization functions *****************************/ 0654 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions 0655 * @ingroup RTEMSBSPsARMSTM32H7 0656 * @brief Initialization and de-initialization functions 0657 * @{ 0658 */ 0659 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); 0660 HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma); 0661 HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData); 0662 0663 HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)); 0664 HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID); 0665 0666 /** 0667 * @} 0668 */ 0669 0670 /* Linked list operation functions ********************************************/ 0671 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions 0672 * @ingroup RTEMSBSPsARMSTM32H7 0673 * @brief Linked list operation functions 0674 * @{ 0675 */ 0676 0677 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); 0678 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); 0679 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); 0680 HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); 0681 HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); 0682 0683 0684 /** 0685 * @} 0686 */ 0687 0688 /* IO operation functions *****************************************************/ 0689 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions 0690 * @ingroup RTEMSBSPsARMSTM32H7 0691 * @brief I/O operation functions 0692 * @{ 0693 */ 0694 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); 0695 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); 0696 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); 0697 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); 0698 HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 0699 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); 0700 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); 0701 0702 /** 0703 * @} 0704 */ 0705 0706 /* Peripheral State and Error functions ***************************************/ 0707 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions 0708 * @ingroup RTEMSBSPsARMSTM32H7 0709 * @brief Peripheral State functions 0710 * @{ 0711 */ 0712 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); 0713 uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); 0714 0715 /** 0716 * @} 0717 */ 0718 0719 /** 0720 * @} 0721 */ 0722 0723 /* Private types -------------------------------------------------------------*/ 0724 /** @defgroup MDMA_Private_Types MDMA Private Types 0725 * @ingroup RTEMSBSPsARMSTM32H7 0726 * @{ 0727 */ 0728 0729 /** 0730 * @} 0731 */ 0732 0733 /* Private defines -----------------------------------------------------------*/ 0734 /** @defgroup MDMA_Private_Defines MDMA Private Defines 0735 * @ingroup RTEMSBSPsARMSTM32H7 0736 * @{ 0737 */ 0738 0739 /** 0740 * @} 0741 */ 0742 0743 /* Private variables ---------------------------------------------------------*/ 0744 /** @defgroup MDMA_Private_Variables MDMA Private Variables 0745 * @ingroup RTEMSBSPsARMSTM32H7 0746 * @{ 0747 */ 0748 0749 /** 0750 * @} 0751 */ 0752 0753 /* Private constants ---------------------------------------------------------*/ 0754 /** @defgroup MDMA_Private_Constants MDMA Private Constants 0755 * @ingroup RTEMSBSPsARMSTM32H7 0756 * @{ 0757 */ 0758 0759 /** 0760 * @} 0761 */ 0762 0763 /* Private macros ------------------------------------------------------------*/ 0764 /** @defgroup MDMA_Private_Macros MDMA Private Macros 0765 * @ingroup RTEMSBSPsARMSTM32H7 0766 * @{ 0767 */ 0768 0769 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ 0770 ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ 0771 ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ 0772 ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) 0773 0774 0775 #define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ 0776 ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ 0777 ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ 0778 ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) 0779 0780 #define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ 0781 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ 0782 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ 0783 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) 0784 0785 0786 #if defined (OCTOSPI2) 0787 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC)) 0788 #else 0789 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) 0790 #endif /* OCTOSPI2 */ 0791 0792 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ 0793 ((__INC__) == MDMA_SRC_INC_BYTE ) || \ 0794 ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \ 0795 ((__INC__) == MDMA_SRC_INC_WORD ) || \ 0796 ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \ 0797 ((__INC__) == MDMA_SRC_DEC_BYTE) || \ 0798 ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \ 0799 ((__INC__) == MDMA_SRC_DEC_WORD) || \ 0800 ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) 0801 0802 #define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \ 0803 ((__INC__) == MDMA_DEST_INC_BYTE ) || \ 0804 ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \ 0805 ((__INC__) == MDMA_DEST_INC_WORD ) || \ 0806 ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \ 0807 ((__INC__) == MDMA_DEST_DEC_BYTE) || \ 0808 ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \ 0809 ((__INC__) == MDMA_DEST_DEC_WORD) || \ 0810 ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) 0811 0812 #define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \ 0813 ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \ 0814 ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \ 0815 ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) 0816 0817 #define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \ 0818 ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \ 0819 ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \ 0820 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) 0821 0822 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ 0823 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ 0824 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ 0825 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) 0826 0827 0828 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ 0829 ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \ 0830 ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \ 0831 ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \ 0832 ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \ 0833 ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \ 0834 ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ 0835 ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) 0836 0837 0838 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ 0839 ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ 0840 ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ 0841 ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \ 0842 ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \ 0843 ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \ 0844 ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \ 0845 ((__BURST__) == MDMA_DEST_BURST_128BEATS)) 0846 0847 #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ 0848 ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ 0849 ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ 0850 ((__MODE__) == MDMA_FULL_TRANSFER)) 0851 0852 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) 0853 0854 #define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) 0855 0856 #define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) 0857 0858 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) 0859 0860 /** 0861 * @} 0862 */ 0863 0864 /* Private functions prototypes ----------------------------------------------*/ 0865 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes 0866 * @ingroup RTEMSBSPsARMSTM32H7 0867 * @{ 0868 */ 0869 0870 /** 0871 * @} 0872 */ 0873 0874 /* Private functions ---------------------------------------------------------*/ 0875 /** @defgroup MDMA_Private_Functions MDMA Private Functions 0876 * @ingroup RTEMSBSPsARMSTM32H7 0877 * @{ 0878 */ 0879 0880 /** 0881 * @} 0882 */ 0883 0884 /** 0885 * @} 0886 */ 0887 0888 /** 0889 * @} 0890 */ 0891 0892 #ifdef __cplusplus 0893 } 0894 #endif 0895 0896 #endif /* STM32H7xx_HAL_MDMA_H */ 0897
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