stm32h7/include/stm32h7xx_hal_hrtim.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_hrtim.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of HRTIM HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_HRTIM_H
0021 #define STM32H7xx_HAL_HRTIM_H
0022
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif
0026
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029
0030 #if defined(HRTIM1)
0031 /** @addtogroup STM32H7xx_HAL_Driver
0032   * @{
0033   */
0034
0035 /** @addtogroup HRTIM HRTIM
0036   * @{
0037   */
0038
0039 /* Exported types ------------------------------------------------------------*/
0040 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
0041   * @{
0042   */
0043 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
0044   * @ingroup RTEMSBSPsARMSTM32H7
0045   * @{
0046   */
0047 #define MAX_HRTIM_TIMER 6U
0048 /**
0049   * @}
0050   */
0051 /**
0052   * @}
0053   */
0054
0055 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
0056   * @ingroup RTEMSBSPsARMSTM32H7
0057   * @{
0058   */
0059
0060 /**
0061   * @brief  HRTIM Configuration Structure definition - Time base related parameters
0062   */
0063 typedef struct
0064 {
0065   uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
0066                                           This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
0067   uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.
0068                                           The HRTIM instance can be configured to act as a slave (waiting for a trigger
0069                                           to be synchronized) or a master (generating a synchronization signal) or both.
0070                                           This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
0071   uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when
0072                                           the HRTIM instance is configured as a slave).
0073                                           This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
0074   uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
0075                                          (significant only when the HRTIM instance is configured as a master).
0076                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
0077   uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization
0078                                           outputs (significant only when the HRTIM instance is configured as a master).
0079                                           This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
0080 } HRTIM_InitTypeDef;
0081
0082 /**
0083   * @brief  HAL State structures definition
0084   */
0085 typedef enum
0086 {
0087   HAL_HRTIM_STATE_RESET            = 0x00U,    /*!< Peripheral is not yet Initialized                  */
0088   HAL_HRTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use           */
0089   HAL_HRTIM_STATE_BUSY             = 0x02U,    /*!< an internal process is ongoing                     */
0090   HAL_HRTIM_STATE_TIMEOUT          = 0x06U,    /*!< Timeout state                                      */
0091   HAL_HRTIM_STATE_ERROR            = 0x07U,    /*!< Error state                                        */
0092 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0093   HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U    /*!< Invalid Callback error */
0094 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
0095 } HAL_HRTIM_StateTypeDef;
0096
0097 /**
0098   * @brief HRTIM Timer Structure definition
0099   */
0100 typedef struct
0101 {
0102   uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
0103                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
0104                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
0105   uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
0106                                        When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
0107                                        When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
0108   uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
0109   uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
0110   uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
0111   uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
0112   uint32_t DMASize;                /*!< Size of the DMA transfer */
0113 } HRTIM_TimerParamTypeDef;
0114
0115 /**
0116   * @brief  HRTIM Handle Structure definition
0117   */
0118 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0119 typedef struct __HRTIM_HandleTypeDef
0120 #else
0121 typedef struct
0122 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
0123 {
0124   HRTIM_TypeDef *              Instance;                     /*!< Register base address */
0125
0126   HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
0127
0128   HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
0129
0130   HAL_LockTypeDef              Lock;                         /*!< Locking object          */
0131
0132   __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
0133
0134   DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */
0135   DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */
0136   DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */
0137   DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */
0138   DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */
0139   DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */
0140
0141 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0142   void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 1 interrupt callback function pointer                         */
0143   void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 2 interrupt callback function pointer                         */
0144   void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 3 interrupt callback function pointer                         */
0145   void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 4 interrupt callback function pointer                         */
0146   void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 5 interrupt callback function pointer                         */
0147   void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                          /*!< System fault interrupt callback function pointer                    */
0148   void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                      /*!< Burst mode period interrupt callback function pointer               */
0149   void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                 /*!< Sync Input interrupt callback function pointer                      */
0150   void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                                /*!< DMA error callback function pointer                                 */
0151
0152   void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Update interrupt callback function pointer                  */
0153   void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Repetition interrupt callback function pointer              */
0154   void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 1 match interrupt callback function pointer         */
0155   void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 2 match interrupt callback function pointer         */
0156   void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 3 match interrupt callback function pointer         */
0157   void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 4 match interrupt callback function pointer         */
0158   void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 1 interrupts callback function pointer              */
0159   void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 2 interrupts callback function pointer              */
0160   void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer      */
0161   void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x counter reset/roll-over interrupt callback function pointer */
0162   void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 1 set interrupt callback function pointer            */
0163   void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 1 reset interrupt callback function pointer          */
0164   void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 2 set interrupt callback function pointer            */
0165   void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 2 reset interrupt callback function pointer          */
0166   void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);  /*!< Timer x Burst DMA completed interrupt callback function pointer     */
0167
0168   void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                              /*!< HRTIM MspInit callback function pointer                             */
0169   void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                            /*!< HRTIM MspInit callback function pointer                             */
0170 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
0171 } HRTIM_HandleTypeDef;
0172
0173 /**
0174   * @brief  Simple output compare mode configuration definition
0175   */
0176 typedef struct
0177 {
0178   uint32_t Period;                   /*!< Specifies the timer period.
0179                                           The period value must be above 3 periods of the fHRTIM clock.
0180                                           Maximum value is = 0xFFDFU */
0181   uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.
0182                                           This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
0183   uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
0184                                           This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
0185   uint32_t Mode;                     /*!< Specifies the counter operating mode.
0186                                           This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */
0187 } HRTIM_TimeBaseCfgTypeDef;
0188
0189 /**
0190   * @brief  Simple output compare mode configuration definition
0191   */
0192 typedef struct
0193 {
0194   uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).
0195                             This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
0196   uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
0197                             The compare value must be above or equal to 3 periods of the fHRTIM clock */
0198   uint32_t Polarity;   /*!< Specifies the output polarity.
0199                             This parameter can be any value of @ref HRTIM_Output_Polarity */
0200   uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.
0201                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
0202 } HRTIM_SimpleOCChannelCfgTypeDef;
0203
0204 /**
0205   * @brief  Simple PWM output mode configuration definition
0206   */
0207 typedef struct
0208 {
0209   uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
0210                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
0211   uint32_t Polarity;        /*!< Specifies the output polarity.
0212                                  This parameter can be any value of @ref HRTIM_Output_Polarity */
0213   uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.
0214                                  This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
0215 } HRTIM_SimplePWMChannelCfgTypeDef;
0216
0217 /**
0218   * @brief  Simple capture mode configuration definition
0219   */
0220 typedef struct
0221 {
0222   uint32_t Event;             /*!< Specifies the external event triggering the capture.
0223                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
0224   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
0225                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
0226   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
0227                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
0228   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
0229                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
0230 } HRTIM_SimpleCaptureChannelCfgTypeDef;
0231
0232 /**
0233   * @brief  Simple One Pulse mode configuration definition
0234   */
0235 typedef struct
0236 {
0237   uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
0238                                    The compare value must be above or equal to 3 periods of the fHRTIM clock */
0239   uint32_t OutputPolarity;    /*!< Specifies the output polarity.
0240                                    This parameter can be any value of @ref HRTIM_Output_Polarity */
0241   uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.
0242                                    This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
0243   uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.
0244                                    This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
0245   uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
0246                                    This parameter can be a value of @ref HRTIM_External_Event_Polarity */
0247   uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
0248                                    This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
0249   uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
0250                                    This parameter can be a value of @ref HRTIM_External_Event_Filter */
0251 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
0252
0253 /**
0254   * @brief  Timer configuration definition
0255   */
0256 typedef struct
0257 {
0258   uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.
0259                                        Specifies which interrupts requests must enabled for the timer.
0260                                        This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
0261                                        or @ref HRTIM_Timing_Unit_Interrupt_Enable */
0262   uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.
0263                                        Specifies which DMA requests must be enabled for the timer.
0264                                        This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
0265                                        or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
0266   uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.
0267                                        Specifies the address of the source address of the DMA transfer */
0268   uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.
0269                                        Specifies the address of the destination address of the DMA transfer */
0270   uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.
0271                                        Specifies the size of the DMA transfer */
0272   uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.
0273                                         Specifies whether or not half mode is enabled
0274                                         This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
0275   uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.
0276                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
0277                                         This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
0278   uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.
0279                                         Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
0280                                         This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
0281   uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.
0282                                         Indicates whether or not the a DAC synchronization event is generated.
0283                                         This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
0284   uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.
0285                                         Specifies whether or not register preload is enabled.
0286                                         This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
0287   uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.
0288                                         Specifies how the update occurs with respect to a burst DMA transaction or
0289                                         update enable inputs (Slave timers only).
0290                                         This parameter can be any value of @ref HRTIM_Update_Gating   */
0291   uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.
0292                                         Specifies how the timer behaves during a burst mode operation.
0293                                         This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
0294   uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.
0295                                         Specifies whether or not registers update is triggered by the repetition event.
0296                                         This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
0297   uint32_t PushPull;               /*!< Relevant for Timer A to Timer E.
0298                                         Specifies whether or not the push-pull mode is enabled.
0299                                         This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
0300   uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer E.
0301                                         Specifies which fault channels are enabled for the timer.
0302                                         This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
0303   uint32_t FaultLock;              /*!< Relevant for Timer A to Timer E.
0304                                         Specifies whether or not fault enabling status is write protected.
0305                                         This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
0306   uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer E.
0307                                         Specifies whether or not dead-time insertion is enabled for the timer.
0308                                         This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
0309   uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer E.
0310                                         Specifies the delayed protection mode.
0311                                         This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
0312   uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer E.
0313                                         Specifies source(s) triggering the timer registers update.
0314                                         This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
0315   uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer E.
0316                                         Specifies source(s) triggering the timer counter reset.
0317                                         This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
0318   uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer E.
0319                                         Specifies whether or not registers update is triggered when the timer counter is reset.
0320                                         This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
0321 } HRTIM_TimerCfgTypeDef;
0322
0323 /**
0324   * @brief  Compare unit configuration definition
0325   */
0326 typedef struct
0327 {
0328   uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.
0329                                       The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
0330                                       The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
0331   uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.
0332                                       This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
0333   uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
0334                                       CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */
0335 } HRTIM_CompareCfgTypeDef;
0336
0337 /**
0338   * @brief  Capture unit configuration definition
0339   */
0340 typedef struct
0341 {
0342   uint32_t Trigger;          /*!< Specifies source(s) triggering the capture.
0343                                   This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
0344 } HRTIM_CaptureCfgTypeDef;
0345
0346 /**
0347   * @brief  Output configuration definition
0348   */
0349 typedef struct
0350 {
0351   uint32_t Polarity;                    /*!< Specifies the output polarity.
0352                                              This parameter can be any value of @ref HRTIM_Output_Polarity */
0353   uint32_t SetSource;                   /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
0354                                              This parameter can be a combination of @ref HRTIM_Output_Set_Source */
0355   uint32_t ResetSource;                 /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
0356                                              This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
0357   uint32_t IdleMode;                    /*!< Specifies whether or not the output is affected by a burst mode operation.
0358                                              This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
0359   uint32_t IdleLevel;                   /*!< Specifies whether the output level is active or inactive when in IDLE state.
0360                                              This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
0361   uint32_t FaultLevel;                  /*!< Specifies whether the output level is active or inactive when in FAULT state.
0362                                              This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
0363   uint32_t ChopperModeEnable;           /*!< Indicates whether or not the chopper mode is enabled
0364                                              This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
0365   uint32_t BurstModeEntryDelayed;       /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
0366                                              This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
0367 } HRTIM_OutputCfgTypeDef;
0368
0369 /**
0370   * @brief  External event filtering in timing units configuration definition
0371   */
0372 typedef struct
0373 {
0374   uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.
0375                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
0376   uint32_t Latch;       /*!< Specifies whether or not the signal is latched.
0377                              This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
0378 } HRTIM_TimerEventFilteringCfgTypeDef;
0379
0380 /**
0381   * @brief  Dead time feature configuration definition
0382   */
0383 typedef struct
0384 {
0385   uint32_t Prescaler;        /*!< Specifies the dead-time prescaler.
0386                                   This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
0387   uint32_t RisingValue;      /*!< Specifies the dead-time following a rising edge.
0388                                   This parameter can be a number between 0x0 and 0x1FFU */
0389   uint32_t RisingSign;       /*!< Specifies whether the dead-time is positive or negative on rising edge.
0390                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
0391   uint32_t RisingLock;       /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
0392                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
0393   uint32_t RisingSignLock;   /*!< Specifies whether or not dead-time rising sign is write protected.
0394                                   This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
0395   uint32_t FallingValue;     /*!< Specifies the dead-time following a falling edge.
0396                                   This parameter can be a number between 0x0 and 0x1FFU */
0397   uint32_t FallingSign;      /*!< Specifies whether the dead-time is positive or negative on falling edge.
0398                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
0399   uint32_t FallingLock;      /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
0400                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
0401   uint32_t FallingSignLock;  /*!< Specifies whether or not dead-time falling sign is write protected.
0402                                   This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
0403 } HRTIM_DeadTimeCfgTypeDef;
0404
0405 /**
0406   * @brief  Chopper mode configuration definition
0407   */
0408 typedef struct
0409 {
0410   uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
0411                               This parameter can be a value of @ref HRTIM_Chopper_Frequency */
0412   uint32_t DutyCycle;    /*!< Specifies the Timer chopper duty cycle value.
0413                               This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
0414   uint32_t StartPulse;   /*!< Specifies the Timer pulse width value.
0415                               This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
0416 } HRTIM_ChopperModeCfgTypeDef;
0417
0418 /**
0419   * @brief  External event channel configuration definition
0420   */
0421 typedef struct
0422 {
0423   uint32_t Source;        /*!< Identifies the source of the external event.
0424                                This parameter can be a value of @ref HRTIM_External_Event_Sources */
0425   uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).
0426                                This parameter can be a value of @ref HRTIM_External_Event_Polarity */
0427   uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.
0428                                This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
0429   uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
0430                                This parameter can be a value of @ref HRTIM_External_Event_Filter */
0431   uint32_t FastMode;      /*!< Indicates whether or not low latency mode is enabled for the external event.
0432                                This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
0433 } HRTIM_EventCfgTypeDef;
0434
0435 /**
0436   * @brief  Fault channel configuration definition
0437   */
0438 typedef struct
0439 {
0440   uint32_t Source;        /*!< Identifies the source of the fault.
0441                                This parameter can be a value of @ref HRTIM_Fault_Sources */
0442   uint32_t Polarity;      /*!< Specifies the polarity of the fault event.
0443                                This parameter can be a value of @ref HRTIM_Fault_Polarity */
0444   uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
0445                                This parameter can be a value of @ref HRTIM_Fault_Filter */
0446   uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.
0447                                This parameter can be a value of @ref HRTIM_Fault_Lock */
0448 } HRTIM_FaultCfgTypeDef;
0449
0450 /**
0451   * @brief  Burst mode configuration definition
0452   */
0453 typedef struct
0454 {
0455   uint32_t Mode;           /*!< Specifies the burst mode operating mode.
0456                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
0457   uint32_t ClockSource;    /*!< Specifies the burst mode clock source.
0458                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
0459   uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.
0460                                 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
0461   uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
0462                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
0463   uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.
0464                                 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
0465   uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.
0466                                 This parameter can be a number between 0x0 and 0xFFFF  */
0467   uint32_t Period;         /*!< Specifies burst mode repetition period.
0468                                 This parameter can be a number between 0x1 and 0xFFFF  */
0469 } HRTIM_BurstModeCfgTypeDef;
0470
0471 /**
0472   * @brief  ADC trigger configuration definition
0473   */
0474 typedef struct
0475 {
0476   uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.
0477                                This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source  */
0478   uint32_t Trigger;       /*!< Specifies the event(s) triggering the ADC conversion.
0479                                This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event  */
0480 } HRTIM_ADCTriggerCfgTypeDef;
0481
0482 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
0483 /**
0484   * @brief  HAL HRTIM Callback ID enumeration definition
0485   */
0486 typedef enum {
0487   HAL_HRTIM_FAULT1CALLBACK_CB_ID               = 0x00U, /*!< Fault 1 interrupt callback ID                         */
0488   HAL_HRTIM_FAULT2CALLBACK_CB_ID               = 0x01U, /*!< Fault 2 interrupt callback ID                         */
0489   HAL_HRTIM_FAULT3CALLBACK_CB_ID               = 0x02U, /*!< Fault 3 interrupt callback ID                         */
0490   HAL_HRTIM_FAULT4CALLBACK_CB_ID               = 0x03U, /*!< Fault 4 interrupt callback ID                         */
0491   HAL_HRTIM_FAULT5CALLBACK_CB_ID               = 0x04U, /*!< Fault 5 interrupt callback ID                         */
0492   HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID          = 0x05U, /*!< System fault interrupt callback ID                    */
0493   HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID      = 0x07U, /*!< Burst mode period interrupt callback ID               */
0494   HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID                      */
0495   HAL_HRTIM_ERRORCALLBACK_CB_ID                = 0x09U, /*!< DMA error callback ID                                 */
0496
0497   HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID      = 0x10U, /*!< Timer x Update interrupt callback ID                  */
0498   HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID      = 0x11U, /*!< Timer x Repetition interrupt callback ID              */
0499   HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID        = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID         */
0500   HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID        = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID         */
0501   HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID        = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID         */
0502   HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID        = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID         */
0503   HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID        = 0x16U, /*!< Timer x Capture 1 interrupts callback ID              */
0504   HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID        = 0x17U, /*!< Timer x Capture 2 interrupts callback ID              */
0505   HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID    = 0x18U, /*!< Timer x Delayed protection interrupt callback ID      */
0506   HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID         = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */
0507   HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID           = 0x1AU, /*!< Timer x output 1 set interrupt callback ID            */
0508   HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID         = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID          */
0509   HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID           = 0x1CU, /*!< Timer x output 2 set interrupt callback ID            */
0510   HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID         = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID          */
0511   HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID     = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID     */
0512
0513   HAL_HRTIM_MSPINIT_CB_ID                      = 0x20U, /*!< HRTIM MspInit callback ID                             */
0514   HAL_HRTIM_MSPDEINIT_CB_ID                    = 0x21U, /*!< HRTIM MspInit callback ID                             */
0515 }HAL_HRTIM_CallbackIDTypeDef;
0516
0517 /**
0518   * @brief  HAL HRTIM Callback function pointer definitions
0519   */
0520 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim);       /*!< HRTIM related callback function pointer         */
0521
0522 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!< HRTIM Timer x related callback function pointer */
0523                                             uint32_t TimerIdx);
0524 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
0525
0526 /**
0527   * @}
0528   */
0529
0530 /* Exported constants --------------------------------------------------------*/
0531 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
0532   * @ingroup RTEMSBSPsARMSTM32H7
0533   * @{
0534   */
0535
0536 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
0537   * @ingroup RTEMSBSPsARMSTM32H7
0538   * @{
0539   * @brief Constants defining the timer indexes
0540   */
0541 #define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */
0542 #define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */
0543 #define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */
0544 #define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */
0545 #define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */
0546 #define HRTIM_TIMERINDEX_MASTER  0x5U   /*!< Index used to access master registers  */
0547 #define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */
0548 /**
0549   * @}
0550   */
0551
0552 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
0553   * @ingroup RTEMSBSPsARMSTM32H7
0554   * @{
0555   * @brief Constants defining timer identifiers
0556   */
0557 #define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier  */
0558 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
0559 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
0560 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
0561 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
0562 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
0563 /**
0564  * @}
0565  */
0566
0567 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
0568   * @ingroup RTEMSBSPsARMSTM32H7
0569   * @{
0570   * @brief Constants defining compare unit identifiers
0571   */
0572 #define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */
0573 #define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */
0574 #define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */
0575 #define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */
0576  /**
0577   * @}
0578   */
0579
0580 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
0581   * @ingroup RTEMSBSPsARMSTM32H7
0582   * @{
0583   * @brief Constants defining capture unit identifiers
0584   */
0585 #define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */
0586 #define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */
0587 /**
0588   * @}
0589   */
0590
0591 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
0592   * @ingroup RTEMSBSPsARMSTM32H7
0593   * @{
0594   * @brief Constants defining timer output identifiers
0595   */
0596 #define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */
0597 #define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */
0598 #define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */
0599 #define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */
0600 #define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */
0601 #define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */
0602 #define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */
0603 #define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */
0604 #define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */
0605 #define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */
0606 /**
0607   * @}
0608   */
0609
0610 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
0611   * @ingroup RTEMSBSPsARMSTM32H7
0612   * @{
0613   * @brief Constants defining ADC triggers identifiers
0614   */
0615 #define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */
0616 #define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */
0617 #define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */
0618 #define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */
0619
0620 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
0621     (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
0622      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
0623      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
0624      ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
0625 /**
0626   * @}
0627   */
0628 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
0629   * @ingroup RTEMSBSPsARMSTM32H7
0630   * @{
0631   * @brief Constants defining external event channel identifiers
0632   */
0633 #define HRTIM_EVENT_NONE    (0x00000000U)     /*!< Undefined event channel */
0634 #define HRTIM_EVENT_1       (0x00000001U)     /*!< External event channel 1  identifier */
0635 #define HRTIM_EVENT_2       (0x00000002U)     /*!< External event channel 2  identifier */
0636 #define HRTIM_EVENT_3       (0x00000003U)     /*!< External event channel 3  identifier */
0637 #define HRTIM_EVENT_4       (0x00000004U)     /*!< External event channel 4  identifier */
0638 #define HRTIM_EVENT_5       (0x00000005U)     /*!< External event channel 5  identifier */
0639 #define HRTIM_EVENT_6       (0x00000006U)     /*!< External event channel 6  identifier */
0640 #define HRTIM_EVENT_7       (0x00000007U)     /*!< External event channel 7  identifier */
0641 #define HRTIM_EVENT_8       (0x00000008U)     /*!< External event channel 8  identifier */
0642 #define HRTIM_EVENT_9       (0x00000009U)     /*!< External event channel 9  identifier */
0643 #define HRTIM_EVENT_10      (0x0000000AU)     /*!< External event channel 10 identifier */
0644 /**
0645   * @}
0646   */
0647
0648 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
0649   * @ingroup RTEMSBSPsARMSTM32H7
0650   * @{
0651   * @brief Constants defining fault channel identifiers
0652   */
0653 #define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */
0654 #define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */
0655 #define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */
0656 #define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */
0657 #define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */
0658 /**
0659   * @}
0660   */
0661
0662
0663  /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
0664    * @ingroup RTEMSBSPsARMSTM32H7
0665   * @{
0666   * @brief Constants defining timer high-resolution clock prescaler ratio.
0667   */
0668 #define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)         */
0669 #define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)     */
0670 #define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)        */
0671 /**
0672   * @}
0673   */
0674
0675 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
0676   * @ingroup RTEMSBSPsARMSTM32H7
0677   * @{
0678   * @brief Constants defining timer counter operating mode.
0679   */
0680 #define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
0681 #define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */
0682 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
0683 /**
0684   * @}
0685   */
0686
0687 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
0688   * @ingroup RTEMSBSPsARMSTM32H7
0689   * @{
0690   * @brief Constants defining half mode enabling status.
0691   */
0692 #define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */
0693 #define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */
0694 /**
0695   * @}
0696   */
0697
0698 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
0699   * @ingroup RTEMSBSPsARMSTM32H7
0700   * @{
0701   * @brief Constants defining the timer behavior following the synchronization event
0702   */
0703 #define HRTIM_SYNCSTART_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
0704 #define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */
0705 /**
0706   * @}
0707   */
0708
0709 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
0710   * @ingroup RTEMSBSPsARMSTM32H7
0711   * @{
0712   * @brief Constants defining the timer behavior following the synchronization event
0713   */
0714 #define HRTIM_SYNCRESET_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
0715 #define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */
0716 /**
0717   * @}
0718   */
0719
0720 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
0721   * @ingroup RTEMSBSPsARMSTM32H7
0722   * @{
0723   * @brief Constants defining on which output the DAC synchronization event is sent
0724   */
0725 #define HRTIM_DACSYNC_NONE          0x00000000U                                 /*!< No DAC synchronization event generated */
0726 #define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
0727 #define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
0728 #define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
0729 /**
0730   * @}
0731   */
0732
0733 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
0734   * @ingroup RTEMSBSPsARMSTM32H7
0735   * @{
0736   * @brief Constants defining whether a write access into a preloadable
0737   *        register is done into the active or the preload register.
0738   */
0739 #define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */
0740 #define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */
0741 /**
0742   * @}
0743   */
0744
0745 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
0746   * @ingroup RTEMSBSPsARMSTM32H7
0747   * @{
0748   * @brief Constants defining how the update occurs relatively to the burst DMA
0749   *        transaction and the external update request on update enable inputs 1 to 3.
0750   */
0751 #define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                           /*!< Update done independently from the DMA burst transfer completion */
0752 #define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
0753 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
0754 #define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
0755 #define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
0756 #define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
0757 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */
0758 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */
0759 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */
0760 /**
0761   * @}
0762   */
0763
0764 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
0765   * @ingroup RTEMSBSPsARMSTM32H7
0766   * @{
0767   * @brief Constants defining how the timer behaves during a burst
0768             mode operation.
0769   */
0770 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U           /*!< Timer counter clock is maintained and the timer operates normally */
0771 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset */
0772 /**
0773   * @}
0774   */
0775
0776 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
0777   * @ingroup RTEMSBSPsARMSTM32H7
0778   * @{
0779   * @brief Constants defining whether registers are updated when the timer
0780   *        repetition period is completed (either due to roll-over or
0781   *        reset events)
0782   */
0783 #define HRTIM_UPDATEONREPETITION_DISABLED  0x00000000U           /*!< Update on repetition disabled */
0784 #define HRTIM_UPDATEONREPETITION_ENABLED   (HRTIM_MCR_MREPU)     /*!< Update on repetition enabled */
0785 /**
0786   * @}
0787   */
0788
0789
0790 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
0791   * @ingroup RTEMSBSPsARMSTM32H7
0792   * @{
0793   * @brief Constants defining whether or not the push-pull mode is enabled for
0794   *        a timer.
0795   */
0796 #define HRTIM_TIMPUSHPULLMODE_DISABLED     0x00000000U           /*!< Push-Pull mode disabled */
0797 #define HRTIM_TIMPUSHPULLMODE_ENABLED      (HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */
0798 /**
0799   * @}
0800   */
0801
0802 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
0803   * @ingroup RTEMSBSPsARMSTM32H7
0804   * @{
0805   * @brief Constants defining whether a fault channel is enabled for a timer
0806   */
0807 #define HRTIM_TIMFAULTENABLE_NONE     0x00000000U           /*!< No fault enabled */
0808 #define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */
0809 #define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */
0810 #define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */
0811 #define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */
0812 #define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */
0813 /**
0814   * @}
0815   */
0816
0817 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
0818   * @ingroup RTEMSBSPsARMSTM32H7
0819   * @{
0820   * @brief Constants defining whether or not fault enabling bits are write
0821   *        protected for a timer
0822   */
0823 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */
0824 #define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */
0825 /**
0826   * @}
0827   */
0828
0829 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
0830   * @ingroup RTEMSBSPsARMSTM32H7
0831   * @{
0832   * @brief Constants defining whether or not fault the dead time insertion
0833   *        feature is enabled for a timer
0834   */
0835 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */
0836 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Dead-time is inserted between output 1 and output 2U */
0837 /**
0838   * @}
0839   */
0840
0841 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
0842   * @ingroup RTEMSBSPsARMSTM32H7
0843   * @{
0844   * @brief Constants defining all possible delayed protection modes
0845   *        for a timer. Also define the source and outputs on which the delayed
0846   *        protection schemes are applied
0847   */
0848 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */
0849 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
0850 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
0851 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
0852 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */
0853 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
0854 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
0855 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
0856 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
0857
0858 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED            (0x00000000U)                                                                             /*!< No action */
0859 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8    (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
0860 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8    (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
0861 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8    (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
0862 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8       (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */
0863 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
0864 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
0865 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9    (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
0866 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9       (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */
0867 /**
0868   * @}
0869   */
0870
0871 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
0872   * @ingroup RTEMSBSPsARMSTM32H7
0873   * @{
0874   * @brief Constants defining whether the registers update is done synchronously
0875   *        with any other timer or master update
0876   */
0877 #define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */
0878 #define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */
0879 #define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */
0880 #define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */
0881 #define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/
0882 #define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */
0883 #define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */
0884 /**
0885   * @}
0886   */
0887
0888 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
0889   * @ingroup RTEMSBSPsARMSTM32H7
0890   * @{
0891   * @brief Constants defining the events that can be selected to trigger the reset
0892   *        of the timer counter
0893   */
0894 #define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */
0895 #define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */
0896 #define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */
0897 #define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */
0898 #define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */
0899 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */
0900 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */
0901 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */
0902 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */
0903 #define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */
0904 #define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */
0905 #define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */
0906 #define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */
0907 #define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */
0908 #define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */
0909 #define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */
0910 #define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */
0911 #define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */
0912 #define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
0913 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
0914 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
0915 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
0916 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
0917 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
0918 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
0919 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
0920 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
0921 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
0922 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
0923 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
0924 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
0925 /**
0926   * @}
0927   */
0928
0929 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
0930   * @ingroup RTEMSBSPsARMSTM32H7
0931   * @{
0932   * @brief Constants defining whether the register are updated upon Timerx
0933   *        counter reset or roll-over to 0 after reaching the period value
0934   *        in continuous mode
0935   */
0936 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U           /*!< Update by timer x reset / roll-over disabled */
0937 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */
0938 /**
0939   * @}
0940   */
0941
0942 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
0943   * @ingroup RTEMSBSPsARMSTM32H7
0944   * @{
0945   * @brief Constants defining whether the compare register is behaving in
0946   *        regular mode (compare match issued as soon as counter equal compare),
0947   *        or in auto-delayed mode
0948   */
0949 #define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */
0950 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
0951 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
0952 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
0953 /**
0954   * @}
0955   */
0956
0957 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
0958   * @ingroup RTEMSBSPsARMSTM32H7
0959   * @{
0960   * @brief Constants defining the behavior of the output signal when the timer
0961            operates in basic output compare mode
0962   */
0963 #define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */
0964 #define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */
0965 #define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */
0966
0967 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
0968               (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
0969                ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
0970                ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
0971 /**
0972   * @}
0973   */
0974
0975 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
0976   * @ingroup RTEMSBSPsARMSTM32H7
0977   * @{
0978   * @brief Constants defining the polarity of a timer output
0979   */
0980 #define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is active HIGH */
0981 #define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
0982 /**
0983   * @}
0984   */
0985
0986 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
0987   * @ingroup RTEMSBSPsARMSTM32H7
0988   * @{
0989   * @brief Constants defining the events that can be selected to configure the
0990   *        set crossbar of a timer output
0991   */
0992 #define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */
0993 #define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
0994 #define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */
0995 #define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */
0996 #define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */
0997 #define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */
0998 #define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */
0999 #define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */
1000 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */
1001 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */
1002 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */
1003 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */
1004 #define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
1005 #define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
1006 #define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
1007 #define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
1008 #define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
1009 #define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
1010 #define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
1011 #define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
1012 #define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
1013 #define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */
1014 #define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */
1015 #define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */
1016 #define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */
1017 #define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */
1018 #define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */
1019 #define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */
1020 #define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */
1021 #define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */
1022 #define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */
1023 #define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */
1024 /**
1025   * @}
1026   */
1027
1028 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1029   * @ingroup RTEMSBSPsARMSTM32H7
1030   * @{
1031   * @brief Constants defining the events that can be selected to configure the
1032   *        reset crossbar of a timer output
1033   */
1034 #define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
1035 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1036 #define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */
1037 #define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */
1038 #define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */
1039 #define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */
1040 #define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */
1041 #define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */
1042 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */
1043 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
1044 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
1045 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
1046 #define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_RST1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
1047 #define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_RST1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
1048 #define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_RST1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
1049 #define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_RST1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
1050 #define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_RST1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
1051 #define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_RST1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
1052 #define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_RST1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
1053 #define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_RST1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
1054 #define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_RST1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
1055 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
1056 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
1057 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
1058 #define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */
1059 #define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */
1060 #define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */
1061 #define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */
1062 #define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */
1063 #define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */
1064 #define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */
1065 #define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */
1066 /**
1067   * @}
1068   */
1069
1070 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
1071   * @ingroup RTEMSBSPsARMSTM32H7
1072   * @{
1073   * @brief Constants defining whether or not the timer output transition to its
1074            IDLE state when burst mode is entered
1075   */
1076 #define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U           /*!< The output is not affected by the burst mode operation */
1077 #define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */
1078  /**
1079   * @}
1080   */
1081
1082 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
1083   * @ingroup RTEMSBSPsARMSTM32H7
1084   * @{
1085   * @brief Constants defining the output level when output is in IDLE state
1086   */
1087 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
1088 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
1089 /**
1090   * @}
1091   */
1092
1093 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
1094   * @ingroup RTEMSBSPsARMSTM32H7
1095   * @{
1096   * @brief Constants defining the output level when output is in FAULT state
1097   */
1098 #define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                  /*!< The output is not affected by the fault input */
1099 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
1100 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
1101 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
1102 /**
1103   * @}
1104   */
1105
1106 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
1107   * @ingroup RTEMSBSPsARMSTM32H7
1108   * @{
1109   * @brief Constants defining whether or not chopper mode is enabled for a timer
1110            output
1111   */
1112 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U           /*!< Output signal is not altered  */
1113 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */
1114 /**
1115   * @}
1116   */
1117
1118 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
1119   * @ingroup RTEMSBSPsARMSTM32H7
1120   * @{
1121   * @brief Constants defining the idle mode entry is delayed by forcing a
1122            dead-time insertion before switching the outputs to their idle state
1123   */
1124 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U           /*!< The programmed Idle state is applied immediately to the Output */
1125 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Dead-time is inserted on output before entering the idle mode */
1126 /**
1127   * @}
1128   */
1129
1130
1131 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
1132   * @ingroup RTEMSBSPsARMSTM32H7
1133   * @{
1134   * @brief Constants defining the events that can be selected to trigger the
1135   *        capture of the timing unit counter
1136   */
1137 #define HRTIM_CAPTURETRIGGER_NONE         0x00000000U              /*!< Capture trigger is disabled */
1138 #define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */
1139 #define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */
1140 #define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */
1141 #define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */
1142 #define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */
1143 #define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */
1144 #define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */
1145 #define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */
1146 #define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */
1147 #define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */
1148 #define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
1149 #define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */
1150 #define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */
1151 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */
1152 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */
1153 #define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */
1154 #define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */
1155 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */
1156 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */
1157 #define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */
1158 #define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */
1159 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */
1160 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */
1161 #define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */
1162 #define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */
1163 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */
1164 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */
1165 #define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */
1166 #define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */
1167 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */
1168 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */
1169 /**
1170   * @}
1171   */
1172
1173 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
1174   * @ingroup RTEMSBSPsARMSTM32H7
1175   * @{
1176   * @brief Constants defining the event filtering applied to external events
1177   *        by a timer
1178   */
1179 #define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
1180 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                          /*!< Blanking from counter reset/roll-over to Compare 1U  */
1181 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                          /*!< Blanking from counter reset/roll-over to Compare 2U  */
1182 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from counter reset/roll-over to Compare 3U  */
1183 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                          /*!< Blanking from counter reset/roll-over to Compare 4U  */
1184 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from another timing unit: TIMFLTR1 source   */
1185 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                  /*!< Blanking from another timing unit: TIMFLTR2 source   */
1186 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Blanking from another timing unit: TIMFLTR3 source   */
1187 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                          /*!< Blanking from another timing unit: TIMFLTR4 source   */
1188 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from another timing unit: TIMFLTR5 source   */
1189 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                  /*!< Blanking from another timing unit: TIMFLTR6 source   */
1190 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Blanking from another timing unit: TIMFLTR7 source   */
1191 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                  /*!< Blanking from another timing unit: TIMFLTR8 source   */
1192 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Windowing from counter reset/roll-over to Compare 2U */
1193 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                          /*!< Windowing from counter reset/roll-over to Compare 3U */
1194 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source    */
1195 /**
1196   * @}
1197   */
1198
1199 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
1200   * @ingroup RTEMSBSPsARMSTM32H7
1201   * @{
1202   * @brief Constants defining whether or not the external event is
1203   *        memorized (latched) and generated as soon as the blanking period
1204   *        is completed or the window ends
1205   */
1206 #define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */
1207 #define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
1208 /**
1209   * @}
1210   */
1211
1212 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
1213   * @ingroup RTEMSBSPsARMSTM32H7
1214   * @{
1215   * @brief Constants defining division ratio between the timer clock frequency
1216   *        (fHRTIM) and the dead-time generator clock (fDTG)
1217   */
1218 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
1219 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
1220 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
1221 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */
1222 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */
1223 /**
1224   * @}
1225   */
1226
1227 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
1228   * @ingroup RTEMSBSPsARMSTM32H7
1229   * @{
1230   * @brief Constants defining whether the dead-time is positive or negative
1231   *        (overlapping signal) on rising edge
1232   */
1233 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on rising edge */
1234 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative dead-time on rising edge */
1235 /**
1236   * @}
1237   */
1238
1239 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
1240   * @ingroup RTEMSBSPsARMSTM32H7
1241   * @{
1242   * @brief Constants defining whether or not the dead-time (rising sign and
1243   *        value) is write protected
1244   */
1245 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising value and sign is writeable */
1246 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Dead-time rising value and sign is read-only */
1247 /**
1248   * @}
1249   */
1250
1251 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
1252   * @ingroup RTEMSBSPsARMSTM32H7
1253   * @{
1254   * @brief Constants defining whether or not the dead-time rising sign is write
1255   *        protected
1256   */
1257 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising sign is writeable */
1258 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Dead-time rising sign is read-only */
1259 /**
1260   * @}
1261   */
1262
1263 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
1264   * @ingroup RTEMSBSPsARMSTM32H7
1265   * @{
1266   * @brief Constants defining whether the dead-time is positive or negative
1267   *        (overlapping signal) on falling edge
1268   */
1269 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on falling edge */
1270 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative dead-time on falling edge */
1271 /**
1272   * @}
1273   */
1274
1275 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
1276   * @ingroup RTEMSBSPsARMSTM32H7
1277   * @{
1278   * @brief Constants defining whether or not the dead-time (falling sign and
1279   *        value) is write protected
1280   */
1281 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling value and sign is writeable */
1282 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Dead-time falling value and sign is read-only */
1283 /**
1284   * @}
1285   */
1286
1287 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
1288   * @ingroup RTEMSBSPsARMSTM32H7
1289   * @{
1290   * @brief Constants defining whether or not the dead-time falling sign is write
1291   *        protected
1292   */
1293 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling sign is writeable */
1294 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Dead-time falling sign is read-only */
1295 /**
1296   * @}
1297   */
1298
1299 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
1300   * @ingroup RTEMSBSPsARMSTM32H7
1301   * @{
1302   * @brief Constants defining the frequency of the generated high frequency carrier
1303   */
1304 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
1305 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
1306 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
1307 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
1308 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
1309 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
1310 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
1311 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
1312 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
1313 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
1314 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
1315 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
1316 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
1317 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
1318 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
1319 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
1320  /**
1321   * @}
1322   */
1323
1324 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
1325   * @ingroup RTEMSBSPsARMSTM32H7
1326   * @{
1327   * @brief Constants defining the duty cycle of the generated high frequency carrier
1328   *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
1329   */
1330 #define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                                       /*!< Only 1st pulse is present */
1331 #define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */
1332 #define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */
1333 #define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */
1334 #define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */
1335 #define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */
1336 #define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */
1337 #define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
1338 /**
1339   * @}
1340   */
1341
1342 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
1343   * @ingroup RTEMSBSPsARMSTM32H7
1344   * @{
1345   * @brief Constants defining the pulse width of the first pulse of the generated
1346   *        high frequency carrier
1347   */
1348 #define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                          /*!< tSTPW = tHRTIM x 16  */
1349 #define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
1350 #define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
1351 #define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
1352 #define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
1353 #define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
1354 #define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
1355 #define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
1356 #define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
1357 #define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
1358 #define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
1359 #define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
1360 #define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
1361 #define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
1362 #define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
1363 #define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
1364 /**
1365   * @}
1366   */
1367
1368 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
1369   * @ingroup RTEMSBSPsARMSTM32H7
1370   * @{
1371   * @brief Constants defining the options for synchronizing multiple HRTIM
1372   *        instances, as a master unit (generating a synchronization signal)
1373   *        or as a slave (waiting for a trigger to be synchronized)
1374   */
1375 #define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
1376 #define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
1377 #define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
1378 /**
1379   * @}
1380   */
1381
1382 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
1383   * @ingroup RTEMSBSPsARMSTM32H7
1384   * @{
1385   * @brief Constants defining defining the synchronization input source
1386   */
1387 #define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                                  /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
1388 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */
1389 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
1390 /**
1391   * @}
1392   */
1393
1394 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
1395   * @ingroup RTEMSBSPsARMSTM32H7
1396   * @{
1397   * @brief Constants defining the source and event to be sent on the
1398   *        synchronization outputs
1399   */
1400 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
1401 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
1402 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
1403 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
1404 /**
1405   * @}
1406   */
1407
1408 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
1409   * @ingroup RTEMSBSPsARMSTM32H7
1410   * @{
1411   * @brief Constants defining the routing and conditioning of the synchronization output event
1412   */
1413 #define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                   /*!< Synchronization output event is disabled */
1414 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
1415 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
1416 /**
1417   * @}
1418   */
1419
1420 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
1421   * @ingroup RTEMSBSPsARMSTM32H7
1422   * @{
1423   * @brief Constants defining available sources associated to external events
1424   */
1425 #define HRTIM_EVENTSRC_1         (0x00000000U)                                  /*!< External event source 1U */
1426 #define HRTIM_EVENTSRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2U */
1427 #define HRTIM_EVENTSRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3U */
1428 #define HRTIM_EVENTSRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4U */
1429 /**
1430   * @}
1431   */
1432
1433 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
1434   * @ingroup RTEMSBSPsARMSTM32H7
1435   * @{
1436   * @brief Constants defining the polarity of an external event
1437   */
1438 #define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */
1439 #define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
1440 /**
1441   * @}
1442   */
1443
1444 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
1445   * @ingroup RTEMSBSPsARMSTM32H7
1446   * @{
1447   * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
1448   *        of an external event
1449   */
1450 #define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */
1451 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
1452 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
1453 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
1454 /**
1455   * @}
1456   */
1457
1458 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
1459   * @ingroup RTEMSBSPsARMSTM32H7
1460   * @{
1461   * @brief Constants defining whether or not an external event is programmed in
1462            fast mode
1463   */
1464 #define HRTIM_EVENTFASTMODE_DISABLE    (0x00000000U)               /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1465 #define HRTIM_EVENTFASTMODE_ENABLE     (HRTIM_EECR1_EE1FAST)       /*!< External Event is acting asynchronously on outputs (low latency mode) */
1466 /**
1467   * @}
1468   */
1469
1470 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
1471   * @ingroup RTEMSBSPsARMSTM32H7
1472   * @{
1473   * @brief Constants defining the frequency used to sample an external event 6
1474   *        input and the length (N) of the digital filter applied
1475   */
1476 #define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */
1477 #define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */
1478 #define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */
1479 #define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */
1480 #define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */
1481 #define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */
1482 #define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */
1483 #define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */
1484 #define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */
1485 #define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */
1486 #define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */
1487 #define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */
1488 #define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */
1489 #define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */
1490 #define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */
1491 #define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */
1492 /**
1493   * @}
1494   */
1495
1496 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
1497   * @ingroup RTEMSBSPsARMSTM32H7
1498   * @{
1499   * @brief Constants defining division ratio between the timer clock frequency
1500   *        fHRTIM) and the external event signal sampling clock (fEEVS)
1501   *        used by the digital filters
1502   */
1503 #define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */
1504 #define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */
1505 #define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */
1506 #define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */
1507 /**
1508   * @}
1509   */
1510
1511 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
1512   * @ingroup RTEMSBSPsARMSTM32H7
1513   * @{
1514   * @brief Constants defining whether a fault is triggered by any external
1515   *        or internal fault source
1516   */
1517 #define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)              /*!< Fault input is FLT input pin */
1518 #define HRTIM_FAULTSOURCE_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1519 /**
1520   * @}
1521   */
1522
1523 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
1524   * @ingroup RTEMSBSPsARMSTM32H7
1525   * @{
1526   * @brief Constants defining the polarity of a fault event
1527   */
1528 #define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)            /*!< Fault input is active low */
1529 #define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
1530 /**
1531   * @}
1532   */
1533
1534 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
1535   * @ingroup RTEMSBSPsARMSTM32H7
1536   * @{
1537   * @ brief Constants defining the frequency used to sample the fault input and
1538   *         the length (N) of the digital filter applied
1539   */
1540 #define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */
1541 #define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */
1542 #define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */
1543 #define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */
1544 #define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */
1545 #define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */
1546 #define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */
1547 #define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */
1548 #define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */
1549 #define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */
1550 #define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */
1551 #define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */
1552 #define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */
1553 #define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */
1554 #define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */
1555 #define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */
1556 /**
1557   * @}
1558   */
1559
1560 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
1561   * @ingroup RTEMSBSPsARMSTM32H7
1562   * @{
1563   * @brief Constants defining whether or not the fault programming bits are
1564            write protected
1565   */
1566 #define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)               /*!< Fault settings bits are read/write */
1567 #define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */
1568 /**
1569   * @}
1570   */
1571
1572 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
1573   * @ingroup RTEMSBSPsARMSTM32H7
1574   * @{
1575   * @brief Constants defining the division ratio between the timer clock
1576   *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
1577   *        by the digital filters.
1578   */
1579 #define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */
1580 #define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */
1581 #define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */
1582 #define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */
1583 /**
1584   * @}
1585   */
1586
1587 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
1588   * @ingroup RTEMSBSPsARMSTM32H7
1589   * @{
1590   * @brief Constants defining if the burst mode is entered once or if it is
1591   *        continuously operating
1592   */
1593 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)           /*!< Burst mode operates in single shot mode */
1594 #define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
1595 /**
1596   * @}
1597   */
1598
1599 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
1600   * @ingroup RTEMSBSPsARMSTM32H7
1601   * @{
1602   * @brief Constants defining the clock source for the burst mode counter
1603   */
1604 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1605 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1606 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1607 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1608 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1609 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1610 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1611 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1612 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1613 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1614 /**
1615   * @}
1616   */
1617
1618 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
1619   * @ingroup RTEMSBSPsARMSTM32H7
1620   * @{
1621   * @brief Constants defining the prescaling ratio of the fHRTIM clock
1622   *        for the burst mode controller
1623   */
1624 #define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */
1625 #define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */
1626 #define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */
1627 #define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */
1628 #define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */
1629 #define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */
1630 #define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */
1631 #define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */
1632 #define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */
1633 #define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */
1634 #define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */
1635 #define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/
1636 #define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */
1637 #define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */
1638 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */
1639 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
1640 /**
1641   * @}
1642   */
1643
1644 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
1645   * @ingroup RTEMSBSPsARMSTM32H7
1646   * @{
1647   * @brief Constants defining whether or not burst mode registers preload
1648            mechanism is enabled, i.e. a write access into a preloadable register
1649           (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
1650   */
1651 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */
1652 #define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */
1653 /**
1654   * @}
1655   */
1656
1657 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
1658   * @ingroup RTEMSBSPsARMSTM32H7
1659   * @{
1660   * @brief Constants defining the events that can be used to trig the burst
1661   *        mode operation
1662   */
1663 #define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U             /*!<  No trigger */
1664 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */
1665 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */
1666 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */
1667 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */
1668 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */
1669 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */
1670 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */
1671 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */
1672 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */
1673 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */
1674 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */
1675 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */
1676 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */
1677 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */
1678 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */
1679 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */
1680 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */
1681 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2        (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2  */
1682 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */
1683 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */
1684 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1        (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1  */
1685 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */
1686 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET       (HRTIM_BMTRGR_TERST)    /*!< Timer E reset  */
1687 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */
1688 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */
1689 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */
1690 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */
1691 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */
1692 #define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */
1693 #define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/
1694 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
1695 /**
1696   * @}
1697   */
1698
1699 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
1700   * @ingroup RTEMSBSPsARMSTM32H7
1701   * @{
1702   * @brief constants defining the source triggering the update of the
1703      HRTIM_ADCxR register (transfer from preload to active register).
1704   */
1705 #define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                   /*!< Master timer */
1706 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */
1707 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */
1708 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
1709 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */
1710 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
1711 /**
1712   * @}
1713   */
1714
1715 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
1716   * @ingroup RTEMSBSPsARMSTM32H7
1717   * @{
1718   * @brief constants defining the events triggering ADC conversion.
1719   *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
1720   *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
1721   */
1722 #define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U              /*!< No ADC trigger event */
1723 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */
1724 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */
1725 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */
1726 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */
1727 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */
1728 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */
1729 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */
1730 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */
1731 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */
1732 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */
1733 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2    (HRTIM_ADC1R_AD1TAC2)    /*!< ADC Trigger on Timer A compare 2U */
1734 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */
1735 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */
1736 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */
1737 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */
1738 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2    (HRTIM_ADC1R_AD1TBC2)    /*!< ADC Trigger on Timer B compare 2U */
1739 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */
1740 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */
1741 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */
1742 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */
1743 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2    (HRTIM_ADC1R_AD1TCC2)    /*!< ADC Trigger on Timer C compare 2U */
1744 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */
1745 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */
1746 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */
1747 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2    (HRTIM_ADC1R_AD1TDC2)    /*!< ADC Trigger on Timer D compare 2U */
1748 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */
1749 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */
1750 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */
1751 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2    (HRTIM_ADC1R_AD1TEC2)    /*!< ADC Trigger on Timer E compare 2U */
1752 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */
1753 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */
1754 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */
1755
1756 #define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */
1757 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */
1758 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */
1759 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */
1760 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */
1761 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */
1762 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */
1763 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */
1764 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */
1765 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */
1766 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */
1767 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */
1768 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3    (HRTIM_ADC2R_AD2TAC3)    /*!< ADC Trigger on Timer A compare 3U */
1769 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */
1770 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */
1771 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */
1772 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3    (HRTIM_ADC2R_AD2TBC3)    /*!< ADC Trigger on Timer B compare 3U */
1773 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */
1774 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */
1775 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */
1776 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3    (HRTIM_ADC2R_AD2TCC3)    /*!< ADC Trigger on Timer C compare 3U */
1777 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */
1778 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */
1779 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */
1780 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */
1781 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3    (HRTIM_ADC2R_AD2TDC3)    /*!< ADC Trigger on Timer D compare 3U */
1782 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */
1783 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */
1784 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */
1785 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */
1786 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */
1787 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */
1788 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */
1789
1790 /**
1791   * @}
1792   */
1793
1794 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
1795   * @ingroup RTEMSBSPsARMSTM32H7
1796   * @{
1797   * @brief Constants defining the registers that can be written during a burst
1798   *        DMA operation
1799   */
1800 #define HRTIM_BURSTDMA_NONE  0x00000000U               /*!< No register is updated by Burst DMA accesses */
1801 #define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
1802 #define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
1803 #define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
1804 #define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
1805 #define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */
1806 #define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */
1807 #define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
1808 #define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
1809 #define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
1810 #define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
1811 #define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */
1812 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
1813 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
1814 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
1815 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
1816 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
1817 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
1818 #define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
1819 #define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
1820 #define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
1821 #define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
1822 /**
1823   * @}
1824   */
1825
1826 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
1827   * @ingroup RTEMSBSPsARMSTM32H7
1828   * @{
1829   * @brief Constants used to enable or disable the burst mode controller
1830   */
1831 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U          /*!< Burst mode disabled */
1832 #define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */
1833 /**
1834   * @}
1835   */
1836
1837 /** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
1838   * @ingroup RTEMSBSPsARMSTM32H7
1839   * @{
1840   * @brief Constants used to enable or disable a fault channel
1841   */
1842 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
1843 #define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */
1844 /**
1845   * @}
1846   */
1847
1848 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
1849   * @ingroup RTEMSBSPsARMSTM32H7
1850   * @{
1851   * @brief Constants used to force timer registers update
1852   */
1853 #define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */
1854 #define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */
1855 #define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */
1856 #define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */
1857 #define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */
1858 #define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */
1859 /**
1860   * @}
1861   */
1862
1863 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
1864   * @ingroup RTEMSBSPsARMSTM32H7
1865   * @{
1866   * @brief Constants used to force timer counter reset
1867   */
1868 #define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Reset the master timer counter */
1869 #define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Reset the timer A counter */
1870 #define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Reset the timer B counter */
1871 #define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Reset the timer C counter */
1872 #define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Reset the timer D counter */
1873 #define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Reset the timer E counter */
1874 /**
1875   * @}
1876   */
1877
1878 /** @defgroup HRTIM_Output_Level HRTIM Output Level
1879   * @ingroup RTEMSBSPsARMSTM32H7
1880   * @{
1881   * @brief Constants defining the level of a timer output
1882   */
1883 #define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Force the output to its active state */
1884 #define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Force the output to its inactive state */
1885
1886 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
1887     (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
1888      ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
1889 /**
1890   * @}
1891   */
1892
1893 /** @defgroup HRTIM_Output_State HRTIM Output State
1894   * @ingroup RTEMSBSPsARMSTM32H7
1895   * @{
1896   * @brief Constants defining the state of a timer output
1897   */
1898 #define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or
1899                                                               inactive level as programmed in the crossbar unit */
1900 #define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
1901                                                               outputs are disabled by software or during a burst mode operation */
1902 #define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
1903                                                               FAULTx inputs */
1904 /**
1905   * @}
1906   */
1907
1908 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
1909   * @ingroup RTEMSBSPsARMSTM32H7
1910   * @{
1911   * @brief Constants defining the operating state of the burst mode controller
1912   */
1913 #define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U          /*!< Normal operation */
1914 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */
1915 /**
1916   * @}
1917   */
1918
1919 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
1920   * @ingroup RTEMSBSPsARMSTM32H7
1921   * @{
1922   * @brief Constants defining on which output the signal is currently applied
1923   *        in push-pull mode
1924   */
1925 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U            /*!< Signal applied on output 1 and output 2 forced inactive */
1926 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
1927 /**
1928   * @}
1929   */
1930
1931 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
1932   * @ingroup RTEMSBSPsARMSTM32H7
1933   * @{
1934   * @brief Constants defining on which output the signal was applied, in
1935   *        push-pull mode balanced fault mode or delayed idle mode, when the
1936   *        protection was triggered
1937   */
1938 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U               /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1939 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1940 /**
1941   * @}
1942   */
1943
1944 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
1945   * @ingroup RTEMSBSPsARMSTM32H7
1946   * @{
1947   */
1948 #define HRTIM_IT_NONE           0x00000000U           /*!< No interrupt enabled */
1949 #define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */
1950 #define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */
1951 #define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */
1952 #define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */
1953 #define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */
1954 #define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */
1955 #define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */
1956 /**
1957   * @}
1958   */
1959
1960 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
1961   * @ingroup RTEMSBSPsARMSTM32H7
1962   * @{
1963   */
1964 #define HRTIM_MASTER_IT_NONE         0x00000000U           /*!< No interrupt enabled */
1965 #define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */
1966 #define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */
1967 #define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */
1968 #define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */
1969 #define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */
1970 #define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */
1971 #define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */
1972 /**
1973   * @}
1974   */
1975
1976 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
1977   * @ingroup RTEMSBSPsARMSTM32H7
1978   * @{
1979   */
1980 #define HRTIM_TIM_IT_NONE       0x00000000U               /*!< No interrupt enabled */
1981 #define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */
1982 #define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */
1983 #define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */
1984 #define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */
1985 #define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */
1986 #define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */
1987 #define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */
1988 #define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */
1989 #define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */
1990 #define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */
1991 #define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */
1992 #define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */
1993 #define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */
1994 #define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */
1995 /**
1996   * @}
1997   */
1998
1999 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
2000   * @ingroup RTEMSBSPsARMSTM32H7
2001   * @{
2002   */
2003 #define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */
2004 #define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */
2005 #define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */
2006 #define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */
2007 #define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */
2008 #define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */
2009 #define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */
2010 /**
2011   * @}
2012   */
2013
2014 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
2015   * @ingroup RTEMSBSPsARMSTM32H7
2016   * @{
2017   */
2018 #define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */
2019 #define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */
2020 #define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */
2021 #define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4    /*!< Master compare 4 interrupt flag */
2022 #define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP     /*!< Master Repetition interrupt flag */
2023 #define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC     /*!< Synchronization input interrupt flag */
2024 #define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD     /*!< Master update interrupt flag */
2025 /**
2026   * @}
2027   */
2028
2029 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
2030   * @ingroup RTEMSBSPsARMSTM32H7
2031   * @{
2032   */
2033 #define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */
2034 #define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */
2035 #define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */
2036 #define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */
2037 #define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */
2038 #define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */
2039 #define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */
2040 #define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */
2041 #define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */
2042 #define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */
2043 #define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */
2044 #define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */
2045 #define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */
2046 #define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */
2047 /**
2048   * @}
2049   */
2050
2051 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
2052   * @ingroup RTEMSBSPsARMSTM32H7
2053   * @{
2054   */
2055 #define HRTIM_MASTER_DMA_NONE         0x00000000U            /*!< No DMA request enable */
2056 #define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */
2057 #define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */
2058 #define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */
2059 #define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */
2060 #define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */
2061 #define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */
2062 #define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */
2063 /**
2064   * @}
2065   */
2066
2067 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
2068   * @ingroup RTEMSBSPsARMSTM32H7
2069   * @{
2070   */
2071 #define HRTIM_TIM_DMA_NONE       0x00000000U               /*!< No DMA request enable */
2072 #define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */
2073 #define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */
2074 #define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */
2075 #define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */
2076 #define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */
2077 #define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */
2078 #define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */
2079 #define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */
2080 #define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */
2081 #define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */
2082 #define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */
2083 #define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */
2084 #define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */
2085 #define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */
2086 /**
2087   * @}
2088   */
2089
2090 /**
2091   * @}
2092   */
2093
2094   /* Private macros --------------------------------------------------------*/
2095 /** @addtogroup HRTIM_Private_Macros
2096   * @{
2097   */
2098 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
2099     (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
2100      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
2101      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
2102      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
2103      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
2104      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
2105
2106 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
2107      (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
2108       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
2109       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
2110       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
2111       ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
2112
2113 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
2114
2115 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
2116     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
2117      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
2118      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
2119      ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
2120
2121 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
2122     (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
2123      ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
2124
2125 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
2126
2127 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
2128     ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
2129      (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
2130       ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
2131     ||                                           \
2132     (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
2133      (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
2134       ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
2135     ||                                           \
2136     (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
2137      (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
2138       ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
2139     ||                                           \
2140     (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
2141      (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
2142       ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
2143     ||                                           \
2144     (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
2145      (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
2146       ((OUTPUT) == HRTIM_OUTPUT_TE2))))
2147
2148 #define IS_HRTIM_EVENT(EVENT)\
2149       (((EVENT) == HRTIM_EVENT_NONE)|| \
2150        ((EVENT) == HRTIM_EVENT_1)   || \
2151        ((EVENT) == HRTIM_EVENT_2)   || \
2152        ((EVENT) == HRTIM_EVENT_3)   || \
2153        ((EVENT) == HRTIM_EVENT_4)   || \
2154        ((EVENT) == HRTIM_EVENT_5)   || \
2155        ((EVENT) == HRTIM_EVENT_6)   || \
2156        ((EVENT) == HRTIM_EVENT_7)   || \
2157        ((EVENT) == HRTIM_EVENT_8)   || \
2158        ((EVENT) == HRTIM_EVENT_9)   || \
2159        ((EVENT) == HRTIM_EVENT_10))
2160
2161 #define IS_HRTIM_FAULT(FAULT)\
2162       (((FAULT) == HRTIM_FAULT_1)   || \
2163        ((FAULT) == HRTIM_FAULT_2)   || \
2164        ((FAULT) == HRTIM_FAULT_3)   || \
2165        ((FAULT) == HRTIM_FAULT_4)   || \
2166        ((FAULT) == HRTIM_FAULT_5))
2167
2168 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
2169         (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
2170          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
2171          ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
2172
2173 #define IS_HRTIM_MODE(MODE)\
2174           (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
2175            ((MODE) == HRTIM_MODE_SINGLESHOT) || \
2176            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
2177
2178 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
2179           (((MODE) == HRTIM_MODE_SINGLESHOT) || \
2180            ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
2181
2182
2183 #define IS_HRTIM_HALFMODE(HALFMODE)\
2184             (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
2185              ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
2186
2187 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
2188               (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
2189                ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
2190
2191 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
2192                 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
2193                  ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
2194
2195 #define IS_HRTIM_DACSYNC(DACSYNC)\
2196                 (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
2197                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
2198                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
2199                  ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
2200
2201 #define IS_HRTIM_PRELOAD(PRELOAD)\
2202                 (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
2203                  ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
2204
2205 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
2206                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
2207                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
2208                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
2209
2210 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
2211                 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
2212                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
2213                  ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
2214                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
2215                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
2216                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
2217                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
2218                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
2219                  ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
2220
2221 #define IS_HRTIM_TIMERBURSTMODE(MODE)                               \
2222                 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
2223                  ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
2224 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \
2225                 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
2226                  ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
2227
2228 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
2229                   (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
2230                    ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
2231 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
2232
2233 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
2234       (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
2235        ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
2236
2237 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
2238     ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \
2239         ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
2240           ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \
2241       ||                                                                     \
2242         (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \
2243          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
2244
2245 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
2246           ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
2247             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
2248             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
2249             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
2250             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
2251             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
2252             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
2253             ||                                                                           \
2254             (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
2255              (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
2256              ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
2257
2258 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
2259
2260 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U)
2261
2262
2263 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
2264               (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
2265                ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
2266
2267 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
2268               (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
2269                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
2270                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
2271                ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
2272
2273 /* Auto delayed mode is only available for compare units 2 and 4U */
2274 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
2275     ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
2276      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
2277       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
2278       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
2279       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
2280     ||                                                                         \
2281     (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
2282      (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
2283       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
2284       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
2285       ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
2286
2287 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
2288               (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
2289                ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
2290
2291 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
2292
2293 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
2294               (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)       || \
2295                ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)     || \
2296                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)     || \
2297                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)    || \
2298                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)    || \
2299                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)    || \
2300                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)    || \
2301                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)  || \
2302                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
2303                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
2304                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
2305                ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
2306                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1)    || \
2307                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2)    || \
2308                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3)    || \
2309                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4)    || \
2310                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5)    || \
2311                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6)    || \
2312                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7)    || \
2313                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8)    || \
2314                ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9)    || \
2315                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)      || \
2316                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)      || \
2317                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)      || \
2318                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)      || \
2319                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)      || \
2320                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)      || \
2321                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)      || \
2322                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)      || \
2323                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)      || \
2324                ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)     || \
2325                ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
2326
2327 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
2328               (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)       || \
2329                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)     || \
2330                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)     || \
2331                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)    || \
2332                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)    || \
2333                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)    || \
2334                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)    || \
2335                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)  || \
2336                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
2337                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
2338                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
2339                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
2340                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1)    || \
2341                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2)    || \
2342                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3)    || \
2343                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4)    || \
2344                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5)    || \
2345                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6)    || \
2346                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7)    || \
2347                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8)    || \
2348                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9)    || \
2349                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)      || \
2350                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)      || \
2351                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)      || \
2352                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)      || \
2353                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)      || \
2354                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)      || \
2355                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)      || \
2356                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)      || \
2357                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)      || \
2358                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)     || \
2359                ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
2360
2361 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
2362               (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
2363                ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
2364
2365 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
2366               (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
2367                ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
2368
2369 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
2370               (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
2371                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
2372                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
2373                ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
2374
2375 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
2376               (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
2377                ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
2378
2379 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
2380               (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
2381                ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
2382
2383
2384 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
2385    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
2386    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
2387    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
2388    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
2389    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
2390    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
2391    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
2392    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
2393    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
2394    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
2395    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
2396    ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
2397    ||                                                           \
2398    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
2399      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
2400       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
2401       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2402       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2403       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
2404       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
2405       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2406       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2407       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
2408       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
2409       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2410       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2411       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
2412       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
2413       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2414       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
2415     ||                                                          \
2416    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
2417      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
2418       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
2419       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2420       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2421       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
2422       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
2423       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2424       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2425       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
2426       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
2427       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2428       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2429       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
2430       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
2431       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2432       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
2433     ||                                                          \
2434    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
2435      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
2436       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
2437       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2438       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2439       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
2440       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
2441       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2442       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2443       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
2444       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
2445       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2446       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2447       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
2448       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
2449       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2450       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
2451     ||                                                          \
2452    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
2453      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
2454       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
2455       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2456       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2457       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
2458       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
2459       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2460       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2461       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
2462       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
2463       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2464       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2465       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
2466       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
2467       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2468       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
2469     ||                                                          \
2470    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
2471      (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
2472       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
2473       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2474       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2475       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
2476       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
2477       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2478       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2479       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
2480       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
2481       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2482       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2483       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
2484       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
2485       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2486       ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
2487
2488 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
2489                 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \
2490                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \
2491                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \
2492                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \
2493                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \
2494                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \
2495                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \
2496                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \
2497                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \
2498                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \
2499                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \
2500                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \
2501                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \
2502                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \
2503                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \
2504                  ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
2505
2506 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
2507               (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
2508                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
2509
2510 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
2511                 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
2512                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
2513                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
2514                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
2515                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
2516
2517 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
2518                 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
2519                  ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
2520
2521 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
2522                     (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
2523                      ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
2524
2525 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
2526                   (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
2527                    ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
2528
2529 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
2530                       (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
2531                        ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
2532
2533 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
2534                           (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
2535                            ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
2536
2537 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
2538                         (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
2539                          ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
2540
2541 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
2542                         (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
2543                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
2544                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
2545                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
2546                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
2547                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
2548                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
2549                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
2550                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
2551                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
2552                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
2553                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
2554                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
2555                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
2556                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
2557                          ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
2558
2559 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
2560                         (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
2561                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
2562                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
2563                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
2564                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
2565                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
2566                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
2567                          ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
2568
2569 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
2570                         (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
2571                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
2572                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
2573                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
2574                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
2575                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
2576                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
2577                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
2578                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
2579                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
2580                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
2581                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
2582                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
2583                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
2584                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
2585                          ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
2586
2587 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
2588               (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
2589                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
2590                ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
2591
2592 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
2593               (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
2594                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
2595                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
2596                ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
2597
2598 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
2599               (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
2600                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
2601                ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
2602
2603 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
2604                 (((EVENTSRC) == HRTIM_EVENTSRC_1)   || \
2605                  ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \
2606                  ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \
2607                  ((EVENTSRC) == HRTIM_EVENTSRC_4))
2608
2609 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
2610     ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
2611        (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
2612         ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
2613       ||                                                            \
2614       (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
2615        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
2616        ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
2617
2618 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
2619                     (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
2620                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
2621                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
2622                      ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
2623
2624 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
2625     (((((EVENT) == HRTIM_EVENT_1) ||                 \
2626        ((EVENT) == HRTIM_EVENT_2) ||                 \
2627        ((EVENT) == HRTIM_EVENT_3) ||                 \
2628        ((EVENT) == HRTIM_EVENT_4) ||                 \
2629        ((EVENT) == HRTIM_EVENT_5)) &&                \
2630       (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
2631        ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
2632     ||                                               \
2633     (((EVENT) == HRTIM_EVENT_6) ||                   \
2634      ((EVENT) == HRTIM_EVENT_7) ||                   \
2635      ((EVENT) == HRTIM_EVENT_8) ||                   \
2636      ((EVENT) == HRTIM_EVENT_9) ||                   \
2637      ((EVENT) == HRTIM_EVENT_10)))
2638
2639
2640 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
2641       ((((EVENT) == HRTIM_EVENT_1) ||            \
2642         ((EVENT) == HRTIM_EVENT_2) ||            \
2643         ((EVENT) == HRTIM_EVENT_3) ||            \
2644         ((EVENT) == HRTIM_EVENT_4) ||            \
2645         ((EVENT) == HRTIM_EVENT_5))              \
2646        ||                                        \
2647       ((((EVENT) == HRTIM_EVENT_6) ||            \
2648         ((EVENT) == HRTIM_EVENT_7) ||            \
2649         ((EVENT) == HRTIM_EVENT_8) ||            \
2650         ((EVENT) == HRTIM_EVENT_9) ||            \
2651         ((EVENT) == HRTIM_EVENT_10)) &&          \
2652         (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
2653         ((FILTER) == HRTIM_EVENTFILTER_1)     || \
2654         ((FILTER) == HRTIM_EVENTFILTER_2)     || \
2655         ((FILTER) == HRTIM_EVENTFILTER_3)     || \
2656         ((FILTER) == HRTIM_EVENTFILTER_4)     || \
2657         ((FILTER) == HRTIM_EVENTFILTER_5)     || \
2658         ((FILTER) == HRTIM_EVENTFILTER_6)     || \
2659         ((FILTER) == HRTIM_EVENTFILTER_7)     || \
2660         ((FILTER) == HRTIM_EVENTFILTER_8)     || \
2661         ((FILTER) == HRTIM_EVENTFILTER_9)     || \
2662         ((FILTER) == HRTIM_EVENTFILTER_10)    || \
2663         ((FILTER) == HRTIM_EVENTFILTER_11)    || \
2664         ((FILTER) == HRTIM_EVENTFILTER_12)    || \
2665         ((FILTER) == HRTIM_EVENTFILTER_13)    || \
2666         ((FILTER) == HRTIM_EVENTFILTER_14)    || \
2667         ((FILTER) == HRTIM_EVENTFILTER_15))))
2668
2669 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
2670              (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
2671               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
2672               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
2673               ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
2674
2675 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
2676               (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
2677               ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
2678
2679 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
2680               (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
2681                ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
2682
2683 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
2684     (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
2685      ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
2686
2687 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
2688                 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
2689                  ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
2690                  ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
2691                  ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
2692                  ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
2693                  ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
2694                  ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
2695                  ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
2696                  ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
2697                  ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
2698                  ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
2699                  ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
2700                  ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
2701                  ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
2702                  ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
2703                  ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
2704
2705 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
2706               (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
2707                ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
2708
2709 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
2710              (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
2711               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
2712               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
2713               ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
2714
2715 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
2716               (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
2717                ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
2718
2719 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
2720               (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
2721                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
2722                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
2723                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
2724                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
2725                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
2726                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
2727                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
2728                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
2729                ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
2730
2731 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
2732               (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
2733                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
2734                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
2735                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
2736                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
2737                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
2738                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
2739                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
2740                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
2741                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
2742                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
2743                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
2744                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
2745                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
2746                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
2747                ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
2748
2749 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
2750               (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
2751                ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
2752
2753 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
2754               (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
2755                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
2756                ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
2757                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
2758                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
2759                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
2760                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
2761                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
2762                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
2763                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
2764                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
2765                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
2766                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
2767                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
2768                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
2769                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
2770                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
2771                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
2772                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP2)       || \
2773                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
2774                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
2775                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP1)       || \
2776                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
2777                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_RESET)      || \
2778                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
2779                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
2780                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
2781                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
2782                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
2783                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
2784                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
2785                ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
2786
2787 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
2788              (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
2789               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
2790               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
2791               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
2792               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
2793               ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
2794
2795 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2796     (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION)   || \
2797      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2798      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910)  || \
2799      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114)  || \
2800      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2801
2802 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \
2803     ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
2804   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2805   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2806   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2807   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2808   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
2809
2810 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2811     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
2812      ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2813
2814 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
2815
2816 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
2817
2818 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
2819
2820
2821 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
2822
2823
2824 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
2825
2826
2827 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
2828
2829 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
2830 /**
2831   * @}
2832   */
2833
2834 /* Exported macros -----------------------------------------------------------*/
2835 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
2836   * @ingroup RTEMSBSPsARMSTM32H7
2837   * @{
2838   */
2839
2840 /** @brief Reset HRTIM handle state
2841   * @param  __HANDLE__ HRTIM handle.
2842   * @retval None
2843   */
2844 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
2845 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                do{                                                       \
2846                                                                     (__HANDLE__)->State             = HAL_HRTIM_STATE_RESET; \
2847                                                                     (__HANDLE__)->MspInitCallback   = NULL;                  \
2848                                                                     (__HANDLE__)->MspDeInitCallback = NULL;                 \
2849                                                                   } while(0)
2850 #else
2851 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
2852 #endif
2853
2854 /** @brief  Enables or disables the timer counter(s)
2855   * @param  __HANDLE__ specifies the HRTIM Handle.
2856   * @param  __TIMERS__ timers to enable/disable
2857   *        This parameter can be any combinations of the following values:
2858   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
2859   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
2860   *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
2861   *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
2862   *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
2863   *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
2864   * @retval None
2865   */
2866 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
2867
2868 /* The counter of a timing unit is disabled only if all the timer outputs */
2869 /* are disabled and no capture is configured                              */
2870 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2871 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2872 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2873 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2874 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2875 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2876   do {\
2877     if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2878       {\
2879         ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
2880       }\
2881     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2882       {\
2883         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
2884           {\
2885             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2886           }\
2887       }\
2888     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2889       {\
2890         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
2891           {\
2892             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2893           }\
2894       }\
2895     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2896       {\
2897         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
2898           {\
2899             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2900           }\
2901       }\
2902     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2903       {\
2904         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
2905           {\
2906             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2907           }\
2908       }\
2909     if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2910       {\
2911         if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
2912           {\
2913             ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2914           }\
2915       }\
2916   } while(0U)
2917
2918
2919 /** @brief  Enables or disables the specified HRTIM common interrupts.
2920   * @param  __HANDLE__ specifies the HRTIM Handle.
2921   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
2922   *        This parameter can be one of the following values:
2923   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2924   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2925   *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
2926   *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
2927   *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
2928   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2929   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2930   * @retval None
2931   */
2932 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
2933 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
2934
2935 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
2936   * @param  __HANDLE__ specifies the HRTIM Handle.
2937   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
2938   *        This parameter can be one of the following values:
2939   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2940   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2941   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2942   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2943   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2944   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2945   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2946   * @retval None
2947   */
2948 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
2949 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
2950
2951 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
2952   * @param  __HANDLE__ specifies the HRTIM Handle.
2953   * @param  __TIMER__ specified the timing unit (Timer A to E)
2954   * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
2955   *        This parameter can be one of the following values:
2956   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
2957   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
2958   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
2959   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
2960   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
2961   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
2962   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
2963   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
2964   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
2965   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
2966   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
2967   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
2968   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
2969   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
2970   * @retval None
2971   */
2972 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
2973 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
2974
2975 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
2976   * @param  __HANDLE__ specifies the HRTIM Handle.
2977   * @param  __INTERRUPT__ specifies the interrupt source to check.
2978   *        This parameter can be one of the following values:
2979   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2980   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2981   *            @arg HRTIM_IT_FLT3: Fault 3 enable
2982   *            @arg HRTIM_IT_FLT4: Fault 4 enable
2983   *            @arg HRTIM_IT_FLT5: Fault 5 enable
2984   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2985   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2986   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2987   */
2988 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2989
2990 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
2991   * @param  __HANDLE__ specifies the HRTIM Handle.
2992   * @param  __INTERRUPT__ specifies the interrupt source to check.
2993   *        This parameter can be one of the following values:
2994   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2995   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2996   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2997   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2998   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2999   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
3000   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
3001   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
3002   */
3003 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
3004
3005 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
3006   * @param  __HANDLE__ specifies the HRTIM Handle.
3007   * @param  __TIMER__ specified the timing unit (Timer A to E)
3008   * @param  __INTERRUPT__ specifies the interrupt source to check.
3009   *        This parameter can be one of the following values:
3010   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
3011   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
3012   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
3013   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
3014   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
3015   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
3016   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
3017   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
3018   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
3019   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
3020   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
3021   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
3022   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
3023   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
3024   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
3025   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
3026   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
3027   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
3028   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
3029   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
3030   *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
3031   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
3032   */
3033 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
3034
3035 /** @brief  Clears the specified HRTIM common pending flag.
3036   * @param  __HANDLE__ specifies the HRTIM Handle.
3037   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
3038   *        This parameter can be one of the following values:
3039   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
3040   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
3041   *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
3042   *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
3043   *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
3044   *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
3045   *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
3046   * @retval None
3047   */
3048 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
3049
3050 /** @brief  Clears the specified HRTIM Master pending flag.
3051   * @param  __HANDLE__ specifies the HRTIM Handle.
3052   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
3053   *        This parameter can be one of the following values:
3054   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
3055   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
3056   *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
3057   *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
3058   *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
3059   *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
3060   *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
3061   * @retval None
3062   */
3063 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
3064
3065 /** @brief  Clears the specified HRTIM Timerx pending flag.
3066   * @param  __HANDLE__ specifies the HRTIM Handle.
3067   * @param  __TIMER__ specified the timing unit (Timer A to E)
3068   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
3069   *        This parameter can be one of the following values:
3070   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
3071   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
3072   *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
3073   *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
3074   *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
3075   *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
3076   *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
3077   *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
3078   *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
3079   *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
3080   *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
3081   *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
3082   *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
3083   *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
3084   * @retval None
3085   */
3086 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
3087
3088 /* DMA HANDLING */
3089 /** @brief  Enables or disables the specified HRTIM Master timer DMA requests.
3090   * @param  __HANDLE__ specifies the HRTIM Handle.
3091   * @param  __DMA__ specifies the DMA request to enable or disable.
3092   *        This parameter can be one of the following values:
3093   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
3094   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
3095   *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
3096   *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
3097   *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
3098   *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
3099   *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
3100   * @retval None
3101   */
3102 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
3103 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
3104
3105 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
3106   * @param  __HANDLE__ specifies the HRTIM Handle.
3107   * @param  __TIMER__ specified the timing unit (Timer A to E)
3108   * @param  __DMA__ specifies the DMA request to enable or disable.
3109   *        This parameter can be one of the following values:
3110   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
3111   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
3112   *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
3113   *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
3114   *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
3115   *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
3116   *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
3117   *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
3118   *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
3119   *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
3120   *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
3121   *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
3122   *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
3123   *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
3124   * @retval None
3125   */
3126 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
3127 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
3128
3129 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
3130 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
3131
3132 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
3133 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
3134
3135 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
3136 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
3137
3138 /** @brief  Sets the HRTIM timer Counter Register value on runtime
3139   * @param  __HANDLE__ HRTIM Handle.
3140   * @param  __TIMER__ HRTIM timer
3141   *                   This parameter can be one of the following values:
3142   *                   @arg 0x5 for master timer
3143   *                   @arg 0x0 to 0x4 for timers A to E
3144   * @param  __COUNTER__ specifies the Counter Register new value.
3145   * @retval None
3146   */
3147 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
3148   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
3149    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
3150
3151 /** @brief  Gets the HRTIM timer Counter Register value on runtime
3152   * @param  __HANDLE__ HRTIM Handle.
3153   * @param  __TIMER__ HRTIM timer
3154   *                   This parameter can be one of the following values:
3155   *                   @arg 0x5 for master timer
3156   *                   @arg 0x0 to 0x4 for timers A to E
3157   * @retval HRTIM timer Counter Register value
3158   */
3159 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
3160   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
3161    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
3162
3163 /** @brief  Sets the HRTIM timer Period value on runtime
3164   * @param  __HANDLE__ HRTIM Handle.
3165   * @param  __TIMER__ HRTIM timer
3166   *                   This parameter can be one of the following values:
3167   *                   @arg 0x5 for master timer
3168   *                   @arg 0x0 to 0x4 for timers A to E
3169   * @param  __PERIOD__ specifies the Period Register new value.
3170   * @retval None
3171   */
3172 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
3173   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
3174    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
3175
3176 /** @brief  Gets the HRTIM timer Period Register value on runtime
3177   * @param  __HANDLE__ HRTIM Handle.
3178   * @param  __TIMER__ HRTIM timer
3179   *                   This parameter can be one of the following values:
3180   *                   @arg 0x5 for master timer
3181   *                   @arg 0x0 to 0x4 for timers A to E
3182   * @retval timer Period Register
3183   */
3184 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
3185   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
3186    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
3187
3188 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
3189   * @param  __HANDLE__ HRTIM Handle.
3190   * @param  __TIMER__ HRTIM timer
3191   *                   This parameter can be one of the following values:
3192   *                   @arg 0x5 for master timer
3193   *                   @arg 0x0 to 0x4 for timers A to E
3194   * @param  __PRESCALER__ specifies the clock prescaler new value.
3195   *                   This parameter can be one of the following values:
3196   *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
3197   *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
3198   *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
3199   * @retval None
3200   */
3201 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
3202   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
3203    (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
3204
3205 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
3206   * @param  __HANDLE__ HRTIM Handle.
3207   * @param  __TIMER__ HRTIM timer
3208   *                   This parameter can be one of the following values:
3209   *                   @arg 0x5 for master timer
3210   *                   @arg 0x0 to 0x4 for timers A to E
3211   * @retval timer clock prescaler value
3212   */
3213 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
3214   (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
3215    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
3216
3217 /** @brief  Sets the HRTIM timer Compare Register value on runtime
3218   * @param  __HANDLE__ HRTIM Handle.
3219   * @param  __TIMER__ HRTIM timer
3220   *                   This parameter can be one of the following values:
3221   *                   @arg 0x0 to 0x4 for timers A to E
3222   * @param  __COMPAREUNIT__ timer compare unit
3223   *                   This parameter can be one of the following values:
3224   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3225   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3226   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3227   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3228   * @param  __COMPARE__ specifies the Compare new value.
3229   * @retval None
3230   */
3231 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
3232       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3233         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
3234          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
3235          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
3236          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
3237          : \
3238         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
3239          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
3240          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
3241          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
3242
3243 /** @brief  Gets the HRTIM timer Compare Register value on runtime
3244   * @param  __HANDLE__ HRTIM Handle.
3245   * @param  __TIMER__ HRTIM timer
3246   *                   This parameter can be one of the following values:
3247   *                   @arg 0x0 to 0x4 for timers A to E
3248   * @param  __COMPAREUNIT__ timer compare unit
3249   *                   This parameter can be one of the following values:
3250   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3251   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3252   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3253   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3254   * @retval Compare value
3255   */
3256 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
3257       (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3258         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
3259          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
3260          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
3261          ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
3262          : \
3263         (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
3264          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
3265          ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
3266          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
3267
3268 /**
3269   * @}
3270   */
3271
3272 /* Exported functions --------------------------------------------------------*/
3273 /** @addtogroup HRTIM_Exported_Functions
3274 * @{
3275 */
3276
3277 /** @addtogroup HRTIM_Exported_Functions_Group1
3278 * @{
3279 */
3280
3281 /* Initialization and Configuration functions  ********************************/
3282 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
3283
3284 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
3285
3286 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
3287
3288 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
3289
3290 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
3291                                            uint32_t TimerIdx,
3292                                            const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
3293 /**
3294   * @}
3295   */
3296
3297 /** @addtogroup HRTIM_Exported_Functions_Group2
3298 * @{
3299 */
3300
3301 /* Simple time base related functions  *****************************************/
3302 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
3303                                            uint32_t TimerIdx);
3304
3305 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
3306                                           uint32_t TimerIdx);
3307
3308 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3309                                               uint32_t TimerIdx);
3310
3311 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3312                                              uint32_t TimerIdx);
3313
3314 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3315                                                uint32_t TimerIdx,
3316                                                uint32_t SrcAddr,
3317                                                uint32_t DestAddr,
3318                                                uint32_t Length);
3319
3320 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3321                                               uint32_t TimerIdx);
3322
3323 /**
3324   * @}
3325   */
3326
3327 /** @addtogroup HRTIM_Exported_Functions_Group3
3328 * @{
3329 */
3330 /* Simple output compare related functions  ************************************/
3331 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3332                                                  uint32_t TimerIdx,
3333                                                  uint32_t OCChannel,
3334                                                  const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
3335
3336 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
3337                                          uint32_t TimerIdx,
3338                                          uint32_t OCChannel);
3339
3340 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
3341                                         uint32_t TimerIdx,
3342                                         uint32_t OCChannel);
3343
3344 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
3345                                             uint32_t TimerIdx,
3346                                             uint32_t OCChannel);
3347
3348 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
3349                                            uint32_t TimerIdx,
3350                                            uint32_t OCChannel);
3351
3352 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3353                                              uint32_t TimerIdx,
3354                                              uint32_t OCChannel,
3355                                              uint32_t SrcAddr,
3356                                              uint32_t DestAddr,
3357                                              uint32_t Length);
3358
3359 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3360                                             uint32_t TimerIdx,
3361                                             uint32_t OCChannel);
3362
3363 /**
3364   * @}
3365   */
3366
3367 /** @addtogroup HRTIM_Exported_Functions_Group4
3368 * @{
3369 */
3370 /* Simple PWM output related functions  ****************************************/
3371 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3372                                                   uint32_t TimerIdx,
3373                                                   uint32_t PWMChannel,
3374                                                   const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
3375
3376 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
3377                                           uint32_t TimerIdx,
3378                                           uint32_t PWMChannel);
3379
3380 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
3381                                          uint32_t TimerIdx,
3382                                          uint32_t PWMChannel);
3383
3384 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
3385                                              uint32_t TimerIdx,
3386                                              uint32_t PWMChannel);
3387
3388 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
3389                                             uint32_t TimerIdx,
3390                                             uint32_t PWMChannel);
3391
3392 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3393                                               uint32_t TimerIdx,
3394                                               uint32_t PWMChannel,
3395                                               uint32_t SrcAddr,
3396                                               uint32_t DestAddr,
3397                                               uint32_t Length);
3398
3399 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3400                                              uint32_t TimerIdx,
3401                                              uint32_t PWMChannel);
3402
3403 /**
3404   * @}
3405   */
3406
3407 /** @addtogroup HRTIM_Exported_Functions_Group5
3408 * @{
3409 */
3410 /* Simple capture related functions  *******************************************/
3411 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3412                                                       uint32_t TimerIdx,
3413                                                       uint32_t CaptureChannel,
3414                                                       const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
3415
3416 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
3417                                               uint32_t TimerIdx,
3418                                               uint32_t CaptureChannel);
3419
3420 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
3421                                              uint32_t TimerIdx,
3422                                              uint32_t CaptureChannel);
3423
3424 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
3425                                                  uint32_t TimerIdx,
3426                                                  uint32_t CaptureChannel);
3427
3428 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
3429                                                 uint32_t TimerIdx,
3430                                                 uint32_t CaptureChannel);
3431
3432 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3433                                                   uint32_t TimerIdx,
3434                                                   uint32_t CaptureChannel,
3435                                                   uint32_t SrcAddr,
3436                                                   uint32_t DestAddr,
3437                                                   uint32_t Length);
3438
3439 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3440                                                  uint32_t TimerIdx,
3441                                                  uint32_t CaptureChannel);
3442
3443 /**
3444   * @}
3445   */
3446
3447 /** @addtogroup HRTIM_Exported_Functions_Group6
3448 * @{
3449 */
3450 /* Simple one pulse related functions  *****************************************/
3451 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3452                                                        uint32_t TimerIdx,
3453                                                        uint32_t OnePulseChannel,
3454                                                        const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
3455
3456 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
3457                                                uint32_t TimerIdx,
3458                                                uint32_t OnePulseChannel);
3459
3460 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
3461                                               uint32_t TimerIdx,
3462                                              uint32_t OnePulseChannel);
3463
3464 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3465                                                   uint32_t TimerIdx,
3466                                                   uint32_t OnePulseChannel);
3467
3468 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3469                                                  uint32_t TimerIdx,
3470                                                  uint32_t OnePulseChannel);
3471
3472 /**
3473   * @}
3474   */
3475
3476 /** @addtogroup HRTIM_Exported_Functions_Group7
3477 * @{
3478 */
3479 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
3480                                             const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
3481
3482 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
3483                                         uint32_t Event,
3484                                         const HRTIM_EventCfgTypeDef* pEventCfg);
3485
3486 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3487                                                  uint32_t Prescaler);
3488
3489 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
3490                                         uint32_t Fault,
3491                                         const HRTIM_FaultCfgTypeDef* pFaultCfg);
3492
3493 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3494                                                  uint32_t Prescaler);
3495
3496 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3497                             uint32_t Faults,
3498                             uint32_t Enable);
3499
3500 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
3501                                              uint32_t ADCTrigger,
3502                                              const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
3503
3504 /**
3505   * @}
3506   */
3507
3508 /** @addtogroup HRTIM_Exported_Functions_Group8
3509 * @{
3510 */
3511 /* Waveform related functions *************************************************/
3512 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
3513                                                 uint32_t TimerIdx,
3514                                                 const HRTIM_TimerCfgTypeDef * pTimerCfg);
3515
3516 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
3517                                                   uint32_t TimerIdx,
3518                                                   uint32_t CompareUnit,
3519                                                   const HRTIM_CompareCfgTypeDef* pCompareCfg);
3520
3521 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
3522                                                   uint32_t TimerIdx,
3523                                                   uint32_t CaptureUnit,
3524                                                   const HRTIM_CaptureCfgTypeDef* pCaptureCfg);
3525
3526 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
3527                                                  uint32_t TimerIdx,
3528                                                  uint32_t Output,
3529                                                  const HRTIM_OutputCfgTypeDef * pOutputCfg);
3530
3531 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
3532                                                    uint32_t TimerIdx,
3533                                                    uint32_t Output,
3534                                                    uint32_t OutputLevel);
3535
3536 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
3537                                                       uint32_t TimerIdx,
3538                                                       uint32_t Event,
3539                                                       const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
3540
3541 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
3542                                            uint32_t TimerIdx,
3543                                            const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
3544
3545 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
3546                                               uint32_t TimerIdx,
3547                                               const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
3548
3549 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
3550                                            uint32_t TimerIdx,
3551                                            uint32_t RegistersToUpdate);
3552
3553
3554 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
3555                                                  uint32_t Timers);
3556
3557 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
3558                                                  uint32_t Timers);
3559
3560 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
3561                                                  uint32_t Timers);
3562
3563 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
3564                                                  uint32_t Timers);
3565
3566 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3567                                                      uint32_t Timers);
3568
3569 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3570                                                     uint32_t Timers);
3571
3572 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
3573                                                 uint32_t OutputsToStart);
3574
3575 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
3576                                                uint32_t OutputsToStop);
3577
3578 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
3579                                          uint32_t Enable);
3580
3581 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
3582
3583 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
3584                                             uint32_t TimerIdx,
3585                                             uint32_t CaptureUnit);
3586
3587 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
3588                                            uint32_t Timers);
3589
3590 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
3591                                           uint32_t Timers);
3592
3593 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
3594                                              uint32_t TimerIdx,
3595                                              uint32_t BurstBufferAddress,
3596                                              uint32_t BurstBufferLength);
3597
3598 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
3599                                           uint32_t Timers);
3600
3601 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
3602                                           uint32_t Timers);
3603
3604 /**
3605   * @}
3606   */
3607
3608 /** @addtogroup HRTIM_Exported_Functions_Group9
3609 * @{
3610 */
3611 /* HRTIM peripheral state functions */
3612 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim);
3613
3614 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
3615                                     uint32_t TimerIdx,
3616                                     uint32_t CaptureUnit);
3617
3618 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
3619                                           uint32_t TimerIdx,
3620                                           uint32_t Output);
3621
3622 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
3623                                           uint32_t TimerIdx,
3624                                           uint32_t Output);
3625
3626 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
3627                                               uint32_t TimerIdx,
3628                                               uint32_t Output);
3629
3630 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim);
3631
3632 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
3633                                             uint32_t TimerIdx);
3634
3635 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
3636                                          uint32_t TimerIdx);
3637
3638 /**
3639   * @}
3640   */
3641
3642 /** @addtogroup HRTIM_Exported_Functions_Group10
3643 * @{
3644 */
3645 /* IRQ handler */
3646 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
3647                           uint32_t TimerIdx);
3648
3649 /* HRTIM events related callback functions */
3650 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
3651 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
3652 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
3653 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
3654 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
3655 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
3656 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
3657 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
3658
3659 /* Timer events related callback functions */
3660 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
3661                                               uint32_t TimerIdx);
3662 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
3663                                               uint32_t TimerIdx);
3664 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
3665                                             uint32_t TimerIdx);
3666 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
3667                                             uint32_t TimerIdx);
3668 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
3669                                             uint32_t TimerIdx);
3670 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
3671                                             uint32_t TimerIdx);
3672 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
3673                                             uint32_t TimerIdx);
3674 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
3675                                             uint32_t TimerIdx);
3676 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
3677                                                 uint32_t TimerIdx);
3678 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
3679                                            uint32_t TimerIdx);
3680 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
3681                                          uint32_t TimerIdx);
3682 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
3683                                            uint32_t TimerIdx);
3684 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
3685                                          uint32_t TimerIdx);
3686 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
3687                                            uint32_t TimerIdx);
3688 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
3689                                                uint32_t TimerIdx);
3690 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
3691
3692 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
3693 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
3694                                              HAL_HRTIM_CallbackIDTypeDef CallbackID,
3695                                              pHRTIM_CallbackTypeDef      pCallback);
3696
3697 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
3698                                                HAL_HRTIM_CallbackIDTypeDef CallbackID);
3699
3700 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *        hhrtim,
3701                                                  HAL_HRTIM_CallbackIDTypeDef  CallbackID,
3702                                                  pHRTIM_TIMxCallbackTypeDef   pCallback);
3703
3704 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,
3705                                                    HAL_HRTIM_CallbackIDTypeDef CallbackID);
3706 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
3707
3708 /**
3709   * @}
3710   */
3711
3712 /**
3713   * @}
3714   */
3715
3716 /**
3717   * @}
3718   */
3719
3720 /**
3721   * @}
3722   */
3723
3724 #endif /* HRTIM1 */
3725
3726 #ifdef __cplusplus
3727 }
3728 #endif
3729
3730 #endif /* STM32H7xx_HAL_HRTIM_H */