stm32h7/include/stm32h7xx_hal_gfxmmu.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_gfxmmu.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of GFXMMU HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_GFXMMU_H
0021 #define STM32H7xx_HAL_GFXMMU_H
0022
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif
0026
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029
0030 #if defined(GFXMMU)
0031
0032 /** @addtogroup STM32H7xx_HAL_Driver
0033   * @{
0034   */
0035
0036 /** @addtogroup GFXMMU
0037   * @{
0038   */
0039
0040 /* Exported types ------------------------------------------------------------*/
0041 /** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
0042   * @ingroup RTEMSBSPsARMSTM32H7
0043   * @{
0044   */
0045
0046 /**
0047   * @brief  HAL GFXMMU states definition
0048   */
0049 typedef enum
0050 {
0051   HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */
0052   HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */
0053 }HAL_GFXMMU_StateTypeDef;
0054
0055 /**
0056   * @brief  GFXMMU buffers structure definition
0057   */
0058 typedef struct
0059 {
0060   uint32_t Buf0Address; /*!< Physical address of buffer 0. */
0061   uint32_t Buf1Address; /*!< Physical address of buffer 1. */
0062   uint32_t Buf2Address; /*!< Physical address of buffer 2. */
0063   uint32_t Buf3Address; /*!< Physical address of buffer 3. */
0064 }GFXMMU_BuffersTypeDef;
0065
0066 /**
0067   * @brief  GFXMMU cache and pre-fetch structure definition
0068   */
0069 typedef struct
0070 {
0071   FunctionalState Activation;          /*!< Cache and pre-fetch enable/disable.
0072                                             @note: All following parameters are useful only if cache and pre-fetch are enabled. */
0073   uint32_t        CacheLock;           /*!< Locking the cache to a buffer.
0074                                             This parameter can be a value of @ref GFXMMU_CacheLock. */
0075   uint32_t        CacheLockBuffer;     /*!< Buffer on which the cache is locked.
0076                                             This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
0077                                             @note: Useful only when lock of the cache is enabled. */
0078   uint32_t        CacheForce;          /*!< Forcing the cache regardless MPU attributes.
0079                                             This parameter can be a value of @ref GFXMMU_CacheForce.
0080                                             @note: Useful only when lock of the cache is enabled. */
0081   uint32_t        OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
0082                                             This parameter can be a value of @ref GFXMMU_OutterBufferability. */
0083   uint32_t        OutterCachability;   /*!< Cachability of an access generated by the GFXMMU cache.
0084                                             This parameter can be a value of @ref GFXMMU_OutterCachability. */
0085   uint32_t        Prefetch;            /*!< Pre-fetch enable/disable.
0086                                             This parameter can be a value of @ref GFXMMU_Prefetch. */
0087 }GFXMMU_CachePrefetchTypeDef;
0088
0089 /**
0090   * @brief  GFXMMU interrupts structure definition
0091   */
0092 typedef struct
0093 {
0094   FunctionalState Activation;     /*!< Interrupts enable/disable */
0095   uint32_t        UsedInterrupts; /*!< Interrupts used.
0096                                        This parameter can be a values combination of @ref GFXMMU_Interrupts.
0097                                        @note: Useful only when interrupts are enabled. */
0098 }GFXMMU_InterruptsTypeDef;
0099
0100 /**
0101   * @brief  GFXMMU init structure definition
0102   */
0103 typedef struct
0104 {
0105   uint32_t                    BlocksPerLine; /*!< Number of blocks of 16 bytes per line.
0106                                                   This parameter can be a value of @ref GFXMMU_BlocksPerLine. */
0107   uint32_t                    DefaultValue;  /*!< Value returned when virtual memory location not physically mapped. */
0108   GFXMMU_BuffersTypeDef       Buffers;       /*!< Physical buffers addresses. */
0109   GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */
0110   GFXMMU_InterruptsTypeDef    Interrupts;    /*!< Interrupts parameters. */
0111 }GFXMMU_InitTypeDef;
0112
0113 /**
0114   * @brief  GFXMMU handle structure definition
0115   */
0116 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0117 typedef struct __GFXMMU_HandleTypeDef
0118 #else
0119 typedef struct
0120 #endif
0121 {
0122   GFXMMU_TypeDef          *Instance; /*!< GFXMMU instance */
0123   GFXMMU_InitTypeDef      Init;      /*!< GFXMMU init parameters */
0124   HAL_GFXMMU_StateTypeDef State;     /*!< GFXMMU state */
0125   __IO uint32_t           ErrorCode; /*!< GFXMMU error code */
0126 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0127   void (*ErrorCallback)     (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
0128   void (*MspInitCallback)   (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
0129   void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
0130 #endif
0131 }GFXMMU_HandleTypeDef;
0132
0133 /**
0134   * @brief  GFXMMU LUT line structure definition
0135   */
0136 typedef struct
0137 {
0138   uint32_t LineNumber;        /*!< LUT line number.
0139                                    This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
0140   uint32_t LineStatus;        /*!< LUT line enable/disable.
0141                                    This parameter can be a value of @ref GFXMMU_LutLineStatus. */
0142   uint32_t FirstVisibleBlock; /*!< First visible block on this line.
0143                                    This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
0144   uint32_t LastVisibleBlock;  /*!< Last visible block on this line.
0145                                    This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
0146   int32_t  LineOffset;        /*!< Offset of block 0 of the current line in physical buffer.
0147                                    This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.
0148                                    @note: Line offset has to be computed with the following formula:
0149                                           LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
0150 }GFXMMU_LutLineTypeDef;
0151
0152 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0153 /**
0154   * @brief  GFXMMU callback ID enumeration definition
0155   */
0156 typedef enum
0157 {
0158   HAL_GFXMMU_ERROR_CB_ID     = 0x00U, /*!< GFXMMU error callback ID */
0159   HAL_GFXMMU_MSPINIT_CB_ID   = 0x01U, /*!< GFXMMU MSP init callback ID */
0160   HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U  /*!< GFXMMU MSP de-init callback ID */
0161 }HAL_GFXMMU_CallbackIDTypeDef;
0162
0163 /**
0164   * @brief  GFXMMU callback pointer definition
0165   */
0166 typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
0167 #endif
0168
0169 /**
0170   * @}
0171   */
0172 /* End of exported types -----------------------------------------------------*/
0173
0174 /* Exported constants --------------------------------------------------------*/
0175 /** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
0176   * @ingroup RTEMSBSPsARMSTM32H7
0177   * @{
0178   */
0179
0180 /** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line
0181   * @ingroup RTEMSBSPsARMSTM32H7
0182   * @{
0183   */
0184 #define GFXMMU_256BLOCKS 0x00000000U     /*!< 256 blocks of 16 bytes per line */
0185 #define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */
0186 /**
0187   * @}
0188   */
0189
0190 /** @defgroup GFXMMU_CacheLock GFXMMU cache lock
0191   * @ingroup RTEMSBSPsARMSTM32H7
0192   * @{
0193   */
0194 #define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U  /*!< Cache not locked to a buffer */
0195 #define GFXMMU_CACHE_LOCK_ENABLE  GFXMMU_CR_CL /*!< Cache locked to a buffer */
0196 /**
0197   * @}
0198   */
0199
0200 /** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer
0201   * @ingroup RTEMSBSPsARMSTM32H7
0202   * @{
0203   */
0204 #define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U     /*!< Cache locked to buffer 0 */
0205 #define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */
0206 #define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */
0207 #define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB   /*!< Cache locked to buffer 3 */
0208 /**
0209   * @}
0210   */
0211
0212 /** @defgroup GFXMMU_CacheForce GFXMMU cache force
0213   * @ingroup RTEMSBSPsARMSTM32H7
0214   * @{
0215   */
0216 #define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U  /*!< Caching not forced */
0217 #define GFXMMU_CACHE_FORCE_ENABLE  GFXMMU_CR_FC /*!< Caching forced */
0218 /**
0219   * @}
0220   */
0221
0222 /** @defgroup GFXMMU_OutterBufferability GFXMMU outer bufferability
0223   * @ingroup RTEMSBSPsARMSTM32H7
0224   * @{
0225   */
0226 #define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U  /*!< No bufferable */
0227 #define GFXMMU_OUTTER_BUFFERABILITY_ENABLE  GFXMMU_CR_OB /*!< Bufferable */
0228 /**
0229   * @}
0230   */
0231
0232 /** @defgroup GFXMMU_OutterCachability GFXMMU outer cachability
0233   * @ingroup RTEMSBSPsARMSTM32H7
0234   * @{
0235   */
0236 #define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U  /*!< No cacheable */
0237 #define GFXMMU_OUTTER_CACHABILITY_ENABLE  GFXMMU_CR_OC /*!< Cacheable */
0238 /**
0239   * @}
0240   */
0241
0242 /** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch
0243   * @ingroup RTEMSBSPsARMSTM32H7
0244   * @{
0245   */
0246 #define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */
0247 #define GFXMMU_PREFETCH_ENABLE  0x00000000U  /*!< Pre-fetch enable */
0248 /**
0249   * @}
0250   */
0251
0252 /** @defgroup GFXMMU_Interrupts GFXMMU interrupts
0253   * @ingroup RTEMSBSPsARMSTM32H7
0254   * @{
0255   */
0256 #define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */
0257 #define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */
0258 #define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */
0259 #define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */
0260 #define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */
0261 /**
0262   * @}
0263   */
0264
0265 /** @defgroup GFXMMU_Error_Code GFXMMU Error Code
0266   * @ingroup RTEMSBSPsARMSTM32H7
0267   * @{
0268   */
0269 #define GFXMMU_ERROR_NONE             0x00000000U    /*!< No error */
0270 #define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */
0271 #define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */
0272 #define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
0273 #define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
0274 #define GFXMMU_ERROR_AHB_MASTER       GFXMMU_SR_AMEF /*!< AHB master error */
0275 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0276 #define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U    /*!< Invalid callback error */
0277 #endif
0278 /**
0279   * @}
0280   */
0281
0282 /** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
0283   * @ingroup RTEMSBSPsARMSTM32H7
0284   * @{
0285   */
0286 #define GFXMMU_LUT_LINE_DISABLE 0x00000000U     /*!< LUT line disabled */
0287 #define GFXMMU_LUT_LINE_ENABLE  GFXMMU_LUTxL_EN /*!< LUT line enabled */
0288 /**
0289   * @}
0290   */
0291
0292 /** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter
0293   * @ingroup RTEMSBSPsARMSTM32H7
0294   * @{
0295   */
0296 #define GFXMMU_CACHE_FORCE_FLUSH      GFXMMU_CCR_FF /*!< Force cache flush */
0297 #define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */
0298 /**
0299   * @}
0300   */
0301
0302 /**
0303   * @}
0304   */
0305 /* End of exported constants -------------------------------------------------*/
0306
0307 /* Exported macros -----------------------------------------------------------*/
0308 /** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
0309   * @ingroup RTEMSBSPsARMSTM32H7
0310  * @{
0311  */
0312
0313 /** @brief  Reset GFXMMU handle state.
0314   * @param  __HANDLE__ GFXMMU handle.
0315   * @retval None
0316   */
0317 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0318 #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
0319                                                         (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
0320                                                         (__HANDLE__)->MspInitCallback = NULL;         \
0321                                                         (__HANDLE__)->MspDeInitCallback = NULL;       \
0322                                                       } while(0)
0323 #else
0324 #define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
0325 #endif
0326
0327 /**
0328   * @}
0329   */
0330 /* End of exported macros ----------------------------------------------------*/
0331
0332 /* Exported functions --------------------------------------------------------*/
0333 /** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
0334   * @{
0335   */
0336
0337 /** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
0338   * @{
0339   */
0340 /* Initialization and de-initialization functions *****************************/
0341 HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
0342 HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
0343 void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
0344 void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
0345 #if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
0346 /* GFXMMU callbacks register/unregister functions *****************************/
0347 HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
0348                                               HAL_GFXMMU_CallbackIDTypeDef CallbackID,
0349                                               pGFXMMU_CallbackTypeDef      pCallback);
0350 HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
0351                                                 HAL_GFXMMU_CallbackIDTypeDef CallbackID);
0352 #endif
0353 /**
0354   * @}
0355   */
0356
0357 /** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
0358   * @{
0359   */
0360 /* Operation functions ********************************************************/
0361 HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
0362                                        uint32_t FirstLine,
0363                                        uint32_t LinesNumber,
0364                                        uint32_t Address);
0365
0366 HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
0367                                              uint32_t FirstLine,
0368                                              uint32_t LinesNumber);
0369
0370 HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);
0371
0372 HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);
0373
0374 HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);
0375
0376 HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
0377                                                  GFXMMU_CachePrefetchTypeDef *CachePrefetch);
0378
0379 void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
0380
0381 void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
0382 /**
0383   * @}
0384   */
0385
0386 /** @defgroup GFXMMU_Exported_Functions_Group3 State functions
0387   * @ingroup RTEMSBSPsARMSTM32H7
0388   * @{
0389   */
0390 /* State function *************************************************************/
0391 HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);
0392
0393 uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
0394 /**
0395   * @}
0396   */
0397
0398 /**
0399   * @}
0400   */
0401 /* End of exported functions -------------------------------------------------*/
0402
0403 /* Private macros ------------------------------------------------------------*/
0404 /** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
0405   * @ingroup RTEMSBSPsARMSTM32H7
0406 * @{
0407 */
0408 #define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \
0409                                           ((VALUE) == GFXMMU_192BLOCKS))
0410
0411 #define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
0412
0413 #define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
0414                                      ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))
0415
0416 #define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
0417                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
0418                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
0419                                             ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))
0420
0421 #define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
0422                                       ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))
0423
0424 #define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
0425                                                ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))
0426
0427 #define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
0428                                              ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))
0429
0430 #define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
0431                                    ((VALUE) == GFXMMU_PREFETCH_ENABLE))
0432
0433 #define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
0434
0435 #define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
0436
0437 #define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
0438
0439 #define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
0440                                           ((VALUE) == GFXMMU_LUT_LINE_ENABLE))
0441
0442 #define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
0443
0444 #define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
0445
0446 #define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
0447                                              ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
0448                                              ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))
0449 /**
0450   * @}
0451   */
0452 /* End of private macros -----------------------------------------------------*/
0453
0454 /**
0455   * @}
0456   */
0457
0458 /**
0459   * @}
0460   */
0461 #endif /* GFXMMU */
0462 #ifdef __cplusplus
0463 }
0464 #endif
0465
0466 #endif /* STM32H7xx_HAL_GFXMMU_H */
0467