stm32h7/include/stm32h7xx_hal_fdcan.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_fdcan.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of FDCAN HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_FDCAN_H
0021 #define STM32H7xx_HAL_FDCAN_H
0022
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029
0030 #if defined(FDCAN1)
0031
0032 /** @addtogroup STM32H7xx_HAL_Driver
0033   * @{
0034   */
0035
0036 /** @addtogroup FDCAN
0037   * @{
0038   */
0039
0040 /* Exported types ------------------------------------------------------------*/
0041 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
0042   * @ingroup RTEMSBSPsARMSTM32H7
0043   * @{
0044   */
0045
0046 /**
0047   * @brief HAL State structures definition
0048   */
0049 typedef enum
0050 {
0051   HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */
0052   HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */
0053   HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */
0054   HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */
0055 } HAL_FDCAN_StateTypeDef;
0056
0057 /**
0058   * @brief FDCAN Init structure definition
0059   */
0060 typedef struct
0061 {
0062   uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.
0063                                               This parameter can be a value of @ref FDCAN_frame_format     */
0064
0065   uint32_t Mode;                         /*!< Specifies the FDCAN mode.
0066                                               This parameter can be a value of @ref FDCAN_operating_mode   */
0067
0068   FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.
0069                                               This parameter can be set to ENABLE or DISABLE               */
0070
0071   FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.
0072                                               This parameter can be set to ENABLE or DISABLE               */
0073
0074   FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.
0075                                               This parameter can be set to ENABLE or DISABLE               */
0076
0077   uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is
0078                                               divided for generating the nominal bit time quanta.
0079                                               This parameter must be a number between 1 and 512            */
0080
0081   uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN
0082                                               hardware is allowed to lengthen or shorten a bit to perform
0083                                               resynchronization.
0084                                               This parameter must be a number between 1 and 128            */
0085
0086   uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.
0087                                               This parameter must be a number between 2 and 256            */
0088
0089   uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.
0090                                               This parameter must be a number between 2 and 128            */
0091
0092   uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is
0093                                               divided for generating the data bit time quanta.
0094                                               This parameter must be a number between 1 and 32             */
0095
0096   uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN
0097                                               hardware is allowed to lengthen or shorten a data bit to
0098                                               perform resynchronization.
0099                                               This parameter must be a number between 1 and 16             */
0100
0101   uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.
0102                                               This parameter must be a number between 1 and 32             */
0103
0104   uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.
0105                                               This parameter must be a number between 1 and 16             */
0106
0107   uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.
0108                                               This parameter must be a number between 0 and 2560           */
0109
0110   uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.
0111                                               This parameter must be a number between 0 and 128            */
0112
0113   uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.
0114                                               This parameter must be a number between 0 and 64             */
0115
0116   uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.
0117                                               This parameter must be a number between 0 and 64             */
0118
0119   uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
0120                                               This parameter can be a value of @ref FDCAN_data_field_size  */
0121
0122   uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.
0123                                               This parameter must be a number between 0 and 64             */
0124
0125   uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
0126                                               This parameter can be a value of @ref FDCAN_data_field_size  */
0127
0128   uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.
0129                                               This parameter must be a number between 0 and 64             */
0130
0131   uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.
0132                                               This parameter can be a value of @ref FDCAN_data_field_size  */
0133
0134   uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.
0135                                               This parameter must be a number between 0 and 32             */
0136
0137   uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.
0138                                               This parameter must be a number between 0 and 32             */
0139
0140   uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
0141                                               This parameter must be a number between 0 and 32             */
0142
0143   uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.
0144                                               This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
0145
0146   uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.
0147                                               This parameter can be a value of @ref FDCAN_data_field_size  */
0148
0149 } FDCAN_InitTypeDef;
0150
0151 /**
0152   * @brief  FDCAN clock calibration unit structure definition
0153   */
0154 typedef struct
0155 {
0156   uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.
0157                                       This parameter can be a value of @ref FDCAN_clock_calibration.       */
0158
0159   uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration
0160                                       is bypassed.
0161                                       This parameter can be a value of @ref FDCAN_clock_divider            */
0162
0163   uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The
0164                                       actual configured number of periods is MinOscClkPeriods x 32.
0165                                       This parameter must be a number between 0x00 and 0xFF                */
0166
0167   uint32_t CalFieldLength;       /*!< Specifies the calibration field length.
0168                                       This parameter can be a value of @ref FDCAN_calibration_field_length */
0169
0170   uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
0171                                       This parameter must be a number between 4 and 25                     */
0172
0173   uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.
0174                                       If set to zero the counter is disabled.
0175                                       This parameter must be a number between 0x0000 and 0xFFFF            */
0176
0177 } FDCAN_ClkCalUnitTypeDef;
0178
0179 /**
0180   * @brief  FDCAN filter structure definition
0181   */
0182 typedef struct
0183 {
0184   uint32_t IdType;           /*!< Specifies the identifier type.
0185                                   This parameter can be a value of @ref FDCAN_id_type       */
0186
0187   uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.
0188                                   This parameter must be a number between:
0189                                    - 0 and 127, if IdType is FDCAN_STANDARD_ID
0190                                    - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */
0191
0192   uint32_t FilterType;       /*!< Specifies the filter type.
0193                                   This parameter can be a value of @ref FDCAN_filter_type.
0194                                   The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
0195                                   only when IdType is FDCAN_EXTENDED_ID.
0196                                   This parameter is ignored if FilterConfig is set to
0197                                   FDCAN_FILTER_TO_RXBUFFER                                  */
0198
0199   uint32_t FilterConfig;     /*!< Specifies the filter configuration.
0200                                   This parameter can be a value of @ref FDCAN_filter_config */
0201
0202   uint32_t FilterID1;        /*!< Specifies the filter identification 1.
0203                                   This parameter must be a number between:
0204                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
0205                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
0206
0207   uint32_t FilterID2;        /*!< Specifies the filter identification 2.
0208                                   This parameter is ignored if FilterConfig is set to
0209                                   FDCAN_FILTER_TO_RXBUFFER.
0210                                   This parameter must be a number between:
0211                                    - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
0212                                    - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */
0213
0214   uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the
0215                                   matching message will be stored.
0216                                   This parameter must be a number between 0 and 63.
0217                                   This parameter is ignored if FilterConfig is different
0218                                   from FDCAN_FILTER_TO_RXBUFFER                             */
0219
0220   uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
0221                                   calibration messages.
0222                                   This parameter is ignored if FilterConfig is different
0223                                   from FDCAN_FILTER_TO_RXBUFFER.
0224                                   This parameter can be:
0225                                    - 0 : ordinary message
0226                                    - 1 : calibration message                                */
0227
0228 } FDCAN_FilterTypeDef;
0229
0230 /**
0231   * @brief  FDCAN Tx header structure definition
0232   */
0233 typedef struct
0234 {
0235   uint32_t Identifier;          /*!< Specifies the identifier.
0236                                      This parameter must be a number between:
0237                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
0238                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
0239
0240   uint32_t IdType;              /*!< Specifies the identifier type for the message that will be
0241                                      transmitted.
0242                                      This parameter can be a value of @ref FDCAN_id_type               */
0243
0244   uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.
0245                                      This parameter can be a value of @ref FDCAN_frame_type            */
0246
0247   uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.
0248                                       This parameter can be a value of @ref FDCAN_data_length_code     */
0249
0250   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
0251                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
0252
0253   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without
0254                                      bit rate switching.
0255                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
0256
0257   uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or
0258                                      FD format.
0259                                      This parameter can be a value of @ref FDCAN_format                */
0260
0261   uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.
0262                                      This parameter can be a value of @ref FDCAN_EFC                   */
0263
0264   uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO
0265                                      element for identification of Tx message status.
0266                                      This parameter must be a number between 0 and 0xFF                */
0267
0268 } FDCAN_TxHeaderTypeDef;
0269
0270 /**
0271   * @brief  FDCAN Rx header structure definition
0272   */
0273 typedef struct
0274 {
0275   uint32_t Identifier;            /*!< Specifies the identifier.
0276                                        This parameter must be a number between:
0277                                         - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
0278                                         - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
0279
0280   uint32_t IdType;                /*!< Specifies the identifier type of the received message.
0281                                        This parameter can be a value of @ref FDCAN_id_type               */
0282
0283   uint32_t RxFrameType;           /*!< Specifies the the received message frame type.
0284                                        This parameter can be a value of @ref FDCAN_frame_type            */
0285
0286   uint32_t DataLength;            /*!< Specifies the received frame length.
0287                                         This parameter can be a value of @ref FDCAN_data_length_code     */
0288
0289   uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.
0290                                        This parameter can be a value of @ref FDCAN_error_state_indicator */
0291
0292   uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit
0293                                        rate switching.
0294                                        This parameter can be a value of @ref FDCAN_bit_rate_switching    */
0295
0296   uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD
0297                                        format.
0298                                        This parameter can be a value of @ref FDCAN_format                */
0299
0300   uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame
0301                                        reception.
0302                                        This parameter must be a number between 0 and 0xFFFF              */
0303
0304   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
0305                                        This parameter must be a number between:
0306                                         - 0 and 127, if IdType is FDCAN_STANDARD_ID
0307                                         - 0 and 63, if IdType is FDCAN_EXTENDED_ID
0308                                        When the frame is a Non-Filter matching frame, this parameter
0309                                        is unused.                                                        */
0310
0311   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
0312                                        Acceptance of non-matching frames may be enabled via
0313                                        HAL_FDCAN_ConfigGlobalFilter().
0314                                        This parameter takes 0 if the frame matched an Rx filter or
0315                                        1 if it did not match any Rx filter                               */
0316
0317 } FDCAN_RxHeaderTypeDef;
0318
0319 /**
0320   * @brief  FDCAN Tx event FIFO structure definition
0321   */
0322 typedef struct
0323 {
0324   uint32_t Identifier;          /*!< Specifies the identifier.
0325                                      This parameter must be a number between:
0326                                       - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
0327                                       - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */
0328
0329   uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.
0330                                      This parameter can be a value of @ref FDCAN_id_type               */
0331
0332   uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.
0333                                      This parameter can be a value of @ref FDCAN_frame_type            */
0334
0335   uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.
0336                                      This parameter can be a value of @ref FDCAN_data_length_code      */
0337
0338   uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
0339                                      This parameter can be a value of @ref FDCAN_error_state_indicator */
0340
0341   uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit
0342                                      rate switching.
0343                                      This parameter can be a value of @ref FDCAN_bit_rate_switching    */
0344
0345   uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD
0346                                      format.
0347                                      This parameter can be a value of @ref FDCAN_format                */
0348
0349   uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame
0350                                      transmission.
0351                                      This parameter must be a number between 0 and 0xFFFF              */
0352
0353   uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element
0354                                      for identification of Tx message status.
0355                                      This parameter must be a number between 0 and 0xFF                */
0356
0357   uint32_t EventType;           /*!< Specifies the event type.
0358                                      This parameter can be a value of @ref FDCAN_event_type            */
0359
0360 } FDCAN_TxEventFifoTypeDef;
0361
0362 /**
0363   * @brief  FDCAN High Priority Message Status structure definition
0364   */
0365 typedef struct
0366 {
0367   uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.
0368                                 This parameter can be:
0369                                  - 0 : Standard Filter List
0370                                  - 1 : Extended Filter List                                */
0371
0372   uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.
0373                                 This parameter can be a number between:
0374                                 - 0 and 127, if FilterList is 0 (Standard)
0375                                 - 0 and 63, if FilterList is 1 (Extended)                  */
0376
0377   uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
0378                                 This parameter can be a value of @ref FDCAN_hp_msg_storage */
0379
0380   uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the
0381                                 message was stored.
0382                                 This parameter is valid only when MessageStorage is:
0383                                   FDCAN_HP_STORAGE_RXFIFO0
0384                                  or
0385                                   FDCAN_HP_STORAGE_RXFIFO1                                 */
0386
0387 } FDCAN_HpMsgStatusTypeDef;
0388
0389 /**
0390   * @brief FDCAN Protocol Status structure definition
0391   */
0392 typedef struct
0393 {
0394   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
0395                                    This parameter can be a value of @ref FDCAN_protocol_error_code             */
0396
0397   uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
0398                                    of a CAN FD format frame with its BRS flag set.
0399                                    This parameter can be a value of @ref FDCAN_protocol_error_code             */
0400
0401   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
0402                                    This parameter can be a value of @ref FDCAN_communication_state             */
0403
0404   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
0405                                    This parameter can be:
0406                                     - 0 : The FDCAN is in Error_Active state
0407                                     - 1 : The FDCAN is in Error_Passive state                                  */
0408
0409   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
0410                                    This parameter can be:
0411                                     - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
0412                                           Error_Warning limit of 96
0413                                     - 1 : at least one of error counters has reached the Error_Warning
0414                                           limit of 96                                                          */
0415
0416   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
0417                                    This parameter can be:
0418                                     - 0 : The FDCAN is not in Bus_Off state
0419                                     - 1 : The FDCAN is in Bus_Off state                                        */
0420
0421   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
0422                                    This parameter can be:
0423                                     - 0 : Last received CAN FD message did not have its ESI flag set
0424                                     - 1 : Last received CAN FD message had its ESI flag set                    */
0425
0426   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
0427                                    This parameter can be:
0428                                     - 0 : Last received CAN FD message did not have its BRS flag set
0429                                     - 1 : Last received CAN FD message had its BRS flag set                    */
0430
0431   uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received
0432                                    since last protocol status.
0433                                    This parameter can be:
0434                                     - 0 : No CAN FD message received
0435                                     - 1 : CAN FD message received                                              */
0436
0437   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
0438                                    This parameter can be:
0439                                     - 0 : No protocol exception event occurred since last read access
0440                                     - 1 : Protocol exception event occurred                                    */
0441
0442   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
0443                                    This parameter can be a number between 0 and 127                            */
0444
0445 } FDCAN_ProtocolStatusTypeDef;
0446
0447 /**
0448   * @brief FDCAN Error Counters structure definition
0449   */
0450 typedef struct
0451 {
0452   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
0453                                 This parameter can be a number between 0 and 255                               */
0454
0455   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
0456                                 This parameter can be a number between 0 and 127                               */
0457
0458   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
0459                                 This parameter can be:
0460                                  - 0 : The Receive Error Counter (RxErrorCnt) is below the error
0461                                        passive level of 128
0462                                  - 1 : The Receive Error Counter (RxErrorCnt) has reached the error
0463                                        passive level of 128                                                    */
0464
0465   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
0466                                 This parameter can be a number between 0 and 255.
0467                                 This counter is incremented each time when a FDCAN protocol error causes
0468                                 the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
0469                                 the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
0470                                 FDCAN_FLAG_ERROR_LOGGING_OVERFLOW                                              */
0471
0472 } FDCAN_ErrorCountersTypeDef;
0473
0474 /**
0475   * @brief FDCAN TT Init structure definition
0476   */
0477 typedef struct
0478 {
0479   uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.
0480                                    This parameter can be a value of @ref FDCAN_operation_mode               */
0481
0482   uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.
0483                                    This parameter can be a value of @ref FDCAN_TT_operation.
0484                                    This parameter is ignored if OperationMode is set to
0485                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
0486
0487   uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.
0488                                    This parameter can be a value of @ref FDCAN_TT_time_master               */
0489
0490   uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
0491                                    numerator : TUR = (Numerator +/- SDL) / Denominator.
0492                                    With : SDL = 2^(SyncDevLimit+5).
0493                                    This parameter must be a number between 0 and 7                          */
0494
0495   uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
0496                                    This parameter must be a number between 0 and 127                        */
0497
0498   uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.
0499                                    This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
0500                                    This parameter is ignored if OperationMode is set to
0501                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
0502
0503   uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after
0504                                    which the application has to serve the application watchdog.
0505                                    The application watchdog is incremented once each 256 NTUs.
0506                                    The application watchdog can be disabled by setting AppWdgLimit to 0.
0507                                    This parameter must be a number between 0 and 255.
0508                                    This parameter is ignored if OperationMode is set to
0509                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
0510
0511   uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.
0512                                    This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
0513                                    This parameter is ignored if OperationMode is set to
0514                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
0515
0516   uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.
0517                                    This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
0518                                    This parameter is ignored if OperationMode is set to
0519                                    FDCAN_TT_COMMUNICATION_LEVEL1                                            */
0520
0521   uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.
0522                                    This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
0523                                    This parameter is ignored if OperationMode is set to
0524                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
0525
0526   uint32_t BasicCyclesNbr;    /*!< Specifies the number of basic cycles in the system matrix.
0527                                    This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
0528
0529   uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
0530                                    This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */
0531
0532   uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.
0533                                    This parameter must be a number between 1 and 16                         */
0534
0535   uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.
0536                                    This is the sum of Tx_Triggers for exclusive, single arbitrating and
0537                                    merged arbitrating windows.
0538                                    This parameter must be a number between 0 and 4095                       */
0539
0540   uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
0541                                    It is advised to set this parameter to the largest applicable value.
0542                                    This parameter must be a number between 0x10000 and 0x1FFFF              */
0543
0544   uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
0545                                    This parameter must be a number between 0x0001 and 0x3FFF                */
0546
0547   uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.
0548                                    This parameter must be a number between 0 and 64                         */
0549
0550   uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.
0551                                    This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
0552
0553   uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.
0554                                    This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */
0555
0556 } FDCAN_TT_ConfigTypeDef;
0557
0558 /**
0559   * @brief  FDCAN Trigger structure definition
0560   */
0561 typedef struct
0562 {
0563   uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.
0564                                This parameter must be a number between 0 and 63                                 */
0565
0566   uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.
0567                                This parameter must be a number between 0 and 0xFFFF                             */
0568
0569   uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.
0570                                This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */
0571
0572   uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.
0573                                This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
0574                                This parameter must be a number between 0 and RepeatFactor                       */
0575
0576   uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.
0577                                If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
0578                                becomes active.
0579                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */
0580
0581   uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.
0582                                If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
0583                                trigger memory element becomes active.
0584                                This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */
0585
0586   uint32_t TriggerType;   /*!< Specifies the trigger type.
0587                                This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */
0588
0589   uint32_t FilterType;    /*!< Specifies the filter identifier type.
0590                                This parameter can be a value of @ref FDCAN_id_type                              */
0591
0592   uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
0593                                This parameter can be a value of @ref FDCAN_Tx_location.
0594                                This parameter is taken in consideration only if the trigger is configured for
0595                                transmission.                                                                    */
0596
0597   uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.
0598                                This parameter is taken in consideration only if the trigger is configured for
0599                                reception.
0600                                This parameter must be a number between:
0601                                 - 0 and 127, if FilterType is FDCAN_STANDARD_ID
0602                                 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */
0603
0604 } FDCAN_TriggerTypeDef;
0605
0606 /**
0607   * @brief  FDCAN TT Operation Status structure definition
0608   */
0609 typedef struct
0610 {
0611   uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.
0612                                   This parameter can be a value of @ref FDCAN_TT_error_level                    */
0613
0614   uint32_t MasterState;      /*!< Specifies the type of the TT master state.
0615                                   This parameter can be a value of @ref FDCAN_TT_master_state                   */
0616
0617   uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.
0618                                   This parameter can be a value of @ref FDCAN_TT_sync_state                     */
0619
0620   uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.
0621                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
0622                                   This parameter can be:
0623                                    - 0 : Global time not valid
0624                                    - 1 : Global time in phase with Time Master                                  */
0625
0626   uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.
0627                                   This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
0628                                   This parameter can be:
0629                                    - 0 : Local clock speed not synchronized to Time Master clock speed
0630                                    - 1 : Synchronization Deviation = SDL                                        */
0631
0632   uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.
0633                                   This parameter can be a number between 0 and 0xFF                             */
0634
0635   uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
0636                                   This parameter can be:
0637                                    - 0 : No global time preset pending
0638                                    - 1 : Node waits for the global time preset to take effect                   */
0639
0640   uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.
0641                                   This parameter can be:
0642                                    - 0 : Reset at the end of each reference message
0643                                    - 1 : Gap finished                                                           */
0644
0645   uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.
0646                                   This parameter can be a number between 0 and 0x7                              */
0647
0648   uint32_t GapStarted;       /*!< Specifies whether a Gap is started.
0649                                   This parameter can be:
0650                                    - 0 : No Gap in schedule
0651                                    - 1 : Gap time after Basic Cycle has started                                 */
0652
0653   uint32_t WaitForEvt;       /*!< Specifies whether a Gap is announced.
0654                                   This parameter can be:
0655                                    - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
0656                                    - 1 : Reference message with Next_is_Gap = 1 received                        */
0657
0658   uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.
0659                                   This parameter can be:
0660                                    - 0 : Application Watchdog served in time
0661                                    - 1 : Failed to serve Application Watchdog in time                           */
0662
0663   uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.
0664                                   This parameter can be:
0665                                    - 0 : No external clock synchronization pending
0666                                    - 1 : Node waits for external clock synchronization to take effect           */
0667
0668   uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.
0669                                   This parameter can be:
0670                                    - 0 : Phase outside range
0671                                    - 1 : Phase inside range                                                     */
0672
0673 } FDCAN_TTOperationStatusTypeDef;
0674
0675 /**
0676   * @brief  FDCAN Message RAM blocks
0677   */
0678 typedef struct
0679 {
0680   uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
0681                                   This parameter must be a 32-bit word address      */
0682
0683   uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
0684                                   This parameter must be a 32-bit word address      */
0685
0686   uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.
0687                                   This parameter must be a 32-bit word address      */
0688
0689   uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.
0690                                   This parameter must be a 32-bit word address      */
0691
0692   uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.
0693                                   This parameter must be a 32-bit word address      */
0694
0695   uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.
0696                                   This parameter must be a 32-bit word address      */
0697
0698   uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.
0699                                   This parameter must be a 32-bit word address      */
0700
0701   uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.
0702                                   This parameter must be a 32-bit word address      */
0703
0704   uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.
0705                                   This parameter must be a 32-bit word address      */
0706
0707   uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.
0708                                   This parameter must be a 32-bit word address      */
0709
0710 } FDCAN_MsgRamAddressTypeDef;
0711
0712 /**
0713   * @brief  FDCAN handle structure definition
0714   */
0715 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
0716 typedef struct __FDCAN_HandleTypeDef
0717 #else
0718 typedef struct
0719 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
0720 {
0721   FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */
0722
0723   TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */
0724
0725   FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */
0726
0727   FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */
0728
0729   uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
0730                                                of latest Tx FIFO/Queue request */
0731
0732   __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */
0733
0734   HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */
0735
0736   __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */
0737
0738 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
0739   void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */
0740   void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */
0741   void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */
0742   void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */
0743   void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */
0744   void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */
0745   void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */
0746   void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */
0747   void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */
0748   void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */
0749   void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */
0750   void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */
0751   void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */
0752   void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */
0753   void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */
0754   void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */
0755   void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */
0756
0757   void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */
0758   void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */
0759 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
0760
0761 } FDCAN_HandleTypeDef;
0762
0763 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
0764 /**
0765   * @brief  HAL FDCAN common Callback ID enumeration definition
0766   */
0767 typedef enum
0768 {
0769   HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U,    /*!< FDCAN Tx Fifo Empty callback ID         */
0770   HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U,    /*!< FDCAN Rx buffer new message callback ID */
0771   HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U,    /*!< FDCAN High priority message callback ID */
0772   HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U,    /*!< FDCAN Timestamp wraparound callback ID  */
0773   HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U,    /*!< FDCAN Timeout occurred callback ID      */
0774   HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U,    /*!< FDCAN Error callback ID                 */
0775
0776   HAL_FDCAN_MSPINIT_CB_ID              = 0x06U,    /*!< FDCAN MspInit callback ID               */
0777   HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U,    /*!< FDCAN MspDeInit callback ID             */
0778
0779 } HAL_FDCAN_CallbackIDTypeDef;
0780
0781 /**
0782   * @brief  HAL FDCAN Callback pointer definition
0783   */
0784 typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */
0785 typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */
0786 typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */
0787 typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */
0788 typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */
0789 typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */
0790 typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */
0791 typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */
0792 typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */
0793 typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */
0794 typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */
0795 typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */
0796 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
0797
0798 /**
0799   * @}
0800   */
0801
0802 /* Exported constants --------------------------------------------------------*/
0803 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
0804   * @ingroup RTEMSBSPsARMSTM32H7
0805   * @{
0806   */
0807
0808 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
0809   * @ingroup RTEMSBSPsARMSTM32H7
0810   * @{
0811   */
0812 #define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */
0813 #define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */
0814 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */
0815 #define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */
0816 #define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */
0817 #define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */
0818 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
0819 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
0820 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
0821 #define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
0822 #define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
0823 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
0824 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
0825 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
0826 #define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */
0827 #define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */
0828 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */
0829 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
0830 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */
0831 #define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */
0832 #define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */
0833 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */
0834 #define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */
0835 #define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */
0836 #define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */
0837
0838 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
0839 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */
0840 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
0841 /**
0842   * @}
0843   */
0844
0845 /** @defgroup FDCAN_frame_format FDCAN Frame Format
0846   * @ingroup RTEMSBSPsARMSTM32H7
0847   * @{
0848   */
0849 #define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */
0850 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */
0851 #define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */
0852 /**
0853   * @}
0854   */
0855
0856 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
0857   * @ingroup RTEMSBSPsARMSTM32H7
0858   * @{
0859   */
0860 #define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */
0861 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
0862 #define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */
0863 #define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */
0864 #define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */
0865 /**
0866   * @}
0867   */
0868
0869 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
0870   * @ingroup RTEMSBSPsARMSTM32H7
0871   * @{
0872   */
0873 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
0874 #define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */
0875 /**
0876   * @}
0877   */
0878
0879 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
0880   * @ingroup RTEMSBSPsARMSTM32H7
0881   * @{
0882   */
0883 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
0884 #define FDCAN_CLOCK_DIV2  ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2  */
0885 #define FDCAN_CLOCK_DIV4  ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4  */
0886 #define FDCAN_CLOCK_DIV6  ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6  */
0887 #define FDCAN_CLOCK_DIV8  ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8  */
0888 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
0889 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
0890 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
0891 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
0892 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
0893 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
0894 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
0895 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
0896 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
0897 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
0898 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
0899 /**
0900   * @}
0901   */
0902
0903 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
0904   * @ingroup RTEMSBSPsARMSTM32H7
0905   * @{
0906   */
0907 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */
0908 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
0909 /**
0910   * @}
0911   */
0912
0913 /** @defgroup FDCAN_calibration_state FDCAN Calibration State
0914   * @ingroup RTEMSBSPsARMSTM32H7
0915   * @{
0916   */
0917 #define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */
0918 #define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */
0919 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
0920 /**
0921   * @}
0922   */
0923
0924 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
0925   * @ingroup RTEMSBSPsARMSTM32H7
0926   * @{
0927   */
0928 #define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */
0929 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
0930 #define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */
0931 /**
0932   * @}
0933   */
0934
0935 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size
0936   * @ingroup RTEMSBSPsARMSTM32H7
0937   * @{
0938   */
0939 #define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */
0940 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
0941 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
0942 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
0943 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
0944 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
0945 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
0946 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
0947 /**
0948   * @}
0949   */
0950
0951 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
0952   * @ingroup RTEMSBSPsARMSTM32H7
0953   * @{
0954   */
0955 #define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */
0956 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
0957 /**
0958   * @}
0959   */
0960
0961 /** @defgroup FDCAN_id_type FDCAN ID Type
0962   * @ingroup RTEMSBSPsARMSTM32H7
0963   * @{
0964   */
0965 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
0966 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
0967 /**
0968   * @}
0969   */
0970
0971 /** @defgroup FDCAN_frame_type FDCAN Frame Type
0972   * @ingroup RTEMSBSPsARMSTM32H7
0973   * @{
0974   */
0975 #define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */
0976 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */
0977 /**
0978   * @}
0979   */
0980
0981 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
0982   * @ingroup RTEMSBSPsARMSTM32H7
0983   * @{
0984   */
0985 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
0986 #define FDCAN_DLC_BYTES_1  ((uint32_t)0x00000001U) /*!< 1 bytes data field  */
0987 #define FDCAN_DLC_BYTES_2  ((uint32_t)0x00000002U) /*!< 2 bytes data field  */
0988 #define FDCAN_DLC_BYTES_3  ((uint32_t)0x00000003U) /*!< 3 bytes data field  */
0989 #define FDCAN_DLC_BYTES_4  ((uint32_t)0x00000004U) /*!< 4 bytes data field  */
0990 #define FDCAN_DLC_BYTES_5  ((uint32_t)0x00000005U) /*!< 5 bytes data field  */
0991 #define FDCAN_DLC_BYTES_6  ((uint32_t)0x00000006U) /*!< 6 bytes data field  */
0992 #define FDCAN_DLC_BYTES_7  ((uint32_t)0x00000007U) /*!< 7 bytes data field  */
0993 #define FDCAN_DLC_BYTES_8  ((uint32_t)0x00000008U) /*!< 8 bytes data field  */
0994 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
0995 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
0996 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
0997 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
0998 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
0999 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
1000 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
1001 /**
1002   * @}
1003   */
1004
1005 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
1006   * @ingroup RTEMSBSPsARMSTM32H7
1007   * @{
1008   */
1009 #define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */
1010 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
1011 /**
1012   * @}
1013   */
1014
1015 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
1016   * @ingroup RTEMSBSPsARMSTM32H7
1017   * @{
1018   */
1019 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
1020 #define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */
1021 /**
1022   * @}
1023   */
1024
1025 /** @defgroup FDCAN_format FDCAN format
1026   * @ingroup RTEMSBSPsARMSTM32H7
1027   * @{
1028   */
1029 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
1030 #define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */
1031 /**
1032   * @}
1033   */
1034
1035 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
1036   * @ingroup RTEMSBSPsARMSTM32H7
1037   * @{
1038   */
1039 #define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */
1040 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */
1041 /**
1042   * @}
1043   */
1044
1045 /** @defgroup FDCAN_filter_type FDCAN Filter Type
1046   * @ingroup RTEMSBSPsARMSTM32H7
1047   * @{
1048   */
1049 #define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */
1050 #define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */
1051 #define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */
1052 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
1053 /**
1054   * @}
1055   */
1056
1057 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
1058   * @ingroup RTEMSBSPsARMSTM32H7
1059   * @{
1060   */
1061 #define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */
1062 #define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */
1063 #define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */
1064 #define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */
1065 #define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */
1066 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */
1067 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */
1068 #define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
1069 /**
1070   * @}
1071   */
1072
1073 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
1074   * @ingroup RTEMSBSPsARMSTM32H7
1075   * @{
1076   */
1077 #define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */
1078 #define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */
1079 #define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */
1080 #define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */
1081 #define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */
1082 #define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */
1083 #define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */
1084 #define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */
1085 #define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */
1086 #define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */
1087 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
1088 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
1089 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
1090 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
1091 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
1092 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
1093 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
1094 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
1095 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
1096 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
1097 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
1098 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
1099 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
1100 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
1101 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
1102 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
1103 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
1104 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
1105 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
1106 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
1107 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
1108 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
1109 /**
1110   * @}
1111   */
1112
1113 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
1114   * @ingroup RTEMSBSPsARMSTM32H7
1115   * @{
1116   */
1117 #define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */
1118 #define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */
1119 #define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */
1120 #define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */
1121 #define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */
1122 #define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */
1123 #define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */
1124 #define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */
1125 #define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */
1126 #define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */
1127 #define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */
1128 #define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */
1129 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
1130 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
1131 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
1132 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
1133 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
1134 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
1135 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
1136 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
1137 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
1138 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
1139 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
1140 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
1141 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
1142 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
1143 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
1144 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
1145 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
1146 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
1147 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
1148 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
1149 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
1150 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
1151 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
1152 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
1153 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
1154 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
1155 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
1156 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
1157 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
1158 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
1159 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
1160 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
1161 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
1162 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
1163 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
1164 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
1165 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
1166 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
1167 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
1168 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
1169 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
1170 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
1171 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
1172 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
1173 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
1174 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
1175 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
1176 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
1177 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
1178 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
1179 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
1180 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
1181 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
1182 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
1183 /**
1184   * @}
1185   */
1186
1187 /** @defgroup FDCAN_event_type FDCAN Event Type
1188   * @ingroup RTEMSBSPsARMSTM32H7
1189   * @{
1190   */
1191 #define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */
1192 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
1193 /**
1194   * @}
1195   */
1196
1197 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
1198   * @ingroup RTEMSBSPsARMSTM32H7
1199   * @{
1200   */
1201 #define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */
1202 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */
1203 #define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
1204 #define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
1205 /**
1206   * @}
1207   */
1208
1209 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
1210   * @ingroup RTEMSBSPsARMSTM32H7
1211   * @{
1212   */
1213 #define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */
1214 #define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */
1215 #define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */
1216 #define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */
1217 #define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */
1218 #define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */
1219 #define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */
1220 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
1221 /**
1222   * @}
1223   */
1224
1225 /** @defgroup FDCAN_communication_state FDCAN communication state
1226   * @ingroup RTEMSBSPsARMSTM32H7
1227   * @{
1228   */
1229 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
1230 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */
1231 #define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */
1232 #define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */
1233 /**
1234   * @}
1235   */
1236
1237 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
1238   * @ingroup RTEMSBSPsARMSTM32H7
1239   * @{
1240   */
1241 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
1242 #define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */
1243 #define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */
1244 /**
1245   * @}
1246   */
1247
1248 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
1249   * @ingroup RTEMSBSPsARMSTM32H7
1250   * @{
1251   */
1252 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
1253 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
1254 /**
1255   * @}
1256   */
1257
1258 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
1259   * @ingroup RTEMSBSPsARMSTM32H7
1260   * @{
1261   */
1262 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
1263 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
1264 #define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */
1265 /**
1266   * @}
1267   */
1268
1269 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
1270   * @ingroup RTEMSBSPsARMSTM32H7
1271   * @{
1272   */
1273 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
1274 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
1275 /**
1276   * @}
1277   */
1278
1279 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
1280   * @ingroup RTEMSBSPsARMSTM32H7
1281   * @{
1282   */
1283 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
1284 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
1285 /**
1286   * @}
1287   */
1288
1289 /** @defgroup FDCAN_Timestamp FDCAN timestamp
1290   * @ingroup RTEMSBSPsARMSTM32H7
1291   * @{
1292   */
1293 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
1294 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */
1295 /**
1296   * @}
1297   */
1298
1299 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
1300   * @ingroup RTEMSBSPsARMSTM32H7
1301   * @{
1302   */
1303 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
1304 #define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
1305 #define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
1306 #define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
1307 #define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
1308 #define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
1309 #define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
1310 #define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
1311 #define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
1312 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
1313 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
1314 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
1315 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
1316 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
1317 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
1318 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
1319 /**
1320   * @}
1321   */
1322
1323 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
1324   * @ingroup RTEMSBSPsARMSTM32H7
1325   * @{
1326   */
1327 #define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */
1328 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
1329 #define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */
1330 #define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */
1331 /**
1332   * @}
1333   */
1334
1335 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
1336   * @ingroup RTEMSBSPsARMSTM32H7
1337   * @{
1338   */
1339 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */
1340 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
1341 /**
1342   * @}
1343   */
1344
1345 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
1346   * @ingroup RTEMSBSPsARMSTM32H7
1347   * @{
1348   */
1349 #define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */
1350 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */
1351 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */
1352 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */
1353 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
1354 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
1355 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
1356 /**
1357   * @}
1358   */
1359
1360 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
1361   * @ingroup RTEMSBSPsARMSTM32H7
1362   * @{
1363   */
1364 #define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */
1365 #define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */
1366 #define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */
1367 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */
1368 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */
1369 #define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */
1370 #define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */
1371 #define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */
1372 #define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */
1373 #define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */
1374 #define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
1375 /**
1376   * @}
1377   */
1378
1379 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
1380   * @ingroup RTEMSBSPsARMSTM32H7
1381   * @{
1382   */
1383 #define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */
1384 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
1385 /**
1386   * @}
1387   */
1388
1389 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
1390   * @ingroup RTEMSBSPsARMSTM32H7
1391   * @{
1392   */
1393 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */
1394 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
1395 /**
1396   * @}
1397   */
1398
1399 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode
1400   * @ingroup RTEMSBSPsARMSTM32H7
1401   * @{
1402   */
1403 #define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
1404 #define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
1405 #define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
1406 /**
1407   * @}
1408   */
1409
1410 /** @defgroup FDCAN_TT_operation FDCAN TT Operation
1411   * @ingroup RTEMSBSPsARMSTM32H7
1412   * @{
1413   */
1414 #define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */
1415 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
1416 /**
1417   * @}
1418   */
1419
1420 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
1421   * @ingroup RTEMSBSPsARMSTM32H7
1422   * @{
1423   */
1424 #define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */
1425 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
1426 /**
1427   * @}
1428   */
1429
1430 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
1431   * @ingroup RTEMSBSPsARMSTM32H7
1432   * @{
1433   */
1434 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */
1435 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */
1436 /**
1437   * @}
1438   */
1439
1440 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
1441   * @ingroup RTEMSBSPsARMSTM32H7
1442   * @{
1443   */
1444 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */
1445 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */
1446 /**
1447   * @}
1448   */
1449
1450 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
1451   * @ingroup RTEMSBSPsARMSTM32H7
1452   * @{
1453   */
1454 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */
1455 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */
1456 /**
1457   * @}
1458   */
1459
1460 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
1461   * @ingroup RTEMSBSPsARMSTM32H7
1462   * @{
1463   */
1464 #define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */
1465 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
1466 /**
1467   * @}
1468   */
1469
1470 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
1471   * @ingroup RTEMSBSPsARMSTM32H7
1472   * @{
1473   */
1474 #define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */
1475 #define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */
1476 #define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */
1477 #define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */
1478 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
1479 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
1480 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
1481 /**
1482   * @}
1483   */
1484
1485 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
1486   * @ingroup RTEMSBSPsARMSTM32H7
1487   * @{
1488   */
1489 #define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */
1490 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
1491 #define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */
1492 /**
1493   * @}
1494   */
1495
1496 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
1497   * @ingroup RTEMSBSPsARMSTM32H7
1498   * @{
1499   */
1500 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */
1501 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */
1502 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */
1503 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
1504 /**
1505   * @}
1506   */
1507
1508 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
1509   * @ingroup RTEMSBSPsARMSTM32H7
1510   * @{
1511   */
1512 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */
1513 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */
1514 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */
1515 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
1516 /**
1517   * @}
1518   */
1519
1520 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
1521   * @ingroup RTEMSBSPsARMSTM32H7
1522   * @{
1523   */
1524 #define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */
1525 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */
1526 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */
1527 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
1528 /**
1529   * @}
1530   */
1531
1532 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
1533   * @ingroup RTEMSBSPsARMSTM32H7
1534   * @{
1535   */
1536 #define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */
1537 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
1538 /**
1539   * @}
1540   */
1541
1542 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
1543   * @ingroup RTEMSBSPsARMSTM32H7
1544   * @{
1545   */
1546 #define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */
1547 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */
1548 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */
1549 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
1550 /**
1551   * @}
1552   */
1553
1554 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
1555   * @ingroup RTEMSBSPsARMSTM32H7
1556   * @{
1557   */
1558 #define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */
1559 #define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */
1560 #define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */
1561 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
1562 /**
1563   * @}
1564   */
1565
1566 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State
1567   * @ingroup RTEMSBSPsARMSTM32H7
1568   * @{
1569   */
1570 #define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
1571 #define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */
1572 #define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */
1573 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */
1574 /**
1575   * @}
1576   */
1577
1578 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
1579   * @ingroup RTEMSBSPsARMSTM32H7
1580   * @{
1581   */
1582 #define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */
1583 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
1584 #define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */
1585 #define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */
1586 /**
1587   * @}
1588   */
1589
1590 /** @defgroup Interrupt_Masks Interrupt masks
1591   * @ingroup RTEMSBSPsARMSTM32H7
1592   * @{
1593   */
1594 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
1595 #define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */
1596 /**
1597   * @}
1598   */
1599
1600 /** @defgroup FDCAN_flags FDCAN Flags
1601   * @ingroup RTEMSBSPsARMSTM32H7
1602   * @{
1603   */
1604 #define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */
1605 #define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */
1606 #define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */
1607 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */
1608 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */
1609 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */
1610 #define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */
1611 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */
1612 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */
1613 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */
1614 #define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */
1615 #define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */
1616 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */
1617 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */
1618 #define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */
1619 #define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */
1620 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */
1621 #define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */
1622 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */
1623 #define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */
1624 #define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */
1625 #define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */
1626 #define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */
1627 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */
1628 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */
1629 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */
1630 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */
1631 #define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */
1632 #define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */
1633 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */
1634 /**
1635   * @}
1636   */
1637
1638 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
1639   * @ingroup RTEMSBSPsARMSTM32H7
1640   * @{
1641   */
1642
1643 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
1644   * @ingroup RTEMSBSPsARMSTM32H7
1645   * @{
1646   */
1647 #define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */
1648 #define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */
1649 #define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */
1650 /**
1651   * @}
1652   */
1653
1654 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
1655   * @ingroup RTEMSBSPsARMSTM32H7
1656   * @{
1657   */
1658 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */
1659 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */
1660 /**
1661   * @}
1662   */
1663
1664 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
1665   * @ingroup RTEMSBSPsARMSTM32H7
1666   * @{
1667   */
1668 #define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */
1669 #define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */
1670 /**
1671   * @}
1672   */
1673
1674 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
1675   * @ingroup RTEMSBSPsARMSTM32H7
1676   * @{
1677   */
1678 #define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */
1679 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
1680 /**
1681   * @}
1682   */
1683
1684 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
1685   * @ingroup RTEMSBSPsARMSTM32H7
1686   * @{
1687   */
1688 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */
1689 #define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */
1690 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
1691 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */
1692 /**
1693   * @}
1694   */
1695
1696 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
1697   * @ingroup RTEMSBSPsARMSTM32H7
1698   * @{
1699   */
1700 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */
1701 #define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */
1702 #define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
1703 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */
1704 /**
1705   * @}
1706   */
1707
1708 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
1709   * @ingroup RTEMSBSPsARMSTM32H7
1710   * @{
1711   */
1712 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */
1713 #define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */
1714 #define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
1715 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */
1716 /**
1717   * @}
1718   */
1719
1720 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
1721   * @ingroup RTEMSBSPsARMSTM32H7
1722   * @{
1723   */
1724 #define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */
1725 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */
1726 #define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */
1727 #define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */
1728 #define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */
1729 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */
1730 /**
1731   * @}
1732   */
1733
1734 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
1735   * @ingroup RTEMSBSPsARMSTM32H7
1736   * @{
1737   */
1738 #define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed      */
1739 #define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed      */
1740 #define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed            */
1741 /**
1742   * @}
1743   */
1744
1745 /**
1746   * @}
1747   */
1748
1749 /** @defgroup FDCAN_TTflags FDCAN TT Flags
1750   * @ingroup RTEMSBSPsARMSTM32H7
1751   * @{
1752   */
1753 #define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */
1754 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */
1755 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */
1756 #define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */
1757 #define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */
1758 #define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
1759 #define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */
1760 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */
1761 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */
1762 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */
1763 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */
1764 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */
1765 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */
1766 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */
1767 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */
1768 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */
1769 #define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */
1770 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */
1771 #define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */
1772 /**
1773   * @}
1774   */
1775
1776 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
1777   * @ingroup RTEMSBSPsARMSTM32H7
1778   * @{
1779   */
1780
1781 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
1782   * @ingroup RTEMSBSPsARMSTM32H7
1783   * @{
1784   */
1785 #define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */
1786 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */
1787 #define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
1788 #define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */
1789 /**
1790   * @}
1791   */
1792
1793 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
1794   * @ingroup RTEMSBSPsARMSTM32H7
1795   * @{
1796   */
1797 #define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */
1798 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
1799 /**
1800   * @}
1801   */
1802
1803 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
1804   * @ingroup RTEMSBSPsARMSTM32H7
1805   * @{
1806   */
1807 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
1808 /**
1809   * @}
1810   */
1811
1812 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
1813   * @ingroup RTEMSBSPsARMSTM32H7
1814   * @{
1815   */
1816 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */
1817 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */
1818 /**
1819   * @}
1820   */
1821
1822 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
1823   * @ingroup RTEMSBSPsARMSTM32H7
1824   * @{
1825   */
1826 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */
1827 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */
1828 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */
1829 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */
1830 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */
1831 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
1832 /**
1833   * @}
1834   */
1835
1836 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
1837   * @ingroup RTEMSBSPsARMSTM32H7
1838   * @{
1839   */
1840 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
1841 #define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */
1842 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */
1843 #define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */
1844 /**
1845   * @}
1846   */
1847
1848 /**
1849   * @}
1850   */
1851
1852 /**
1853   * @}
1854   */
1855
1856 /* Exported macro ------------------------------------------------------------*/
1857 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
1858   * @ingroup RTEMSBSPsARMSTM32H7
1859   * @{
1860   */
1861
1862 /** @brief  Reset FDCAN handle state.
1863   * @param  __HANDLE__ FDCAN handle.
1864   * @retval None
1865   */
1866 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
1867 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
1868                                                        (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
1869                                                        (__HANDLE__)->MspInitCallback = NULL;           \
1870                                                        (__HANDLE__)->MspDeInitCallback = NULL;         \
1871                                                      } while(0)
1872 #else
1873 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
1874 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
1875
1876 /**
1877   * @brief  Enable the specified FDCAN interrupts.
1878   * @param  __HANDLE__ FDCAN handle.
1879   * @param  __INTERRUPT__ FDCAN interrupt.
1880   *         This parameter can be any combination of @arg FDCAN_Interrupts
1881   * @retval None
1882   */
1883 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \
1884   do{                                                                \
1885     (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
1886     FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \
1887   }while(0)
1888
1889
1890 /**
1891   * @brief  Disable the specified FDCAN interrupts.
1892   * @param  __HANDLE__ FDCAN handle.
1893   * @param  __INTERRUPT__ FDCAN interrupt.
1894   *         This parameter can be any combination of @arg FDCAN_Interrupts
1895   * @retval None
1896   */
1897 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \
1898   do{                                                                   \
1899     ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
1900     FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
1901   }while(0)
1902
1903 /**
1904   * @brief  Check whether the specified FDCAN interrupt is set or not.
1905   * @param  __HANDLE__ FDCAN handle.
1906   * @param  __INTERRUPT__ FDCAN interrupt.
1907   *         This parameter can be one of @arg FDCAN_Interrupts
1908   * @retval ITStatus
1909   */
1910 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
1911                                                        ((__HANDLE__)->Instance->IR &\
1912                                                         (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
1913
1914 /**
1915   * @brief  Clear the specified FDCAN interrupts.
1916   * @param  __HANDLE__ FDCAN handle.
1917   * @param  __INTERRUPT__ specifies the interrupts to clear.
1918   *         This parameter can be any combination of @arg FDCAN_Interrupts
1919   * @retval None
1920   */
1921 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)                  \
1922   do {                                                                   \
1923     ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
1924     FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
1925   } while(0);
1926
1927 /**
1928   * @brief  Check whether the specified FDCAN flag is set or not.
1929   * @param  __HANDLE__ FDCAN handle.
1930   * @param  __FLAG__ FDCAN flag.
1931   *         This parameter can be one of @arg FDCAN_flags
1932   * @retval FlagStatus
1933   */
1934 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \
1935                                                     ((__HANDLE__)->Instance->IR &\
1936                                                      (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
1937
1938 /**
1939   * @brief  Clear the specified FDCAN flags.
1940   * @param  __HANDLE__ FDCAN handle.
1941   * @param  __FLAG__ specifies the flags to clear.
1942   *         This parameter can be any combination of @arg FDCAN_flags
1943   * @retval None
1944   */
1945 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)                \
1946   do {                                                              \
1947     ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
1948     FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
1949   } while(0);
1950
1951 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
1952   * @param  __HANDLE__ FDCAN handle.
1953   * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.
1954   *         This parameter can be a value of @arg FDCAN_Interrupts
1955   * @retval ITStatus
1956   */
1957 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
1958                                                               ((__HANDLE__)->Instance->IE &\
1959                                                                (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \
1960                                                                    (__INTERRUPT__)))
1961
1962 /**
1963   * @brief  Enable the specified FDCAN TT interrupts.
1964   * @param  __HANDLE__ FDCAN handle.
1965   * @param  __INTERRUPT__ FDCAN TT interrupt.
1966   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
1967   * @retval None
1968   */
1969 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
1970
1971 /**
1972   * @brief  Disable the specified FDCAN TT interrupts.
1973   * @param  __HANDLE__ FDCAN handle.
1974   * @param  __INTERRUPT__ FDCAN TT interrupt.
1975   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
1976   * @retval None
1977   */
1978 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
1979
1980 /**
1981   * @brief  Check whether the specified FDCAN TT interrupt is set or not.
1982   * @param  __HANDLE__ FDCAN handle.
1983   * @param  __INTERRUPT__ FDCAN TT interrupt.
1984   *         This parameter can be one of @arg FDCAN_TTInterrupts
1985   * @retval ITStatus
1986   */
1987 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
1988
1989 /**
1990   * @brief  Clear the specified FDCAN TT interrupts.
1991   * @param  __HANDLE__ FDCAN handle.
1992   * @param  __INTERRUPT__ specifies the TT interrupts to clear.
1993   *         This parameter can be any combination of @arg FDCAN_TTInterrupts
1994   * @retval None
1995   */
1996 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
1997
1998 /**
1999   * @brief  Check whether the specified FDCAN TT flag is set or not.
2000   * @param  __HANDLE__ FDCAN handle.
2001   * @param  __FLAG__ FDCAN TT flag.
2002   *         This parameter can be one of @arg FDCAN_TTflags
2003   * @retval FlagStatus
2004   */
2005 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
2006
2007 /**
2008   * @brief  Clear the specified FDCAN TT flags.
2009   * @param  __HANDLE__ FDCAN handle.
2010   * @param  __FLAG__ specifies the TT flags to clear.
2011   *         This parameter can be any combination of @arg FDCAN_TTflags
2012   * @retval None
2013   */
2014 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
2015
2016 /** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.
2017   * @param  __HANDLE__ FDCAN handle.
2018   * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
2019   *         This parameter can be a value of @arg FDCAN_TTInterrupts
2020   * @retval ITStatus
2021   */
2022 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
2023
2024 /**
2025   * @}
2026   */
2027
2028 /* Exported functions --------------------------------------------------------*/
2029 /** @addtogroup FDCAN_Exported_Functions
2030   * @{
2031   */
2032
2033 /** @addtogroup FDCAN_Exported_Functions_Group1
2034   * @{
2035   */
2036 /* Initialization and de-initialization functions *****************************/
2037 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
2038 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
2039 void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
2040 void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
2041 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
2042 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
2043
2044 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
2045 /* Callbacks Register/UnRegister functions  ***********************************/
2046 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
2047                                              pFDCAN_CallbackTypeDef pCallback);
2048 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
2049 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
2050                                                              pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
2051 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
2052 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
2053                                                         pFDCAN_TxEventFifoCallbackTypeDef pCallback);
2054 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
2055 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
2056                                                     pFDCAN_RxFifo0CallbackTypeDef pCallback);
2057 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
2058 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
2059                                                     pFDCAN_RxFifo1CallbackTypeDef pCallback);
2060 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
2061 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
2062                                                              pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
2063 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
2064 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
2065                                                           pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
2066 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
2067 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
2068                                                         pFDCAN_ErrorStatusCallbackTypeDef pCallback);
2069 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
2070 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
2071                                                            pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
2072 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
2073 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
2074                                                        pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
2075 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
2076 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
2077                                                         pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
2078 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
2079 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
2080                                                          pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
2081 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
2082 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
2083 /**
2084   * @}
2085   */
2086
2087 /** @addtogroup FDCAN_Exported_Functions_Group2
2088   * @{
2089   */
2090 /* Configuration functions ****************************************************/
2091 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
2092                                                    const FDCAN_ClkCalUnitTypeDef *sCcuConfig);
2093 uint32_t          HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan);
2094 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
2095 uint32_t          HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
2096 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
2097 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
2098                                                uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
2099                                                uint32_t RejectRemoteExt);
2100 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
2101 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
2102 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
2103 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
2104 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
2105 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
2106 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
2107 uint16_t          HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
2108 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
2109 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
2110                                                  uint32_t TimeoutPeriod);
2111 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2112 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2113 uint16_t          HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
2114 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2115 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
2116                                                       uint32_t TdcFilter);
2117 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
2118 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
2119 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
2120 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
2121 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
2122 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
2123 /**
2124   * @}
2125   */
2126
2127 /** @addtogroup FDCAN_Exported_Functions_Group3
2128   * @{
2129   */
2130 /* Control functions **********************************************************/
2131 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
2132 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
2133 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
2134                                                 const uint8_t *pTxData);
2135 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
2136                                                  const uint8_t *pTxData, uint32_t BufferIndex);
2137 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
2138 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
2139 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
2140 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
2141                                          FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
2142 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
2143 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
2144                                                          FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
2145 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
2146                                               FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
2147 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
2148                                              FDCAN_ErrorCountersTypeDef *ErrorCounters);
2149 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
2150 uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
2151 uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
2152 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
2153 uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
2154 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
2155 /**
2156   * @}
2157   */
2158
2159 /** @addtogroup FDCAN_Exported_Functions_Group4
2160   * @{
2161   */
2162 /* TT Configuration and control functions**************************************/
2163 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams);
2164 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier,
2165                                                       uint32_t Payload);
2166 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig);
2167 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
2168 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
2169 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
2170 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource,
2171                                                       uint32_t TimeMarkValue, uint32_t RepeatFactor,
2172                                                       uint32_t StartCycle);
2173 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2174 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2175 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2176 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2177 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
2178 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
2179 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
2180 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
2181 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
2182 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
2183 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
2184 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
2185 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
2186 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
2187                                                   FDCAN_TTOperationStatusTypeDef *TTOpStatus);
2188 /**
2189   * @}
2190   */
2191
2192 /** @addtogroup FDCAN_Exported_Functions_Group5
2193   * @{
2194   */
2195 /* Interrupts management ******************************************************/
2196 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
2197 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
2198                                                     uint32_t InterruptLine);
2199 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
2200                                                  uint32_t BufferIndexes);
2201 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
2202 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
2203 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
2204 void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
2205 /**
2206   * @}
2207   */
2208
2209 /** @addtogroup FDCAN_Exported_Functions_Group6
2210   * @{
2211   */
2212 /* Callback functions *********************************************************/
2213 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
2214 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
2215 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
2216 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
2217 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
2218 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
2219 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
2220 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
2221 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
2222 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
2223 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
2224 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
2225 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
2226 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
2227 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
2228 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
2229 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
2230 /**
2231   * @}
2232   */
2233
2234 /** @addtogroup FDCAN_Exported_Functions_Group7
2235   * @{
2236   */
2237 /* Peripheral State functions *************************************************/
2238 uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
2239 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
2240 /**
2241   * @}
2242   */
2243
2244 /**
2245   * @}
2246   */
2247
2248 /* Private types -------------------------------------------------------------*/
2249 /** @defgroup FDCAN_Private_Types FDCAN Private Types
2250   * @ingroup RTEMSBSPsARMSTM32H7
2251   * @{
2252   */
2253
2254 /**
2255   * @}
2256   */
2257
2258 /* Private variables ---------------------------------------------------------*/
2259 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
2260   * @ingroup RTEMSBSPsARMSTM32H7
2261   * @{
2262   */
2263
2264 /**
2265   * @}
2266   */
2267
2268 /* Private constants ---------------------------------------------------------*/
2269 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
2270   * @ingroup RTEMSBSPsARMSTM32H7
2271   * @{
2272   */
2273
2274 /**
2275   * @}
2276   */
2277
2278 /* Private macros ------------------------------------------------------------*/
2279 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
2280   * @ingroup RTEMSBSPsARMSTM32H7
2281   * @{
2282   */
2283 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \
2284                                        ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
2285                                        ((FORMAT) == FDCAN_FRAME_FD_BRS   ))
2286 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \
2287                              ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
2288                              ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \
2289                              ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \
2290                              ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))
2291
2292 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
2293                                                  ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
2294
2295 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
2296                                ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
2297                                ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
2298                                ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
2299                                ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
2300                                ((CKDIV) == FDCAN_CLOCK_DIV10) || \
2301                                ((CKDIV) == FDCAN_CLOCK_DIV12) || \
2302                                ((CKDIV) == FDCAN_CLOCK_DIV14) || \
2303                                ((CKDIV) == FDCAN_CLOCK_DIV16) || \
2304                                ((CKDIV) == FDCAN_CLOCK_DIV18) || \
2305                                ((CKDIV) == FDCAN_CLOCK_DIV20) || \
2306                                ((CKDIV) == FDCAN_CLOCK_DIV22) || \
2307                                ((CKDIV) == FDCAN_CLOCK_DIV24) || \
2308                                ((CKDIV) == FDCAN_CLOCK_DIV26) || \
2309                                ((CKDIV) == FDCAN_CLOCK_DIV28) || \
2310                                ((CKDIV) == FDCAN_CLOCK_DIV30))
2311 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
2312 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
2313 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
2314 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
2315 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
2316 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
2317 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
2318 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
2319 #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
2320 #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
2321 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
2322                                   ((SIZE) == FDCAN_DATA_BYTES_12) || \
2323                                   ((SIZE) == FDCAN_DATA_BYTES_16) || \
2324                                   ((SIZE) == FDCAN_DATA_BYTES_20) || \
2325                                   ((SIZE) == FDCAN_DATA_BYTES_24) || \
2326                                   ((SIZE) == FDCAN_DATA_BYTES_32) || \
2327                                   ((SIZE) == FDCAN_DATA_BYTES_48) || \
2328                                   ((SIZE) == FDCAN_DATA_BYTES_64))
2329 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
2330                                            ((MODE) == FDCAN_TX_QUEUE_OPERATION))
2331 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
2332                                    ((ID_TYPE) == FDCAN_EXTENDED_ID))
2333 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \
2334                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \
2335                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \
2336                                      ((CONFIG) == FDCAN_FILTER_REJECT       ) || \
2337                                      ((CONFIG) == FDCAN_FILTER_HP           ) || \
2338                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
2339                                      ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
2340                                      ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))
2341 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
2342                                         ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
2343                                         ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
2344                                         ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
2345                                         ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
2346                                         ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
2347                                         ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
2348                                         ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
2349                                         ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
2350                                         ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
2351                                         ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
2352                                         ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
2353                                         ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
2354                                         ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
2355                                         ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
2356                                         ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
2357 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
2358                                 ((FIFO) == FDCAN_RX_FIFO1))
2359 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
2360                                      ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
2361 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
2362                                         ((TYPE) == FDCAN_FILTER_DUAL ) || \
2363                                         ((TYPE) == FDCAN_FILTER_MASK ))
2364 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \
2365                                         ((TYPE) == FDCAN_FILTER_DUAL         ) || \
2366                                         ((TYPE) == FDCAN_FILTER_MASK         ) || \
2367                                         ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
2368 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \
2369                                    ((TYPE) == FDCAN_REMOTE_FRAME))
2370 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
2371                            ((DLC) == FDCAN_DLC_BYTES_1 ) || \
2372                            ((DLC) == FDCAN_DLC_BYTES_2 ) || \
2373                            ((DLC) == FDCAN_DLC_BYTES_3 ) || \
2374                            ((DLC) == FDCAN_DLC_BYTES_4 ) || \
2375                            ((DLC) == FDCAN_DLC_BYTES_5 ) || \
2376                            ((DLC) == FDCAN_DLC_BYTES_6 ) || \
2377                            ((DLC) == FDCAN_DLC_BYTES_7 ) || \
2378                            ((DLC) == FDCAN_DLC_BYTES_8 ) || \
2379                            ((DLC) == FDCAN_DLC_BYTES_12) || \
2380                            ((DLC) == FDCAN_DLC_BYTES_16) || \
2381                            ((DLC) == FDCAN_DLC_BYTES_20) || \
2382                            ((DLC) == FDCAN_DLC_BYTES_24) || \
2383                            ((DLC) == FDCAN_DLC_BYTES_32) || \
2384                            ((DLC) == FDCAN_DLC_BYTES_48) || \
2385                            ((DLC) == FDCAN_DLC_BYTES_64))
2386 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
2387                            ((ESI) == FDCAN_ESI_PASSIVE))
2388 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
2389                            ((BRS) == FDCAN_BRS_ON ))
2390 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
2391                            ((FDF) == FDCAN_FD_CAN     ))
2392 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \
2393                            ((EFC) == FDCAN_STORE_TX_EVENTS))
2394 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
2395 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
2396 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
2397                                        ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \
2398                                        ((FIFO) == FDCAN_CFG_RX_FIFO1     ))
2399 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
2400                                             ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
2401                                             ((DESTINATION) == FDCAN_REJECT            ))
2402 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
2403                                              ((DESTINATION) == FDCAN_REJECT_REMOTE))
2404 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
2405                                    ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
2406 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
2407                                        ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
2408 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
2409                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
2410                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
2411                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
2412                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
2413                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
2414                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
2415                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
2416                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
2417                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
2418                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
2419                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
2420                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
2421                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
2422                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
2423                                                  ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
2424 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \
2425                                      ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
2426                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \
2427                                      ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))
2428 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
2429                                                    ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
2430 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
2431                                                ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
2432                                                ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))
2433 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
2434                                                         ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
2435 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \
2436                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
2437                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
2438                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
2439                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
2440                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
2441                                            ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
2442 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \
2443                                         ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \
2444                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \
2445                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
2446                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
2447                                         ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \
2448                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \
2449                                         ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \
2450                                         ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \
2451                                         ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \
2452                                         ((TYPE) == FDCAN_TT_END_OF_LIST           ))
2453 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
2454                                               ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
2455 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
2456                                               ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
2457 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
2458                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
2459                                        ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
2460 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \
2461                                           ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
2462 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \
2463                                            ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
2464 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
2465                                              ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
2466 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
2467                                                       ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
2468 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
2469                                                        ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
2470 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
2471                                                       ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
2472 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
2473                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
2474                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
2475                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
2476                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
2477                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
2478                                                  ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
2479 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \
2480                                             ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
2481                                             ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))
2482 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
2483 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
2484 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
2485 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
2486 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
2487 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
2488                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
2489                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
2490                                                  ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
2491 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
2492                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
2493                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
2494                                             ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
2495 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
2496 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \
2497                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
2498                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
2499                                                ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
2500 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
2501                                                    ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
2502 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
2503                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
2504                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
2505                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
2506
2507 #define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
2508
2509 #define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
2510 /**
2511   * @}
2512   */
2513
2514 /* Private functions prototypes ----------------------------------------------*/
2515 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
2516   * @ingroup RTEMSBSPsARMSTM32H7
2517   * @{
2518   */
2519
2520 /**
2521   * @}
2522   */
2523
2524 /* Private functions ---------------------------------------------------------*/
2525 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
2526   * @ingroup RTEMSBSPsARMSTM32H7
2527   * @{
2528   */
2529
2530 /**
2531   * @}
2532   */
2533 /**
2534   * @}
2535   */
2536
2537 /**
2538   * @}
2539   */
2540 #endif /* FDCAN1 */
2541
2542 #ifdef __cplusplus
2543 }
2544 #endif
2545
2546 #endif /* STM32H7xx_HAL_FDCAN_H */
2547
2548