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File indexing completed on 2025-05-11 08:23:35 

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_eth.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of ETH HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_ETH_H
0021 #define STM32H7xx_HAL_ETH_H
0022 
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026 
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029 
0030 #if defined(ETH)
0031 
0032 /** @addtogroup STM32H7xx_HAL_Driver
0033   * @{
0034   */
0035 
0036 /** @addtogroup ETH
0037   * @{
0038   */
0039 
0040 /* Exported types ------------------------------------------------------------*/
0041 #ifndef ETH_TX_DESC_CNT
0042 #define ETH_TX_DESC_CNT         4U
0043 #endif /* ETH_TX_DESC_CNT */
0044 
0045 #ifndef ETH_RX_DESC_CNT
0046 #define ETH_RX_DESC_CNT         4U
0047 #endif /* ETH_RX_DESC_CNT */
0048 
0049 #ifndef ETH_SWRESET_TIMEOUT
0050 #define ETH_SWRESET_TIMEOUT     500U
0051 #endif /* ETH_SWRESET_TIMEOUT */
0052 
0053 #ifndef ETH_MDIO_BUS_TIMEOUT
0054 #define ETH_MDIO_BUS_TIMEOUT    1000U
0055 #endif /* ETH_MDIO_BUS_TIMEOUT */
0056 
0057 #ifndef ETH_MAC_US_TICK
0058 #define ETH_MAC_US_TICK         1000000U
0059 #endif /* ETH_MAC_US_TICK */
0060 
0061 /*********************** Descriptors struct def section ************************/
0062 /** @defgroup ETH_Exported_Types ETH Exported Types
0063   * @ingroup RTEMSBSPsARMSTM32H7
0064   * @{
0065   */
0066 
0067 /**
0068   * @brief  ETH DMA Descriptor structure definition
0069   */
0070 typedef struct
0071 {
0072   __IO uint32_t DESC0;
0073   __IO uint32_t DESC1;
0074   __IO uint32_t DESC2;
0075   __IO uint32_t DESC3;
0076   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
0077   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
0078 } ETH_DMADescTypeDef;
0079 /**
0080   *
0081   */
0082 
0083 /**
0084   * @brief  ETH Buffers List structure definition
0085   */
0086 typedef struct __ETH_BufferTypeDef
0087 {
0088   uint8_t *buffer;                /*<! buffer address */
0089 
0090   uint32_t len;                   /*<! buffer length */
0091 
0092   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
0093 } ETH_BufferTypeDef;
0094 /**
0095   *
0096   */
0097 
0098 /**
0099   * @brief  DMA Transmit Descriptors Wrapper structure definition
0100   */
0101 typedef struct
0102 {
0103   uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
0104 
0105   uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
0106 
0107   uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
0108 
0109   uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
0110 
0111   uint32_t BuffersInUse;                   /*<! Buffers in Use */
0112 
0113   uint32_t releaseIndex;                  /*<! Release index */
0114 } ETH_TxDescListTypeDef;
0115 /**
0116   *
0117   */
0118 
0119 /**
0120   * @brief  Transmit Packet Configuration structure definition
0121   */
0122 typedef struct
0123 {
0124   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
0125                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
0126 
0127   uint32_t Length;                  /*!< Total packet length   */
0128 
0129   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
0130 
0131   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
0132                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
0133 
0134   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
0135                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
0136 
0137   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
0138                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
0139 
0140   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
0141                                         This parameter can be a value from 0x0 to 0x3FFF */
0142 
0143   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
0144                                         This parameter can be a value from 0x0 to 0x3FFFF */
0145 
0146   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
0147                                         This parameter can be a value from 0x5 to 0xF */
0148 
0149   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
0150                                         This parameter can be a value from 0x0 to 0xFFFF*/
0151 
0152   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
0153                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
0154 
0155   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
0156                                         This parameter can be a value from 0x0 to 0x3FFFF */
0157 
0158   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
0159                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
0160 
0161   void *pData;                     /*!< Specifies Application packet pointer to save   */
0162 
0163 } ETH_TxPacketConfigTypeDef;
0164 /**
0165   *
0166   */
0167 
0168 /**
0169   * @brief  ETH Timestamp structure definition
0170   */
0171 typedef struct
0172 {
0173   uint32_t TimeStampLow;
0174   uint32_t TimeStampHigh;
0175 
0176 } ETH_TimeStampTypeDef;
0177 /**
0178   *
0179   */
0180 
0181 #ifdef HAL_ETH_USE_PTP
0182 /**
0183   * @brief  ETH Timeupdate structure definition
0184   */
0185 typedef struct
0186 {
0187   uint32_t Seconds;
0188   uint32_t NanoSeconds;
0189 } ETH_TimeTypeDef;
0190 /**
0191   *
0192   */
0193 #endif  /* HAL_ETH_USE_PTP */
0194 
0195 /**
0196   * @brief  DMA Receive Descriptors Wrapper structure definition
0197   */
0198 typedef struct
0199 {
0200   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
0201 
0202   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
0203                                              If 0, DMA will not generate the Rx complete interrupt. */
0204 
0205   uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
0206 
0207   uint32_t RxDescCnt;                 /*<! Number of descriptors . */
0208 
0209   uint32_t RxDataLength;              /*<! Received Data Length. */
0210 
0211   uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
0212 
0213   uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
0214 
0215   uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
0216 
0217   ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
0218 
0219   void *pRxStart;                     /*<! Pointer to the first buff. */
0220 
0221   void *pRxEnd;                       /*<! Pointer to the last buff. */
0222 
0223 } ETH_RxDescListTypeDef;
0224 /**
0225   *
0226   */
0227 
0228 /**
0229   * @brief  ETH MAC Configuration Structure definition
0230   */
0231 typedef struct
0232 {
0233   uint32_t
0234   SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
0235                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
0236 
0237   FunctionalState
0238   ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
0239 
0240   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
0241                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
0242 
0243   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
0244 
0245   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
0246 
0247   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
0248 
0249   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
0250 
0251   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
0252 
0253   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
0254 
0255   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
0256                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
0257                                                            without reporting a giant packet error */
0258 
0259   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
0260                                                            This parameter can be a value of @ref ETH_Speed */
0261 
0262   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
0263                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
0264 
0265   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
0266 
0267   FunctionalState
0268   CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
0269 
0270   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
0271 
0272   FunctionalState
0273   CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
0274 
0275   FunctionalState
0276   RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
0277 
0278   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
0279                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
0280 
0281   FunctionalState
0282   DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
0283 
0284   uint32_t
0285   PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
0286                                                            This parameter can be a value of @ref ETH_Preamble_Length */
0287 
0288   FunctionalState
0289   UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
0290 
0291   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
0292 
0293   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
0294 
0295   uint32_t
0296   GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
0297                                                     greater than the value programmed in this field in units of bytes
0298                                                     This parameter must be a number between
0299                                                     Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
0300 
0301   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
0302 
0303   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
0304                                                            This parameter can be a value from 0x0 to 0xFF */
0305 
0306   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
0307 
0308   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
0309                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
0310 
0311   uint32_t
0312   PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
0313                                                    This parameter must be a number between
0314                                                    Min_Data = 0x0 and Max_Data = 0xFFFF.*/
0315 
0316   FunctionalState
0317   ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
0318 
0319   uint32_t
0320   PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
0321                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
0322 
0323   FunctionalState
0324   TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
0325                                                    or the MAC back pressure operation in Half Duplex mode */
0326 
0327   FunctionalState
0328   UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
0329 
0330   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
0331                                                   and disables its transmitter for a specified (Pause) time */
0332 
0333   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
0334                                                       This parameter can be a value of @ref ETH_Transmit_Mode */
0335 
0336   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
0337                                                              This parameter can be a value of @ref ETH_Receive_Mode */
0338 
0339   FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
0340 
0341   FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
0342 
0343   FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
0344 } ETH_MACConfigTypeDef;
0345 /**
0346   *
0347   */
0348 
0349 /**
0350   * @brief  ETH DMA Configuration Structure definition
0351   */
0352 typedef struct
0353 {
0354   uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
0355                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
0356 
0357   FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
0358                                                             burst transfers on Read and Write channels  */
0359 
0360   uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
0361                                                      This parameter can be a value of @ref ETH_Burst_Mode */
0362   FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
0363                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
0364 
0365   FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
0366 
0367   uint32_t
0368   TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
0369                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
0370 
0371   FunctionalState
0372   SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
0373                                                       Packet of Transmit data even before
0374                                                       obtaining the status for the first one. */
0375 
0376   uint32_t
0377   RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
0378                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
0379 
0380   FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
0381 
0382   FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
0383 
0384   uint32_t
0385   MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
0386                                                   This parameter can be a value from 0x40 to 0x3FFF */
0387 
0388 } ETH_DMAConfigTypeDef;
0389 /**
0390   *
0391   */
0392 
0393 /**
0394   * @brief  HAL ETH Media Interfaces enum definition
0395   */
0396 typedef enum
0397 {
0398   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
0399   HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
0400 } ETH_MediaInterfaceTypeDef;
0401 /**
0402   *
0403   */
0404 
0405 #ifdef HAL_ETH_USE_PTP
0406 /**
0407   * @brief  HAL ETH PTP Update type enum definition
0408   */
0409 typedef enum
0410 {
0411   HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
0412   HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
0413 } ETH_PtpUpdateTypeDef;
0414 /**
0415   *
0416   */
0417 #endif  /* HAL_ETH_USE_PTP */
0418 
0419 /**
0420   * @brief  ETH Init Structure definition
0421   */
0422 typedef struct
0423 {
0424   uint8_t
0425   *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
0426 
0427   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
0428 
0429   ETH_DMADescTypeDef
0430   *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
0431 
0432   ETH_DMADescTypeDef
0433   *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
0434 
0435   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
0436 
0437 } ETH_InitTypeDef;
0438 /**
0439   *
0440   */
0441 
0442 #ifdef HAL_ETH_USE_PTP
0443 /**
0444   * @brief  ETH PTP Init Structure definition
0445   */
0446 typedef struct
0447 {
0448   uint32_t                    Timestamp;                    /*!< Enable Timestamp */
0449   uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
0450   uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
0451   uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
0452   uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
0453   uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
0454   uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
0455   uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
0456   uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
0457   uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
0458   uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
0459   uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
0460   uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
0461   uint32_t                    TimestampSnapshots;           /*!< Select PTP packets for Taking Snapshots */
0462   uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
0463   uint32_t
0464   TimestampChecksumCorrection;  /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
0465   uint32_t                    TimestampStatusMode;          /*!< Transmit Timestamp Status Mode */
0466   uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
0467   uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
0468 
0469 } ETH_PTP_ConfigTypeDef;
0470 /**
0471   *
0472   */
0473 #endif  /* HAL_ETH_USE_PTP */
0474 
0475 /**
0476   * @brief  HAL State structures definition
0477   */
0478 typedef uint32_t HAL_ETH_StateTypeDef;
0479 /**
0480   *
0481   */
0482 
0483 /**
0484   * @brief  HAL ETH Rx Get Buffer Function definition
0485   */
0486 typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
0487 /**
0488   *
0489   */
0490 
0491 /**
0492   * @brief  HAL ETH Rx Set App Data Function definition
0493   */
0494 typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
0495                                             uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
0496 /**
0497   *
0498   */
0499 
0500 /**
0501   * @brief  HAL ETH Tx Free Function definition
0502   */
0503 typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
0504 /**
0505   *
0506   */
0507 
0508 /**
0509   * @brief  HAL ETH Tx Free Function definition
0510   */
0511 typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
0512                                            ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
0513 /**
0514   *
0515   */
0516 
0517 /**
0518   * @brief  ETH Handle Structure definition
0519   */
0520 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0521 typedef struct __ETH_HandleTypeDef
0522 #else
0523 typedef struct
0524 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
0525 {
0526   ETH_TypeDef                *Instance;                 /*!< Register base address       */
0527 
0528   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
0529 
0530   ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
0531                                                             addresses and current descriptor index  */
0532 
0533   ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
0534                                                             addresses and current descriptor index  */
0535 
0536 #ifdef HAL_ETH_USE_PTP
0537   ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
0538 #endif /* HAL_ETH_USE_PTP */
0539 
0540   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
0541                                                               and also related to Tx operations. This parameter can
0542                                                               be a value of @ref ETH_State_Codes */
0543 
0544   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
0545                                                              This parameter can be a value of @ref ETH_Error_Code.*/
0546 
0547   __IO uint32_t
0548   DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
0549                                                              This parameter can be a combination of
0550                                                              @ref ETH_DMA_Status_Flags */
0551 
0552   __IO uint32_t
0553   MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
0554                                                              This parameter can be a combination of
0555                                                              @ref ETH_MAC_Rx_Tx_Status */
0556 
0557   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
0558                                                              This parameter can be a value of
0559                                                              @ref ETH_MAC_Wake_Up_Event */
0560 
0561   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
0562                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
0563 
0564   __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
0565                                                              This parameter can be a value of
0566                                                              @ref ETH_PTP_Config_Status */
0567 
0568 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0569 
0570   void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
0571   void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
0572   void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
0573   void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
0574   void (* EEECallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH EEE Callback   */
0575   void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
0576 
0577   void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
0578   void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
0579 
0580 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
0581 
0582   pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
0583   pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
0584   pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
0585   pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
0586 
0587 } ETH_HandleTypeDef;
0588 /**
0589   *
0590   */
0591 
0592 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0593 /**
0594   * @brief  HAL ETH Callback ID enumeration definition
0595   */
0596 typedef enum
0597 {
0598   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
0599   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
0600   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
0601   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
0602   HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
0603   HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
0604   HAL_ETH_EEE_CB_ID                = 0x07U,    /*!< ETH EEE Callback ID               */
0605   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
0606 
0607 } HAL_ETH_CallbackIDTypeDef;
0608 
0609 /**
0610   * @brief  HAL ETH Callback pointer definition
0611   */
0612 typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
0613 
0614 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
0615 
0616 /**
0617   * @brief  ETH MAC filter structure definition
0618   */
0619 typedef struct
0620 {
0621   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
0622 
0623   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
0624 
0625   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
0626 
0627   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
0628 
0629   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
0630 
0631   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
0632 
0633   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
0634 
0635   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
0636 
0637   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
0638 
0639   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
0640 
0641   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
0642                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
0643 } ETH_MACFilterConfigTypeDef;
0644 /**
0645   *
0646   */
0647 
0648 /**
0649   * @brief  ETH Power Down structure definition
0650   */
0651 typedef struct
0652 {
0653   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
0654 
0655   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
0656 
0657   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
0658 
0659   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
0660 
0661 } ETH_PowerDownConfigTypeDef;
0662 /**
0663   *
0664   */
0665 
0666 /**
0667   * @}
0668   */
0669 
0670 /* Exported constants --------------------------------------------------------*/
0671 /** @defgroup ETH_Exported_Constants ETH Exported Constants
0672   * @ingroup RTEMSBSPsARMSTM32H7
0673   * @{
0674   */
0675 
0676 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
0677   * @ingroup RTEMSBSPsARMSTM32H7
0678   * @{
0679   */
0680 
0681 /*
0682    DMA Tx Normal Descriptor Read Format
0683   -----------------------------------------------------------------------------------------------
0684   TDES0 |                         Buffer1 or Header Address  [31:0]                              |
0685   -----------------------------------------------------------------------------------------------
0686   TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
0687   -----------------------------------------------------------------------------------------------
0688   TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
0689   -----------------------------------------------------------------------------------------------
0690   TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
0691   -----------------------------------------------------------------------------------------------
0692 */
0693 
0694 /**
0695   * @brief  Bit definition of TDES0 RF register
0696   */
0697 #define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
0698 
0699 /**
0700   * @brief  Bit definition of TDES1 RF register
0701   */
0702 #define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
0703 
0704 /**
0705   * @brief  Bit definition of TDES2 RF register
0706   */
0707 #define ETH_DMATXNDESCRF_IOC          0x80000000U  /*!< Interrupt on Completion */
0708 #define ETH_DMATXNDESCRF_TTSE         0x40000000U  /*!< Transmit Timestamp Enable */
0709 #define ETH_DMATXNDESCRF_B2L          0x3FFF0000U  /*!< Buffer 2 Length */
0710 #define ETH_DMATXNDESCRF_VTIR         0x0000C000U  /*!< VLAN Tag Insertion or Replacement mask */
0711 #define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U  /*!< Do not add a VLAN tag. */
0712 #define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U  /*!< Remove the VLAN tag from the packets before transmission. */
0713 #define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U  /*!< Insert a VLAN tag. */
0714 #define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U  /*!< Replace the VLAN tag. */
0715 #define ETH_DMATXNDESCRF_B1L          0x00003FFFU  /*!< Buffer 1 Length */
0716 #define ETH_DMATXNDESCRF_HL           0x000003FFU  /*!< Header Length */
0717 
0718 /**
0719   * @brief  Bit definition of TDES3 RF register
0720   */
0721 #define ETH_DMATXNDESCRF_OWN                                 0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
0722 #define ETH_DMATXNDESCRF_CTXT                                0x40000000U  /*!< Context Type */
0723 #define ETH_DMATXNDESCRF_FD                                  0x20000000U  /*!< First Descriptor */
0724 #define ETH_DMATXNDESCRF_LD                                  0x10000000U  /*!< Last Descriptor */
0725 #define ETH_DMATXNDESCRF_CPC                                 0x0C000000U  /*!< CRC Pad Control mask */
0726 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U  /*!< CRC Pad Control: CRC and Pad Insertion */
0727 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
0728 #define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U  /*!< CRC Pad Control: Disable CRC Insertion */
0729 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U  /*!< CRC Pad Control: CRC Replacement */
0730 #define ETH_DMATXNDESCRF_SAIC                                0x03800000U  /*!< SA Insertion Control mask*/
0731 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U  /*!< SA Insertion Control: Do not include the source address */
0732 #define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U  /*!< SA Insertion Control: Include or insert the source address */
0733 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U  /*!< SA Insertion Control: Replace the source address */
0734 #define ETH_DMATXNDESCRF_THL                                 0x00780000U  /*!< TCP Header Length */
0735 #define ETH_DMATXNDESCRF_TSE                                 0x00040000U  /*!< TCP segmentation enable */
0736 #define ETH_DMATXNDESCRF_CIC                                 0x00030000U  /*!< Checksum Insertion Control: 4 cases */
0737 #define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U  /*!< Do Nothing: Checksum Engine is disabled */
0738 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U  /*!< Only IP header checksum calculation and insertion are enabled. */
0739 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U  /*!< IP header checksum and payload checksum calculation and insertion are
0740                                                                                         enabled, but pseudo header
0741                                                                                         checksum is not
0742                                                                                         calculated in hardware */
0743 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U  /*!< IP Header checksum and payload checksum calculation and insertion are
0744                                                                                         enabled, and pseudo header
0745                                                                                         checksum is
0746                                                                                         calculated in hardware. */
0747 #define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU  /*!< TCP Payload Length */
0748 #define ETH_DMATXNDESCRF_FL                                  0x00007FFFU  /*!< Transmit End of Ring */
0749 
0750 /*
0751    DMA Tx Normal Descriptor Write Back Format
0752   -----------------------------------------------------------------------------------------------
0753   TDES0 |                         Timestamp Low                                                  |
0754   -----------------------------------------------------------------------------------------------
0755   TDES1 |                         Timestamp High                                                 |
0756   -----------------------------------------------------------------------------------------------
0757   TDES2 |                           Reserved[31:0]                                               |
0758   -----------------------------------------------------------------------------------------------
0759   TDES3 | OWN(31) |                          Status[30:0]                                        |
0760   -----------------------------------------------------------------------------------------------
0761 */
0762 
0763 /**
0764   * @brief  Bit definition of TDES0 WBF register
0765   */
0766 #define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
0767 
0768 /**
0769   * @brief  Bit definition of TDES1 WBF register
0770   */
0771 #define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
0772 
0773 /**
0774   * @brief  Bit definition of TDES3 WBF register
0775   */
0776 #define ETH_DMATXNDESCWBF_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
0777 #define ETH_DMATXNDESCWBF_CTXT                    0x40000000U  /*!< Context Type */
0778 #define ETH_DMATXNDESCWBF_FD                      0x20000000U  /*!< First Descriptor */
0779 #define ETH_DMATXNDESCWBF_LD                      0x10000000U  /*!< Last Descriptor */
0780 #define ETH_DMATXNDESCWBF_TTSS                    0x00020000U  /*!< Tx Timestamp Status */
0781 #define ETH_DMATXNDESCWBF_DP                      0x04000000U  /*!< Disable Padding */
0782 #define ETH_DMATXNDESCWBF_TTSE                    0x02000000U  /*!< Transmit Timestamp Enable */
0783 #define ETH_DMATXNDESCWBF_ES                      0x00008000U  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
0784 #define ETH_DMATXNDESCWBF_JT                      0x00004000U  /*!< Jabber Timeout */
0785 #define ETH_DMATXNDESCWBF_FF                      0x00002000U  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
0786 #define ETH_DMATXNDESCWBF_PCE                     0x00001000U  /*!< Payload Checksum Error */
0787 #define ETH_DMATXNDESCWBF_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
0788 #define ETH_DMATXNDESCWBF_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
0789 #define ETH_DMATXNDESCWBF_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
0790 #define ETH_DMATXNDESCWBF_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
0791 #define ETH_DMATXNDESCWBF_CC                      0x000000F0U  /*!< Collision Count */
0792 #define ETH_DMATXNDESCWBF_ED                      0x00000008U  /*!< Excessive Deferral */
0793 #define ETH_DMATXNDESCWBF_UF                      0x00000004U  /*!< Underflow Error: late data arrival from the memory */
0794 #define ETH_DMATXNDESCWBF_DB                      0x00000002U  /*!< Deferred Bit */
0795 #define ETH_DMATXNDESCWBF_IHE                     0x00000004U  /*!< IP Header Error */
0796 
0797 /*
0798    DMA Tx Context Descriptor
0799   -----------------------------------------------------------------------------------------------
0800   TDES0 |                               Timestamp Low                                            |
0801   -----------------------------------------------------------------------------------------------
0802   TDES1 |                               Timestamp High                                           |
0803   -----------------------------------------------------------------------------------------------
0804   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
0805   -----------------------------------------------------------------------------------------------
0806   TDES3 | OWN(31) |                          Status[30:0]                                        |
0807   -----------------------------------------------------------------------------------------------
0808 */
0809 
0810 /**
0811   * @brief  Bit definition of Tx context descriptor register 0
0812   */
0813 #define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
0814 
0815 /**
0816   * @brief  Bit definition of Tx context descriptor register 1
0817   */
0818 #define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
0819 
0820 /**
0821   * @brief  Bit definition of Tx context descriptor register 2
0822   */
0823 #define ETH_DMATXCDESC_IVT                     0xFFFF0000U  /*!< Inner VLAN Tag */
0824 #define ETH_DMATXCDESC_MSS                     0x00003FFFU  /*!< Maximum Segment Size */
0825 
0826 /**
0827   * @brief  Bit definition of Tx context descriptor register 3
0828   */
0829 #define ETH_DMATXCDESC_OWN                     0x80000000U     /*!< OWN bit: descriptor is owned by DMA engine */
0830 #define ETH_DMATXCDESC_CTXT                    0x40000000U     /*!< Context Type */
0831 #define ETH_DMATXCDESC_OSTC                    0x08000000U     /*!< One-Step Timestamp Correction Enable */
0832 #define ETH_DMATXCDESC_TCMSSV                  0x04000000U     /*!< One-Step Timestamp Correction Input or MSS Valid */
0833 #define ETH_DMATXCDESC_CDE                     0x00800000U     /*!< Context Descriptor Error */
0834 #define ETH_DMATXCDESC_IVTIR                   0x000C0000U     /*!< Inner VLAN Tag Insert or Replace Mask */
0835 #define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U     /*!< Do not add the inner VLAN tag. */
0836 #define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U     /*!< Remove the inner VLAN tag from the packets before transmission. */
0837 #define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U     /*!< Insert the inner VLAN tag. */
0838 #define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U     /*!< Replace the inner VLAN tag. */
0839 #define ETH_DMATXCDESC_IVLTV                   0x00020000U     /*!< Inner VLAN Tag Valid */
0840 #define ETH_DMATXCDESC_VLTV                    0x00010000U     /*!< VLAN Tag Valid */
0841 #define ETH_DMATXCDESC_VT                      0x0000FFFFU     /*!< VLAN Tag */
0842 
0843 /**
0844   * @}
0845   */
0846 
0847 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
0848   * @ingroup RTEMSBSPsARMSTM32H7
0849   * @{
0850   */
0851 
0852 /*
0853   DMA Rx Normal Descriptor read format
0854   -----------------------------------------------------------------------------------------------------------
0855   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
0856   -----------------------------------------------------------------------------------------------------------
0857   RDES1 |                                            Reserved                                               |
0858   -----------------------------------------------------------------------------------------------------------
0859   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
0860   -----------------------------------------------------------------------------------------------------------
0861   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
0862   -----------------------------------------------------------------------------------------------------------
0863 */
0864 
0865 /**
0866   * @brief  Bit definition of Rx normal descriptor register 0 read format
0867   */
0868 #define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU  /*!< Header or Buffer 1 Address Pointer  */
0869 
0870 /**
0871   * @brief  Bit definition of Rx normal descriptor register 2 read format
0872   */
0873 #define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU  /*!< Buffer 2 Address Pointer  */
0874 
0875 /**
0876   * @brief  Bit definition of Rx normal descriptor register 3 read format
0877   */
0878 #define ETH_DMARXNDESCRF_OWN              0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
0879 #define ETH_DMARXNDESCRF_IOC              0x40000000U  /*!< Interrupt Enabled on Completion  */
0880 #define ETH_DMARXNDESCRF_BUF2V            0x02000000U  /*!< Buffer 2 Address Valid */
0881 #define ETH_DMARXNDESCRF_BUF1V            0x01000000U  /*!< Buffer 1 Address Valid */
0882 
0883 /*
0884   DMA Rx Normal Descriptor write back format
0885   ---------------------------------------------------------------------------------------------------------------------
0886   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
0887   ---------------------------------------------------------------------------------------------------------------------
0888   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
0889   ---------------------------------------------------------------------------------------------------------------------
0890   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
0891   ---------------------------------------------------------------------------------------------------------------------
0892   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
0893   ---------------------------------------------------------------------------------------------------------------------
0894 */
0895 
0896 /**
0897   * @brief  Bit definition of Rx normal descriptor register 0 write back format
0898   */
0899 #define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U  /*!< Inner VLAN Tag  */
0900 #define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU  /*!< Outer VLAN Tag  */
0901 
0902 /**
0903   * @brief  Bit definition of Rx normal descriptor register 1 write back format
0904   */
0905 #define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
0906 #define ETH_DMARXNDESCWBF_TD              0x00008000U  /*!< Timestamp Dropped  */
0907 #define ETH_DMARXNDESCWBF_TSA             0x00004000U  /*!< Timestamp Available  */
0908 #define ETH_DMARXNDESCWBF_PV              0x00002000U  /*!< PTP Version  */
0909 #define ETH_DMARXNDESCWBF_PFT             0x00001000U  /*!< PTP Packet Type  */
0910 #define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U  /*!< PTP Message Type: No PTP message received  */
0911 #define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U  /*!< PTP Message Type: SYNC (all clock types)  */
0912 #define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U  /*!< PTP Message Type: Follow_Up (all clock types)  */
0913 #define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U  /*!< PTP Message Type: Delay_Req (all clock types)  */
0914 #define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U  /*!< PTP Message Type: Delay_Resp (all clock types)  */
0915 #define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
0916 #define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
0917 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
0918 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U  /*!< PTP Message Type: Announce  */
0919 #define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U  /*!< PTP Message Type: Management  */
0920 #define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U  /*!< PTP Message Type: Signaling  */
0921 #define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U  /*!< PTP Message Type: PTP packet with Reserved message type  */
0922 #define ETH_DMARXNDESCWBF_IPCE            0x00000080U  /*!< IP Payload Error */
0923 #define ETH_DMARXNDESCWBF_IPCB            0x00000040U  /*!< IP Checksum Bypassed */
0924 #define ETH_DMARXNDESCWBF_IPV6            0x00000020U  /*!< IPv6 header Present */
0925 #define ETH_DMARXNDESCWBF_IPV4            0x00000010U  /*!< IPv4 header Present */
0926 #define ETH_DMARXNDESCWBF_IPHE            0x00000008U  /*!< IP Header Error */
0927 #define ETH_DMARXNDESCWBF_PT              0x00000003U  /*!< Payload Type mask */
0928 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U  /*!< Payload Type: Unknown type or IP/AV payload not processed */
0929 #define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U  /*!< Payload Type: UDP */
0930 #define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U  /*!< Payload Type: TCP  */
0931 #define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U  /*!< Payload Type: ICMP */
0932 
0933 /**
0934   * @brief  Bit definition of Rx normal descriptor register 2 write back format
0935   */
0936 #define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
0937 #define ETH_DMARXNDESCWBF_L4FM            0x10000000U  /*!< Layer 4 Filter Match                  */
0938 #define ETH_DMARXNDESCWBF_L3FM            0x08000000U  /*!< Layer 3 Filter Match                  */
0939 #define ETH_DMARXNDESCWBF_MADRM           0x07F80000U  /*!< MAC Address Match or Hash Value       */
0940 #define ETH_DMARXNDESCWBF_HF              0x00040000U  /*!< Hash Filter Status                    */
0941 #define ETH_DMARXNDESCWBF_DAF             0x00020000U  /*!< Destination Address Filter Fail       */
0942 #define ETH_DMARXNDESCWBF_SAF             0x00010000U  /*!< SA Address Filter Fail                */
0943 #define ETH_DMARXNDESCWBF_VF              0x00008000U  /*!< VLAN Filter Status                    */
0944 #define ETH_DMARXNDESCWBF_ARPNR           0x00000400U  /*!< ARP Reply Not Generated               */
0945 
0946 /**
0947   * @brief  Bit definition of Rx normal descriptor register 3 write back format
0948   */
0949 #define ETH_DMARXNDESCWBF_OWN             0x80000000U  /*!< Own Bit */
0950 #define ETH_DMARXNDESCWBF_CTXT            0x40000000U  /*!< Receive Context Descriptor */
0951 #define ETH_DMARXNDESCWBF_FD              0x20000000U  /*!< First Descriptor */
0952 #define ETH_DMARXNDESCWBF_LD              0x10000000U  /*!< Last Descriptor */
0953 #define ETH_DMARXNDESCWBF_RS2V            0x08000000U  /*!< Receive Status RDES2 Valid */
0954 #define ETH_DMARXNDESCWBF_RS1V            0x04000000U  /*!< Receive Status RDES1 Valid */
0955 #define ETH_DMARXNDESCWBF_RS0V            0x02000000U  /*!< Receive Status RDES0 Valid */
0956 #define ETH_DMARXNDESCWBF_CE              0x01000000U  /*!< CRC Error */
0957 #define ETH_DMARXNDESCWBF_GP              0x00800000U  /*!< Giant Packet */
0958 #define ETH_DMARXNDESCWBF_RWT             0x00400000U  /*!< Receive Watchdog Timeout */
0959 #define ETH_DMARXNDESCWBF_OE              0x00200000U  /*!< Overflow Error */
0960 #define ETH_DMARXNDESCWBF_RE              0x00100000U  /*!< Receive Error */
0961 #define ETH_DMARXNDESCWBF_DE              0x00080000U  /*!< Dribble Bit Error */
0962 #define ETH_DMARXNDESCWBF_LT              0x00070000U  /*!< Length/Type Field */
0963 #define ETH_DMARXNDESCWBF_LT_LP           0x00000000U  /*!< The packet is a length packet */
0964 #define ETH_DMARXNDESCWBF_LT_TP           0x00010000U  /*!< The packet is a type packet */
0965 #define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U  /*!< The packet is a ARP Request packet type */
0966 #define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U  /*!< The packet is a type packet with VLAN Tag */
0967 #define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U  /*!< The packet is a type packet with Double VLAN Tag */
0968 #define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U  /*!< The packet is a MAC Control packet type */
0969 #define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U  /*!< The packet is a OAM packet type */
0970 #define ETH_DMARXNDESCWBF_ES              0x00008000U  /*!< Error Summary */
0971 #define ETH_DMARXNDESCWBF_PL              0x00007FFFU  /*!< Packet Length */
0972 
0973 /*
0974   DMA Rx context Descriptor
0975   ---------------------------------------------------------------------------------------------------------------------
0976   RDES0 |                                     Timestamp Low[31:0]                                                     |
0977   ---------------------------------------------------------------------------------------------------------------------
0978   RDES1 |                                     Timestamp High[31:0]                                                    |
0979   ---------------------------------------------------------------------------------------------------------------------
0980   RDES2 |                                          Reserved                                                           |
0981   ---------------------------------------------------------------------------------------------------------------------
0982   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
0983   ---------------------------------------------------------------------------------------------------------------------
0984 */
0985 
0986 /**
0987   * @brief  Bit definition of Rx context descriptor register 0
0988   */
0989 #define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU  /*!< Receive Packet Timestamp Low  */
0990 
0991 /**
0992   * @brief  Bit definition of Rx context descriptor register 1
0993   */
0994 #define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU  /*!< Receive Packet Timestamp High  */
0995 
0996 /**
0997   * @brief  Bit definition of Rx context descriptor register 3
0998   */
0999 #define ETH_DMARXCDESC_OWN                    0x80000000U  /*!< Own Bit  */
1000 #define ETH_DMARXCDESC_CTXT                   0x40000000U  /*!< Receive Context Descriptor  */
1001 
1002 /**
1003   * @}
1004   */
1005 
1006 /** @defgroup ETH_Frame_settings ETH frame settings
1007   * @ingroup RTEMSBSPsARMSTM32H7
1008   * @{
1009   */
1010 #define ETH_MAX_PACKET_SIZE                   1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
1011 #define ETH_HEADER                            14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
1012 #define ETH_CRC                               4U    /*!< Ethernet CRC */
1013 #define ETH_VLAN_TAG                          4U    /*!< optional 802.1q VLAN Tag */
1014 #define ETH_MIN_PAYLOAD                       46U    /*!< Minimum Ethernet payload size */
1015 #define ETH_MAX_PAYLOAD                       1500U    /*!< Maximum Ethernet payload size */
1016 #define ETH_JUMBO_FRAME_PAYLOAD               9000U    /*!< Jumbo frame payload size */
1017 /**
1018   * @}
1019   */
1020 
1021 /** @defgroup ETH_Error_Code ETH Error Code
1022   * @ingroup RTEMSBSPsARMSTM32H7
1023   * @{
1024   */
1025 #define HAL_ETH_ERROR_NONE                    0x00000000U   /*!< No error            */
1026 #define HAL_ETH_ERROR_PARAM                   0x00000001U   /*!< Busy error          */
1027 #define HAL_ETH_ERROR_BUSY                    0x00000002U   /*!< Parameter error     */
1028 #define HAL_ETH_ERROR_TIMEOUT                 0x00000004U   /*!< Timeout error       */
1029 #define HAL_ETH_ERROR_DMA                     0x00000008U   /*!< DMA transfer error  */
1030 #define HAL_ETH_ERROR_MAC                     0x00000010U   /*!< MAC transfer error  */
1031 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1032 #define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U    /*!< Invalid Callback error  */
1033 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1034 /**
1035   * @}
1036   */
1037 
1038 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
1039   * @ingroup RTEMSBSPsARMSTM32H7
1040   * @{
1041   */
1042 #define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
1043 #define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
1044 #define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
1045 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
1046 #define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
1047 #define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
1048 /**
1049   * @}
1050   */
1051 
1052 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
1053   * @ingroup RTEMSBSPsARMSTM32H7
1054   * @{
1055   */
1056 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
1057 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
1058 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
1059 /**
1060   * @}
1061   */
1062 
1063 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
1064   * @ingroup RTEMSBSPsARMSTM32H7
1065   * @{
1066   */
1067 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
1068 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
1069 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
1070 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
1071 /**
1072   * @}
1073   */
1074 
1075 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
1076   * @ingroup RTEMSBSPsARMSTM32H7
1077   * @{
1078   */
1079 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
1080 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
1081 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
1082 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
1083 /**
1084   * @}
1085   */
1086 
1087 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
1088   * @ingroup RTEMSBSPsARMSTM32H7
1089   * @{
1090   */
1091 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
1092 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
1093 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
1094 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
1095 /**
1096   * @}
1097   */
1098 
1099 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
1100   * @ingroup RTEMSBSPsARMSTM32H7
1101   * @{
1102   */
1103 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
1104 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
1105 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
1106 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
1107 /**
1108   * @}
1109   */
1110 
1111 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
1112   * @ingroup RTEMSBSPsARMSTM32H7
1113   * @{
1114   */
1115 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
1116 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
1117 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
1118 /**
1119   * @}
1120   */
1121 
1122 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
1123   * @ingroup RTEMSBSPsARMSTM32H7
1124   * @{
1125   */
1126 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
1127 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
1128 /**
1129   * @}
1130   */
1131 
1132 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
1133   * @ingroup RTEMSBSPsARMSTM32H7
1134   * @{
1135   */
1136 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
1137 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
1138 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
1139 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
1140 /**
1141   * @}
1142   */
1143 
1144 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
1145   * @ingroup RTEMSBSPsARMSTM32H7
1146   * @{
1147   */
1148 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
1149 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
1150 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
1151 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
1152 /**
1153   * @}
1154   */
1155 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1156   * @ingroup RTEMSBSPsARMSTM32H7
1157   * @{
1158   */
1159 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
1160 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1161 /**
1162   * @}
1163   */
1164 
1165 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1166   * @ingroup RTEMSBSPsARMSTM32H7
1167   * @{
1168   */
1169 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
1170 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1171 /**
1172   * @}
1173   */
1174 
1175 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1176   * @ingroup RTEMSBSPsARMSTM32H7
1177   * @{
1178   */
1179 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
1180 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
1181 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
1182 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
1183 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
1184 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
1185 /**
1186   * @}
1187   */
1188 
1189 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1190   * @ingroup RTEMSBSPsARMSTM32H7
1191   * @{
1192   */
1193 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
1194 #define ETH_DMAARBITRATION_RX1_TX1   0x00000000U
1195 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
1196 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
1197 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
1198 #define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
1199 #define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
1200 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
1201 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
1202 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1203 #define ETH_DMAARBITRATION_TX1_RX1   0x00000000U
1204 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1205 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1206 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1207 #define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1208 #define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1209 #define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1210 #define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1211 /**
1212   * @}
1213   */
1214 
1215 /** @defgroup ETH_Burst_Mode ETH Burst Mode
1216   * @ingroup RTEMSBSPsARMSTM32H7
1217   * @{
1218   */
1219 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
1220 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
1221 #define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
1222 /**
1223   * @}
1224   */
1225 
1226 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1227   * @ingroup RTEMSBSPsARMSTM32H7
1228   * @{
1229   */
1230 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
1231 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
1232 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
1233 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
1234 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
1235 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
1236 /**
1237   * @}
1238   */
1239 
1240 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1241   * @ingroup RTEMSBSPsARMSTM32H7
1242   * @{
1243   */
1244 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
1245 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
1246 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
1247 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
1248 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
1249 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
1250 /**
1251   * @}
1252   */
1253 
1254 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1255   * @ingroup RTEMSBSPsARMSTM32H7
1256   * @{
1257   */
1258 #define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
1259 #define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
1260 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
1261 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
1262 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
1263 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
1264 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
1265 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
1266 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
1267 #define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
1268 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
1269 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
1270 #define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
1271 /**
1272   * @}
1273   */
1274 
1275 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1276   * @ingroup RTEMSBSPsARMSTM32H7
1277   * @{
1278   */
1279 #define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U
1280 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
1281 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
1282 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
1283 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
1284 #define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U
1285 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
1286 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
1287 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
1288 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
1289 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
1290 #define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
1291 #define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
1292 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
1293 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
1294 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
1295 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
1296 /**
1297   * @}
1298   */
1299 
1300 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1301   * @ingroup RTEMSBSPsARMSTM32H7
1302   * @{
1303   */
1304 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
1305 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
1306 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
1307 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
1308 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
1309 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
1310 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
1311 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
1312 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
1313 /**
1314   * @}
1315   */
1316 
1317 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1318   * @ingroup RTEMSBSPsARMSTM32H7
1319   * @{
1320   */
1321 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
1322 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
1323 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
1324 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
1325 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
1326 /**
1327   * @}
1328   */
1329 
1330 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
1331   * @ingroup RTEMSBSPsARMSTM32H7
1332   * @{
1333   */
1334 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
1335 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
1336 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
1337 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
1338 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
1339 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
1340 /**
1341   * @}
1342   */
1343 
1344 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1345   * @ingroup RTEMSBSPsARMSTM32H7
1346   * @{
1347   */
1348 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
1349 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
1350 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
1351 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
1352 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
1353 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
1354 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
1355 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
1356 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
1357 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
1358 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
1359 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
1360 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
1361 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
1362 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
1363 /**
1364   * @}
1365   */
1366 
1367 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1368   * @ingroup RTEMSBSPsARMSTM32H7
1369   * @{
1370   */
1371 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
1372 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
1373 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
1374 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
1375 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
1376 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
1377 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
1378 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
1379 /**
1380   * @}
1381   */
1382 
1383 /** @defgroup ETH_Speed  ETH Speed
1384   * @ingroup RTEMSBSPsARMSTM32H7
1385   * @{
1386   */
1387 #define ETH_SPEED_10M        0x00000000U
1388 #define ETH_SPEED_100M       ETH_MACCR_FES
1389 /**
1390   * @}
1391   */
1392 
1393 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1394   * @ingroup RTEMSBSPsARMSTM32H7
1395   * @{
1396   */
1397 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
1398 #define ETH_HALFDUPLEX_MODE       0x00000000U
1399 /**
1400   * @}
1401   */
1402 
1403 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1404   * @ingroup RTEMSBSPsARMSTM32H7
1405   * @{
1406   */
1407 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
1408 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
1409 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
1410 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
1411 /**
1412   * @}
1413   */
1414 
1415 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1416   * @ingroup RTEMSBSPsARMSTM32H7
1417   * @{
1418   */
1419 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
1420 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
1421 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
1422 /**
1423   * @}
1424   */
1425 
1426 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1427   * @ingroup RTEMSBSPsARMSTM32H7
1428   * @{
1429   */
1430 #define ETH_SOURCEADDRESS_DISABLE           0x00000000U
1431 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
1432 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
1433 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
1434 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
1435 /**
1436   * @}
1437   */
1438 
1439 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1440   * @ingroup RTEMSBSPsARMSTM32H7
1441   * @{
1442   */
1443 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
1444 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1445 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
1446 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1447 /**
1448   * @}
1449   */
1450 
1451 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1452   * @ingroup RTEMSBSPsARMSTM32H7
1453   * @{
1454   */
1455 #define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U
1456 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
1457 /**
1458   * @}
1459   */
1460 
1461 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1462   * @ingroup RTEMSBSPsARMSTM32H7
1463   * @{
1464   */
1465 #define ETH_MAC_ADDRESS0     0x00000000U
1466 #define ETH_MAC_ADDRESS1     0x00000008U
1467 #define ETH_MAC_ADDRESS2     0x00000010U
1468 #define ETH_MAC_ADDRESS3     0x00000018U
1469 /**
1470   * @}
1471   */
1472 
1473 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1474   * @ingroup RTEMSBSPsARMSTM32H7
1475   * @{
1476   */
1477 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
1478 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
1479 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
1480 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
1481 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
1482 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
1483 /**
1484   * @}
1485   */
1486 
1487 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1488   * @ingroup RTEMSBSPsARMSTM32H7
1489   * @{
1490   */
1491 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
1492 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
1493 /**
1494   * @}
1495   */
1496 
1497 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1498   * @ingroup RTEMSBSPsARMSTM32H7
1499   * @{
1500   */
1501 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
1502 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
1503 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
1504 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
1505 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
1506 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
1507 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
1508 /**
1509   * @}
1510   */
1511 
1512 /** @defgroup ETH_State_Codes ETH States
1513   * @ingroup RTEMSBSPsARMSTM32H7
1514   * @{
1515   */
1516 #define HAL_ETH_STATE_RESET                0x00000000U    /*!< Peripheral not yet Initialized or disabled */
1517 #define HAL_ETH_STATE_READY                0x00000010U    /*!< Peripheral Communication started           */
1518 #define HAL_ETH_STATE_BUSY                 0x00000023U    /*!< an internal process is ongoing             */
1519 #define HAL_ETH_STATE_STARTED              0x00000023U    /*!< an internal process is started             */
1520 #define HAL_ETH_STATE_ERROR                0x000000E0U    /*!< Error State                                */
1521 /**
1522   * @}
1523   */
1524 
1525 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
1526   * @ingroup RTEMSBSPsARMSTM32H7
1527   * @{
1528   */
1529 #define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
1530 #define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
1531 /**
1532   * @}
1533   */
1534 
1535 /**
1536   * @}
1537   */
1538 
1539 /* Exported macro ------------------------------------------------------------*/
1540 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1541   * @ingroup RTEMSBSPsARMSTM32H7
1542   * @{
1543   */
1544 
1545 /** @brief Reset ETH handle state
1546   * @param  __HANDLE__: specifies the ETH handle.
1547   * @retval None
1548   */
1549 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1550 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1551                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1552                                                       (__HANDLE__)->MspInitCallback = NULL;             \
1553                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
1554                                                     } while(0)
1555 #else
1556 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1557                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1558                                                     } while(0)
1559 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1560 
1561 /**
1562   * @brief  Enables the specified ETHERNET DMA interrupts.
1563   * @param  __HANDLE__   : ETH Handle
1564   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1565   *   enabled @ref ETH_DMA_Interrupts
1566   * @retval None
1567   */
1568 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1569 
1570 /**
1571   * @brief  Disables the specified ETHERNET DMA interrupts.
1572   * @param  __HANDLE__   : ETH Handle
1573   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1574   *   disabled. @ref ETH_DMA_Interrupts
1575   * @retval None
1576   */
1577 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1578 
1579 /**
1580   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
1581   * @param  __HANDLE__   : ETH Handle
1582   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1583   * @retval The ETH DMA IT Source enabled or disabled
1584   */
1585 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1586   (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
1587 
1588 /**
1589   * @brief  Gets the ETHERNET DMA IT pending bit.
1590   * @param  __HANDLE__   : ETH Handle
1591   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1592   * @retval The state of ETH DMA IT (SET or RESET)
1593   */
1594 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \
1595   (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
1596 
1597 /**
1598   * @brief  Clears the ETHERNET DMA IT pending bit.
1599   * @param  __HANDLE__   : ETH Handle
1600   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1601   * @retval None
1602   */
1603 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1604 
1605 /**
1606   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
1607   * @param  __HANDLE__: ETH Handle
1608   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1609   * @retval The state of ETH DMA FLAG (SET or RESET).
1610   */
1611 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1612 
1613 /**
1614   * @brief  Clears the specified ETHERNET DMA flag.
1615   * @param  __HANDLE__: ETH Handle
1616   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1617   * @retval The state of ETH DMA FLAG (SET or RESET).
1618   */
1619 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1620 
1621 /**
1622   * @brief  Enables the specified ETHERNET MAC interrupts.
1623   * @param  __HANDLE__   : ETH Handle
1624   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1625   *   enabled @ref ETH_MAC_Interrupts
1626   * @retval None
1627   */
1628 
1629 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1630 
1631 /**
1632   * @brief  Disables the specified ETHERNET MAC interrupts.
1633   * @param  __HANDLE__   : ETH Handle
1634   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1635   *   enabled @ref ETH_MAC_Interrupts
1636   * @retval None
1637   */
1638 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1639 
1640 /**
1641   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
1642   * @param  __HANDLE__: ETH Handle
1643   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1644   * @retval The state of ETH MAC IT (SET or RESET).
1645   */
1646 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\
1647                                                                               ( __INTERRUPT__)) == ( __INTERRUPT__))
1648 
1649 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
1650 #define ETH_WAKEUP_EXTI_LINE  0x00400000U  /* !<  86 - 64 = 22 */
1651 
1652 /**
1653   * @brief Enable the ETH WAKEUP Exti Line.
1654   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1655   *   @arg ETH_WAKEUP_EXTI_LINE
1656   * @retval None.
1657   */
1658 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1659 
1660 /**
1661   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1662   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1663   *   @arg ETH_WAKEUP_EXTI_LINE
1664   * @retval EXTI ETH WAKEUP Line Status.
1665   */
1666 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
1667 
1668 /**
1669   * @brief Clear the ETH WAKEUP Exti flag.
1670   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1671   *   @arg ETH_WAKEUP_EXTI_LINE
1672   * @retval None.
1673   */
1674 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
1675 
1676 #if defined(DUAL_CORE)
1677 /**
1678   * @brief Enable the ETH WAKEUP Exti Line by Core2.
1679   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1680   *   @arg ETH_WAKEUP_EXTI_LINE
1681   * @retval None.
1682   */
1683 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))
1684 
1685 /**
1686   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1687   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1688   *   @arg ETH_WAKEUP_EXTI_LINE
1689   * @retval EXTI ETH WAKEUP Line Status.
1690   */
1691 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))
1692 
1693 /**
1694   * @brief Clear the ETH WAKEUP Exti flag.
1695   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1696   *   @arg ETH_WAKEUP_EXTI_LINE
1697   * @retval None.
1698   */
1699 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
1700 #endif /* DUAL_CORE */
1701 
1702 /**
1703   * @brief  enable rising edge interrupt on selected EXTI line.
1704   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1705   *  @arg ETH_WAKEUP_EXTI_LINE
1706   * @retval None
1707   */
1708 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1709   (EXTI->RTSR3 |= (__EXTI_LINE__))
1710 
1711 /**
1712   * @brief  enable falling edge interrupt on selected EXTI line.
1713   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1714   *  @arg ETH_WAKEUP_EXTI_LINE
1715   * @retval None
1716   */
1717 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1718   (EXTI->FTSR3 |= (__EXTI_LINE__))
1719 
1720 /**
1721   * @brief  enable falling edge interrupt on selected EXTI line.
1722   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1723   *  @arg ETH_WAKEUP_EXTI_LINE
1724   * @retval None
1725   */
1726 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1727   (EXTI->FTSR3 |= (__EXTI_LINE__))
1728 
1729 /**
1730   * @brief  Generates a Software interrupt on selected EXTI line.
1731   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1732   *  @arg ETH_WAKEUP_EXTI_LINE
1733   * @retval None
1734   */
1735 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1736 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
1737                                                            (__FLAG__)) == (__FLAG__)) ? SET : RESET)
1738 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
1739 
1740 /**
1741   * @}
1742   */
1743 
1744 /* Include ETH HAL Extension module */
1745 #include "stm32h7xx_hal_eth_ex.h"
1746 
1747 /* Exported functions --------------------------------------------------------*/
1748 
1749 /** @addtogroup ETH_Exported_Functions
1750   * @{
1751   */
1752 
1753 /** @addtogroup ETH_Exported_Functions_Group1
1754   * @{
1755   */
1756 /* Initialization and de initialization functions  **********************************/
1757 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1758 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1759 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1760 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1761 
1762 /* Callbacks Register/UnRegister functions  ***********************************/
1763 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1764 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
1765                                            pETH_CallbackTypeDef pCallback);
1766 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1767 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1768 
1769 /**
1770   * @}
1771   */
1772 
1773 /** @addtogroup ETH_Exported_Functions_Group2
1774   * @{
1775   */
1776 /* IO operation functions *******************************************************/
1777 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1778 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1779 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1780 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1781 
1782 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
1783 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
1784                                                      pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
1785 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
1786 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
1787 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
1788 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
1789 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
1790 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
1791 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
1792 
1793 #ifdef HAL_ETH_USE_PTP
1794 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
1795 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
1796 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
1797 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
1798 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
1799                                             ETH_TimeTypeDef *timeoffset);
1800 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
1801 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
1802 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
1803 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
1804 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
1805 #endif /* HAL_ETH_USE_PTP */
1806 
1807 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
1808 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
1809 
1810 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
1811                                            uint32_t RegValue);
1812 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
1813                                           uint32_t *pRegValue);
1814 
1815 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1816 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1817 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1818 void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
1819 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1820 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1821 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1822 void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
1823 void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
1824 void              HAL_ETH_TxFreeCallback(uint32_t *buff);
1825 void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
1826 /**
1827   * @}
1828   */
1829 
1830 /** @addtogroup ETH_Exported_Functions_Group3
1831   * @{
1832   */
1833 /* Peripheral Control functions  **********************************************/
1834 /* MAC & DMA Configuration APIs  **********************************************/
1835 HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1836 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1837 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1838 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1839 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1840 
1841 /* MAC VLAN Processing APIs    ************************************************/
1842 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
1843                                               uint32_t VLANIdentifier);
1844 
1845 /* MAC L2 Packet Filtering APIs  **********************************************/
1846 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1847 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
1848 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1849 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
1850                                                 const uint8_t *pMACAddr);
1851 
1852 /* MAC Power Down APIs    *****************************************************/
1853 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
1854                                              const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1855 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1856 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1857 
1858 /**
1859   * @}
1860   */
1861 
1862 /** @addtogroup ETH_Exported_Functions_Group4
1863   * @{
1864   */
1865 /* Peripheral State functions  **************************************************/
1866 HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
1867 uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
1868 uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
1869 uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
1870 uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
1871 /**
1872   * @}
1873   */
1874 
1875 /**
1876   * @}
1877   */
1878 
1879 /**
1880   * @}
1881   */
1882 
1883 /**
1884   * @}
1885   */
1886 
1887 #endif /* ETH */
1888 
1889 #ifdef __cplusplus
1890 }
1891 #endif
1892 
1893 #endif /* STM32H7xx_HAL_ETH_H */
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