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0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_dma2d.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of DMA2D HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_DMA2D_H
0021 #define STM32H7xx_HAL_DMA2D_H
0022 
0023 #ifdef __cplusplus
0024 extern "C" {
0025 #endif
0026 
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029 
0030 /** @addtogroup STM32H7xx_HAL_Driver
0031   * @{
0032   */
0033 
0034 #if defined (DMA2D)
0035 
0036 /** @addtogroup DMA2D DMA2D
0037   * @brief DMA2D HAL module driver
0038   * @{
0039   */
0040 
0041 /* Exported types ------------------------------------------------------------*/
0042 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
0043   * @ingroup RTEMSBSPsARMSTM32H7
0044   * @{
0045   */
0046 #define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */
0047 
0048 /**
0049   * @brief DMA2D CLUT Structure definition
0050   */
0051 typedef struct
0052 {
0053   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
0054 
0055   uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
0056                                          This parameter can be one value of @ref DMA2D_CLUT_CM. */
0057 
0058   uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
0059                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
0060 } DMA2D_CLUTCfgTypeDef;
0061 
0062 /**
0063   * @brief DMA2D Init structure definition
0064   */
0065 typedef struct
0066 {
0067   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
0068                                                 This parameter can be one value of @ref DMA2D_Mode. */
0069 
0070   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
0071                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
0072 
0073   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
0074                                                 This parameter must be a number between
0075                                                 Min_Data = 0x0000 and Max_Data = 0x3FFF. */
0076   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
0077                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
0078 
0079   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
0080                                                for the output pixel format converter.
0081                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
0082 
0083 
0084   uint32_t             BytesSwap;         /*!< Select byte regular mode or bytes swap mode (two by two).
0085                                                This parameter can be one value of @ref DMA2D_Bytes_Swap. */
0086 
0087   uint32_t             LineOffsetMode;    /*!< Configures how is expressed the line offset for the foreground, background and output.
0088                                                This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
0089 
0090 } DMA2D_InitTypeDef;
0091 
0092 
0093 /**
0094   * @brief DMA2D Layer structure definition
0095   */
0096 typedef struct
0097 {
0098   uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
0099                                                This parameter must be a number between
0100                                                Min_Data = 0x0000 and Max_Data = 0x3FFF. */
0101 
0102   uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
0103                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
0104 
0105   uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
0106                                                This parameter can be one value of @ref DMA2D_Alpha_Mode. */
0107 
0108   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value
0109                                                in case of A8 or A4 color mode.
0110                                                This parameter must be a number between Min_Data = 0x00
0111                                                and Max_Data = 0xFF except for the color modes detailed below.
0112                                                @note In case of A8 or A4 color mode (ARGB),
0113                                                this parameter must be a number between
0114                                                Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
0115                                                - InputAlpha[24:31] is the alpha value ALPHA[0:7]
0116                                                - InputAlpha[16:23] is the red value RED[0:7]
0117                                                - InputAlpha[8:15] is the green value GREEN[0:7]
0118                                                - InputAlpha[0:7] is the blue value BLUE[0:7]. */
0119   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
0120                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
0121 
0122   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
0123                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
0124 
0125   uint32_t             ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
0126                                                This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
0127 
0128 } DMA2D_LayerCfgTypeDef;
0129 
0130 /**
0131   * @brief  HAL DMA2D State structures definition
0132   */
0133 typedef enum
0134 {
0135   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
0136   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
0137   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
0138   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
0139   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
0140   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
0141 } HAL_DMA2D_StateTypeDef;
0142 
0143 /**
0144   * @brief  DMA2D handle Structure definition
0145   */
0146 typedef struct __DMA2D_HandleTypeDef
0147 {
0148   DMA2D_TypeDef               *Instance;                                  /*!< DMA2D register base address.           */
0149 
0150   DMA2D_InitTypeDef           Init;                                       /*!< DMA2D communication parameters.        */
0151 
0152   void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);        /*!< DMA2D transfer complete callback.      */
0153 
0154   void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D transfer error callback.         */
0155 
0156 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0157   void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D line event callback.             */
0158 
0159   void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */
0160 
0161   void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);         /*!< DMA2D Msp Init callback.               */
0162 
0163   void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);       /*!< DMA2D Msp DeInit callback.             */
0164 
0165 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
0166 
0167   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                  /*!< DMA2D Layers parameters                */
0168 
0169   HAL_LockTypeDef             Lock;                                       /*!< DMA2D lock.                            */
0170 
0171   __IO HAL_DMA2D_StateTypeDef State;                                      /*!< DMA2D transfer state.                  */
0172 
0173   __IO uint32_t               ErrorCode;                                  /*!< DMA2D error code.                      */
0174 } DMA2D_HandleTypeDef;
0175 
0176 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0177 /**
0178   * @brief  HAL DMA2D Callback pointer definition
0179   */
0180 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */
0181 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
0182 /**
0183   * @}
0184   */
0185 
0186 /* Exported constants --------------------------------------------------------*/
0187 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
0188   * @ingroup RTEMSBSPsARMSTM32H7
0189   * @{
0190   */
0191 
0192 /** @defgroup DMA2D_Error_Code DMA2D Error Code
0193   * @ingroup RTEMSBSPsARMSTM32H7
0194   * @{
0195   */
0196 #define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */
0197 #define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */
0198 #define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */
0199 #define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */
0200 #define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */
0201 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0202 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */
0203 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
0204 
0205 /**
0206   * @}
0207   */
0208 
0209 /** @defgroup DMA2D_Mode DMA2D Mode
0210   * @ingroup RTEMSBSPsARMSTM32H7
0211   * @{
0212   */
0213 #define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
0214 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
0215 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
0216 #define DMA2D_R2M                   (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
0217 #define DMA2D_M2M_BLEND_FG          DMA2D_CR_MODE_2                     /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
0218 #define DMA2D_M2M_BLEND_BG          (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
0219 /**
0220   * @}
0221   */
0222 
0223 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
0224   * @ingroup RTEMSBSPsARMSTM32H7
0225   * @{
0226   */
0227 #define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */
0228 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
0229 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
0230 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
0231 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
0232 /**
0233   * @}
0234   */
0235 
0236 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
0237   * @ingroup RTEMSBSPsARMSTM32H7
0238   * @{
0239   */
0240 #define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */
0241 #define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */
0242 #define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */
0243 #define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */
0244 #define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */
0245 #define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */
0246 #define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */
0247 #define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */
0248 #define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */
0249 #define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */
0250 #define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */
0251 #define DMA2D_INPUT_YCBCR           0x0000000BU  /*!< YCbCr color mode */
0252 /**
0253   * @}
0254   */
0255 
0256 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
0257   * @ingroup RTEMSBSPsARMSTM32H7
0258   * @{
0259   */
0260 #define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value                     */
0261 #define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */
0262 #define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value
0263                                                       with original alpha channel value                              */
0264 /**
0265   * @}
0266   */
0267 
0268 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion
0269   * @ingroup RTEMSBSPsARMSTM32H7
0270   * @{
0271   */
0272 #define DMA2D_REGULAR_ALPHA         0x00000000U  /*!< No modification of the alpha channel value */
0273 #define DMA2D_INVERTED_ALPHA        0x00000001U  /*!< Invert the alpha channel value */
0274 /**
0275   * @}
0276   */
0277 
0278 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
0279   * @ingroup RTEMSBSPsARMSTM32H7
0280   * @{
0281   */
0282 #define DMA2D_RB_REGULAR            0x00000000U  /*!< Select regular mode (RGB or ARGB) */
0283 #define DMA2D_RB_SWAP               0x00000001U  /*!< Select swap mode (BGR or ABGR) */
0284 /**
0285   * @}
0286   */
0287 
0288 
0289 
0290 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
0291   * @ingroup RTEMSBSPsARMSTM32H7
0292   * @{
0293   */
0294 #define DMA2D_LOM_PIXELS            0x00000000U   /*!< Line offsets expressed in pixels */
0295 #define DMA2D_LOM_BYTES             DMA2D_CR_LOM  /*!< Line offsets expressed in bytes */
0296 /**
0297   * @}
0298   */
0299 
0300 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
0301   * @ingroup RTEMSBSPsARMSTM32H7
0302   * @{
0303   */
0304 #define DMA2D_BYTES_REGULAR         0x00000000U      /*!< Bytes in regular order in output FIFO */
0305 #define DMA2D_BYTES_SWAP            DMA2D_OPFCCR_SB  /*!< Bytes are swapped two by two in output FIFO */
0306 /**
0307   * @}
0308   */
0309 
0310 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
0311   * @ingroup RTEMSBSPsARMSTM32H7
0312   * @{
0313   */
0314 #define DMA2D_NO_CSS               0x00000000U  /*!< No chroma sub-sampling 4:4:4 */
0315 #define DMA2D_CSS_422              0x00000001U  /*!< chroma sub-sampling 4:2:2 */
0316 #define DMA2D_CSS_420              0x00000002U  /*!< chroma sub-sampling 4:2:0 */
0317 /**
0318   * @}
0319   */
0320 
0321 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
0322   * @ingroup RTEMSBSPsARMSTM32H7
0323   * @{
0324   */
0325 #define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */
0326 #define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */
0327 /**
0328   * @}
0329   */
0330 
0331 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
0332   * @ingroup RTEMSBSPsARMSTM32H7
0333   * @{
0334   */
0335 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
0336 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
0337 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
0338 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
0339 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
0340 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
0341 /**
0342   * @}
0343   */
0344 
0345 /** @defgroup DMA2D_Flags DMA2D Flags
0346   * @ingroup RTEMSBSPsARMSTM32H7
0347   * @{
0348   */
0349 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
0350 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
0351 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
0352 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
0353 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
0354 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
0355 /**
0356   * @}
0357   */
0358 
0359 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0360 /**
0361   * @brief  HAL DMA2D common Callback ID enumeration definition
0362   */
0363 typedef enum
0364 {
0365   HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */
0366   HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */
0367   HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */
0368   HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */
0369   HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */
0370   HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */
0371 } HAL_DMA2D_CallbackIDTypeDef;
0372 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
0373 
0374 
0375 /**
0376   * @}
0377   */
0378 /* Exported macros ------------------------------------------------------------*/
0379 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
0380   * @ingroup RTEMSBSPsARMSTM32H7
0381   * @{
0382   */
0383 
0384 /** @brief Reset DMA2D handle state
0385   * @param  __HANDLE__ specifies the DMA2D handle.
0386   * @retval None
0387   */
0388 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0389 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
0390                                                        (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
0391                                                        (__HANDLE__)->MspInitCallback = NULL;       \
0392                                                        (__HANDLE__)->MspDeInitCallback = NULL;     \
0393                                                      }while(0)
0394 #else
0395 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
0396 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
0397 
0398 
0399 /**
0400   * @brief  Enable the DMA2D.
0401   * @param  __HANDLE__ DMA2D handle
0402   * @retval None.
0403   */
0404 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
0405 
0406 
0407 /* Interrupt & Flag management */
0408 /**
0409   * @brief  Get the DMA2D pending flags.
0410   * @param  __HANDLE__ DMA2D handle
0411   * @param  __FLAG__ flag to check.
0412   *          This parameter can be any combination of the following values:
0413   *            @arg DMA2D_FLAG_CE:  Configuration error flag
0414   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
0415   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
0416   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
0417   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
0418   *            @arg DMA2D_FLAG_TE:  Transfer error flag
0419   * @retval The state of FLAG.
0420   */
0421 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
0422 
0423 /**
0424   * @brief  Clear the DMA2D pending flags.
0425   * @param  __HANDLE__ DMA2D handle
0426   * @param  __FLAG__ specifies the flag to clear.
0427   *          This parameter can be any combination of the following values:
0428   *            @arg DMA2D_FLAG_CE:  Configuration error flag
0429   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
0430   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
0431   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
0432   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
0433   *            @arg DMA2D_FLAG_TE:  Transfer error flag
0434   * @retval None
0435   */
0436 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
0437 
0438 /**
0439   * @brief  Enable the specified DMA2D interrupts.
0440   * @param  __HANDLE__ DMA2D handle
0441   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.
0442   *          This parameter can be any combination of the following values:
0443   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
0444   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
0445   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
0446   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
0447   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
0448   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
0449   * @retval None
0450   */
0451 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
0452 
0453 /**
0454   * @brief  Disable the specified DMA2D interrupts.
0455   * @param  __HANDLE__ DMA2D handle
0456   * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.
0457   *          This parameter can be any combination of the following values:
0458   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
0459   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
0460   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
0461   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
0462   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
0463   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
0464   * @retval None
0465   */
0466 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
0467 
0468 /**
0469   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
0470   * @param  __HANDLE__ DMA2D handle
0471   * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.
0472   *          This parameter can be one of the following values:
0473   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
0474   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
0475   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
0476   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
0477   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
0478   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
0479   * @retval The state of INTERRUPT source.
0480   */
0481 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
0482 
0483 /**
0484   * @}
0485   */
0486 
0487 /* Exported functions --------------------------------------------------------*/
0488 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
0489   * @{
0490   */
0491 
0492 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
0493   * @{
0494   */
0495 
0496 /* Initialization and de-initialization functions *******************************/
0497 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
0498 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
0499 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
0500 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
0501 /* Callbacks Register/UnRegister functions  ***********************************/
0502 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
0503 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
0504                                              pDMA2D_CallbackTypeDef pCallback);
0505 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
0506 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
0507 
0508 /**
0509   * @}
0510   */
0511 
0512 
0513 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
0514   * @{
0515   */
0516 
0517 /* IO operation functions *******************************************************/
0518 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
0519                                   uint32_t Height);
0520 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
0521                                           uint32_t DstAddress, uint32_t Width,  uint32_t Height);
0522 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
0523                                      uint32_t Height);
0524 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
0525                                              uint32_t DstAddress, uint32_t Width, uint32_t Height);
0526 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
0527 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
0528 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
0529 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
0530 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
0531                                           uint32_t LayerIdx);
0532 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
0533                                              uint32_t LayerIdx);
0534 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
0535 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
0536 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
0537 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
0538 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
0539 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
0540 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
0541 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
0542 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
0543 
0544 /**
0545   * @}
0546   */
0547 
0548 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
0549   * @{
0550   */
0551 
0552 /* Peripheral Control functions *************************************************/
0553 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
0554 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
0555 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
0556 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
0557 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
0558 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
0559 
0560 /**
0561   * @}
0562   */
0563 
0564 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
0565   * @{
0566   */
0567 
0568 /* Peripheral State functions ***************************************************/
0569 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
0570 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
0571 
0572 /**
0573   * @}
0574   */
0575 
0576 /**
0577   * @}
0578   */
0579 
0580 /* Private constants ---------------------------------------------------------*/
0581 
0582 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
0583   * @{
0584   */
0585 
0586 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
0587   * @ingroup RTEMSBSPsARMSTM32H7
0588   * @{
0589   */
0590 #define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
0591 /**
0592   * @}
0593   */
0594 
0595 /** @defgroup DMA2D_Color_Value DMA2D Color Value
0596   * @ingroup RTEMSBSPsARMSTM32H7
0597   * @{
0598   */
0599 #define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */
0600 /**
0601   * @}
0602   */
0603 
0604 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
0605   * @ingroup RTEMSBSPsARMSTM32H7
0606   * @{
0607   */
0608 #define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */
0609 /**
0610   * @}
0611   */
0612 
0613 /** @defgroup DMA2D_Layers DMA2D Layers
0614   * @ingroup RTEMSBSPsARMSTM32H7
0615   * @{
0616   */
0617 #define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */
0618 #define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */
0619 /**
0620   * @}
0621   */
0622 
0623 /** @defgroup DMA2D_Offset DMA2D Offset
0624   * @ingroup RTEMSBSPsARMSTM32H7
0625   * @{
0626   */
0627 #define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */
0628 /**
0629   * @}
0630   */
0631 
0632 /** @defgroup DMA2D_Size DMA2D Size
0633   * @ingroup RTEMSBSPsARMSTM32H7
0634   * @{
0635   */
0636 #define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */
0637 #define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */
0638 /**
0639   * @}
0640   */
0641 
0642 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
0643   * @ingroup RTEMSBSPsARMSTM32H7
0644   * @{
0645   */
0646 #define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */
0647 /**
0648   * @}
0649   */
0650 
0651 /**
0652   * @}
0653   */
0654 
0655 
0656 /* Private macros ------------------------------------------------------------*/
0657 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
0658   * @ingroup RTEMSBSPsARMSTM32H7
0659   * @{
0660   */
0661 #define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER)\
0662                                                || ((LAYER) == DMA2D_FOREGROUND_LAYER))
0663 
0664 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)          || ((MODE) == DMA2D_M2M_PFC) || \
0665                                                ((MODE) == DMA2D_M2M_BLEND)    || ((MODE) == DMA2D_R2M)     || \
0666                                                ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
0667 
0668 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
0669                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
0670                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || \
0671                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
0672                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
0673 
0674 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
0675 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
0676 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
0677 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
0678 
0679 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
0680                                                ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
0681                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || \
0682                                                ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
0683                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
0684                                                ((INPUT_CM) == DMA2D_INPUT_L8)       || \
0685                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || \
0686                                                ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
0687                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || \
0688                                                ((INPUT_CM) == DMA2D_INPUT_A8)       || \
0689                                                ((INPUT_CM) == DMA2D_INPUT_A4)       || \
0690                                                ((INPUT_CM) == DMA2D_INPUT_YCBCR))
0691 
0692 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
0693                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
0694                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
0695 
0696 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
0697                                                  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
0698 
0699 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
0700                                    ((RB_Swap) == DMA2D_RB_SWAP))
0701 
0702 #define IS_DMA2D_LOM_MODE(LOM)          (((LOM) == DMA2D_LOM_PIXELS) || \
0703                                          ((LOM) == DMA2D_LOM_BYTES))
0704 
0705 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
0706                                          ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
0707 
0708 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS)  || \
0709                                            ((CSS) == DMA2D_CSS_422) || \
0710                                            ((CSS) == DMA2D_CSS_420))
0711 
0712 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
0713 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
0714 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
0715 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
0716                                                ((IT) == DMA2D_IT_TW)  || ((IT) == DMA2D_IT_TC)  || \
0717                                                ((IT) == DMA2D_IT_TE)  || ((IT) == DMA2D_IT_CE))
0718 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
0719                                                ((FLAG) == DMA2D_FLAG_TW)  || ((FLAG) == DMA2D_FLAG_TC)  || \
0720                                                ((FLAG) == DMA2D_FLAG_TE)  || ((FLAG) == DMA2D_FLAG_CE))
0721 /**
0722   * @}
0723   */
0724 
0725 /**
0726   * @}
0727   */
0728 
0729 #endif /* defined (DMA2D) */
0730 
0731 /**
0732   * @}
0733   */
0734 
0735 #ifdef __cplusplus
0736 }
0737 #endif
0738 
0739 #endif /* STM32H7xx_HAL_DMA2D_H */
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