stm32h7/include/stm32h7xx_hal_cortex.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_cortex.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of CORTEX HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file in
0013   * the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_CORTEX_H
0021 #define STM32H7xx_HAL_CORTEX_H
0022
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif
0026
0027 /* Includes ------------------------------------------------------------------*/
0028 #include "stm32h7xx_hal_def.h"
0029
0030 /** @addtogroup STM32H7xx_HAL_Driver
0031   * @{
0032   */
0033
0034 /** @addtogroup CORTEX
0035   * @{
0036   */
0037 /* Exported types ------------------------------------------------------------*/
0038 /** @defgroup CORTEX_Exported_Types Cortex Exported Types
0039   * @ingroup RTEMSBSPsARMSTM32H7
0040   * @{
0041   */
0042
0043 #if (__MPU_PRESENT == 1)
0044 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
0045   * @ingroup RTEMSBSPsARMSTM32H7
0046   * @brief  MPU Region initialization structure
0047   * @{
0048   */
0049 typedef struct
0050 {
0051   uint8_t                Enable;                /*!< Specifies the status of the region.
0052                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
0053   uint8_t                Number;                /*!< Specifies the number of the region to protect.
0054                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
0055   uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
0056   uint8_t                Size;                  /*!< Specifies the size of the region to protect.
0057                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
0058   uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
0059                                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
0060   uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
0061                                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
0062   uint8_t                AccessPermission;      /*!< Specifies the region access permission type.
0063                                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
0064   uint8_t                DisableExec;           /*!< Specifies the instruction access status.
0065                                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
0066   uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.
0067                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
0068   uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.
0069                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
0070   uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.
0071                                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
0072 }MPU_Region_InitTypeDef;
0073 /**
0074   * @}
0075   */
0076 #endif /* __MPU_PRESENT */
0077
0078 /**
0079   * @}
0080   */
0081
0082 /* Exported constants --------------------------------------------------------*/
0083
0084 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
0085   * @ingroup RTEMSBSPsARMSTM32H7
0086   * @{
0087   */
0088
0089 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
0090   * @ingroup RTEMSBSPsARMSTM32H7
0091   * @{
0092   */
0093 #define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
0094                                                                  4 bits for subpriority */
0095 #define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
0096                                                                  3 bits for subpriority */
0097 #define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
0098                                                                  2 bits for subpriority */
0099 #define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
0100                                                                  1 bits for subpriority */
0101 #define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
0102                                                                  0 bits for subpriority */
0103 /**
0104   * @}
0105   */
0106
0107 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
0108   * @ingroup RTEMSBSPsARMSTM32H7
0109   * @{
0110   */
0111 #define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
0112 #define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
0113
0114 /**
0115   * @}
0116   */
0117
0118 #if (__MPU_PRESENT == 1)
0119 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
0120   * @ingroup RTEMSBSPsARMSTM32H7
0121   * @{
0122   */
0123 #define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
0124 #define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
0125 #define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
0126 #define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
0127 /**
0128   * @}
0129   */
0130
0131 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
0132   * @ingroup RTEMSBSPsARMSTM32H7
0133   * @{
0134   */
0135 #define  MPU_REGION_ENABLE     ((uint8_t)0x01)
0136 #define  MPU_REGION_DISABLE    ((uint8_t)0x00)
0137 /**
0138   * @}
0139   */
0140
0141 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
0142   * @ingroup RTEMSBSPsARMSTM32H7
0143   * @{
0144   */
0145 #define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
0146 #define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
0147 /**
0148   * @}
0149   */
0150
0151 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
0152   * @ingroup RTEMSBSPsARMSTM32H7
0153   * @{
0154   */
0155 #define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
0156 #define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
0157 /**
0158   * @}
0159   */
0160
0161 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
0162   * @ingroup RTEMSBSPsARMSTM32H7
0163   * @{
0164   */
0165 #define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
0166 #define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
0167 /**
0168   * @}
0169   */
0170
0171 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
0172   * @ingroup RTEMSBSPsARMSTM32H7
0173   * @{
0174   */
0175 #define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
0176 #define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
0177 /**
0178   * @}
0179   */
0180
0181 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
0182   * @ingroup RTEMSBSPsARMSTM32H7
0183   * @{
0184   */
0185 #define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
0186 #define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
0187 #define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
0188 /**
0189   * @}
0190   */
0191
0192 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
0193   * @ingroup RTEMSBSPsARMSTM32H7
0194   * @{
0195   */
0196 #define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
0197 #define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
0198 #define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
0199 #define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
0200 #define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
0201 #define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
0202 #define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
0203 #define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
0204 #define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
0205 #define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
0206 #define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
0207 #define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
0208 #define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
0209 #define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
0210 #define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
0211 #define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
0212 #define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
0213 #define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
0214 #define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
0215 #define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
0216 #define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
0217 #define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
0218 #define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
0219 #define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
0220 #define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
0221 #define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
0222 #define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
0223 #define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
0224 /**
0225   * @}
0226   */
0227
0228 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
0229   * @ingroup RTEMSBSPsARMSTM32H7
0230   * @{
0231   */
0232 #define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
0233 #define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
0234 #define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
0235 #define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
0236 #define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
0237 #define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
0238 /**
0239   * @}
0240   */
0241
0242 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
0243   * @ingroup RTEMSBSPsARMSTM32H7
0244   * @{
0245   */
0246 #define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
0247 #define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
0248 #define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
0249 #define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
0250 #define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
0251 #define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
0252 #define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
0253 #define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
0254 #if !defined(CORE_CM4)
0255 #define  MPU_REGION_NUMBER8    ((uint8_t)0x08)
0256 #define  MPU_REGION_NUMBER9    ((uint8_t)0x09)
0257 #define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)
0258 #define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)
0259 #define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)
0260 #define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)
0261 #define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)
0262 #define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)
0263 #endif /* !defined(CORE_CM4) */
0264
0265 /**
0266   * @}
0267   */
0268 #endif /* __MPU_PRESENT */
0269
0270 /**
0271   * @}
0272   */
0273
0274
0275 /* Exported Macros -----------------------------------------------------------*/
0276 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
0277   * @ingroup RTEMSBSPsARMSTM32H7
0278   * @{
0279   */
0280
0281 /**
0282   * @}
0283   */
0284
0285
0286
0287 /** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
0288   * @ingroup RTEMSBSPsARMSTM32H7
0289   * @{
0290   */
0291 #define CM7_CPUID        ((uint32_t)0x00000003)
0292
0293 #if defined(DUAL_CORE)
0294 #define CM4_CPUID        ((uint32_t)0x00000001)
0295 #endif /*DUAL_CORE*/
0296 /**
0297   * @}
0298   */
0299
0300
0301 /* Exported functions --------------------------------------------------------*/
0302 /** @addtogroup CORTEX_Exported_Functions
0303   * @{
0304   */
0305
0306 /** @addtogroup CORTEX_Exported_Functions_Group1
0307  * @{
0308  */
0309 /* Initialization and de-initialization functions *****************************/
0310 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
0311 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
0312 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
0313 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
0314 void HAL_NVIC_SystemReset(void);
0315 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
0316 /**
0317   * @}
0318   */
0319
0320 /** @addtogroup CORTEX_Exported_Functions_Group2
0321  * @{
0322  */
0323 /* Peripheral Control functions ***********************************************/
0324 #if (__MPU_PRESENT == 1)
0325 void HAL_MPU_Enable(uint32_t MPU_Control);
0326 void HAL_MPU_Disable(void);
0327 void HAL_MPU_EnableRegion(uint32_t RegionNumber);
0328 void HAL_MPU_DisableRegion(uint32_t RegionNumber);
0329 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
0330 #endif /* __MPU_PRESENT */
0331 uint32_t HAL_NVIC_GetPriorityGrouping(void);
0332 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
0333 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
0334 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
0335 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
0336 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
0337 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
0338 void HAL_SYSTICK_IRQHandler(void);
0339 void HAL_SYSTICK_Callback(void);
0340 uint32_t HAL_GetCurrentCPUID(void);
0341
0342
0343 /**
0344   * @}
0345   */
0346
0347 /**
0348   * @}
0349   */
0350
0351 /* Private types -------------------------------------------------------------*/
0352 /* Private variables ---------------------------------------------------------*/
0353 /* Private constants ---------------------------------------------------------*/
0354 /* Private macros ------------------------------------------------------------*/
0355 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros
0356   * @ingroup RTEMSBSPsARMSTM32H7
0357   * @{
0358   */
0359 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
0360                                        ((GROUP) == NVIC_PRIORITYGROUP_1) || \
0361                                        ((GROUP) == NVIC_PRIORITYGROUP_2) || \
0362                                        ((GROUP) == NVIC_PRIORITYGROUP_3) || \
0363                                        ((GROUP) == NVIC_PRIORITYGROUP_4))
0364
0365 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)
0366
0367 #define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)
0368
0369 #define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)
0370
0371 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
0372                                        ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
0373
0374 #if (__MPU_PRESENT == 1)
0375 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
0376                                      ((STATE) == MPU_REGION_DISABLE))
0377
0378 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
0379                                           ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
0380
0381 #define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
0382                                           ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
0383
0384 #define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
0385                                           ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
0386
0387 #define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
0388                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
0389
0390 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
0391                                 ((TYPE) == MPU_TEX_LEVEL1)  || \
0392                                 ((TYPE) == MPU_TEX_LEVEL2))
0393
0394 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
0395                                                   ((TYPE) == MPU_REGION_PRIV_RW)     || \
0396                                                   ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
0397                                                   ((TYPE) == MPU_REGION_FULL_ACCESS) || \
0398                                                   ((TYPE) == MPU_REGION_PRIV_RO)     || \
0399                                                   ((TYPE) == MPU_REGION_PRIV_RO_URO))
0400
0401 #if !defined(CORE_CM4)
0402 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
0403                                          ((NUMBER) == MPU_REGION_NUMBER1)  || \
0404                                          ((NUMBER) == MPU_REGION_NUMBER2)  || \
0405                                          ((NUMBER) == MPU_REGION_NUMBER3)  || \
0406                                          ((NUMBER) == MPU_REGION_NUMBER4)  || \
0407                                          ((NUMBER) == MPU_REGION_NUMBER5)  || \
0408                                          ((NUMBER) == MPU_REGION_NUMBER6)  || \
0409                                          ((NUMBER) == MPU_REGION_NUMBER7)  || \
0410                                          ((NUMBER) == MPU_REGION_NUMBER8)  || \
0411                                          ((NUMBER) == MPU_REGION_NUMBER9)  || \
0412                                          ((NUMBER) == MPU_REGION_NUMBER10) || \
0413                                          ((NUMBER) == MPU_REGION_NUMBER11) || \
0414                                          ((NUMBER) == MPU_REGION_NUMBER12) || \
0415                                          ((NUMBER) == MPU_REGION_NUMBER13) || \
0416                                          ((NUMBER) == MPU_REGION_NUMBER14) || \
0417                                          ((NUMBER) == MPU_REGION_NUMBER15))
0418 #else
0419 #define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \
0420                                          ((NUMBER) == MPU_REGION_NUMBER1)  || \
0421                                          ((NUMBER) == MPU_REGION_NUMBER2)  || \
0422                                          ((NUMBER) == MPU_REGION_NUMBER3)  || \
0423                                          ((NUMBER) == MPU_REGION_NUMBER4)  || \
0424                                          ((NUMBER) == MPU_REGION_NUMBER5)  || \
0425                                          ((NUMBER) == MPU_REGION_NUMBER6)  || \
0426                                          ((NUMBER) == MPU_REGION_NUMBER7))
0427 #endif /* !defined(CORE_CM4) */
0428
0429 #define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
0430                                      ((SIZE) == MPU_REGION_SIZE_64B)   || \
0431                                      ((SIZE) == MPU_REGION_SIZE_128B)  || \
0432                                      ((SIZE) == MPU_REGION_SIZE_256B)  || \
0433                                      ((SIZE) == MPU_REGION_SIZE_512B)  || \
0434                                      ((SIZE) == MPU_REGION_SIZE_1KB)   || \
0435                                      ((SIZE) == MPU_REGION_SIZE_2KB)   || \
0436                                      ((SIZE) == MPU_REGION_SIZE_4KB)   || \
0437                                      ((SIZE) == MPU_REGION_SIZE_8KB)   || \
0438                                      ((SIZE) == MPU_REGION_SIZE_16KB)  || \
0439                                      ((SIZE) == MPU_REGION_SIZE_32KB)  || \
0440                                      ((SIZE) == MPU_REGION_SIZE_64KB)  || \
0441                                      ((SIZE) == MPU_REGION_SIZE_128KB) || \
0442                                      ((SIZE) == MPU_REGION_SIZE_256KB) || \
0443                                      ((SIZE) == MPU_REGION_SIZE_512KB) || \
0444                                      ((SIZE) == MPU_REGION_SIZE_1MB)   || \
0445                                      ((SIZE) == MPU_REGION_SIZE_2MB)   || \
0446                                      ((SIZE) == MPU_REGION_SIZE_4MB)   || \
0447                                      ((SIZE) == MPU_REGION_SIZE_8MB)   || \
0448                                      ((SIZE) == MPU_REGION_SIZE_16MB)  || \
0449                                      ((SIZE) == MPU_REGION_SIZE_32MB)  || \
0450                                      ((SIZE) == MPU_REGION_SIZE_64MB)  || \
0451                                      ((SIZE) == MPU_REGION_SIZE_128MB) || \
0452                                      ((SIZE) == MPU_REGION_SIZE_256MB) || \
0453                                      ((SIZE) == MPU_REGION_SIZE_512MB) || \
0454                                      ((SIZE) == MPU_REGION_SIZE_1GB)   || \
0455                                      ((SIZE) == MPU_REGION_SIZE_2GB)   || \
0456                                      ((SIZE) == MPU_REGION_SIZE_4GB))
0457
0458 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
0459 #endif /* __MPU_PRESENT */
0460
0461 /**
0462   * @}
0463   */
0464
0465 /**
0466   * @}
0467   */
0468
0469 /**
0470   * @}
0471   */
0472
0473 #ifdef __cplusplus
0474 }
0475 #endif
0476
0477 #endif /* STM32H7xx_HAL_CORTEX_H */
0478
0479