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File indexing completed on 2025-05-11 08:23:35
0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_hal_cec.h 0004 * @author MCD Application Team 0005 * @brief Header file of CEC HAL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_HAL_CEC_H 0021 #define STM32H7xx_HAL_CEC_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx_hal_def.h" 0029 0030 #if defined (CEC) 0031 0032 /** @addtogroup STM32H7xx_HAL_Driver 0033 * @{ 0034 */ 0035 0036 /** @addtogroup CEC 0037 * @{ 0038 */ 0039 0040 /* Exported types ------------------------------------------------------------*/ 0041 /** @defgroup CEC_Exported_Types CEC Exported Types 0042 * @ingroup RTEMSBSPsARMSTM32H7 0043 * @{ 0044 */ 0045 0046 /** 0047 * @brief CEC Init Structure definition 0048 */ 0049 typedef struct 0050 { 0051 uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. 0052 It can be one of CEC_Signal_Free_Time 0053 and belongs to the set {0,...,7} where 0054 0x0 is the default configuration 0055 else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ 0056 0057 uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, 0058 it can be a value of CEC_Tolerance : 0059 it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ 0060 0061 uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising 0062 Error stops the reception. 0063 CEC_NO_RX_STOP_ON_BRE: reception is not stopped. 0064 CEC_RX_STOP_ON_BRE: reception is stopped. */ 0065 0066 uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an 0067 Error-Bit is generated on the 0068 CEC line upon Bit Rising Error detection. 0069 CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. 0070 CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ 0071 0072 uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an 0073 Error-Bit is generated on the 0074 CEC line upon Long Bit Period Error detection. 0075 CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. 0076 CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ 0077 0078 uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an 0079 Error-Bit generation on the CEC line 0080 upon an error detected on a broadcast message. 0081 0082 It supersedes BREGEN and LBPEGEN bits for a broadcast message error 0083 handling. It can take two values: 0084 0085 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. 0086 a) BRE detection: error-bit generation on the CEC line if 0087 BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. 0088 b) LBPE detection: error-bit generation on the CEC line 0089 if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 0090 0091 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. 0092 no error-bit generation in case neither a) nor b) are satisfied. 0093 Additionally, there is no error-bit generation in case of Short Bit 0094 Period Error detection in a broadcast message while LSTN bit is set. */ 0095 0096 uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. 0097 CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. 0098 CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end 0099 of message transmission/reception. */ 0100 0101 uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. 0102 It can take two values: 0103 0104 CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed 0105 to its own address (OAR). Messages addressed to different destination 0106 are ignored. 0107 Broadcast messages are always received. 0108 0109 CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its 0110 own address (OAR) with positive acknowledge. Messages addressed to 0111 different destination are received, but without interfering with the 0112 CEC bus: no acknowledge sent. */ 0113 0114 uint16_t OwnAddress; /*!< Own addresses configuration 0115 This parameter can be a value of CEC_OWN_ADDRESS */ 0116 0117 uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ 0118 0119 0120 } CEC_InitTypeDef; 0121 0122 /** 0123 * @brief HAL CEC State definition 0124 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState 0125 (see CEC_State_Definition). 0126 * - gState contains CEC state information related to global Handle management 0127 * and also information related to Tx operations. 0128 * gState value coding follow below described bitmap : 0129 * b7 (not used) 0130 * x : Should be set to 0 0131 * b6 Error information 0132 * 0 : No Error 0133 * 1 : Error 0134 * b5 CEC peripheral initialization status 0135 * 0 : Reset (peripheral not initialized) 0136 * 1 : Init done (peripheral initialized. HAL CEC Init function already called) 0137 * b4-b3 (not used) 0138 * xx : Should be set to 00 0139 * b2 Intrinsic process state 0140 * 0 : Ready 0141 * 1 : Busy (peripheral busy with some configuration or internal operations) 0142 * b1 (not used) 0143 * x : Should be set to 0 0144 * b0 Tx state 0145 * 0 : Ready (no Tx operation ongoing) 0146 * 1 : Busy (Tx operation ongoing) 0147 * - RxState contains information related to Rx operations. 0148 * RxState value coding follow below described bitmap : 0149 * b7-b6 (not used) 0150 * xx : Should be set to 00 0151 * b5 CEC peripheral initialization status 0152 * 0 : Reset (peripheral not initialized) 0153 * 1 : Init done (peripheral initialized) 0154 * b4-b2 (not used) 0155 * xxx : Should be set to 000 0156 * b1 Rx state 0157 * 0 : Ready (no Rx operation ongoing) 0158 * 1 : Busy (Rx operation ongoing) 0159 * b0 (not used) 0160 * x : Should be set to 0. 0161 */ 0162 typedef uint32_t HAL_CEC_StateTypeDef; 0163 0164 /** 0165 * @brief CEC handle Structure definition 0166 */ 0167 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0168 typedef struct __CEC_HandleTypeDef 0169 #else 0170 typedef struct 0171 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 0172 { 0173 CEC_TypeDef *Instance; /*!< CEC registers base address */ 0174 0175 CEC_InitTypeDef Init; /*!< CEC communication parameters */ 0176 0177 const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ 0178 0179 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ 0180 0181 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ 0182 0183 HAL_LockTypeDef Lock; /*!< Locking object */ 0184 0185 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management 0186 and also related to Tx operations. 0187 This parameter can be a value of HAL_CEC_StateTypeDef */ 0188 0189 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. 0190 This parameter can be a value of HAL_CEC_StateTypeDef */ 0191 0192 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register 0193 in case error is reported */ 0194 0195 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0196 void (* TxCpltCallback)(struct __CEC_HandleTypeDef 0197 *hcec); /*!< CEC Tx Transfer completed callback */ 0198 void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, 0199 uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ 0200 void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ 0201 0202 void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ 0203 void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ 0204 0205 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ 0206 } CEC_HandleTypeDef; 0207 0208 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0209 /** 0210 * @brief HAL CEC Callback ID enumeration definition 0211 */ 0212 typedef enum 0213 { 0214 HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ 0215 HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ 0216 HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ 0217 HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ 0218 HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ 0219 } HAL_CEC_CallbackIDTypeDef; 0220 0221 /** 0222 * @brief HAL CEC Callback pointer definition 0223 */ 0224 typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ 0225 typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, 0226 uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed 0227 callback function */ 0228 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 0229 /** 0230 * @} 0231 */ 0232 0233 /* Exported constants --------------------------------------------------------*/ 0234 /** @defgroup CEC_Exported_Constants CEC Exported Constants 0235 * @ingroup RTEMSBSPsARMSTM32H7 0236 * @{ 0237 */ 0238 /** @defgroup CEC_State_Definition CEC State Code Definition 0239 * @ingroup RTEMSBSPsARMSTM32H7 0240 * @{ 0241 */ 0242 #define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized 0243 Value is allowed for gState and RxState */ 0244 #define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use 0245 Value is allowed for gState and RxState */ 0246 #define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing 0247 Value is allowed for gState only */ 0248 #define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing 0249 Value is allowed for RxState only */ 0250 #define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing 0251 Value is allowed for gState only */ 0252 #define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing 0253 Value is allowed for gState only */ 0254 #define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ 0255 /** 0256 * @} 0257 */ 0258 /** @defgroup CEC_Error_Code CEC Error Code 0259 * @ingroup RTEMSBSPsARMSTM32H7 0260 * @{ 0261 */ 0262 #define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ 0263 #define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ 0264 #define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ 0265 #define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ 0266 #define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ 0267 #define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ 0268 #define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ 0269 #define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ 0270 #define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ 0271 #define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ 0272 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0273 #define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ 0274 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 0275 /** 0276 * @} 0277 */ 0278 0279 /** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter 0280 * @ingroup RTEMSBSPsARMSTM32H7 0281 * @{ 0282 */ 0283 #define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) 0284 #define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) 0285 #define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) 0286 #define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) 0287 #define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) 0288 #define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) 0289 #define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) 0290 #define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) 0291 /** 0292 * @} 0293 */ 0294 0295 /** @defgroup CEC_Tolerance CEC Receiver Tolerance 0296 * @ingroup RTEMSBSPsARMSTM32H7 0297 * @{ 0298 */ 0299 #define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) 0300 #define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) 0301 /** 0302 * @} 0303 */ 0304 0305 /** @defgroup CEC_BRERxStop CEC Reception Stop on Error 0306 * @ingroup RTEMSBSPsARMSTM32H7 0307 * @{ 0308 */ 0309 #define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) 0310 #define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) 0311 /** 0312 * @} 0313 */ 0314 0315 /** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported 0316 * @ingroup RTEMSBSPsARMSTM32H7 0317 * @{ 0318 */ 0319 #define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 0320 #define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) 0321 /** 0322 * @} 0323 */ 0324 0325 /** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported 0326 * @ingroup RTEMSBSPsARMSTM32H7 0327 * @{ 0328 */ 0329 #define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) 0330 #define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) 0331 /** 0332 * @} 0333 */ 0334 0335 /** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message 0336 * @ingroup RTEMSBSPsARMSTM32H7 0337 * @{ 0338 */ 0339 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) 0340 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) 0341 /** 0342 * @} 0343 */ 0344 0345 /** @defgroup CEC_SFT_Option CEC Signal Free Time start option 0346 * @ingroup RTEMSBSPsARMSTM32H7 0347 * @{ 0348 */ 0349 #define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) 0350 #define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) 0351 /** 0352 * @} 0353 */ 0354 0355 /** @defgroup CEC_Listening_Mode CEC Listening mode option 0356 * @ingroup RTEMSBSPsARMSTM32H7 0357 * @{ 0358 */ 0359 #define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) 0360 #define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) 0361 /** 0362 * @} 0363 */ 0364 0365 /** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register 0366 * @ingroup RTEMSBSPsARMSTM32H7 0367 * @{ 0368 */ 0369 #define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) 0370 /** 0371 * @} 0372 */ 0373 0374 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header 0375 * @ingroup RTEMSBSPsARMSTM32H7 0376 * @{ 0377 */ 0378 #define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) 0379 /** 0380 * @} 0381 */ 0382 0383 /** @defgroup CEC_OWN_ADDRESS CEC Own Address 0384 * @ingroup RTEMSBSPsARMSTM32H7 0385 * @{ 0386 */ 0387 #define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ 0388 #define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ 0389 #define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ 0390 #define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ 0391 #define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ 0392 #define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ 0393 #define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ 0394 #define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ 0395 #define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ 0396 #define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ 0397 #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ 0398 #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ 0399 #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ 0400 #define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ 0401 #define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ 0402 #define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ 0403 /** 0404 * @} 0405 */ 0406 0407 /** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition 0408 * @ingroup RTEMSBSPsARMSTM32H7 0409 * @{ 0410 */ 0411 #define CEC_IT_TXACKE CEC_IER_TXACKEIE 0412 #define CEC_IT_TXERR CEC_IER_TXERRIE 0413 #define CEC_IT_TXUDR CEC_IER_TXUDRIE 0414 #define CEC_IT_TXEND CEC_IER_TXENDIE 0415 #define CEC_IT_TXBR CEC_IER_TXBRIE 0416 #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 0417 #define CEC_IT_RXACKE CEC_IER_RXACKEIE 0418 #define CEC_IT_LBPE CEC_IER_LBPEIE 0419 #define CEC_IT_SBPE CEC_IER_SBPEIE 0420 #define CEC_IT_BRE CEC_IER_BREIE 0421 #define CEC_IT_RXOVR CEC_IER_RXOVRIE 0422 #define CEC_IT_RXEND CEC_IER_RXENDIE 0423 #define CEC_IT_RXBR CEC_IER_RXBRIE 0424 /** 0425 * @} 0426 */ 0427 0428 /** @defgroup CEC_Flags_Definitions CEC Flags definition 0429 * @ingroup RTEMSBSPsARMSTM32H7 0430 * @{ 0431 */ 0432 #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 0433 #define CEC_FLAG_TXERR CEC_ISR_TXERR 0434 #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 0435 #define CEC_FLAG_TXEND CEC_ISR_TXEND 0436 #define CEC_FLAG_TXBR CEC_ISR_TXBR 0437 #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 0438 #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 0439 #define CEC_FLAG_LBPE CEC_ISR_LBPE 0440 #define CEC_FLAG_SBPE CEC_ISR_SBPE 0441 #define CEC_FLAG_BRE CEC_ISR_BRE 0442 #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 0443 #define CEC_FLAG_RXEND CEC_ISR_RXEND 0444 #define CEC_FLAG_RXBR CEC_ISR_RXBR 0445 /** 0446 * @} 0447 */ 0448 0449 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags 0450 * @ingroup RTEMSBSPsARMSTM32H7 0451 * @{ 0452 */ 0453 #define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ 0454 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) 0455 /** 0456 * @} 0457 */ 0458 0459 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag 0460 * @ingroup RTEMSBSPsARMSTM32H7 0461 * @{ 0462 */ 0463 #define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) 0464 /** 0465 * @} 0466 */ 0467 0468 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag 0469 * @ingroup RTEMSBSPsARMSTM32H7 0470 * @{ 0471 */ 0472 #define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) 0473 /** 0474 * @} 0475 */ 0476 0477 /** 0478 * @} 0479 */ 0480 0481 /* Exported macros -----------------------------------------------------------*/ 0482 /** @defgroup CEC_Exported_Macros CEC Exported Macros 0483 * @ingroup RTEMSBSPsARMSTM32H7 0484 * @{ 0485 */ 0486 0487 /** @brief Reset CEC handle gstate & RxState 0488 * @param __HANDLE__ CEC handle. 0489 * @retval None 0490 */ 0491 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0492 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 0493 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 0494 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 0495 (__HANDLE__)->MspInitCallback = NULL; \ 0496 (__HANDLE__)->MspDeInitCallback = NULL; \ 0497 } while(0) 0498 #else 0499 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 0500 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 0501 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 0502 } while(0) 0503 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 0504 /** @brief Checks whether or not the specified CEC interrupt flag is set. 0505 * @param __HANDLE__ specifies the CEC Handle. 0506 * @param __FLAG__ specifies the flag to check. 0507 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 0508 * @arg CEC_FLAG_TXERR: Tx Error. 0509 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 0510 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 0511 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 0512 * @arg CEC_FLAG_ARBLST: Arbitration Lost 0513 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 0514 * @arg CEC_FLAG_LBPE: Rx Long period Error 0515 * @arg CEC_FLAG_SBPE: Rx Short period Error 0516 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 0517 * @arg CEC_FLAG_RXOVR: Rx Overrun. 0518 * @arg CEC_FLAG_RXEND: End Of Reception. 0519 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 0520 * @retval ITStatus 0521 */ 0522 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 0523 0524 /** @brief Clears the interrupt or status flag when raised (write at 1) 0525 * @param __HANDLE__ specifies the CEC Handle. 0526 * @param __FLAG__ specifies the interrupt/status flag to clear. 0527 * This parameter can be one of the following values: 0528 * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error 0529 * @arg CEC_FLAG_TXERR: Tx Error. 0530 * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. 0531 * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). 0532 * @arg CEC_FLAG_TXBR: Tx-Byte Request. 0533 * @arg CEC_FLAG_ARBLST: Arbitration Lost 0534 * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge 0535 * @arg CEC_FLAG_LBPE: Rx Long period Error 0536 * @arg CEC_FLAG_SBPE: Rx Short period Error 0537 * @arg CEC_FLAG_BRE: Rx Bit Rising Error 0538 * @arg CEC_FLAG_RXOVR: Rx Overrun. 0539 * @arg CEC_FLAG_RXEND: End Of Reception. 0540 * @arg CEC_FLAG_RXBR: Rx-Byte Received. 0541 * @retval none 0542 */ 0543 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 0544 0545 /** @brief Enables the specified CEC interrupt. 0546 * @param __HANDLE__ specifies the CEC Handle. 0547 * @param __INTERRUPT__ specifies the CEC interrupt to enable. 0548 * This parameter can be one of the following values: 0549 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 0550 * @arg CEC_IT_TXERR: Tx Error IT Enable 0551 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 0552 * @arg CEC_IT_TXEND: End of transmission IT Enable 0553 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 0554 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 0555 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 0556 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 0557 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 0558 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 0559 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 0560 * @arg CEC_IT_RXEND: End Of Reception IT Enable 0561 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 0562 * @retval none 0563 */ 0564 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 0565 0566 /** @brief Disables the specified CEC interrupt. 0567 * @param __HANDLE__ specifies the CEC Handle. 0568 * @param __INTERRUPT__ specifies the CEC interrupt to disable. 0569 * This parameter can be one of the following values: 0570 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 0571 * @arg CEC_IT_TXERR: Tx Error IT Enable 0572 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 0573 * @arg CEC_IT_TXEND: End of transmission IT Enable 0574 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 0575 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 0576 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 0577 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 0578 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 0579 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 0580 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 0581 * @arg CEC_IT_RXEND: End Of Reception IT Enable 0582 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 0583 * @retval none 0584 */ 0585 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 0586 0587 /** @brief Checks whether or not the specified CEC interrupt is enabled. 0588 * @param __HANDLE__ specifies the CEC Handle. 0589 * @param __INTERRUPT__ specifies the CEC interrupt to check. 0590 * This parameter can be one of the following values: 0591 * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 0592 * @arg CEC_IT_TXERR: Tx Error IT Enable 0593 * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable 0594 * @arg CEC_IT_TXEND: End of transmission IT Enable 0595 * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable 0596 * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable 0597 * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable 0598 * @arg CEC_IT_LBPE: Rx Long period Error IT Enable 0599 * @arg CEC_IT_SBPE: Rx Short period Error IT Enable 0600 * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable 0601 * @arg CEC_IT_RXOVR: Rx Overrun IT Enable 0602 * @arg CEC_IT_RXEND: End Of Reception IT Enable 0603 * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable 0604 * @retval FlagStatus 0605 */ 0606 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) 0607 0608 /** @brief Enables the CEC device 0609 * @param __HANDLE__ specifies the CEC Handle. 0610 * @retval none 0611 */ 0612 #define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) 0613 0614 /** @brief Disables the CEC device 0615 * @param __HANDLE__ specifies the CEC Handle. 0616 * @retval none 0617 */ 0618 #define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) 0619 0620 /** @brief Set Transmission Start flag 0621 * @param __HANDLE__ specifies the CEC Handle. 0622 * @retval none 0623 */ 0624 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) 0625 0626 /** @brief Set Transmission End flag 0627 * @param __HANDLE__ specifies the CEC Handle. 0628 * @retval none 0629 * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. 0630 */ 0631 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) 0632 0633 /** @brief Get Transmission Start flag 0634 * @param __HANDLE__ specifies the CEC Handle. 0635 * @retval FlagStatus 0636 */ 0637 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) 0638 0639 /** @brief Get Transmission End flag 0640 * @param __HANDLE__ specifies the CEC Handle. 0641 * @retval FlagStatus 0642 */ 0643 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) 0644 0645 /** @brief Clear OAR register 0646 * @param __HANDLE__ specifies the CEC Handle. 0647 * @retval none 0648 */ 0649 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) 0650 0651 /** @brief Set OAR register (without resetting previously set address in case of multi-address mode) 0652 * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand 0653 * @param __HANDLE__ specifies the CEC Handle. 0654 * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) 0655 * @retval none 0656 */ 0657 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ 0658 (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) 0659 0660 /** 0661 * @} 0662 */ 0663 0664 /* Exported functions --------------------------------------------------------*/ 0665 /** @addtogroup CEC_Exported_Functions 0666 * @{ 0667 */ 0668 0669 /** @addtogroup CEC_Exported_Functions_Group1 0670 * @{ 0671 */ 0672 /* Initialization and de-initialization functions ****************************/ 0673 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); 0674 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); 0675 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); 0676 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); 0677 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); 0678 0679 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 0680 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, 0681 pCEC_CallbackTypeDef pCallback); 0682 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); 0683 0684 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); 0685 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); 0686 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 0687 /** 0688 * @} 0689 */ 0690 0691 /** @addtogroup CEC_Exported_Functions_Group2 0692 * @{ 0693 */ 0694 /* I/O operation functions ***************************************************/ 0695 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, 0696 const uint8_t *pData, uint32_t Size); 0697 uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); 0698 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); 0699 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); 0700 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); 0701 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); 0702 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); 0703 /** 0704 * @} 0705 */ 0706 0707 /** @addtogroup CEC_Exported_Functions_Group3 0708 * @{ 0709 */ 0710 /* Peripheral State functions ************************************************/ 0711 HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); 0712 uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); 0713 /** 0714 * @} 0715 */ 0716 0717 /** 0718 * @} 0719 */ 0720 0721 /* Private types -------------------------------------------------------------*/ 0722 /** @defgroup CEC_Private_Types CEC Private Types 0723 * @ingroup RTEMSBSPsARMSTM32H7 0724 * @{ 0725 */ 0726 0727 /** 0728 * @} 0729 */ 0730 0731 /* Private variables ---------------------------------------------------------*/ 0732 /** @defgroup CEC_Private_Variables CEC Private Variables 0733 * @ingroup RTEMSBSPsARMSTM32H7 0734 * @{ 0735 */ 0736 0737 /** 0738 * @} 0739 */ 0740 0741 /* Private constants ---------------------------------------------------------*/ 0742 /** @defgroup CEC_Private_Constants CEC Private Constants 0743 * @ingroup RTEMSBSPsARMSTM32H7 0744 * @{ 0745 */ 0746 0747 /** 0748 * @} 0749 */ 0750 0751 /* Private macros ------------------------------------------------------------*/ 0752 /** @defgroup CEC_Private_Macros CEC Private Macros 0753 * @ingroup RTEMSBSPsARMSTM32H7 0754 * @{ 0755 */ 0756 0757 #define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) 0758 0759 #define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ 0760 ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) 0761 0762 #define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ 0763 ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) 0764 0765 #define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ 0766 ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) 0767 0768 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ 0769 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) 0770 0771 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ 0772 (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ 0773 ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) 0774 0775 #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ 0776 ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) 0777 0778 #define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ 0779 ((__MODE__) == CEC_FULL_LISTENING_MODE)) 0780 0781 /** @brief Check CEC message size. 0782 * The message size is the payload size: without counting the header, 0783 * it varies from 0 byte (ping operation, one header only, no payload) to 0784 * 15 bytes (1 opcode and up to 14 operands following the header). 0785 * @param __SIZE__ CEC message size. 0786 * @retval Test result (TRUE or FALSE). 0787 */ 0788 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) 0789 0790 /** @brief Check CEC device Own Address Register (OAR) setting. 0791 * OAR address is written in a 15-bit field within CEC_CFGR register. 0792 * @param __ADDRESS__ CEC own address. 0793 * @retval Test result (TRUE or FALSE). 0794 */ 0795 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) 0796 0797 /** @brief Check CEC initiator or destination logical address setting. 0798 * Initiator and destination addresses are coded over 4 bits. 0799 * @param __ADDRESS__ CEC initiator or logical address. 0800 * @retval Test result (TRUE or FALSE). 0801 */ 0802 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) 0803 /** 0804 * @} 0805 */ 0806 /* Private functions ---------------------------------------------------------*/ 0807 /** @defgroup CEC_Private_Functions CEC Private Functions 0808 * @ingroup RTEMSBSPsARMSTM32H7 0809 * @{ 0810 */ 0811 0812 /** 0813 * @} 0814 */ 0815 0816 /** 0817 * @} 0818 */ 0819 0820 /** 0821 * @} 0822 */ 0823 0824 #endif /* CEC */ 0825 0826 #ifdef __cplusplus 0827 } 0828 #endif 0829 0830 #endif /* STM32H7xxHAL_CEC_H */
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