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0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_hal_adc_ex.h 0004 * @author MCD Application Team 0005 * @brief Header file of ADC HAL extended module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_HAL_ADC_EX_H 0021 #define STM32H7xx_HAL_ADC_EX_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx_hal_def.h" 0029 0030 /** @addtogroup STM32H7xx_HAL_Driver 0031 * @{ 0032 */ 0033 0034 /** @addtogroup ADCEx 0035 * @{ 0036 */ 0037 0038 /* Exported types ------------------------------------------------------------*/ 0039 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 0040 * @ingroup RTEMSBSPsARMSTM32H7 0041 * @{ 0042 */ 0043 0044 /** 0045 * @brief ADC Injected Conversion Oversampling structure definition 0046 */ 0047 typedef struct 0048 { 0049 uint32_t Ratio; /*!< Configures the oversampling ratio. */ 0050 #if defined(ADC_VER_V5_V90) 0051 /* On devices STM32H72xx and STM32H73xx this parameter can be a value from 1 to 1023 for ADC1/2 and value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/ 0052 #else 0053 /* This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 0054 #endif 0055 0056 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 0057 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 0058 } ADC_InjOversamplingTypeDef; 0059 0060 /** 0061 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 0062 * @note Parameters of this structure are shared within 2 scopes: 0063 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 0064 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 0065 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 0066 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 0067 * ADC state can be either: 0068 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 0069 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 0070 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 0071 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 0072 * on ADC groups regular and injected. 0073 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 0074 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 0075 */ 0076 typedef struct 0077 { 0078 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 0079 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 0080 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 0081 0082 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 0083 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 0084 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 0085 the new channel setting (or parameter number of conversions adjusted) */ 0086 0087 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 0088 Unit: ADC clock cycles. 0089 Conversion time is the addition of sampling time and processing time 0090 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 0091 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 0092 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 0093 It overwrites the last setting. 0094 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 0095 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 0096 Refer to device datasheet for timings values. */ 0097 0098 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 0099 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 0100 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 0101 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 0102 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 0103 It overwrites the last setting. 0104 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 0105 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 0106 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 0107 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 0108 of another parameter update on the fly) */ 0109 0110 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 0111 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 0112 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 0113 0114 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 0115 Offset value must be a positive number. 0116 Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used). 0117 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024). 0118 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 0119 without continuous mode or external trigger that could launch a conversion). */ 0120 0121 uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. 0122 This parameter is applied only for 16-bit or 8-bit resolution. 0123 This parameter can be set to ENABLE or DISABLE. */ 0124 #if defined(ADC_VER_V5_V90) 0125 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 0126 This parameter can be a value of @ref ADCEx_OffsetSign. 0127 Note: 0128 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 0129 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 0130 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 0131 This parameter value can be ENABLE or DISABLE. 0132 Note: 0133 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 0134 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 0135 0136 #endif 0137 0138 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 0139 This parameter is applied only for 16-bit or 8-bit resolution. 0140 This parameter can be set to ENABLE or DISABLE. */ 0141 0142 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 0143 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 0144 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 0145 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0146 configure a channel on injected group can impact the configuration of other channels previously set. */ 0147 0148 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 0149 (main sequence subdivided in successive parts). 0150 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 0151 Discontinuous mode can be enabled only if continuous mode is disabled. 0152 This parameter can be set to ENABLE or DISABLE. 0153 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 0154 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 0155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0156 configure a channel on injected group can impact the configuration of other channels previously set. */ 0157 0158 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 0159 This parameter can be set to ENABLE or DISABLE. 0160 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 0161 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 0162 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 0163 To maintain JAUTO always enabled, DMA must be configured in circular mode. 0164 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0165 configure a channel on injected group can impact the configuration of other channels previously set. */ 0166 0167 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 0168 This parameter can be set to ENABLE or DISABLE. 0169 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 0170 new injected context is set when queue is full, error is triggered by interruption and through function 0171 'HAL_ADCEx_InjectedQueueOverflowCallback'. 0172 Caution: This feature request that the sequence is fully configured before injected conversion start. 0173 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 0174 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0175 configure a channel on injected group can impact the configuration of other channels previously set. 0176 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 0177 0178 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 0179 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 0180 This parameter can be a value of @ref ADC_injected_external_trigger_source. 0181 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0182 configure a channel on injected group can impact the configuration of other channels previously set. */ 0183 0184 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 0185 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 0186 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 0187 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 0188 configure a channel on injected group can impact the configuration of other channels previously set. */ 0189 0190 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 0191 This parameter can be set to ENABLE or DISABLE. 0192 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 0193 0194 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 0195 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 0196 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 0197 } ADC_InjectionConfTypeDef; 0198 0199 /** 0200 * @brief Structure definition of ADC multimode 0201 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 0202 * Both Master and Slave ADCs must be disabled. 0203 */ 0204 typedef struct 0205 { 0206 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 0207 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 0208 0209 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 0210 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 0211 0212 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 0213 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 0214 Delay range depends on selected resolution: 0215 from 1 to 9 clock cycles for 16 bits, 0216 from 1 to 9 clock cycles for 14 bits 0217 from 1 to 8 clock cycles for 12 bits 0218 from 1 to 6 clock cycles for 10 bits 0219 from 1 to 6 clock cycles for 8 bits */ 0220 } ADC_MultiModeTypeDef; 0221 0222 /** 0223 * @} 0224 */ 0225 0226 /* Exported constants --------------------------------------------------------*/ 0227 0228 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 0229 * @ingroup RTEMSBSPsARMSTM32H7 0230 * @{ 0231 */ 0232 0233 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 0234 * @ingroup RTEMSBSPsARMSTM32H7 0235 * @{ 0236 */ 0237 /* ADC group regular trigger sources for all ADC instances */ 0238 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 0239 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 0240 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0241 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 0242 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0243 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0244 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 0245 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 0246 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0247 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 0248 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 0249 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 0250 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0251 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 0252 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0253 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 0254 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 0255 #if defined(HRTIM1) 0256 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */ 0257 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */ 0258 #endif /* HRTIM1 */ 0259 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 0260 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 0261 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ 0262 /** 0263 * @} 0264 */ 0265 0266 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 0267 * @ingroup RTEMSBSPsARMSTM32H7 0268 * @{ 0269 */ 0270 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 0271 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 0272 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 0273 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 0274 /** 0275 * @} 0276 */ 0277 0278 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 0279 * @ingroup RTEMSBSPsARMSTM32H7 0280 * @{ 0281 */ 0282 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 0283 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 0284 /** 0285 * @} 0286 */ 0287 0288 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 0289 * @ingroup RTEMSBSPsARMSTM32H7 0290 * @{ 0291 */ 0292 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 0293 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 0294 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 0295 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 0296 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 0297 /** 0298 * @} 0299 */ 0300 0301 #if defined(ADC_VER_V5_V90) 0302 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 0303 * @ingroup RTEMSBSPsARMSTM32H7 0304 * @{ 0305 */ 0306 #define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ 0307 #define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ 0308 /** 0309 * @} 0310 */ 0311 #endif 0312 0313 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 0314 * @ingroup RTEMSBSPsARMSTM32H7 0315 * @{ 0316 */ 0317 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 0318 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 0319 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 0320 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 0321 /** 0322 * @} 0323 */ 0324 0325 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 0326 * @ingroup RTEMSBSPsARMSTM32H7 0327 * @{ 0328 */ 0329 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 0330 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 0331 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 0332 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 0333 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 0334 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 0335 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 0336 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 0337 0338 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 0339 * @ingroup RTEMSBSPsARMSTM32H7 0340 * @{ 0341 */ 0342 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 0343 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 0344 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 0345 /** 0346 * @} 0347 */ 0348 0349 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 0350 * @ingroup RTEMSBSPsARMSTM32H7 0351 * @{ 0352 */ 0353 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 0354 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 0355 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 0356 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 0357 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 0358 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 0359 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 0360 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 0361 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 0362 /** 0363 * @} 0364 */ 0365 0366 /** 0367 * @} 0368 */ 0369 0370 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 0371 * @ingroup RTEMSBSPsARMSTM32H7 0372 * @{ 0373 */ 0374 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 0375 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 0376 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 0377 /** 0378 * @} 0379 */ 0380 0381 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 0382 * @ingroup RTEMSBSPsARMSTM32H7 0383 * @{ 0384 */ 0385 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 0386 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 0387 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 0388 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 0389 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 0390 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 0391 /** 0392 * @} 0393 */ 0394 0395 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 0396 * @ingroup RTEMSBSPsARMSTM32H7 0397 * @{ 0398 */ 0399 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 0400 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 0401 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 0402 ADC_SMPR1_SMP0) 0403 /** 0404 * @} 0405 */ 0406 0407 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 0408 * @ingroup RTEMSBSPsARMSTM32H7 0409 * @{ 0410 */ 0411 /* ADC_CFGR fields of parameters that can be updated when no conversion 0412 (neither regular nor injected) is on-going */ 0413 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) 0414 /** 0415 * @} 0416 */ 0417 #if defined(ADC_VER_V5_V90) 0418 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 0419 * @ingroup RTEMSBSPsARMSTM32H7 0420 * @{ 0421 */ 0422 /* ADC_CFGR fields of parameters that can be updated when no conversion 0423 (neither regular nor injected) is on-going */ 0424 #define ADC3_CFGR_FIELDS_2 ((ADC3_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 0425 /** 0426 * @} 0427 */ 0428 #endif 0429 0430 #if defined(DFSDM1_Channel0) 0431 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 0432 * @ingroup RTEMSBSPsARMSTM32H7 0433 * @{ 0434 */ 0435 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 0436 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 0437 /** 0438 * @} 0439 */ 0440 #endif 0441 0442 /** 0443 * @} 0444 */ 0445 0446 /* Exported macros -----------------------------------------------------------*/ 0447 0448 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 0449 * @ingroup RTEMSBSPsARMSTM32H7 0450 * @{ 0451 */ 0452 0453 /** @brief Force ADC instance in multimode mode independent (multimode disable). 0454 * @note This macro must be used only in case of transition from multimode 0455 * to mode independent and in case of unknown previous state, 0456 * to ensure ADC configuration is in mode independent. 0457 * @note Standard way of multimode configuration change is done from 0458 * HAL ADC handle of ADC master using function 0459 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 0460 * Usage of this macro is not the Standard way of multimode 0461 * configuration and can lead to have HAL ADC handles status 0462 * misaligned. Usage of this macro must be limited to cases 0463 * mentioned above. 0464 * @param __HANDLE__ ADC handle. 0465 * @retval None 0466 */ 0467 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 0468 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 0469 0470 /** 0471 * @} 0472 */ 0473 0474 /* Private macros ------------------------------------------------------------*/ 0475 0476 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 0477 * @ingroup RTEMSBSPsARMSTM32H7 0478 * @{ 0479 */ 0480 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 0481 /* code of final user. */ 0482 0483 /** 0484 * @brief Test if conversion trigger of injected group is software start 0485 * or external trigger. 0486 * @param __HANDLE__ ADC handle. 0487 * @retval SET (software start) or RESET (external trigger). 0488 */ 0489 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 0490 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 0491 0492 /** 0493 * @brief Check if conversion is on going on regular or injected groups. 0494 * @param __HANDLE__ ADC handle. 0495 * @retval SET (conversion is on going) or RESET (no conversion is on going). 0496 */ 0497 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 0498 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 0499 ) ? RESET : SET) 0500 0501 /** 0502 * @brief Check if conversion is on going on injected group. 0503 * @param __HANDLE__ ADC handle. 0504 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 0505 */ 0506 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 0507 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 0508 0509 0510 #if defined (ADC3) 0511 /** 0512 * @brief Check whether or not ADC is independent. 0513 * @param __HANDLE__ ADC handle. 0514 * @note When multimode feature is not available, the macro always returns SET. 0515 * @retval SET (ADC is independent) or RESET (ADC is not). 0516 */ 0517 0518 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 0519 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 0520 )? \ 0521 SET \ 0522 : \ 0523 RESET \ 0524 ) 0525 #endif 0526 0527 /** 0528 * @brief Set the selected injected Channel rank. 0529 * @param __CHANNELNB__ Channel number. 0530 * @param __RANKNB__ Rank number. 0531 * @retval None 0532 */ 0533 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 0534 0535 /** 0536 * @brief Configure ADC injected context queue 0537 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 0538 * @retval None 0539 */ 0540 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 0541 0542 /** 0543 * @brief Configure ADC discontinuous conversion mode for injected group 0544 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 0545 * @retval None 0546 */ 0547 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 0548 0549 /** 0550 * @brief Configure ADC discontinuous conversion mode for regular group 0551 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 0552 * @retval None 0553 */ 0554 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 0555 0556 /** 0557 * @brief Configure the number of discontinuous conversions for regular group. 0558 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 0559 * @retval None 0560 */ 0561 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 0562 0563 /** 0564 * @brief Configure the ADC auto delay mode. 0565 * @param __AUTOWAIT__ Auto delay bit enable or disable. 0566 * @retval None 0567 */ 0568 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 0569 0570 /** 0571 * @brief Configure ADC continuous conversion mode. 0572 * @param __CONTINUOUS_MODE__ Continuous mode. 0573 * @retval None 0574 */ 0575 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 0576 0577 /** 0578 * @brief Enable the ADC DMA continuous request. 0579 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 0580 * @retval None 0581 */ 0582 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 0583 0584 #if defined(ADC_VER_V5_V90) 0585 /** 0586 * @brief Configure the ADC DMA continuous request. 0587 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 0588 * @retval None 0589 */ 0590 #define ADC3_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC3_CFGR_DMACFG_Pos) 0591 #endif 0592 /** 0593 * @brief Configure the channel number into offset OFRx register. 0594 * @param __CHANNEL__ ADC Channel. 0595 * @retval None 0596 */ 0597 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 0598 0599 /** 0600 * @brief Configure the channel number into differential mode selection register. 0601 * @param __CHANNEL__ ADC Channel. 0602 * @retval None 0603 */ 0604 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 0605 0606 /** 0607 * @brief Configure calibration factor in differential mode to be set into calibration register. 0608 * @param __CALIBRATION_FACTOR__ Calibration factor value. 0609 * @retval None 0610 */ 0611 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 0612 0613 /** 0614 * @brief Calibration factor in differential mode to be retrieved from calibration register. 0615 * @param __CALIBRATION_FACTOR__ Calibration factor value. 0616 * @retval None 0617 */ 0618 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 0619 0620 /** 0621 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 0622 * @param __THRESHOLD__ Threshold value. 0623 * @retval None 0624 */ 0625 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 0626 0627 /** 0628 * @brief Configure the ADC DMA continuous request for ADC multimode. 0629 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 0630 * @retval None 0631 */ 0632 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 0633 0634 /** 0635 * @brief Shift the offset in function of the selected ADC resolution. 0636 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 0637 * If resolution 16 bits, no shift. 0638 * If resolution 14 bits, shift of 2 ranks on the left. 0639 * If resolution 12 bits, shift of 4 ranks on the left. 0640 * If resolution 10 bits, shift of 6 ranks on the left. 0641 * If resolution 8 bits, shift of 8 ranks on the left. 0642 * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2)) 0643 * @param __HANDLE__: ADC handle 0644 * @param __OFFSET__: Value to be shifted 0645 * @retval None 0646 */ 0647 #if defined(ADC_VER_V5_3) 0648 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 0649 ( \ 0650 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0651 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0652 : \ 0653 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0654 ) 0655 #else 0656 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 0657 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 0658 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0659 : \ 0660 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0661 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0662 : \ 0663 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0664 ) 0665 #endif /* ADC_VER_V5_3 */ 0666 0667 #if defined(ADC_VER_V5_V90) 0668 #define ADC3_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 0669 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC3_CFGR_RES) >> 3UL) * 2UL)) 0670 0671 #endif /* ADC_VER_V5_V90 */ 0672 0673 /** 0674 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 0675 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 0676 * If resolution 16 bits, no shift. 0677 * If resolution 14 bits, shift of 2 ranks on the left. 0678 * If resolution 12 bits, shift of 4 ranks on the left. 0679 * If resolution 10 bits, shift of 6 ranks on the left. 0680 * If resolution 8 bits, shift of 8 ranks on the left. 0681 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 0682 * @param __HANDLE__: ADC handle 0683 * @param __THRESHOLD__: Value to be shifted 0684 * @retval None 0685 */ 0686 #if defined(ADC_VER_V5_3) 0687 #if defined(ADC_VER_V5_V90) 0688 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 0689 ( ((__HANDLE__)->Instance == ADC3) \ 0690 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC3_CFGR_RES)>> 3UL)*2UL)) \ 0691 : \ 0692 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0693 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0694 : \ 0695 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0696 ) 0697 #else 0698 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 0699 ( \ 0700 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0701 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0702 : \ 0703 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0704 ) 0705 #endif 0706 0707 #else 0708 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 0709 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 0710 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0711 : \ 0712 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0713 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0714 : \ 0715 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0716 ) 0717 #endif /* ADC_VER_V5_3 */ 0718 0719 /** 0720 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 0721 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 0722 * If resolution 16 bits, no shift. 0723 * If resolution 14 bits, shift of 2 ranks on the left. 0724 * If resolution 12 bits, shift of 4 ranks on the left. 0725 * If resolution 10 bits, shift of 6 ranks on the left. 0726 * If resolution 8 bits, shift of 8 ranks on the left. 0727 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 0728 * @param __HANDLE__: ADC handle 0729 * @param __THRESHOLD__: Value to be shifted 0730 * @retval None 0731 */ 0732 #if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90) 0733 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 0734 ( \ 0735 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0736 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0737 : \ 0738 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0739 ) 0740 #else 0741 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 0742 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 0743 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0744 : \ 0745 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 0746 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 0747 : \ 0748 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 0749 ) 0750 #endif /* ADC_VER_V5_3 */ 0751 /** 0752 * @brief Clear Common Control Register. 0753 * @param __HANDLE__ ADC handle. 0754 * @retval None 0755 */ 0756 /** 0757 * @brief Report common register to ADC1 and ADC2 0758 * @param __HANDLE__: ADC handle 0759 * @retval Common control register 0760 */ 0761 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 0762 #if defined (ADC3) 0763 /** 0764 * @brief Report common register to ADC3 0765 * @param __HANDLE__: ADC handle 0766 * @retval Common control register 0767 */ 0768 #define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON) 0769 #endif 0770 /** 0771 * @brief Report Master Instance 0772 * @param __HANDLE__: ADC handle 0773 * @note return same instance if ADC of input handle is independent ADC 0774 * @retval Master Instance 0775 */ 0776 #if defined (ADC3) 0777 #define ADC_MASTER_REGISTER(__HANDLE__) \ 0778 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 0779 )? \ 0780 ((__HANDLE__)->Instance) \ 0781 : \ 0782 (ADC1) \ 0783 ) 0784 #else 0785 #define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1)) 0786 #endif 0787 0788 /** 0789 * @brief Check whether or not dual regular conversions are enabled 0790 * @param __HANDLE__: ADC handle 0791 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 0792 */ 0793 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 0794 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 0795 )? \ 0796 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 0797 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 0798 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 0799 : \ 0800 RESET \ 0801 ) 0802 0803 /** 0804 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 0805 * @param __HANDLE__: ADC handle 0806 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 0807 */ 0808 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 0809 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 0810 )? \ 0811 SET \ 0812 : \ 0813 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 0814 ) 0815 #if defined (ADC3) 0816 /** 0817 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 0818 * @param __HANDLE__: ADC handle 0819 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 0820 */ 0821 #define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 0822 ( ( ((__HANDLE__)->Instance == ADC3) \ 0823 )? \ 0824 SET \ 0825 : \ 0826 ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 0827 ) 0828 #endif 0829 /** 0830 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 0831 * @param __HANDLE__: ADC handle 0832 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 0833 */ 0834 #if defined (ADC3) 0835 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 0836 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 0837 )? \ 0838 SET \ 0839 : \ 0840 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 0841 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 0842 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 0843 #else 0844 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 0845 ( ( ((__HANDLE__)->Instance == ADC1) \ 0846 )? \ 0847 SET \ 0848 : \ 0849 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 0850 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 0851 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 0852 #endif 0853 0854 /** 0855 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 0856 * @param __HANDLE__: ADC handle 0857 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 0858 */ 0859 #if defined (ADC3) 0860 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 0861 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 0862 )? \ 0863 SET \ 0864 : \ 0865 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 0866 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 0867 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 0868 #else 0869 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 0870 ( ( ((__HANDLE__)->Instance == ADC1) \ 0871 )? \ 0872 SET \ 0873 : \ 0874 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 0875 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 0876 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 0877 #endif 0878 0879 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 0880 ADC_CCR_PRESC | \ 0881 ADC_CCR_VBATEN | \ 0882 ADC_CCR_TSEN | \ 0883 ADC_CCR_VREFEN | \ 0884 ADC_CCR_DAMDF | \ 0885 ADC_CCR_DELAY | \ 0886 ADC_CCR_DUAL ) 0887 0888 /** 0889 * @brief Set handle instance of the ADC slave associated to the ADC master. 0890 * @param __HANDLE_MASTER__ ADC master handle. 0891 * @param __HANDLE_SLAVE__ ADC slave handle. 0892 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 0893 * @retval None 0894 */ 0895 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 0896 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 0897 0898 0899 /** 0900 * @brief Verify the ADC instance connected to the temperature sensor. 0901 * @param __HANDLE__ ADC handle. 0902 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 0903 */ 0904 #if defined(ADC3) 0905 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 0906 #else 0907 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 0908 #endif 0909 0910 /** 0911 * @brief Verify the ADC instance connected to the battery voltage VBAT. 0912 * @param __HANDLE__ ADC handle. 0913 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 0914 */ 0915 #if defined(ADC3) 0916 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 0917 #else 0918 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 0919 #endif 0920 0921 /** 0922 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 0923 * @param __HANDLE__ ADC handle. 0924 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 0925 */ 0926 #if defined(ADC3) 0927 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 0928 #else 0929 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 0930 #endif 0931 0932 /** 0933 * @brief Verify the length of scheduled injected conversions group. 0934 * @param __LENGTH__ number of programmed conversions. 0935 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 0936 */ 0937 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 0938 0939 /** 0940 * @brief Calibration factor size verification (11 bits maximum). 0941 * @param __CALIBRATION_FACTOR__ Calibration factor value. 0942 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 0943 */ 0944 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FFU)) 0945 0946 #if defined(ADC_VER_V5_V90) 0947 /** 0948 * @brief Calibration factor size verification (7 bits maximum on ADC3). 0949 * @param __CALIBRATION_FACTOR__ Calibration factor value. 0950 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 0951 */ 0952 #define IS_ADC_CALFACT_ADC3(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 0953 #endif 0954 0955 /** 0956 * @brief Verify the ADC channel setting. 0957 * @param __CHANNEL__ programmed ADC channel. 0958 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 0959 */ 0960 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 0961 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 0962 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 0963 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 0964 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 0965 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 0966 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 0967 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 0968 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 0969 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 0970 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 0971 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 0972 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 0973 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 0974 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 0975 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 0976 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 0977 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 0978 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 0979 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 0980 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 0981 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 0982 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 0983 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \ 0984 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 0985 0986 /** 0987 * @brief Verify the ADC channel setting in differential mode for ADC1. 0988 * @param __CHANNEL__: programmed ADC channel. 0989 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 0990 */ 0991 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 0992 ((__CHANNEL__) == ADC_CHANNEL_2) ||\ 0993 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 0994 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 0995 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 0996 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 0997 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 0998 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 0999 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 1000 ((__CHANNEL__) == ADC_CHANNEL_18) ) 1001 1002 /** 1003 * @brief Verify the ADC channel setting in differential mode for ADC2. 1004 * @param __CHANNEL__: programmed ADC channel. 1005 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1006 */ 1007 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 1008 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 1009 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 1010 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 1011 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 1012 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 1013 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 1014 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 1015 ((__CHANNEL__) == ADC_CHANNEL_18) ) 1016 1017 /** 1018 * @brief Verify the ADC channel setting in differential mode for ADC3. 1019 * @param __CHANNEL__: programmed ADC channel. 1020 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1021 */ 1022 #define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 1023 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 1024 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 1025 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 1026 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 1027 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 1028 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 1029 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 1030 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 1031 ((__CHANNEL__) == ADC_CHANNEL_15) ) 1032 1033 /** 1034 * @brief Verify the ADC single-ended input or differential mode setting. 1035 * @param __SING_DIFF__ programmed channel setting. 1036 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 1037 */ 1038 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 1039 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 1040 1041 /** 1042 * @brief Verify the ADC offset management setting. 1043 * @param __OFFSET_NUMBER__ ADC offset management. 1044 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 1045 */ 1046 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 1047 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 1048 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 1049 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 1050 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 1051 #if defined(ADC_VER_V5_V90) 1052 /** 1053 * @brief Verify the ADC offset sign setting. 1054 * @param __OFFSET_SIGN__ ADC offset sign. 1055 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 1056 */ 1057 #define IS_ADC3_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_NEGATIVE) || \ 1058 ((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_POSITIVE) ) 1059 #endif /* ADC_VER_V5_V90 */ 1060 /** 1061 * @brief Verify the ADC injected channel setting. 1062 * @param __CHANNEL__ programmed ADC injected channel. 1063 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1064 */ 1065 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 1066 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 1067 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 1068 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 1069 1070 /** 1071 * @brief Verify the ADC injected conversions external trigger. 1072 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 1073 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 1074 */ 1075 #if defined (HRTIM1) 1076 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1077 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1078 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1079 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1080 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1081 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1082 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1083 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1084 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1085 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1086 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1089 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1090 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1091 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1092 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \ 1093 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \ 1094 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 1095 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 1096 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 1097 \ 1098 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 1099 #else 1100 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 1101 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 1102 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 1103 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 1104 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 1105 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 1106 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 1107 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 1108 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 1109 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 1110 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 1111 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 1112 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 1113 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 1114 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 1115 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 1116 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 1117 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 1118 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 1119 \ 1120 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 1121 #endif /* HRTIM */ 1122 /** 1123 * @brief Verify the ADC edge trigger setting for injected group. 1124 * @param __EDGE__ programmed ADC edge trigger setting. 1125 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1126 */ 1127 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 1128 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 1129 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 1130 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 1131 1132 /** 1133 * @brief Verify the ADC multimode setting. 1134 * @param __MODE__ programmed ADC multimode setting. 1135 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1136 */ 1137 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 1138 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 1139 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 1140 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 1141 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 1142 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 1143 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 1144 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 1145 1146 /** 1147 * @brief Verify the ADC dual data mode setting. 1148 * @param MODE: programmed ADC dual mode setting. 1149 * @retval SET (MODE is valid) or RESET (MODE is invalid) 1150 */ 1151 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 1152 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 1153 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 1154 1155 /** 1156 * @brief Verify the ADC multimode delay setting. 1157 * @param __DELAY__ programmed ADC multimode delay setting. 1158 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 1159 */ 1160 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 1161 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 1162 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 1163 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 1164 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 1165 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 1166 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 1167 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 1168 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) ) 1169 1170 /** 1171 * @brief Verify the ADC analog watchdog setting. 1172 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 1173 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 1174 */ 1175 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 1176 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 1177 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 1178 1179 /** 1180 * @brief Verify the ADC analog watchdog mode setting. 1181 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 1182 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 1183 */ 1184 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 1185 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 1186 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 1187 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 1188 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 1189 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 1190 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 1191 1192 #if defined(ADC_VER_V5_V90) 1193 /** 1194 * @brief Verify the ADC analog watchdog filtering setting. 1195 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 1196 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 1197 */ 1198 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE_ADC3(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC3_AWD_FILTERING_NONE) || \ 1199 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_2SAMPLES) || \ 1200 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_3SAMPLES) || \ 1201 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_4SAMPLES) || \ 1202 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_5SAMPLES) || \ 1203 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_6SAMPLES) || \ 1204 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_7SAMPLES) || \ 1205 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_8SAMPLES) ) 1206 1207 #endif /* ADC_VER_V5_V90 */ 1208 1209 /** 1210 * @brief Verify the ADC conversion (regular or injected or both). 1211 * @param __CONVERSION__ ADC conversion group. 1212 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 1213 */ 1214 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 1215 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 1216 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 1217 1218 /** 1219 * @brief Verify the ADC event type. 1220 * @param __EVENT__ ADC event. 1221 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 1222 */ 1223 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 1224 ((__EVENT__) == ADC_AWD_EVENT) || \ 1225 ((__EVENT__) == ADC_AWD2_EVENT) || \ 1226 ((__EVENT__) == ADC_AWD3_EVENT) || \ 1227 ((__EVENT__) == ADC_OVR_EVENT) || \ 1228 ((__EVENT__) == ADC_JQOVF_EVENT) ) 1229 1230 /** 1231 * @brief Verify the ADC oversampling ratio. 1232 * @param RATIO: programmed ADC oversampling ratio. 1233 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 1234 */ 1235 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) 1236 1237 #if defined(ADC_VER_V5_V90) 1238 /** 1239 * @brief Verify the ADC3 oversampling ratio. 1240 * @param __RATIO__ programmed ADC oversampling ratio. 1241 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 1242 */ 1243 #define IS_ADC_OVERSAMPLING_RATIO_ADC3(__RATIO__) (((__RATIO__) == ADC3_OVERSAMPLING_RATIO_2 ) || \ 1244 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_4 ) || \ 1245 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_8 ) || \ 1246 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_16 ) || \ 1247 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_32 ) || \ 1248 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_64 ) || \ 1249 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_128 ) || \ 1250 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_256 )) 1251 #endif /* ADC_VER_V5_V90 */ 1252 1253 /** 1254 * @brief Verify the ADC oversampling shift. 1255 * @param __SHIFT__ programmed ADC oversampling shift. 1256 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 1257 */ 1258 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 1259 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 1260 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 1261 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 1262 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 1263 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 1264 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 1265 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 1266 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ 1267 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ 1268 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ 1269 ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) 1270 1271 /** 1272 * @brief Verify the ADC oversampling triggered mode. 1273 * @param __MODE__ programmed ADC oversampling triggered mode. 1274 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1275 */ 1276 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 1277 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 1278 1279 /** 1280 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 1281 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 1282 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 1283 */ 1284 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 1285 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 1286 1287 /** 1288 * @brief Verify the DFSDM mode configuration. 1289 * @param __HANDLE__ ADC handle. 1290 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 1291 * this reason, the input parameter is the ADC handle and not the configuration parameter 1292 * directly. 1293 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 1294 */ 1295 #if defined(DFSDM1_Channel0) 1296 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 1297 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 1298 #else 1299 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 1300 #endif 1301 1302 /** 1303 * @brief Return the DFSDM configuration mode. 1304 * @param __HANDLE__ ADC handle. 1305 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 1306 * For this reason, the input parameter is the ADC handle and not the configuration parameter 1307 * directly. 1308 * @retval DFSDM configuration mode 1309 */ 1310 #if defined(DFSDM1_Channel0) 1311 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 1312 #else 1313 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 1314 #endif 1315 1316 /** 1317 * @} 1318 */ 1319 1320 1321 /* Exported functions --------------------------------------------------------*/ 1322 /** @addtogroup ADCEx_Exported_Functions 1323 * @{ 1324 */ 1325 1326 /** @addtogroup ADCEx_Exported_Functions_Group1 1327 * @{ 1328 */ 1329 /* IO operation functions *****************************************************/ 1330 1331 /* ADC calibration */ 1332 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); 1333 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 1334 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 1335 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 1336 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 1337 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc); 1338 1339 1340 /* Blocking mode: Polling */ 1341 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 1342 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 1343 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1344 1345 /* Non-blocking mode: Interruption */ 1346 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 1347 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 1348 1349 /* ADC multimode */ 1350 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1351 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1352 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 1353 1354 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1355 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 1356 1357 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 1358 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 1359 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 1360 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 1361 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 1362 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 1363 1364 /* ADC group regular conversions stop */ 1365 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 1366 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 1367 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 1368 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 1369 1370 /** 1371 * @} 1372 */ 1373 1374 /** @addtogroup ADCEx_Exported_Functions_Group2 1375 * @{ 1376 */ 1377 /* Peripheral Control functions ***********************************************/ 1378 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); 1379 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 1380 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 1381 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 1382 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 1383 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 1384 1385 /** 1386 * @} 1387 */ 1388 1389 /** 1390 * @} 1391 */ 1392 1393 /** 1394 * @} 1395 */ 1396 1397 /** 1398 * @} 1399 */ 1400 1401 #ifdef __cplusplus 1402 } 1403 #endif 1404 1405 #endif /* STM32H7xx_HAL_ADC_EX_H */ 1406 1407
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