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0001 /** 0002 ****************************************************************************** 0003 * @file stm32h7xx_hal_adc.h 0004 * @author MCD Application Team 0005 * @brief Header file of ADC HAL module. 0006 ****************************************************************************** 0007 * @attention 0008 * 0009 * Copyright (c) 2017 STMicroelectronics. 0010 * All rights reserved. 0011 * 0012 * This software is licensed under terms that can be found in the LICENSE file 0013 * in the root directory of this software component. 0014 * If no LICENSE file comes with this software, it is provided AS-IS. 0015 * 0016 ****************************************************************************** 0017 */ 0018 0019 /* Define to prevent recursive inclusion -------------------------------------*/ 0020 #ifndef STM32H7xx_HAL_ADC_H 0021 #define STM32H7xx_HAL_ADC_H 0022 0023 #ifdef __cplusplus 0024 extern "C" { 0025 #endif 0026 0027 /* Includes ------------------------------------------------------------------*/ 0028 #include "stm32h7xx_hal_def.h" 0029 0030 /* Include low level driver */ 0031 #include "stm32h7xx_ll_adc.h" 0032 0033 /** @addtogroup STM32H7xx_HAL_Driver 0034 * @{ 0035 */ 0036 0037 /** @addtogroup ADC 0038 * @{ 0039 */ 0040 0041 /* Exported types ------------------------------------------------------------*/ 0042 /** @defgroup ADC_Exported_Types ADC Exported Types 0043 * @ingroup RTEMSBSPsARMSTM32H7 0044 * @{ 0045 */ 0046 0047 /** 0048 * @brief ADC group regular oversampling structure definition 0049 */ 0050 typedef struct 0051 { 0052 uint32_t Ratio; /*!< Configures the oversampling ratio. */ 0053 #if defined(ADC_VER_V5_V90) 0054 /* On devices STM32H72xx and STM32H73xx, this parameter can be a value from 1 to 1023 for ADC1/2 or a value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/ 0055 #else 0056 /*This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 0057 #endif 0058 0059 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 0060 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 0061 0062 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 0063 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 0064 0065 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 0066 The oversampling is either temporary stopped or reset upon an injected 0067 sequence interruption. 0068 If oversampling is enabled on both regular and injected groups, this parameter 0069 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 0070 (the oversampling buffer is zeroed during injection sequence). 0071 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 0072 0073 } ADC_OversamplingTypeDef; 0074 0075 /** 0076 * @brief Structure definition of ADC instance and ADC group regular. 0077 * @note Parameters of this structure are shared within 2 scopes: 0078 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 0079 * ScanConvMode, EOCSelection, LowPowerAutoWait. 0080 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 0081 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 0082 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 0083 * ADC state can be either: 0084 * - For all parameters: ADC disabled 0085 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 0086 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 0087 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 0088 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 0089 * (which fulfills the ADC state condition) on the fly). 0090 */ 0091 typedef struct 0092 { 0093 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 0094 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 0095 Note: The ADC clock configuration is common to all ADC instances. 0096 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 0097 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 0098 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 0099 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 0100 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 0101 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 0102 Note: This parameter can be modified only if all ADC instances are disabled. */ 0103 0104 uint32_t Resolution; /*!< Configure the ADC resolution. 0105 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 0106 0107 #if defined(ADC_VER_V5_V90) 0108 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 0109 Refer to reference manual for alignments formats versus resolutions. 0110 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN 0111 This parameter is reserved for ADC3 on devices STM32H72xx and STM32H73xx*/ 0112 #endif 0113 0114 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 0115 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 0116 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 0117 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 0118 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 0119 Scan direction is upward: from rank 1 to rank 'n'. 0120 This parameter can be a value of @ref ADC_Scan_mode */ 0121 0122 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 0123 This parameter can be a value of @ref ADC_EOCSelection. */ 0124 0125 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 0126 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 0127 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 0128 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 0129 for low frequency applications. 0130 This parameter can be set to ENABLE or DISABLE. 0131 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 0132 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 0133 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 0134 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, 0135 use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 0136 0137 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 0138 after the first ADC conversion start trigger occurred (software start or external trigger). 0139 This parameter can be set to ENABLE or DISABLE. */ 0140 0141 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 0142 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 0143 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 0144 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 0145 continuous mode or external trigger that could launch a conversion). */ 0146 0147 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 0148 (main sequence subdivided in successive parts). 0149 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 0150 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 0151 This parameter can be set to ENABLE or DISABLE. */ 0152 0153 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 0154 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 0155 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 0156 0157 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 0158 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 0159 This parameter can be a value of @ref ADC_regular_external_trigger_source. 0160 Caution: external trigger source is common to all ADC instances. */ 0161 0162 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 0163 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 0164 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 0165 0166 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. 0167 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 0168 This parameter can be a value of @ref ADC_ConversionDataManagement. 0169 Note: This parameter must be modified when no conversion is on going on both regular and injected groups 0170 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).*/ 0171 #if defined(ADC_VER_V5_V90) 0172 /*Note: On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 0173 0174 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. 0175 This parameter can be a value of @ref ADC_regular_sampling_mode. 0176 Note: 0177 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 0178 0179 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 0180 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 0181 This parameter can be set to ENABLE or DISABLE. 0182 Notes: 0183 - In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 0184 - Specific to ADC3 only on devices STM32H72xx and STM32H73xx */ 0185 #endif 0186 0187 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 0188 This parameter applies to ADC group regular only. 0189 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 0190 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 0191 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 0192 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 0193 Note: Error reporting with respect to the conversion mode: 0194 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 0195 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 0196 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 0197 0198 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 0199 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 0200 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 0201 This parameter can be set to ENABLE or DISABLE. 0202 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 0203 0204 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 0205 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 0206 0207 } ADC_InitTypeDef; 0208 0209 /** 0210 * @brief Structure definition of ADC channel for regular group 0211 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 0212 * ADC state can be either: 0213 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 0214 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 0215 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 0216 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 0217 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 0218 * on the fly). 0219 */ 0220 typedef struct 0221 { 0222 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 0223 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 0224 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 0225 0226 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 0227 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 0228 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 0229 the new channel setting (or parameter number of conversions adjusted) */ 0230 0231 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 0232 Unit: ADC clock cycles 0233 Conversion time is the addition of sampling time and processing time 0234 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 0235 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 0236 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 0237 It overwrites the last setting. 0238 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 0239 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 0240 Refer to device datasheet for timings values. */ 0241 0242 uint32_t SingleDiff; /*!< Select single-ended or differential input. 0243 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 0244 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 0245 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 0246 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 0247 It overwrites the last setting. 0248 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 0249 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 0250 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 0251 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 0252 of another parameter update on the fly) */ 0253 0254 uint32_t OffsetNumber; /*!< Select the offset number 0255 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 0256 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 0257 0258 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 0259 Offset value must be a positive number. 0260 Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used). 0261 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024). 0262 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 0263 without continuous mode or external trigger that could launch a conversion). */ 0264 0265 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. 0266 This parameter is applied only for 16-bit or 8-bit resolution. 0267 This parameter can be set to ENABLE or DISABLE.*/ 0268 #if defined(ADC_VER_V5_V90) 0269 uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 0270 This parameter can be a value of @ref ADCEx_OffsetSign. 0271 Note: 0272 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 0273 without continuous mode or external trigger that could launch a conversion). 0274 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0275 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 0276 This parameter value can be ENABLE or DISABLE. 0277 Note: 0278 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 0279 without continuous mode or external trigger that could launch a conversion). 0280 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0281 #endif 0282 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 0283 This parameter is applied only for 16-bit or 8-bit resolution. 0284 This parameter can be set to ENABLE or DISABLE. */ 0285 0286 } ADC_ChannelConfTypeDef; 0287 0288 /** 0289 * @brief Structure definition of ADC analog watchdog 0290 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 0291 * ADC state can be either: 0292 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 0293 */ 0294 typedef struct 0295 { 0296 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 0297 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 0298 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 0299 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 0300 0301 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 0302 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 0303 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 0304 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 0305 0306 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 0307 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 0308 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 0309 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 0310 0311 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 0312 This parameter can be set to ENABLE or DISABLE */ 0313 0314 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 0315 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 0316 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 0317 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 0318 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 0319 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 0320 impacted: the comparison of analog watchdog thresholds is done 0321 on oversampling intermediate computation (after ratio, before shift 0322 application): intermediate register bitfield [32:7] (26 most significant bits). */ 0323 0324 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 0325 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 0326 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 0327 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 0328 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 0329 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 0330 impacted: the comparison of analog watchdog thresholds is done 0331 on oversampling intermediate computation (after ratio, before shift 0332 application): intermediate register bitfield [32:7] (26 most significant bits). */ 0333 #if defined(ADC_VER_V5_V90) 0334 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. 0335 Before setting flag or raising interrupt, analog watchdog can wait to have several 0336 consecutive out-of-window samples. This parameter allows to configure this number. 0337 This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE. 0338 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. */ 0339 #endif 0340 } ADC_AnalogWDGConfTypeDef; 0341 0342 /** 0343 * @brief ADC group injected contexts queue configuration 0344 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 0345 */ 0346 typedef struct 0347 { 0348 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 0349 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 0350 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 0351 0352 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 0353 } ADC_InjectionConfigTypeDef; 0354 0355 /** @defgroup ADC_States ADC States 0356 * @ingroup RTEMSBSPsARMSTM32H7 0357 * @{ 0358 */ 0359 0360 /** 0361 * @brief HAL ADC state machine: ADC states definition (bitfields) 0362 * @note ADC state machine is managed by bitfields, state must be compared 0363 * with bit by bit. 0364 * For example: 0365 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 0366 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 0367 */ 0368 /* States of ADC global scope */ 0369 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 0370 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 0371 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 0372 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 0373 0374 /* States of ADC errors */ 0375 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 0376 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 0377 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 0378 0379 /* States of ADC group regular */ 0380 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 0381 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 0382 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 0383 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 0384 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 0385 0386 /* States of ADC group injected */ 0387 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 0388 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 0389 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 0390 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 0391 0392 /* States of ADC analog watchdogs */ 0393 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 0394 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 0395 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 0396 0397 /* States of ADC multi-mode */ 0398 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 0399 0400 /** 0401 * @} 0402 */ 0403 0404 /** 0405 * @brief ADC handle Structure definition 0406 */ 0407 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 0408 typedef struct __ADC_HandleTypeDef 0409 #else 0410 typedef struct 0411 #endif 0412 { 0413 ADC_TypeDef *Instance; /*!< Register base address */ 0414 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 0415 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 0416 HAL_LockTypeDef Lock; /*!< ADC locking object */ 0417 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 0418 __IO uint32_t ErrorCode; /*!< ADC Error code */ 0419 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 0420 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 0421 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 0422 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 0423 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 0424 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 0425 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 0426 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 0427 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 0428 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 0429 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 0430 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 0431 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 0432 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 0433 } ADC_HandleTypeDef; 0434 0435 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 0436 /** 0437 * @brief HAL ADC Callback ID enumeration definition 0438 */ 0439 typedef enum 0440 { 0441 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 0442 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 0443 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 0444 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 0445 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 0446 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 0447 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 0448 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 0449 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 0450 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 0451 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 0452 } HAL_ADC_CallbackIDTypeDef; 0453 0454 /** 0455 * @brief HAL ADC Callback pointer definition 0456 */ 0457 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 0458 0459 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 0460 0461 /** 0462 * @} 0463 */ 0464 0465 0466 /* Exported constants --------------------------------------------------------*/ 0467 0468 /** @defgroup ADC_Exported_Constants ADC Exported Constants 0469 * @ingroup RTEMSBSPsARMSTM32H7 0470 * @{ 0471 */ 0472 0473 /** @defgroup ADC_Error_Code ADC Error Code 0474 * @ingroup RTEMSBSPsARMSTM32H7 0475 * @{ 0476 */ 0477 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 0478 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 0479 enable/disable, erroneous state, ...) */ 0480 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 0481 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 0482 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 0483 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 0484 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 0485 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 0486 /** 0487 * @} 0488 */ 0489 0490 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 0491 * @ingroup RTEMSBSPsARMSTM32H7 0492 * @{ 0493 */ 0494 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 0495 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 0496 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 0497 0498 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 0499 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 0500 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 0501 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 0502 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 0503 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 0504 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 0505 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 0506 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 0507 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 0508 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 0509 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 0510 /** 0511 * @} 0512 */ 0513 0514 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 0515 * @ingroup RTEMSBSPsARMSTM32H7 0516 * @{ 0517 */ 0518 #define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0519 #define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0520 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 0521 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 0522 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 0523 0524 #if defined (ADC_VER_V5_X) 0525 #define ADC_RESOLUTION_14B_OPT (LL_ADC_RESOLUTION_14B_OPT) /*!< ADC resolution 14 bits optimized for power consumption, available on for devices revision V only */ 0526 #define ADC_RESOLUTION_12B_OPT (LL_ADC_RESOLUTION_12B_OPT) /*!< ADC resolution 12 bits optimized for power consumption, available on for devices revision V only */ 0527 #endif 0528 0529 #if defined(ADC_VER_V5_V90) 0530 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0531 #endif /* ADC_VER_V5_V90 */ 0532 /** 0533 * @} 0534 */ 0535 0536 #if defined(ADC_VER_V5_V90) 0537 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 0538 * @ingroup RTEMSBSPsARMSTM32H7 0539 * @{ 0540 */ 0541 #define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 0542 #define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 0543 /** 0544 * @} 0545 */ 0546 #endif 0547 0548 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 0549 * @ingroup RTEMSBSPsARMSTM32H7 0550 * @{ 0551 */ 0552 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 0553 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 0554 /** 0555 * @} 0556 */ 0557 0558 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 0559 * @ingroup RTEMSBSPsARMSTM32H7 0560 * @{ 0561 */ 0562 /* ADC group regular trigger sources for all ADC instances */ 0563 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 0564 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0565 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0566 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0567 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0568 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 0569 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0570 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */ 0571 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 0572 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 0573 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 0574 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 0575 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 0576 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 0577 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 0578 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 0579 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 0580 #define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */ 0581 #define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */ 0582 #define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 0583 #define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 0584 #define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */ 0585 #if defined(TIM23) 0586 #define ADC_EXTERNALTRIG_T23_TRGO (LL_ADC_REG_TRIG_EXT_TIM23_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM23 TRGO event. Trigger edge set to rising edge (default setting). */ 0587 #endif /*TIM23*/ 0588 #if defined(TIM24) 0589 #define ADC_EXTERNALTRIG_T24_TRGO (LL_ADC_REG_TRIG_EXT_TIM24_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM24 TRGO event. Trigger edge set to rising edge (default setting). */ 0590 #endif /*TIM24*/ 0591 /** 0592 * @} 0593 */ 0594 0595 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 0596 * @ingroup RTEMSBSPsARMSTM32H7 0597 * @{ 0598 */ 0599 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 0600 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 0601 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 0602 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 0603 /** 0604 * @} 0605 */ 0606 #if defined(ADC_VER_V5_V90) 0607 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode 0608 * @ingroup RTEMSBSPsARMSTM32H7 0609 * @{ 0610 */ 0611 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ 0612 #define ADC_SAMPLING_MODE_BULB (ADC3_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event. 0613 Notes: 0614 - First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) 0615 - Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0616 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC3_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events: 0617 Trigger rising edge = start sampling 0618 Trigger falling edge = stop sampling and start conversion 0619 Note: Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0620 /** 0621 * @} 0622 */ 0623 #endif 0624 0625 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 0626 * @ingroup RTEMSBSPsARMSTM32H7 0627 * @{ 0628 */ 0629 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 0630 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 0631 /** 0632 * @} 0633 */ 0634 0635 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 0636 * @ingroup RTEMSBSPsARMSTM32H7 0637 * @{ 0638 */ 0639 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 0640 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 0641 /** 0642 * @} 0643 */ 0644 0645 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 0646 * @ingroup RTEMSBSPsARMSTM32H7 0647 * @{ 0648 */ 0649 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 0650 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 0651 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 0652 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 0653 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 0654 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 0655 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 0656 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 0657 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 0658 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 0659 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 0660 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 0661 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 0662 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 0663 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 0664 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 0665 /** 0666 * @} 0667 */ 0668 0669 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 0670 * @ingroup RTEMSBSPsARMSTM32H7 0671 * @{ 0672 */ 0673 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0674 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0675 #define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0676 #define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0677 #define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0678 #define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0679 #define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0680 #define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC1, ADC2 */ 0681 /** 0682 * @} 0683 */ 0684 #if defined(ADC_VER_V5_V90) 0685 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 0686 * @ingroup RTEMSBSPsARMSTM32H7 0687 * @{ 0688 */ 0689 #define ADC3_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0690 #define ADC3_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0691 #define ADC3_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0692 #define ADC3_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0693 #define ADC3_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0694 #define ADC3_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0695 #define ADC3_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0696 #define ADC3_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_ADC3_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles, On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0697 #define ADC3_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_ADC3_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. 0698 On devices STM32H72xx and STM32H73xx, parameter available only on ADC instance: ADC3 */ 0699 /** 0700 * @} 0701 */ 0702 #endif 0703 0704 /** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode 0705 * @ingroup RTEMSBSPsARMSTM32H7 0706 * @{ 0707 */ 0708 #define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET) 0709 #define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY) 0710 /** 0711 * @} 0712 */ 0713 0714 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 0715 * @ingroup RTEMSBSPsARMSTM32H7 0716 * @{ 0717 */ 0718 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 0719 /* all ADC instances (refer to Reference Manual). */ 0720 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 0721 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 0722 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 0723 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 0724 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 0725 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 0726 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 0727 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 0728 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 0729 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 0730 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 0731 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 0732 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 0733 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 0734 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 0735 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 0736 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 0737 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 0738 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 0739 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 0740 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */ 0741 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */ 0742 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */ 0743 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 0744 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 0745 #if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2) 0746 #define ADC_CHANNEL_DAC2CH1_ADC2 (LL_ADC_CHANNEL_DAC2CH1_ADC2) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */ 0747 #endif 0748 /** 0749 * @} 0750 */ 0751 0752 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 0753 * @ingroup RTEMSBSPsARMSTM32H7 0754 * @{ 0755 */ 0756 #define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */ 0757 #define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ 0758 #define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ 0759 #define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */ 0760 /** 0761 * @} 0762 */ 0763 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 0764 * @ingroup RTEMSBSPsARMSTM32H7 0765 * @{ 0766 */ 0767 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 0768 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 0769 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 0770 /** 0771 * @} 0772 */ 0773 0774 #if defined(ADC_VER_V5_V90) 0775 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration 0776 * @ingroup RTEMSBSPsARMSTM32H7 0777 * @{ 0778 */ 0779 #define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0780 #define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0781 #define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0782 #define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0783 #define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0784 #define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0785 #define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0786 #define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0787 /** 0788 * @} 0789 */ 0790 #endif 0791 0792 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 0793 * @ingroup RTEMSBSPsARMSTM32H7 0794 * @{ 0795 */ 0796 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 0797 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 0798 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 0799 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 0800 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 0801 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 0802 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 0803 /** 0804 * @} 0805 */ 0806 #if defined(ADC_VER_V5_V90) 0807 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 0808 * @ingroup RTEMSBSPsARMSTM32H7 0809 * @{ 0810 */ 0811 #define ADC3_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0812 #define ADC3_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0813 #define ADC3_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0814 #define ADC3_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0815 #define ADC3_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0816 #define ADC3_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0817 #define ADC3_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0818 #define ADC3_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0819 #define ADC3_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0820 #define ADC3_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift). Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ 0821 /** 0822 * @} 0823 */ 0824 #endif 0825 0826 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 0827 * @ingroup RTEMSBSPsARMSTM32H7 0828 * @{ 0829 */ 0830 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 0831 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 0832 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 0833 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 0834 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 0835 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 0836 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 0837 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 0838 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 0839 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */ 0840 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */ 0841 #define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */ 0842 /** 0843 * @} 0844 */ 0845 0846 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 0847 * @ingroup RTEMSBSPsARMSTM32H7 0848 * @{ 0849 */ 0850 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 0851 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 0852 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 0853 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 0854 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 0855 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 0856 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 0857 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 0858 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 0859 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 0860 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 0861 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 0862 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 0863 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 0864 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 0865 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 0866 /** 0867 * @} 0868 */ 0869 0870 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 0871 * @ingroup RTEMSBSPsARMSTM32H7 0872 * @{ 0873 */ 0874 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 0875 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 0876 /** 0877 * @} 0878 */ 0879 0880 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 0881 * @ingroup RTEMSBSPsARMSTM32H7 0882 * @{ 0883 */ 0884 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 0885 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 0886 /** 0887 * @} 0888 */ 0889 0890 0891 /** @defgroup ADC_Event_type ADC Event type 0892 * @ingroup RTEMSBSPsARMSTM32H7 0893 * @{ 0894 */ 0895 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 0896 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 0897 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 0898 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 0899 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 0900 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 0901 /** 0902 * @} 0903 */ 0904 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 0905 0906 /** @defgroup ADC_interrupts_definition ADC interrupts definition 0907 * @ingroup RTEMSBSPsARMSTM32H7 0908 * @{ 0909 */ 0910 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 0911 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 0912 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 0913 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 0914 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 0915 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 0916 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 0917 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 0918 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 0919 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 0920 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 0921 0922 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 0923 0924 /** 0925 * @} 0926 */ 0927 0928 /** @defgroup ADC_flags_definition ADC flags definition 0929 * @ingroup RTEMSBSPsARMSTM32H7 0930 * @{ 0931 */ 0932 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 0933 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 0934 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 0935 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 0936 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 0937 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 0938 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 0939 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 0940 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 0941 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 0942 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 0943 #define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC LDO output voltage ready bit */ 0944 /** 0945 * @} 0946 */ 0947 0948 /** 0949 * @} 0950 */ 0951 0952 /* Private macro -------------------------------------------------------------*/ 0953 0954 /** @defgroup ADC_Private_Macros ADC Private Macros 0955 * @ingroup RTEMSBSPsARMSTM32H7 0956 * @{ 0957 */ 0958 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 0959 /* code of final user. */ 0960 0961 /** 0962 * @brief Verify the ADC data conversion setting. 0963 * @param DATA : programmed DATA conversion mode. 0964 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 0965 */ 0966 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 0967 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 0968 (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \ 0969 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 0970 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 0971 0972 /** 0973 * @brief Return resolution bits in CFGR register RES[1:0] field. 0974 * @param __HANDLE__ ADC handle 0975 * @retval Value of bitfield RES in CFGR register. 0976 */ 0977 #define ADC_GET_RESOLUTION(__HANDLE__) \ 0978 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 0979 0980 /** 0981 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 0982 * @param __HANDLE__ ADC handle 0983 * @retval None 0984 */ 0985 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 0986 0987 /** 0988 * @brief Verification of ADC state: enabled or disabled. 0989 * @param __HANDLE__ ADC handle 0990 * @retval SET (ADC enabled) or RESET (ADC disabled) 0991 */ 0992 #define ADC_IS_ENABLE(__HANDLE__) \ 0993 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 0994 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 0995 ) ? SET : RESET) 0996 0997 /** 0998 * @brief Check if conversion is on going on regular group. 0999 * @param __HANDLE__ ADC handle 1000 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 1001 */ 1002 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 1003 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 1004 1005 /** 1006 * @brief Check if ADC clock mode is synchronous 1007 * @param __HANDLE__: ADC handle 1008 * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous) 1009 */ 1010 #if defined (ADC3) 1011 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \ 1012 (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \ 1013 ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) \ 1014 :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL)) 1015 #else 1016 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL) 1017 1018 #endif 1019 1020 /** 1021 * @brief Simultaneously clear and set specific bits of the handle State. 1022 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 1023 * the first parameter is the ADC handle State, the second parameter is the 1024 * bit field to clear, the third and last parameter is the bit field to set. 1025 * @retval None 1026 */ 1027 #define ADC_STATE_CLR_SET MODIFY_REG 1028 1029 /** 1030 * @brief Verify that a given value is aligned with the ADC resolution range. 1031 * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits). 1032 * @param __ADC_VALUE__ value checked against the resolution. 1033 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1034 */ 1035 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1036 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 1037 1038 #if defined(ADC_VER_V5_V90) 1039 /** 1040 * @brief Verify that a given value is aligned with the ADC resolution range. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. 1041 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 1042 * @param __ADC_VALUE__ value checked against the resolution. 1043 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 1044 */ 1045 #define IS_ADC3_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 1046 ((__ADC_VALUE__) <= __LL_ADC3_DIGITAL_SCALE(__RESOLUTION__)) 1047 #endif 1048 /** 1049 * @brief Verify the length of the scheduled regular conversions group. 1050 * @param __LENGTH__ number of programmed conversions. 1051 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 1052 */ 1053 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 1054 1055 1056 /** 1057 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 1058 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 1059 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 1060 */ 1061 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 1062 1063 1064 /** 1065 * @brief Verify the ADC clock setting. 1066 * @param __ADC_CLOCK__ programmed ADC clock. 1067 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 1068 */ 1069 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 1070 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 1071 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 1072 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 1073 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 1074 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 1075 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 1076 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 1077 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 1078 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 1079 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 1080 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 1081 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 1082 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 1083 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 1084 1085 /** 1086 * @brief Verify the ADC resolution setting. 1087 * @param __RESOLUTION__ programmed ADC resolution. 1088 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1089 */ 1090 #if defined(ADC_VER_V5_V90) 1091 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 1092 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 1093 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1094 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1095 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 1096 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 1097 #elif defined (ADC_VER_V5_X) 1098 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 1099 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 1100 ((__RESOLUTION__) == ADC_RESOLUTION_14B_OPT) || \ 1101 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1102 ((__RESOLUTION__) == ADC_RESOLUTION_12B_OPT) || \ 1103 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1104 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 1105 #else /* ADC_VER_V5_3 */ 1106 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 1107 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 1108 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 1109 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 1110 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 1111 #endif /* ADC_VER_V5_V90*/ 1112 1113 /** 1114 * @brief Verify the ADC resolution setting when limited to 8 bits. 1115 * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits. 1116 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 1117 */ 1118 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B)) 1119 1120 #if defined(ADC_VER_V5_V90) 1121 /** 1122 * @brief Verify the ADC converted data alignment. Applicable for ADC3 on devices STM32H72xx and STM32H73xx. 1123 * @param __ALIGN__ programmed ADC converted data alignment. 1124 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 1125 */ 1126 #define IS_ADC3_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC3_DATAALIGN_RIGHT) || \ 1127 ((__ALIGN__) == ADC3_DATAALIGN_LEFT) ) 1128 1129 /** 1130 * @brief Verify the ADC regular conversions external trigger. 1131 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger. 1132 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid) 1133 */ 1134 #define IS_ADC3_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \ 1135 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \ 1136 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) ) 1137 1138 #endif 1139 1140 /** 1141 * @brief Verify the ADC scan mode. 1142 * @param __SCAN_MODE__ programmed ADC scan mode. 1143 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 1144 */ 1145 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 1146 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 1147 1148 /** 1149 * @brief Verify the ADC edge trigger setting for regular group. 1150 * @param __EDGE__ programmed ADC edge trigger setting. 1151 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 1152 */ 1153 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 1154 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 1155 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 1156 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 1157 1158 /** 1159 * @brief Verify the ADC regular conversions external trigger. 1160 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 1161 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 1162 */ 1163 #if defined(ADC_VER_V5_V90) 1164 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1165 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1166 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1167 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1168 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1169 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1170 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1171 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1172 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1173 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1174 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1175 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1176 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1177 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1178 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1179 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1180 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \ 1181 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \ 1182 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 1183 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 1184 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 1185 ((__REGTRIG__) == ADC_EXTERNALTRIG_T23_TRGO) || \ 1186 ((__REGTRIG__) == ADC_EXTERNALTRIG_T24_TRGO) || \ 1187 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1188 #else 1189 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 1190 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 1191 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 1192 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 1193 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 1194 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 1195 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 1196 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 1197 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 1198 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 1199 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 1200 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 1201 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 1202 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 1203 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 1204 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 1205 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \ 1206 ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \ 1207 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 1208 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 1209 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 1210 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 1211 #endif /* ADC_VER_V5_V90*/ 1212 1213 1214 /** 1215 * @brief Verify the ADC regular conversions check for converted data availability. 1216 * @param __EOC_SELECTION__ converted data availability check. 1217 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 1218 */ 1219 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 1220 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 1221 1222 /** 1223 * @brief Verify the ADC regular conversions overrun handling. 1224 * @param __OVR__ ADC regular conversions overrun handling. 1225 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 1226 */ 1227 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 1228 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 1229 1230 /** 1231 * @brief Verify the ADC conversions sampling time. 1232 * @param __TIME__ ADC conversions sampling time. 1233 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 1234 */ 1235 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 1236 ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 1237 ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \ 1238 ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \ 1239 ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \ 1240 ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \ 1241 ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \ 1242 ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) ) 1243 1244 /** 1245 * @brief Verify the ADC regular channel setting. 1246 * @param __CHANNEL__ programmed ADC regular channel. 1247 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 1248 */ 1249 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 1250 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 1251 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 1252 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 1253 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 1254 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 1255 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 1256 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 1257 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 1258 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 1259 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 1260 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 1261 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1262 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1263 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1264 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1265 1266 /** 1267 * @} 1268 */ 1269 1270 1271 /* Private constants ---------------------------------------------------------*/ 1272 1273 /** @defgroup ADC_Private_Constants ADC Private Constants 1274 * @ingroup RTEMSBSPsARMSTM32H7 1275 * @{ 1276 */ 1277 1278 /* Fixed timeout values for ADC conversion (including sampling time) */ 1279 /* Maximum sampling time is 810.5 ADC clock cycle */ 1280 /* Maximum conversion time is 16.5 + Maximum sampling time */ 1281 /* or 16.5 + 810.5 = 827 ADC clock cycles */ 1282 /* Minimum ADC Clock frequency is 0.35 MHz */ 1283 /* Maximum conversion time is */ 1284 /* 827 / 0.35 MHz = 2.36 ms */ 1285 1286 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1287 1288 /* Delay for temperature sensor stabilization time. */ 1289 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1290 /* Unit: us */ 1291 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1292 1293 /* Delay for ADC voltage regulator startup time */ 1294 /* Maximum delay is 10 microseconds */ 1295 /* (refer device RM, parameter Tadcvreg_stup). */ 1296 #define ADC_STAB_DELAY_US (10UL) /*!< ADC voltage regulator startup time */ 1297 1298 /** 1299 * @} 1300 */ 1301 1302 /* Exported macro ------------------------------------------------------------*/ 1303 1304 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1305 * @ingroup RTEMSBSPsARMSTM32H7 1306 * @{ 1307 */ 1308 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1309 /* final user. */ 1310 1311 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1312 * @ingroup RTEMSBSPsARMSTM32H7 1313 * @{ 1314 */ 1315 1316 /** @brief Reset ADC handle state. 1317 * @param __HANDLE__ ADC handle 1318 * @retval None 1319 */ 1320 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1321 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1322 do{ \ 1323 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1324 (__HANDLE__)->MspInitCallback = NULL; \ 1325 (__HANDLE__)->MspDeInitCallback = NULL; \ 1326 } while(0) 1327 #else 1328 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1329 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1330 #endif 1331 1332 /** 1333 * @brief Enable ADC interrupt. 1334 * @param __HANDLE__ ADC handle 1335 * @param __INTERRUPT__ ADC Interrupt 1336 * This parameter can be one of the following values: 1337 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1338 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1339 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1340 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1341 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1342 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1343 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1344 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1345 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1346 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1347 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1348 * @retval None 1349 */ 1350 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1351 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1352 1353 /** 1354 * @brief Disable ADC interrupt. 1355 * @param __HANDLE__ ADC handle 1356 * @param __INTERRUPT__ ADC Interrupt 1357 * This parameter can be one of the following values: 1358 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1359 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1360 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1361 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1362 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1363 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1364 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1365 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1366 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1367 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1368 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1369 * @retval None 1370 */ 1371 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1372 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1373 1374 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1375 * @param __HANDLE__ ADC handle 1376 * @param __INTERRUPT__ ADC interrupt source to check 1377 * This parameter can be one of the following values: 1378 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1379 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1380 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1381 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1382 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1383 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1384 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1385 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1386 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1387 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1388 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1389 * @retval State of interruption (SET or RESET) 1390 */ 1391 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1392 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1393 1394 /** 1395 * @brief Check whether the specified ADC flag is set or not. 1396 * @param __HANDLE__ ADC handle 1397 * @param __FLAG__ ADC flag 1398 * This parameter can be one of the following values: 1399 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1400 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1401 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1402 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1403 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1404 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1405 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1406 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1407 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1408 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1409 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag 1410 * @arg @ref ADC_FLAG_LDORDY ADC LDO output voltage ready bit. 1411 * @retval State of flag (TRUE or FALSE). 1412 */ 1413 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1414 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1415 1416 /** 1417 * @brief Clear the specified ADC flag. 1418 * @param __HANDLE__ ADC handle 1419 * @param __FLAG__ ADC flag 1420 * This parameter can be one of the following values: 1421 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1422 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1423 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1424 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1425 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1426 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1427 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1428 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1429 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1430 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1431 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1432 * @retval None 1433 */ 1434 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1435 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1436 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1437 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1443 * @ingroup RTEMSBSPsARMSTM32H7 1444 * @{ 1445 */ 1446 1447 /** 1448 * @brief Helper macro to get ADC channel number in decimal format 1449 * from literals ADC_CHANNEL_x. 1450 * @note Example: 1451 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1452 * will return decimal number "4". 1453 * @note The input can be a value from functions where a channel 1454 * number is returned, either defined with number 1455 * or with bitfield (only one bit must be set). 1456 * @param __CHANNEL__ This parameter can be one of the following values: 1457 * @arg @ref ADC_CHANNEL_0 (3) 1458 * @arg @ref ADC_CHANNEL_1 (3) 1459 * @arg @ref ADC_CHANNEL_2 (3) 1460 * @arg @ref ADC_CHANNEL_3 (3) 1461 * @arg @ref ADC_CHANNEL_4 (3) 1462 * @arg @ref ADC_CHANNEL_5 (3) 1463 * @arg @ref ADC_CHANNEL_6 1464 * @arg @ref ADC_CHANNEL_7 1465 * @arg @ref ADC_CHANNEL_8 1466 * @arg @ref ADC_CHANNEL_9 1467 * @arg @ref ADC_CHANNEL_10 1468 * @arg @ref ADC_CHANNEL_11 1469 * @arg @ref ADC_CHANNEL_12 1470 * @arg @ref ADC_CHANNEL_13 1471 * @arg @ref ADC_CHANNEL_14 1472 * @arg @ref ADC_CHANNEL_15 1473 * @arg @ref ADC_CHANNEL_16 1474 * @arg @ref ADC_CHANNEL_17 1475 * @arg @ref ADC_CHANNEL_18 1476 * @arg @ref ADC_CHANNEL_VREFINT (1) 1477 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1478 * @arg @ref ADC_CHANNEL_VBAT (1) 1479 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 1480 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 1481 * 1482 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 1483 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 1484 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1485 * Other channels are slow channels (conversion rate: refer to reference manual). 1486 * @retval Value between Min_Data=0 and Max_Data=18 1487 */ 1488 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1489 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1490 1491 /** 1492 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1493 * from number in decimal format. 1494 * @note Example: 1495 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1496 * will return a data equivalent to "ADC_CHANNEL_4". 1497 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1498 * @retval Returned value can be one of the following values: 1499 * @arg @ref ADC_CHANNEL_0 (3) 1500 * @arg @ref ADC_CHANNEL_1 (3) 1501 * @arg @ref ADC_CHANNEL_2 (3) 1502 * @arg @ref ADC_CHANNEL_3 (3) 1503 * @arg @ref ADC_CHANNEL_4 (3) 1504 * @arg @ref ADC_CHANNEL_5 (3) 1505 * @arg @ref ADC_CHANNEL_6 1506 * @arg @ref ADC_CHANNEL_7 1507 * @arg @ref ADC_CHANNEL_8 1508 * @arg @ref ADC_CHANNEL_9 1509 * @arg @ref ADC_CHANNEL_10 1510 * @arg @ref ADC_CHANNEL_11 1511 * @arg @ref ADC_CHANNEL_12 1512 * @arg @ref ADC_CHANNEL_13 1513 * @arg @ref ADC_CHANNEL_14 1514 * @arg @ref ADC_CHANNEL_15 1515 * @arg @ref ADC_CHANNEL_16 1516 * @arg @ref ADC_CHANNEL_17 1517 * @arg @ref ADC_CHANNEL_18 1518 * @arg @ref ADC_CHANNEL_VREFINT (1) 1519 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1520 * @arg @ref ADC_CHANNEL_VBAT (1) 1521 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 1522 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 1523 * 1524 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 1525 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 1526 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1527 * Other channels are slow channels (conversion rate: refer to reference manual).\n 1528 * (1, 2) For ADC channel read back from ADC register, 1529 * comparison with internal channel parameter to be done 1530 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1531 */ 1532 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1533 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1534 1535 /** 1536 * @brief Helper macro to determine whether the selected channel 1537 * corresponds to literal definitions of driver. 1538 * @note The different literal definitions of ADC channels are: 1539 * - ADC internal channel: 1540 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1541 * - ADC external channel (channel connected to a GPIO pin): 1542 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1543 * @note The channel parameter must be a value defined from literal 1544 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1545 * ADC_CHANNEL_TEMPSENSOR, ...), 1546 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1547 * must not be a value from functions where a channel number is 1548 * returned from ADC registers, 1549 * because internal and external channels share the same channel 1550 * number in ADC registers. The differentiation is made only with 1551 * parameters definitions of driver. 1552 * @param __CHANNEL__ This parameter can be one of the following values: 1553 * @arg @ref ADC_CHANNEL_0 (3) 1554 * @arg @ref ADC_CHANNEL_1 (3) 1555 * @arg @ref ADC_CHANNEL_2 (3) 1556 * @arg @ref ADC_CHANNEL_3 (3) 1557 * @arg @ref ADC_CHANNEL_4 (3) 1558 * @arg @ref ADC_CHANNEL_5 (3) 1559 * @arg @ref ADC_CHANNEL_6 1560 * @arg @ref ADC_CHANNEL_7 1561 * @arg @ref ADC_CHANNEL_8 1562 * @arg @ref ADC_CHANNEL_9 1563 * @arg @ref ADC_CHANNEL_10 1564 * @arg @ref ADC_CHANNEL_11 1565 * @arg @ref ADC_CHANNEL_12 1566 * @arg @ref ADC_CHANNEL_13 1567 * @arg @ref ADC_CHANNEL_14 1568 * @arg @ref ADC_CHANNEL_15 1569 * @arg @ref ADC_CHANNEL_16 1570 * @arg @ref ADC_CHANNEL_17 1571 * @arg @ref ADC_CHANNEL_18 1572 * @arg @ref ADC_CHANNEL_VREFINT (1) 1573 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1574 * @arg @ref ADC_CHANNEL_VBAT (1) 1575 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 1576 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 1577 * 1578 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 1579 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 1580 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1581 * Other channels are slow channels (conversion rate: refer to reference manual). 1582 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1583 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1584 */ 1585 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1586 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1587 1588 /** 1589 * @brief Helper macro to convert a channel defined from parameter 1590 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1591 * ADC_CHANNEL_TEMPSENSOR, ...), 1592 * to its equivalent parameter definition of a ADC external channel 1593 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1594 * @note The channel parameter can be, additionally to a value 1595 * defined from parameter definition of a ADC internal channel 1596 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1597 * a value defined from parameter definition of 1598 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1599 * or a value from functions where a channel number is returned 1600 * from ADC registers. 1601 * @param __CHANNEL__ This parameter can be one of the following values: 1602 * @arg @ref ADC_CHANNEL_0 (3) 1603 * @arg @ref ADC_CHANNEL_1 (3) 1604 * @arg @ref ADC_CHANNEL_2 (3) 1605 * @arg @ref ADC_CHANNEL_3 (3) 1606 * @arg @ref ADC_CHANNEL_4 (3) 1607 * @arg @ref ADC_CHANNEL_5 (3) 1608 * @arg @ref ADC_CHANNEL_6 1609 * @arg @ref ADC_CHANNEL_7 1610 * @arg @ref ADC_CHANNEL_8 1611 * @arg @ref ADC_CHANNEL_9 1612 * @arg @ref ADC_CHANNEL_10 1613 * @arg @ref ADC_CHANNEL_11 1614 * @arg @ref ADC_CHANNEL_12 1615 * @arg @ref ADC_CHANNEL_13 1616 * @arg @ref ADC_CHANNEL_14 1617 * @arg @ref ADC_CHANNEL_15 1618 * @arg @ref ADC_CHANNEL_16 1619 * @arg @ref ADC_CHANNEL_17 1620 * @arg @ref ADC_CHANNEL_18 1621 * @arg @ref ADC_CHANNEL_VREFINT (1) 1622 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1623 * @arg @ref ADC_CHANNEL_VBAT (1) 1624 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 1625 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 1626 * 1627 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 1628 * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n 1629 * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1630 * Other channels are slow channels (conversion rate: refer to reference manual). 1631 * @retval Returned value can be one of the following values: 1632 * @arg @ref ADC_CHANNEL_0 1633 * @arg @ref ADC_CHANNEL_1 1634 * @arg @ref ADC_CHANNEL_2 1635 * @arg @ref ADC_CHANNEL_3 1636 * @arg @ref ADC_CHANNEL_4 1637 * @arg @ref ADC_CHANNEL_5 1638 * @arg @ref ADC_CHANNEL_6 1639 * @arg @ref ADC_CHANNEL_7 1640 * @arg @ref ADC_CHANNEL_8 1641 * @arg @ref ADC_CHANNEL_9 1642 * @arg @ref ADC_CHANNEL_10 1643 * @arg @ref ADC_CHANNEL_11 1644 * @arg @ref ADC_CHANNEL_12 1645 * @arg @ref ADC_CHANNEL_13 1646 * @arg @ref ADC_CHANNEL_14 1647 * @arg @ref ADC_CHANNEL_15 1648 * @arg @ref ADC_CHANNEL_16 1649 * @arg @ref ADC_CHANNEL_17 1650 * @arg @ref ADC_CHANNEL_18 1651 */ 1652 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1653 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1654 1655 /** 1656 * @brief Helper macro to determine whether the internal channel 1657 * selected is available on the ADC instance selected. 1658 * @note The channel parameter must be a value defined from parameter 1659 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1660 * ADC_CHANNEL_TEMPSENSOR, ...), 1661 * must not be a value defined from parameter definition of 1662 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1663 * or a value from functions where a channel number is 1664 * returned from ADC registers, 1665 * because internal and external channels share the same channel 1666 * number in ADC registers. The differentiation is made only with 1667 * parameters definitions of driver. 1668 * @param __ADC_INSTANCE__ ADC instance 1669 * @param __CHANNEL__ This parameter can be one of the following values: 1670 * @arg @ref ADC_CHANNEL_VREFINT (1) 1671 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1672 * @arg @ref ADC_CHANNEL_VBAT (1) 1673 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2) 1674 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2) 1675 * 1676 * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n 1677 * (2) On STM32H7, parameter available only on ADC instance: ADC2. 1678 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1679 * Value "1" if the internal channel selected is available on the ADC instance selected. 1680 */ 1681 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1682 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1683 1684 /** 1685 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1686 * or ADC slave from raw value with both ADC conversion data concatenated. 1687 * @note This macro is intended to be used when multimode transfer by DMA 1688 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1689 * In this case the transferred data need to processed with this macro 1690 * to separate the conversion data of ADC master and ADC slave. 1691 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1692 * @arg @ref LL_ADC_MULTI_MASTER 1693 * @arg @ref LL_ADC_MULTI_SLAVE 1694 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1695 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1696 */ 1697 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1698 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1699 1700 /** 1701 * @brief Helper macro to select the ADC common instance 1702 * to which is belonging the selected ADC instance. 1703 * @note ADC common register instance can be used for: 1704 * - Set parameters common to several ADC instances 1705 * - Multimode (for devices with several ADC instances) 1706 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1707 * @param __ADCx__ ADC instance 1708 * @retval ADC common register instance 1709 */ 1710 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1711 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1712 1713 /** 1714 * @brief Helper macro to check if all ADC instances sharing the same 1715 * ADC common instance are disabled. 1716 * @note This check is required by functions with setting conditioned to 1717 * ADC state: 1718 * All ADC instances of the ADC common group must be disabled. 1719 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1720 * @note On devices with only 1 ADC common instance, parameter of this macro 1721 * is useless and can be ignored (parameter kept for compatibility 1722 * with devices featuring several ADC common instances). 1723 * @param __ADCXY_COMMON__ ADC common instance 1724 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1725 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1726 * are disabled. 1727 * Value "1" if at least one ADC instance sharing the same ADC common instance 1728 * is enabled. 1729 */ 1730 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1731 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1732 1733 /** 1734 * @brief Helper macro to define the ADC conversion data full-scale digital 1735 * value corresponding to the selected ADC resolution. 1736 * @note ADC conversion data full-scale corresponds to voltage range 1737 * determined by analog voltage references Vref+ and Vref- 1738 * (refer to reference manual). 1739 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1740 * @arg @ref ADC_RESOLUTION_16B 1741 * @arg @ref ADC_RESOLUTION_14B 1742 * @arg @ref ADC_RESOLUTION_12B 1743 * @arg @ref ADC_RESOLUTION_10B 1744 * @arg @ref ADC_RESOLUTION_8B 1745 * @retval ADC conversion data full-scale digital value 1746 */ 1747 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1748 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1749 1750 /** 1751 * @brief Helper macro to convert the ADC conversion data from 1752 * a resolution to another resolution. 1753 * @param __DATA__ ADC conversion data to be converted 1754 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1755 * This parameter can be one of the following values: 1756 * @arg @ref ADC_RESOLUTION_16B 1757 * @arg @ref ADC_RESOLUTION_14B 1758 * @arg @ref ADC_RESOLUTION_12B 1759 * @arg @ref ADC_RESOLUTION_10B 1760 * @arg @ref ADC_RESOLUTION_8B 1761 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1762 * This parameter can be one of the following values: 1763 * @arg @ref ADC_RESOLUTION_16B 1764 * @arg @ref ADC_RESOLUTION_14B 1765 * @arg @ref ADC_RESOLUTION_12B 1766 * @arg @ref ADC_RESOLUTION_10B 1767 * @arg @ref ADC_RESOLUTION_8B 1768 * @retval ADC conversion data to the requested resolution 1769 */ 1770 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1771 __ADC_RESOLUTION_CURRENT__,\ 1772 __ADC_RESOLUTION_TARGET__) \ 1773 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1774 (__ADC_RESOLUTION_CURRENT__),\ 1775 (__ADC_RESOLUTION_TARGET__)) 1776 1777 /** 1778 * @brief Helper macro to calculate the voltage (unit: mVolt) 1779 * corresponding to a ADC conversion data (unit: digital value). 1780 * @note Analog reference voltage (Vref+) must be either known from 1781 * user board environment or can be calculated using ADC measurement 1782 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1783 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1784 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1785 * (unit: digital value). 1786 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1787 * @arg @ref ADC_RESOLUTION_16B 1788 * @arg @ref ADC_RESOLUTION_14B 1789 * @arg @ref ADC_RESOLUTION_12B 1790 * @arg @ref ADC_RESOLUTION_10B 1791 * @arg @ref ADC_RESOLUTION_8B 1792 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1793 */ 1794 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1795 __ADC_DATA__,\ 1796 __ADC_RESOLUTION__) \ 1797 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1798 (__ADC_DATA__),\ 1799 (__ADC_RESOLUTION__)) 1800 1801 /** 1802 * @brief Helper macro to calculate analog reference voltage (Vref+) 1803 * (unit: mVolt) from ADC conversion data of internal voltage 1804 * reference VrefInt. 1805 * @note Computation is using VrefInt calibration value 1806 * stored in system memory for each device during production. 1807 * @note This voltage depends on user board environment: voltage level 1808 * connected to pin Vref+. 1809 * On devices with small package, the pin Vref+ is not present 1810 * and internally bonded to pin Vdda. 1811 * @note On this STM32 series, calibration data of internal voltage reference 1812 * VrefInt corresponds to a resolution of 12 bits, 1813 * this is the recommended ADC resolution to convert voltage of 1814 * internal voltage reference VrefInt. 1815 * Otherwise, this macro performs the processing to scale 1816 * ADC conversion data to 12 bits. 1817 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1818 * of internal voltage reference VrefInt (unit: digital value). 1819 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1820 * @arg @ref ADC_RESOLUTION_16B 1821 * @arg @ref ADC_RESOLUTION_14B 1822 * @arg @ref ADC_RESOLUTION_12B 1823 * @arg @ref ADC_RESOLUTION_10B 1824 * @arg @ref ADC_RESOLUTION_8B 1825 * @retval Analog reference voltage (unit: mV) 1826 */ 1827 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1828 __ADC_RESOLUTION__) \ 1829 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1830 (__ADC_RESOLUTION__)) 1831 1832 /** 1833 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1834 * from ADC conversion data of internal temperature sensor. 1835 * @note Computation is using temperature sensor calibration values 1836 * stored in system memory for each device during production. 1837 * @note Calculation formula: 1838 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1839 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1840 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1841 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1842 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1843 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1844 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1845 * TEMP_DEGC_CAL1 (calibrated in factory) 1846 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1847 * TEMP_DEGC_CAL2 (calibrated in factory) 1848 * Caution: Calculation relevancy under reserve that calibration 1849 * parameters are correct (address and data). 1850 * To calculate temperature using temperature sensor 1851 * datasheet typical values (generic values less, therefore 1852 * less accurate than calibrated values), 1853 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1854 * @note As calculation input, the analog reference voltage (Vref+) must be 1855 * defined as it impacts the ADC LSB equivalent voltage. 1856 * @note Analog reference voltage (Vref+) must be either known from 1857 * user board environment or can be calculated using ADC measurement 1858 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1859 * @note On this STM32 series, calibration data of temperature sensor 1860 * corresponds to a resolution of 12 bits, 1861 * this is the recommended ADC resolution to convert voltage of 1862 * temperature sensor. 1863 * Otherwise, this macro performs the processing to scale 1864 * ADC conversion data to 12 bits. 1865 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1866 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1867 * temperature sensor (unit: digital value). 1868 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1869 * sensor voltage has been measured. 1870 * This parameter can be one of the following values: 1871 * @arg @ref ADC_RESOLUTION_16B 1872 * @arg @ref ADC_RESOLUTION_14B 1873 * @arg @ref ADC_RESOLUTION_12B 1874 * @arg @ref ADC_RESOLUTION_10B 1875 * @arg @ref ADC_RESOLUTION_8B 1876 * @retval Temperature (unit: degree Celsius) 1877 */ 1878 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1879 __TEMPSENSOR_ADC_DATA__,\ 1880 __ADC_RESOLUTION__) \ 1881 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1882 (__TEMPSENSOR_ADC_DATA__),\ 1883 (__ADC_RESOLUTION__)) 1884 1885 /** 1886 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1887 * from ADC conversion data of internal temperature sensor. 1888 * @note Computation is using temperature sensor typical values 1889 * (refer to device datasheet). 1890 * @note Calculation formula: 1891 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1892 * / Avg_Slope + CALx_TEMP 1893 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1894 * (unit: digital value) 1895 * Avg_Slope = temperature sensor slope 1896 * (unit: uV/Degree Celsius) 1897 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1898 * temperature CALx_TEMP (unit: mV) 1899 * Caution: Calculation relevancy under reserve the temperature sensor 1900 * of the current device has characteristics in line with 1901 * datasheet typical values. 1902 * If temperature sensor calibration values are available on 1903 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1904 * temperature calculation will be more accurate using 1905 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1906 * @note As calculation input, the analog reference voltage (Vref+) must be 1907 * defined as it impacts the ADC LSB equivalent voltage. 1908 * @note Analog reference voltage (Vref+) must be either known from 1909 * user board environment or can be calculated using ADC measurement 1910 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1911 * @note ADC measurement data must correspond to a resolution of 12bits 1912 * (full scale digital value 4095). If not the case, the data must be 1913 * preliminarily rescaled to an equivalent resolution of 12 bits. 1914 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1915 * On STM32H7, refer to device datasheet parameter "Avg_Slope". 1916 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1917 * On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1918 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1919 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1920 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1921 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1922 * This parameter can be one of the following values: 1923 * @arg @ref ADC_RESOLUTION_16B 1924 * @arg @ref ADC_RESOLUTION_14B 1925 * @arg @ref ADC_RESOLUTION_12B 1926 * @arg @ref ADC_RESOLUTION_10B 1927 * @arg @ref ADC_RESOLUTION_8B 1928 * @retval Temperature (unit: degree Celsius) 1929 */ 1930 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1931 __TEMPSENSOR_TYP_CALX_V__,\ 1932 __TEMPSENSOR_CALX_TEMP__,\ 1933 __VREFANALOG_VOLTAGE__,\ 1934 __TEMPSENSOR_ADC_DATA__,\ 1935 __ADC_RESOLUTION__) \ 1936 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1937 (__TEMPSENSOR_TYP_CALX_V__),\ 1938 (__TEMPSENSOR_CALX_TEMP__),\ 1939 (__VREFANALOG_VOLTAGE__),\ 1940 (__TEMPSENSOR_ADC_DATA__),\ 1941 (__ADC_RESOLUTION__)) 1942 1943 /** 1944 * @} 1945 */ 1946 1947 /** 1948 * @} 1949 */ 1950 1951 /* Include ADC HAL Extended module */ 1952 #include "stm32h7xx_hal_adc_ex.h" 1953 1954 /* Exported functions --------------------------------------------------------*/ 1955 /** @addtogroup ADC_Exported_Functions 1956 * @{ 1957 */ 1958 1959 /** @addtogroup ADC_Exported_Functions_Group1 1960 * @brief Initialization and Configuration functions 1961 * @{ 1962 */ 1963 /* Initialization and de-initialization functions ****************************/ 1964 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1965 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1966 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1967 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1968 1969 1970 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1971 /* Callbacks Register/UnRegister functions ***********************************/ 1972 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 1973 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1974 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1975 /** 1976 * @} 1977 */ 1978 1979 /** @addtogroup ADC_Exported_Functions_Group2 1980 * @brief IO operation functions 1981 * @{ 1982 */ 1983 /* IO operation functions *****************************************************/ 1984 1985 /* Blocking mode: Polling */ 1986 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1987 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1988 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1989 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1990 1991 /* Non-blocking mode: Interruption */ 1992 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1993 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1994 1995 /* Non-blocking mode: DMA */ 1996 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1997 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1998 1999 /* ADC retrieve conversion value intended to be used with polling or interruption */ 2000 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 2001 2002 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 2003 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 2004 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 2005 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 2006 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 2007 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 2008 /** 2009 * @} 2010 */ 2011 2012 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 2013 * @brief Peripheral Control functions 2014 * @{ 2015 */ 2016 /* Peripheral Control functions ***********************************************/ 2017 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 2018 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 2019 2020 /** 2021 * @} 2022 */ 2023 2024 /* Peripheral State functions *************************************************/ 2025 /** @addtogroup ADC_Exported_Functions_Group4 2026 * @{ 2027 */ 2028 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 2029 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 2030 2031 /** 2032 * @} 2033 */ 2034 2035 /** 2036 * @} 2037 */ 2038 2039 /* Private functions -----------------------------------------------------------*/ 2040 /** @addtogroup ADC_Private_Functions ADC Private Functions 2041 * @{ 2042 */ 2043 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 2044 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 2045 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 2046 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 2047 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 2048 void ADC_DMAError(DMA_HandleTypeDef *hdma); 2049 void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc); 2050 2051 /** 2052 * @} 2053 */ 2054 2055 /** 2056 * @} 2057 */ 2058 2059 /** 2060 * @} 2061 */ 2062 2063 #ifdef __cplusplus 2064 } 2065 #endif 2066 2067 2068 #endif /* STM32H7xx_HAL_ADC_H */ 2069
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