include/Legacy/stm32h7xx_hal_eth_legacy.h

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_hal_eth_legacy.h
0004   * @author  MCD Application Team
0005   * @brief   Header file of ETH HAL module.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018
0019 /* Define to prevent recursive inclusion -------------------------------------*/
0020 #ifndef STM32H7xx_HAL_ETH_LEGACY_H
0021 #define STM32H7xx_HAL_ETH_LEGACY_H
0022
0023 #ifdef __cplusplus
0024  extern "C" {
0025 #endif
0026
0027
0028 /* Includes ------------------------------------------------------------------*/
0029 #include "stm32h7xx_hal_def.h"
0030
0031 #if defined(ETH)
0032
0033 /** @addtogroup STM32H7xx_HAL_Driver
0034   * @{
0035   */
0036
0037 /** @addtogroup ETH
0038   * @{
0039   */
0040
0041 /* Exported types ------------------------------------------------------------*/
0042 #ifndef ETH_TX_DESC_CNT
0043  #define ETH_TX_DESC_CNT         4U
0044 #endif
0045
0046 #ifndef ETH_RX_DESC_CNT
0047  #define ETH_RX_DESC_CNT         4U
0048 #endif
0049
0050 /*********************** Descriptors struct def section ************************/
0051 /** @defgroup ETH_Exported_Types ETH Exported Types
0052   * @ingroup RTEMSBSPsARMSTM32H7
0053   * @{
0054   */
0055
0056 /**
0057   * @brief  ETH DMA Descriptor structure definition
0058   */
0059 typedef struct
0060 {
0061   __IO uint32_t DESC0;
0062   __IO uint32_t DESC1;
0063   __IO uint32_t DESC2;
0064   __IO uint32_t DESC3;
0065   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
0066   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
0067 }ETH_DMADescTypeDef;
0068 /**
0069   *
0070   */
0071
0072 /**
0073   * @brief  ETH Buffers List structure definition
0074   */
0075 typedef struct __ETH_BufferTypeDef
0076 {
0077   uint8_t *buffer;                /*<! buffer address */
0078
0079   uint32_t len;                   /*<! buffer length */
0080
0081   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
0082 }ETH_BufferTypeDef;
0083 /**
0084   *
0085   */
0086
0087 /**
0088   * @brief  DMA Transmit Descriptors Wrapper structure definition
0089   */
0090 typedef struct
0091 {
0092   uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
0093
0094   uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
0095
0096   uint32_t* PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
0097
0098   uint32_t* CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
0099
0100   uint32_t BuffersInUse;                   /*<! Buffers in Use */
0101 }ETH_TxDescListTypeDef;
0102 /**
0103   *
0104   */
0105
0106  /**
0107   * @brief  Transmit Packet Configuration structure definition
0108   */
0109 typedef struct
0110 {
0111   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
0112                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
0113
0114   uint32_t Length;                  /*!< Total packet length   */
0115
0116   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
0117
0118   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
0119                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
0120
0121   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
0122                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
0123
0124   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
0125                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
0126
0127   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
0128                                         This parameter can be a value from 0x0 to 0x3FFF */
0129
0130   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
0131                                         This parameter can be a value from 0x0 to 0x3FFFF */
0132
0133   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
0134                                         This parameter can be a value from 0x5 to 0xF */
0135
0136   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
0137                                         This parameter can be a value from 0x0 to 0xFFFF*/
0138
0139   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
0140                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
0141
0142   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
0143                                         This parameter can be a value from 0x0 to 0x3FFFF */
0144
0145   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
0146                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
0147
0148 }ETH_TxPacketConfig;
0149 /**
0150   *
0151   */
0152
0153 /**
0154  * @brief  DMA Receive Descriptors Wrapper structure definition
0155  */
0156 typedef struct
0157 {
0158   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
0159
0160   uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */
0161
0162   uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */
0163
0164   uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */
0165
0166   uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.
0167                                              If 0 no context descriptor is present in last received packet. */
0168
0169   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
0170                                              If 0, DMA will not generate the Rx complete interrupt. */
0171 }ETH_RxDescListTypeDef;
0172 /**
0173   *
0174   */
0175
0176 /**
0177   * @brief  Received Packet Information structure definition
0178   */
0179 typedef struct
0180 {
0181   uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */
0182
0183   uint32_t VlanTag;         /*<! Vlan Tag value */
0184
0185   uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */
0186
0187   uint32_t Checksum;        /*<! Rx Checksum status.
0188                                  This parameter can be a value of @ref ETH_Rx_Checksum_Status */
0189
0190   uint32_t HeaderType;      /*<! IP header type.
0191                                  This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
0192
0193   uint32_t PayloadType;     /*<! Payload type.
0194                                  This parameter can be a value of @ref ETH_Rx_Payload_Type */
0195
0196   uint32_t MacFilterStatus; /*<! MAC filter status.
0197                                  This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
0198
0199   uint32_t L3FilterStatus;  /*<! L3 filter status
0200                                  This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
0201
0202   uint32_t L4FilterStatus;  /*<! L4 filter status
0203                                  This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
0204
0205   uint32_t ErrorCode;       /*<! Rx error code
0206                                  This parameter can be a combination of @ref ETH_Rx_Error_Code */
0207
0208 } ETH_RxPacketInfo;
0209 /**
0210   *
0211   */
0212
0213 /**
0214   * @brief  ETH MAC Configuration Structure definition
0215   */
0216 typedef struct
0217 {
0218   uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
0219                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
0220
0221   FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
0222
0223   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
0224                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
0225
0226   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
0227
0228   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
0229
0230   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
0231
0232   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
0233
0234   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path
0235                                                            When enabled, the MAC allows no more then 2048 bytes to be received.
0236                                                            When disabled, the MAC can receive up to 16384 bytes. */
0237
0238   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path
0239                                                            When enabled, the MAC allows no more then 2048 bytes to be sent.
0240                                                            When disabled, the MAC can send up to 16384 bytes. */
0241
0242   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
0243                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
0244                                                            without reporting a giant packet error */
0245
0246   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
0247                                                            This parameter can be a value of @ref ETH_Speed */
0248
0249   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
0250                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
0251
0252   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
0253
0254   FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
0255
0256   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
0257
0258   FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
0259
0260   FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
0261
0262   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
0263                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
0264
0265   FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
0266
0267   uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
0268                                                            This parameter can be a value of @ref ETH_Preamble_Length */
0269
0270   FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
0271
0272   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
0273
0274   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
0275
0276   uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
0277                                                       greater than the value programmed in this field in units of bytes
0278                                                           This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
0279
0280   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
0281
0282   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
0283                                                            This parameter can be a value from 0x0 to 0xFF */
0284
0285   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
0286
0287   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
0288                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
0289
0290    uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
0291                                                    This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
0292
0293   FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
0294
0295   uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
0296                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
0297
0298   FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
0299                                                    or the MAC back pressure operation in Half Duplex mode */
0300
0301   FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
0302
0303   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
0304                                                   and disables its transmitter for a specified (Pause) time */
0305
0306   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
0307                                                       This parameter can be a value of @ref ETH_Transmit_Mode */
0308
0309   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
0310                                                              This parameter can be a value of @ref ETH_Receive_Mode */
0311
0312   FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
0313
0314   FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
0315
0316   FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
0317 } ETH_MACConfigTypeDef;
0318 /**
0319   *
0320   */
0321
0322 /**
0323   * @brief  ETH DMA Configuration Structure definition
0324   */
0325  typedef struct
0326  {
0327    uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
0328                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
0329
0330    FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
0331                                                             burst transfers on Read and Write channels  */
0332
0333    uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
0334                                                      This parameter can be a value of @ref ETH_Burst_Mode */
0335
0336    FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
0337                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
0338
0339    FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
0340
0341    uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
0342                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
0343
0344    FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
0345                                                       Packet of Transmit data even before obtaining the status for the first one. */
0346
0347    uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
0348                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
0349
0350    FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
0351
0352    FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
0353
0354    uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
0355                                                   This parameter can be a value from 0x40 to 0x3FFF */
0356 } ETH_DMAConfigTypeDef;
0357 /**
0358   *
0359   */
0360
0361 /**
0362   * @brief  HAL ETH Media Interfaces enum definition
0363   */
0364 typedef enum
0365 {
0366   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
0367   HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
0368 }ETH_MediaInterfaceTypeDef;
0369 /**
0370   *
0371   */
0372
0373 /**
0374   * @brief  ETH Init Structure definition
0375   */
0376 typedef struct
0377 {
0378
0379   uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
0380
0381   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
0382
0383   ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
0384
0385   ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
0386
0387   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
0388
0389 }ETH_InitTypeDef;
0390 /**
0391   *
0392   */
0393
0394 /**
0395   * @brief  HAL State structures definition
0396   */
0397 typedef uint32_t HAL_ETH_StateTypeDef;
0398 /**
0399   *
0400   */
0401
0402 /**
0403   * @brief  ETH Handle Structure definition
0404   */
0405 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0406 typedef struct __ETH_HandleTypeDef
0407 #else
0408 typedef struct
0409 #endif
0410 {
0411   ETH_TypeDef                *Instance;                 /*!< Register base address       */
0412
0413   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
0414
0415   ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
0416                                                             addresses and current descriptor index  */
0417
0418   ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
0419                                                             addresses and current descriptor index  */
0420
0421   HAL_LockTypeDef            Lock;                      /*!< Locking object             */
0422
0423   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
0424                                                               and also related to Tx operations.
0425                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
0426
0427   __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.
0428                                                              This parameter can be a value of @ref HAL_ETH_StateTypeDef */
0429
0430   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
0431                                                              This parameter can be a value of of @ref ETH_Error_Code */
0432
0433   __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
0434                                                              This parameter can be a combination of @ref ETH_DMA_Status_Flags */
0435
0436   __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
0437                                                              This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
0438
0439   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
0440                                                              This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
0441
0442   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
0443                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
0444
0445 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0446
0447   void    (* TxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);   /*!< ETH Tx Complete Callback */
0448   void    (* RxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Rx  Complete Callback     */
0449   void    (* DMAErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH DMA Error Callback   */
0450   void    (* MACErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH MAC Error Callback     */
0451   void    (* PMTCallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Power Management Callback            */
0452   void    (* EEECallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH EEE Callback   */
0453   void    (* WakeUpCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Wake UP Callback   */
0454
0455   void    (* MspInitCallback)    ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp Init callback              */
0456   void    (* MspDeInitCallback)  ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp DeInit callback            */
0457
0458 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
0459
0460 } ETH_HandleTypeDef;
0461 /**
0462   *
0463   */
0464
0465 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0466 /**
0467   * @brief  HAL ETH Callback ID enumeration definition
0468   */
0469 typedef enum
0470 {
0471   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
0472   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
0473
0474   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
0475   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
0476   HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID         */
0477   HAL_ETH_MAC_ERROR_CB_ID          = 0x05U,    /*!< ETH MAC Error Callback ID         */
0478   HAL_ETH_PMT_CB_ID                = 0x06U,     /*!< ETH Power Management Callback ID  */
0479   HAL_ETH_EEE_CB_ID                = 0x07U,     /*!< ETH EEE Callback ID               */
0480   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
0481
0482
0483 }HAL_ETH_CallbackIDTypeDef;
0484
0485 /**
0486   * @brief  HAL ETH Callback pointer definition
0487   */
0488 typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
0489
0490 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
0491
0492 /**
0493   * @brief  ETH MAC filter structure definition
0494   */
0495 typedef struct{
0496   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
0497
0498   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
0499
0500   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
0501
0502   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
0503
0504   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
0505
0506   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
0507
0508   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
0509
0510   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
0511
0512   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
0513
0514   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
0515
0516   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
0517                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
0518 }ETH_MACFilterConfigTypeDef;
0519 /**
0520   *
0521   */
0522
0523 /**
0524   * @brief  ETH Power Down structure definition
0525   */
0526 typedef struct{
0527   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
0528
0529   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
0530
0531   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
0532
0533   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
0534
0535 }ETH_PowerDownConfigTypeDef;
0536 /**
0537   *
0538   */
0539
0540 /**
0541   * @}
0542   */
0543
0544 /* Exported constants --------------------------------------------------------*/
0545 /** @defgroup ETH_Exported_Constants ETH Exported Constants
0546   * @ingroup RTEMSBSPsARMSTM32H7
0547   * @{
0548   */
0549
0550 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
0551   * @ingroup RTEMSBSPsARMSTM32H7
0552   * @{
0553   */
0554
0555 /*
0556    DMA Tx Normal Descriptor Read Format
0557   -----------------------------------------------------------------------------------------------
0558   TDES0 |                         Buffer1 or Header Address  [31:0]                              |
0559   -----------------------------------------------------------------------------------------------
0560   TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
0561   -----------------------------------------------------------------------------------------------
0562   TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
0563   -----------------------------------------------------------------------------------------------
0564   TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
0565   -----------------------------------------------------------------------------------------------
0566 */
0567
0568 /**
0569   * @brief  Bit definition of TDES0 RF register
0570   */
0571 #define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
0572
0573 /**
0574   * @brief  Bit definition of TDES1 RF register
0575   */
0576 #define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
0577
0578 /**
0579   * @brief  Bit definition of TDES2 RF register
0580   */
0581 #define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000U)  /*!< Interrupt on Completion */
0582 #define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000U)  /*!< Transmit Timestamp Enable */
0583 #define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000U)  /*!< Buffer 2 Length */
0584 #define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000U)  /*!< VLAN Tag Insertion or Replacement mask */
0585 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)  /*!< Do not add a VLAN tag. */
0586 #define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000U)  /*!< Remove the VLAN tag from the packets before transmission. */
0587 #define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000U)  /*!< Insert a VLAN tag. */
0588 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)  /*!< Replace the VLAN tag. */
0589 #define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFFU)  /*!< Buffer 1 Length */
0590 #define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FFU)  /*!< Header Length */
0591
0592 /**
0593   * @brief  Bit definition of TDES3 RF register
0594   */
0595 #define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
0596 #define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000U)  /*!< Context Type */
0597 #define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000U)  /*!< First Descriptor */
0598 #define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000U)  /*!< Last Descriptor */
0599 #define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000U)  /*!< CRC Pad Control mask */
0600 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000U)  /*!< CRC Pad Control: CRC and Pad Insertion */
0601 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000U)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
0602 #define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000U)  /*!< CRC Pad Control: Disable CRC Insertion */
0603 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000U)  /*!< CRC Pad Control: CRC Replacement */
0604 #define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000U)  /*!< SA Insertion Control mask*/
0605 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000U)  /*!< SA Insertion Control: Do not include the source address */
0606 #define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000U)  /*!< SA Insertion Control: Include or insert the source address */
0607 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000U)  /*!< SA Insertion Control: Replace the source address */
0608 #define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000U)  /*!< TCP Header Length */
0609 #define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000U)  /*!< TCP segmentation enable */
0610 #define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000U)  /*!< Checksum Insertion Control: 4 cases */
0611 #define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is disabled */
0612 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000U)  /*!< Only IP header checksum calculation and insertion are enabled. */
0613 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000U)  /*!< IP header checksum and payload checksum calculation and insertion are
0614                                                                                           enabled, but pseudo header checksum is not calculated in hardware */
0615 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000U)  /*!< IP Header checksum and payload checksum calculation and insertion are
0616                                                                                           enabled, and pseudo header checksum is calculated in hardware. */
0617 #define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFFU)  /*!< TCP Payload Length */
0618 #define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFFU)  /*!< Transmit End of Ring */
0619
0620 /*
0621    DMA Tx Normal Descriptor Write Back Format
0622   -----------------------------------------------------------------------------------------------
0623   TDES0 |                         Timestamp Low                                                  |
0624   -----------------------------------------------------------------------------------------------
0625   TDES1 |                         Timestamp High                                                 |
0626   -----------------------------------------------------------------------------------------------
0627   TDES2 |                           Reserved[31:0]                                               |
0628   -----------------------------------------------------------------------------------------------
0629   TDES3 | OWN(31) |                          Status[30:0]                                        |
0630   -----------------------------------------------------------------------------------------------
0631 */
0632
0633 /**
0634   * @brief  Bit definition of TDES0 WBF register
0635   */
0636 #define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
0637
0638 /**
0639   * @brief  Bit definition of TDES1 WBF register
0640   */
0641 #define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
0642
0643 /**
0644   * @brief  Bit definition of TDES3 WBF register
0645   */
0646 #define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
0647 #define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000U)  /*!< Context Type */
0648 #define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000U)  /*!< First Descriptor */
0649 #define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000U)  /*!< Last Descriptor */
0650 #define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Timestamp Status */
0651 #define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */
0652 #define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Timestamp Enable */
0653 #define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
0654 #define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */
0655 #define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000U)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
0656 #define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */
0657 #define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */
0658 #define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */
0659 #define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */
0660 #define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */
0661 #define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0U)  /*!< Collision Count */
0662 #define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008U)  /*!< Excessive Deferral */
0663 #define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004U)  /*!< Underflow Error: late data arrival from the memory */
0664 #define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002U)  /*!< Deferred Bit */
0665 #define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004U)  /*!< IP Header Error */
0666
0667
0668 /*
0669    DMA Tx Context Descriptor
0670   -----------------------------------------------------------------------------------------------
0671   TDES0 |                               Timestamp Low                                            |
0672   -----------------------------------------------------------------------------------------------
0673   TDES1 |                               Timestamp High                                           |
0674   -----------------------------------------------------------------------------------------------
0675   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
0676   -----------------------------------------------------------------------------------------------
0677   TDES3 | OWN(31) |                          Status[30:0]                                        |
0678   -----------------------------------------------------------------------------------------------
0679 */
0680
0681 /**
0682   * @brief  Bit definition of Tx context descriptor register 0
0683   */
0684 #define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
0685
0686 /**
0687   * @brief  Bit definition of Tx context descriptor register 1
0688   */
0689 #define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
0690
0691 /**
0692   * @brief  Bit definition of Tx context descriptor register 2
0693   */
0694 #define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag */
0695 #define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFFU)  /*!< Maximum Segment Size */
0696
0697 /**
0698   * @brief  Bit definition of Tx context descriptor register 3
0699   */
0700 #define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000U)     /*!< OWN bit: descriptor is owned by DMA engine */
0701 #define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000U)     /*!< Context Type */
0702 #define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000U)     /*!< One-Step Timestamp Correction Enable */
0703 #define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000U)     /*!< One-Step Timestamp Correction Input or MSS Valid */
0704 #define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000U)     /*!< Context Descriptor Error */
0705 #define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000U)     /*!< Inner VLAN Tag Insert or Replace Mask */
0706 #define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000U)     /*!< Do not add the inner VLAN tag. */
0707 #define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000U)     /*!< Remove the inner VLAN tag from the packets before transmission. */
0708 #define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000U)     /*!< Insert the inner VLAN tag. */
0709 #define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000U)     /*!< Replace the inner VLAN tag. */
0710 #define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000U)     /*!< Inner VLAN Tag Valid */
0711 #define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000U)     /*!< VLAN Tag Valid */
0712 #define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFFU)     /*!< VLAN Tag */
0713
0714 /**
0715   * @}
0716   */
0717
0718
0719 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
0720   * @ingroup RTEMSBSPsARMSTM32H7
0721   * @{
0722   */
0723
0724 /*
0725   DMA Rx Normal Descriptor read format
0726   -----------------------------------------------------------------------------------------------------------
0727   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
0728   -----------------------------------------------------------------------------------------------------------
0729   RDES1 |                                            Reserved                                               |
0730   -----------------------------------------------------------------------------------------------------------
0731   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
0732   -----------------------------------------------------------------------------------------------------------
0733   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
0734   -----------------------------------------------------------------------------------------------------------
0735 */
0736
0737 /**
0738   * @brief  Bit definition of Rx normal descriptor register 0 read format
0739   */
0740 #define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFFU)  /*!< Header or Buffer 1 Address Pointer  */
0741
0742 /**
0743   * @brief  Bit definition of Rx normal descriptor register 2 read format
0744   */
0745 #define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFFU)  /*!< Buffer 2 Address Pointer  */
0746
0747 /**
0748   * @brief  Bit definition of Rx normal descriptor register 3 read format
0749   */
0750 #define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */
0751 #define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000U)  /*!< Interrupt Enabled on Completion  */
0752 #define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000U)  /*!< Buffer 2 Address Valid */
0753 #define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000U)  /*!< Buffer 1 Address Valid */
0754
0755 /*
0756   DMA Rx Normal Descriptor write back format
0757   ---------------------------------------------------------------------------------------------------------------------
0758   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
0759     ---------------------------------------------------------------------------------------------------------------------
0760   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
0761   ---------------------------------------------------------------------------------------------------------------------
0762   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
0763   ---------------------------------------------------------------------------------------------------------------------
0764   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
0765   ---------------------------------------------------------------------------------------------------------------------
0766 */
0767
0768 /**
0769   * @brief  Bit definition of Rx normal descriptor register 0 write back format
0770   */
0771 #define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag  */
0772 #define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFFU)  /*!< Outer VLAN Tag  */
0773
0774 /**
0775   * @brief  Bit definition of Rx normal descriptor register 1 write back format
0776   */
0777 #define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000U)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
0778 #define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000U)  /*!< Timestamp Dropped  */
0779 #define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000U)  /*!< Timestamp Available  */
0780 #define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000U)  /*!< PTP Version  */
0781 #define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000U)  /*!< PTP Packet Type  */
0782 #define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000U)  /*!< PTP Message Type: No PTP message received  */
0783 #define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100U)  /*!< PTP Message Type: SYNC (all clock types)  */
0784 #define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200U)  /*!< PTP Message Type: Follow_Up (all clock types)  */
0785 #define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300U)  /*!< PTP Message Type: Delay_Req (all clock types)  */
0786 #define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400U)  /*!< PTP Message Type: Delay_Resp (all clock types)  */
0787 #define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500U)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
0788 #define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600U)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
0789 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700U)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
0790 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800U)  /*!< PTP Message Type: Announce  */
0791 #define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900U)  /*!< PTP Message Type: Management  */
0792 #define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00U)  /*!< PTP Message Type: Signaling  */
0793 #define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00U)  /*!< PTP Message Type: PTP packet with Reserved message type  */
0794 #define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080U)  /*!< IP Payload Error */
0795 #define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040U)  /*!< IP Checksum Bypassed */
0796 #define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020U)  /*!< IPv6 header Present */
0797 #define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010U)  /*!< IPv4 header Present */
0798 #define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008U)  /*!< IP Header Error */
0799 #define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003U)  /*!< Payload Type mask */
0800 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000U)  /*!< Payload Type: Unknown type or IP/AV payload not processed */
0801 #define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001U)  /*!< Payload Type: UDP */
0802 #define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002U)  /*!< Payload Type: TCP  */
0803 #define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003U)  /*!< Payload Type: ICMP */
0804
0805 /**
0806   * @brief  Bit definition of Rx normal descriptor register 2 write back format
0807   */
0808 #define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000U)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
0809 #define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000U)  /*!< Layer 4 Filter Match                  */
0810 #define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000U)  /*!< Layer 3 Filter Match                  */
0811 #define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000U)  /*!< MAC Address Match or Hash Value       */
0812 #define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000U)  /*!< Hash Filter Status                    */
0813 #define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000U)  /*!< Destination Address Filter Fail       */
0814 #define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000U)  /*!< SA Address Filter Fail                */
0815 #define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000U)  /*!< VLAN Filter Status                    */
0816 #define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400U)  /*!< ARP Reply Not Generated               */
0817
0818
0819 /**
0820   * @brief  Bit definition of Rx normal descriptor register 3 write back format
0821   */
0822 #define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit */
0823 #define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor */
0824 #define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000U)  /*!< First Descriptor */
0825 #define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000U)  /*!< Last Descriptor */
0826 #define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000U)  /*!< Receive Status RDES2 Valid */
0827 #define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000U)  /*!< Receive Status RDES1 Valid */
0828 #define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000U)  /*!< Receive Status RDES0 Valid */
0829 #define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000U)  /*!< CRC Error */
0830 #define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000U)  /*!< Giant Packet */
0831 #define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000U)  /*!< Receive Watchdog Timeout */
0832 #define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000U)  /*!< Overflow Error */
0833 #define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000U)  /*!< Receive Error */
0834 #define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000U)  /*!< Dribble Bit Error */
0835 #define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000U)  /*!< Length/Type Field */
0836 #define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000U)  /*!< The packet is a length packet */
0837 #define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000U)  /*!< The packet is a type packet */
0838 #define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000U)  /*!< The packet is a ARP Request packet type */
0839 #define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000U)  /*!< The packet is a type packet with VLAN Tag */
0840 #define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000U)  /*!< The packet is a type packet with Double VLAN Tag */
0841 #define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000U)  /*!< The packet is a MAC Control packet type */
0842 #define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000U)  /*!< The packet is a OAM packet type */
0843 #define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000U)  /*!< Error Summary */
0844 #define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFFU)  /*!< Packet Length */
0845
0846 /*
0847   DMA Rx context Descriptor
0848   ---------------------------------------------------------------------------------------------------------------------
0849   RDES0 |                                     Timestamp Low[31:0]                                                     |
0850     ---------------------------------------------------------------------------------------------------------------------
0851   RDES1 |                                     Timestamp High[31:0]                                                    |
0852   ---------------------------------------------------------------------------------------------------------------------
0853   RDES2 |                                          Reserved                                                           |
0854   ---------------------------------------------------------------------------------------------------------------------
0855   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
0856   ---------------------------------------------------------------------------------------------------------------------
0857 */
0858
0859 /**
0860   * @brief  Bit definition of Rx context descriptor register 0
0861   */
0862 #define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp Low  */
0863
0864 /**
0865   * @brief  Bit definition of Rx context descriptor register 1
0866   */
0867 #define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp High  */
0868
0869 /**
0870   * @brief  Bit definition of Rx context descriptor register 3
0871   */
0872 #define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit  */
0873 #define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor  */
0874
0875 /**
0876   * @}
0877   */
0878
0879 /** @defgroup ETH_Frame_settings ETH frame settings
0880   * @ingroup RTEMSBSPsARMSTM32H7
0881   * @{
0882   */
0883 #define ETH_MAX_PACKET_SIZE      ((uint32_t)1528U)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
0884 #define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
0885 #define ETH_CRC                  ((uint32_t)4U)    /*!< Ethernet CRC */
0886 #define ETH_VLAN_TAG             ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
0887 #define ETH_MIN_PAYLOAD          ((uint32_t)46U)    /*!< Minimum Ethernet payload size */
0888 #define ETH_MAX_PAYLOAD          ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */
0889 #define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000U)    /*!< Jumbo frame payload size */
0890 /**
0891   * @}
0892   */
0893
0894 /** @defgroup ETH_Error_Code ETH Error Code
0895   * @ingroup RTEMSBSPsARMSTM32H7
0896   * @{
0897   */
0898 #define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
0899 #define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
0900 #define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
0901 #define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
0902 #define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */
0903 #define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */
0904 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
0905 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
0906 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
0907 /**
0908   * @}
0909   */
0910
0911 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
0912   * @ingroup RTEMSBSPsARMSTM32H7
0913   * @{
0914   */
0915 #define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001U)
0916 #define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002U)
0917 #define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004U)
0918 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008U)
0919 #define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010U)
0920 #define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020U)
0921 /**
0922   * @}
0923   */
0924
0925 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
0926   * @ingroup RTEMSBSPsARMSTM32H7
0927   * @{
0928   */
0929 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
0930 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
0931 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
0932 /**
0933   * @}
0934   */
0935
0936 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
0937   * @ingroup RTEMSBSPsARMSTM32H7
0938   * @{
0939   */
0940 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
0941 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
0942 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
0943 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
0944 /**
0945   * @}
0946   */
0947
0948 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
0949   * @ingroup RTEMSBSPsARMSTM32H7
0950   * @{
0951   */
0952 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
0953 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
0954 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
0955 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
0956 /**
0957   * @}
0958   */
0959
0960 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
0961   * @ingroup RTEMSBSPsARMSTM32H7
0962   * @{
0963   */
0964 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
0965 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
0966 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
0967 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
0968 /**
0969   * @}
0970   */
0971
0972 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
0973   * @ingroup RTEMSBSPsARMSTM32H7
0974   * @{
0975   */
0976 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
0977 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
0978 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
0979 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
0980 /**
0981   * @}
0982   */
0983
0984 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
0985   * @ingroup RTEMSBSPsARMSTM32H7
0986   * @{
0987   */
0988 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
0989 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
0990 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
0991 /**
0992   * @}
0993   */
0994
0995 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
0996   * @ingroup RTEMSBSPsARMSTM32H7
0997   * @{
0998   */
0999 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
1000 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
1001 /**
1002   * @}
1003   */
1004
1005 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
1006   * @ingroup RTEMSBSPsARMSTM32H7
1007   * @{
1008   */
1009 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
1010 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
1011 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
1012 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
1013 /**
1014   * @}
1015   */
1016
1017 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
1018   * @ingroup RTEMSBSPsARMSTM32H7
1019   * @{
1020   */
1021 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
1022 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
1023 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
1024 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
1025 /**
1026   * @}
1027   */
1028
1029 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1030   * @ingroup RTEMSBSPsARMSTM32H7
1031   * @{
1032   */
1033 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
1034 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1035 /**
1036   * @}
1037   */
1038
1039 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1040   * @ingroup RTEMSBSPsARMSTM32H7
1041   * @{
1042   */
1043 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
1044 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1045 /**
1046   * @}
1047   */
1048
1049 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1050   * @ingroup RTEMSBSPsARMSTM32H7
1051   * @{
1052   */
1053 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
1054 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
1055 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
1056 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
1057 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
1058 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
1059 /**
1060   * @}
1061   */
1062
1063 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1064   * @ingroup RTEMSBSPsARMSTM32H7
1065   * @{
1066   */
1067 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
1068 #define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000U)
1069 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
1070 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
1071 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
1072 #define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
1073 #define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
1074 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
1075 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
1076 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1077 #define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000U)
1078 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1079 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1080 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1081 #define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1082 #define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1083 #define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1084 #define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1085 /**
1086   * @}
1087   */
1088
1089  /** @defgroup ETH_Burst_Mode ETH Burst Mode
1090    * @ingroup RTEMSBSPsARMSTM32H7
1091   * @{
1092   */
1093 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
1094 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
1095 #define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000U)
1096 /**
1097   * @}
1098   */
1099
1100 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1101   * @ingroup RTEMSBSPsARMSTM32H7
1102   * @{
1103   */
1104 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
1105 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
1106 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
1107 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
1108 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
1109 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
1110 /**
1111   * @}
1112   */
1113
1114 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1115   * @ingroup RTEMSBSPsARMSTM32H7
1116   * @{
1117   */
1118 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
1119 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
1120 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
1121 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
1122 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
1123 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
1124 /**
1125   * @}
1126   */
1127
1128 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1129   * @ingroup RTEMSBSPsARMSTM32H7
1130   * @{
1131   */
1132 #define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
1133 #define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
1134 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
1135 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
1136 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
1137 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
1138 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
1139 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
1140 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
1141 #define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
1142 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
1143 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
1144 #define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
1145 /**
1146   * @}
1147   */
1148
1149 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1150   * @ingroup RTEMSBSPsARMSTM32H7
1151   * @{
1152   */
1153 #define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
1154 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
1155 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
1156 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
1157 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
1158 #define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
1159 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
1160 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
1161 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
1162 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
1163 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
1164 #define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
1165 #define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
1166 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
1167 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
1168 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
1169 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
1170 /**
1171   * @}
1172   */
1173
1174 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1175   * @ingroup RTEMSBSPsARMSTM32H7
1176   * @{
1177   */
1178 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
1179 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
1180 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
1181 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
1182 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
1183 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
1184 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
1185 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
1186 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
1187 /**
1188   * @}
1189   */
1190
1191 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1192   * @ingroup RTEMSBSPsARMSTM32H7
1193   * @{
1194   */
1195 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
1196 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
1197 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
1198 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
1199 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
1200 /**
1201   * @}
1202   */
1203
1204 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
1205   * @ingroup RTEMSBSPsARMSTM32H7
1206   * @{
1207   */
1208 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
1209 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
1210 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
1211 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
1212 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
1213 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
1214 /**
1215   * @}
1216   */
1217
1218 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1219   * @ingroup RTEMSBSPsARMSTM32H7
1220   * @{
1221   */
1222 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
1223 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
1224 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
1225 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
1226 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
1227 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
1228 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
1229 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
1230 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
1231 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
1232 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
1233 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
1234 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
1235 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
1236 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
1237 /**
1238   * @}
1239   */
1240
1241 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1242   * @ingroup RTEMSBSPsARMSTM32H7
1243   * @{
1244   */
1245 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
1246 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
1247 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
1248 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
1249 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
1250 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
1251 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
1252 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
1253 /**
1254   * @}
1255   */
1256
1257 /** @defgroup ETH_Speed  ETH Speed
1258   * @ingroup RTEMSBSPsARMSTM32H7
1259   * @{
1260   */
1261 #define ETH_SPEED_10M        ((uint32_t)0x00000000U)
1262 #define ETH_SPEED_100M       ETH_MACCR_FES
1263 /**
1264   * @}
1265   */
1266
1267 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1268   * @ingroup RTEMSBSPsARMSTM32H7
1269   * @{
1270   */
1271 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
1272 #define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000U)
1273 /**
1274   * @}
1275   */
1276
1277 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1278   * @ingroup RTEMSBSPsARMSTM32H7
1279   * @{
1280   */
1281 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
1282 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
1283 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
1284 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
1285 /**
1286   * @}
1287   */
1288
1289 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1290   * @ingroup RTEMSBSPsARMSTM32H7
1291   * @{
1292   */
1293 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
1294 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
1295 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
1296 /**
1297   * @}
1298   */
1299
1300 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1301   * @ingroup RTEMSBSPsARMSTM32H7
1302   * @{
1303   */
1304 #define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000U)
1305 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
1306 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
1307 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
1308 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
1309 /**
1310   * @}
1311   */
1312
1313 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1314   * @ingroup RTEMSBSPsARMSTM32H7
1315   * @{
1316   */
1317 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
1318 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1319 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
1320 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1321 /**
1322   * @}
1323   */
1324
1325 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1326   * @ingroup RTEMSBSPsARMSTM32H7
1327   * @{
1328   */
1329 #define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)
1330 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
1331 /**
1332   * @}
1333   */
1334
1335 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1336   * @ingroup RTEMSBSPsARMSTM32H7
1337   * @{
1338   */
1339 #define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
1340 #define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
1341 #define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
1342 #define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
1343 /**
1344   * @}
1345   */
1346
1347 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1348   * @ingroup RTEMSBSPsARMSTM32H7
1349   * @{
1350   */
1351 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
1352 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
1353 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
1354 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
1355 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
1356 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
1357 /**
1358   * @}
1359   */
1360
1361 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1362   * @ingroup RTEMSBSPsARMSTM32H7
1363   * @{
1364   */
1365 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
1366 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
1367 /**
1368   * @}
1369   */
1370
1371 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1372   * @ingroup RTEMSBSPsARMSTM32H7
1373   * @{
1374   */
1375 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
1376 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
1377 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
1378 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
1379 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
1380 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
1381 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
1382 /**
1383   * @}
1384   */
1385
1386 /** @defgroup HAL_ETH_StateTypeDef ETH States
1387   * @ingroup RTEMSBSPsARMSTM32H7
1388   * @{
1389   */
1390 #define HAL_ETH_STATE_RESET       ((uint32_t)0x00000000U)    /*!< Peripheral not yet Initialized or disabled */
1391 #define HAL_ETH_STATE_READY       ((uint32_t)0x00000010U)    /*!< Peripheral Communication started           */
1392 #define HAL_ETH_STATE_BUSY        ((uint32_t)0x00000023U)    /*!< an internal process is ongoing             */
1393 #define HAL_ETH_STATE_BUSY_TX     ((uint32_t)0x00000021U)    /*!< Transmission process is ongoing            */
1394 #define HAL_ETH_STATE_BUSY_RX     ((uint32_t)0x00000022U)    /*!< Reception process is ongoing               */
1395 #define HAL_ETH_STATE_ERROR       ((uint32_t)0x000000E0U)    /*!< Error State                                */
1396 /**
1397   * @}
1398   */
1399 /**
1400   * @}
1401   */
1402
1403 /* Exported macro ------------------------------------------------------------*/
1404 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1405   * @ingroup RTEMSBSPsARMSTM32H7
1406   * @{
1407   */
1408
1409 /** @brief Reset ETH handle state
1410   * @param  __HANDLE__: specifies the ETH handle.
1411   * @retval None
1412   */
1413 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1414 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1415                                                        (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1416                                                        (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
1417                                                        (__HANDLE__)->MspInitCallback = NULL;             \
1418                                                        (__HANDLE__)->MspDeInitCallback = NULL;           \
1419                                                      } while(0)
1420 #else
1421 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1422                                                        (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1423                                                        (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
1424                                                      } while(0)
1425 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1426
1427 /**
1428   * @brief  Enables the specified ETHERNET DMA interrupts.
1429   * @param  __HANDLE__   : ETH Handle
1430   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1431   *   enabled @ref ETH_DMA_Interrupts
1432   * @retval None
1433   */
1434 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1435
1436 /**
1437   * @brief  Disables the specified ETHERNET DMA interrupts.
1438   * @param  __HANDLE__   : ETH Handle
1439   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1440   *   disabled. @ref ETH_DMA_Interrupts
1441   * @retval None
1442   */
1443 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1444
1445 /**
1446   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
1447   * @param  __HANDLE__   : ETH Handle
1448   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1449   * @retval The ETH DMA IT Source enabled or disabled
1450   */
1451 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
1452
1453 /**
1454   * @brief  Gets the ETHERNET DMA IT pending bit.
1455   * @param  __HANDLE__   : ETH Handle
1456   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1457   * @retval The state of ETH DMA IT (SET or RESET)
1458   */
1459 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
1460
1461 /**
1462   * @brief  Clears the ETHERNET DMA IT pending bit.
1463   * @param  __HANDLE__   : ETH Handle
1464   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1465   * @retval None
1466   */
1467 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1468
1469 /**
1470   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
1471 * @param  __HANDLE__: ETH Handle
1472   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1473   * @retval The state of ETH DMA FLAG (SET or RESET).
1474   */
1475 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1476
1477 /**
1478   * @brief  Clears the specified ETHERNET DMA flag.
1479 * @param  __HANDLE__: ETH Handle
1480   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1481   * @retval The state of ETH DMA FLAG (SET or RESET).
1482   */
1483 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1484
1485 /**
1486   * @brief  Enables the specified ETHERNET MAC interrupts.
1487   * @param  __HANDLE__   : ETH Handle
1488   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1489   *   enabled @ref ETH_MAC_Interrupts
1490   * @retval None
1491   */
1492 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1493
1494 /**
1495   * @brief  Disables the specified ETHERNET MAC interrupts.
1496   * @param  __HANDLE__   : ETH Handle
1497   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1498   *   enabled @ref ETH_MAC_Interrupts
1499   * @retval None
1500   */
1501 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1502
1503 /**
1504   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
1505   * @param  __HANDLE__: ETH Handle
1506   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1507   * @retval The state of ETH MAC IT (SET or RESET).
1508   */
1509 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
1510
1511 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
1512 #define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000U)  /* !<  86 - 64 = 22 */
1513
1514 /**
1515   * @brief Enable the ETH WAKEUP Exti Line.
1516   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1517   *   @arg ETH_WAKEUP_EXTI_LINE
1518   * @retval None.
1519   */
1520 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1521
1522 /**
1523   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1524   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1525   *   @arg ETH_WAKEUP_EXTI_LINE
1526   * @retval EXTI ETH WAKEUP Line Status.
1527   */
1528 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
1529
1530 /**
1531   * @brief Clear the ETH WAKEUP Exti flag.
1532   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1533   *   @arg ETH_WAKEUP_EXTI_LINE
1534   * @retval None.
1535   */
1536 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
1537
1538 #if defined(DUAL_CORE)
1539 /**
1540   * @brief Enable the ETH WAKEUP Exti Line by Core2.
1541   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1542   *   @arg ETH_WAKEUP_EXTI_LINE
1543   * @retval None.
1544   */
1545 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))
1546
1547 /**
1548   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1549   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1550   *   @arg ETH_WAKEUP_EXTI_LINE
1551   * @retval EXTI ETH WAKEUP Line Status.
1552   */
1553 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))
1554
1555 /**
1556   * @brief Clear the ETH WAKEUP Exti flag.
1557   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1558   *   @arg ETH_WAKEUP_EXTI_LINE
1559   * @retval None.
1560   */
1561 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
1562 #endif
1563
1564 /**
1565   * @brief  enable rising edge interrupt on selected EXTI line.
1566   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1567   *  @arg ETH_WAKEUP_EXTI_LINE
1568   * @retval None
1569   */
1570 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1571                                                                 (EXTI->RTSR3 |= (__EXTI_LINE__))
1572
1573 /**
1574   * @brief  enable falling edge interrupt on selected EXTI line.
1575   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1576   *  @arg ETH_WAKEUP_EXTI_LINE
1577   * @retval None
1578   */
1579 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1580                                                                  (EXTI->FTSR3 |= (__EXTI_LINE__))
1581
1582 /**
1583   * @brief  enable falling edge interrupt on selected EXTI line.
1584   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1585   *  @arg ETH_WAKEUP_EXTI_LINE
1586   * @retval None
1587   */
1588 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1589                                                                         (EXTI->FTSR3 |= (__EXTI_LINE__))
1590
1591 /**
1592   * @brief  Generates a Software interrupt on selected EXTI line.
1593   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1594   *  @arg ETH_WAKEUP_EXTI_LINE
1595   * @retval None
1596   */
1597 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1598
1599 /**
1600   * @}
1601   */
1602
1603 /* Include ETH HAL Extension module */
1604 #include "stm32h7xx_hal_eth_ex.h"
1605
1606 /* Exported functions --------------------------------------------------------*/
1607
1608 /** @addtogroup ETH_Exported_Functions
1609   * @{
1610   */
1611
1612 /** @addtogroup ETH_Exported_Functions_Group1
1613   * @{
1614   */
1615 /* Initialization and de initialization functions  **********************************/
1616 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1617 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1618 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1619 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1620 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
1621
1622 /* Callbacks Register/UnRegister functions  ***********************************/
1623 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1624 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
1625 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1626 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1627
1628 /**
1629   * @}
1630   */
1631
1632 /** @addtogroup ETH_Exported_Functions_Group2
1633   * @{
1634   */
1635 /* IO operation functions *******************************************************/
1636 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1637 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1638 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1639 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1640
1641 uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
1642 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
1643 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
1644 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
1645 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
1646
1647 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
1648 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
1649
1650 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
1651 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
1652
1653 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1654 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1655 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1656 void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
1657 void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
1658 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1659 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1660 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1661 /**
1662   * @}
1663   */
1664
1665 /** @addtogroup ETH_Exported_Functions_Group3
1666   * @{
1667   */
1668 /* Peripheral Control functions  **********************************************/
1669 /* MAC & DMA Configuration APIs  **********************************************/
1670 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1671 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1672 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1673 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1674 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1675
1676 /* MAC VLAN Processing APIs    ************************************************/
1677 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
1678
1679 /* MAC L2 Packet Filtering APIs  **********************************************/
1680 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1681 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1682 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1683 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
1684
1685 /* MAC Power Down APIs    *****************************************************/
1686 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1687 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1688 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1689
1690 /**
1691   * @}
1692   */
1693
1694 /** @addtogroup ETH_Exported_Functions_Group4
1695   * @{
1696   */
1697 /* Peripheral State functions  **************************************************/
1698 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
1699 uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);
1700 uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
1701 uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
1702 uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
1703 /**
1704   * @}
1705   */
1706
1707 /**
1708   * @}
1709   */
1710
1711 /**
1712   * @}
1713   */
1714
1715 /**
1716   * @}
1717   */
1718
1719 #endif /* ETH */
1720
1721 #ifdef __cplusplus
1722 }
1723 #endif
1724
1725 #endif /* STM32H7xx_HAL_ETH_LEGACY_H */