stm32h7/hal/stm32h7xx_ll_usart.c

0001 /**
0002   ******************************************************************************
0003   * @file    stm32h7xx_ll_usart.c
0004   * @author  MCD Application Team
0005   * @brief   USART LL module driver.
0006   ******************************************************************************
0007   * @attention
0008   *
0009   * Copyright (c) 2017 STMicroelectronics.
0010   * All rights reserved.
0011   *
0012   * This software is licensed under terms that can be found in the LICENSE file
0013   * in the root directory of this software component.
0014   * If no LICENSE file comes with this software, it is provided AS-IS.
0015   *
0016   ******************************************************************************
0017   */
0018 #if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
0019
0020 /* Includes ------------------------------------------------------------------*/
0021 #include "stm32h7xx_ll_usart.h"
0022 #include "stm32h7xx_ll_rcc.h"
0023 #include "stm32h7xx_ll_bus.h"
0024 #ifdef USE_FULL_ASSERT
0025 #include "stm32_assert.h"
0026 #else
0027 #define assert_param(expr) ((void)0U)
0028 #endif /* USE_FULL_ASSERT */
0029
0030 /** @addtogroup STM32H7xx_LL_Driver
0031   * @{
0032   */
0033
0034 #if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
0035  || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
0036
0037 /** @addtogroup USART_LL
0038   * @{
0039   */
0040
0041 /* Private types -------------------------------------------------------------*/
0042 /* Private variables ---------------------------------------------------------*/
0043 /* Private constants ---------------------------------------------------------*/
0044 /** @addtogroup USART_LL_Private_Constants
0045   * @{
0046   */
0047
0048 /* Definition of default baudrate value used for USART initialisation */
0049 #define USART_DEFAULT_BAUDRATE          (9600U)
0050
0051 /**
0052   * @}
0053   */
0054
0055 /* Private macros ------------------------------------------------------------*/
0056 /** @addtogroup USART_LL_Private_Macros
0057   * @{
0058   */
0059
0060 #define IS_LL_USART_PRESCALER(__VALUE__)  (((__VALUE__) == LL_USART_PRESCALER_DIV1) \
0061                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \
0062                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \
0063                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \
0064                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \
0065                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \
0066                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \
0067                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \
0068                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \
0069                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \
0070                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \
0071                                            || ((__VALUE__) == LL_USART_PRESCALER_DIV256))
0072
0073 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
0074  *              divided by the smallest oversampling used on the USART (i.e. 8)    */
0075 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
0076
0077 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
0078 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
0079
0080 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
0081                                           || ((__VALUE__) == LL_USART_DIRECTION_RX) \
0082                                           || ((__VALUE__) == LL_USART_DIRECTION_TX) \
0083                                           || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
0084
0085 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
0086                                        || ((__VALUE__) == LL_USART_PARITY_EVEN) \
0087                                        || ((__VALUE__) == LL_USART_PARITY_ODD))
0088
0089 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
0090                                           || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
0091                                           || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
0092
0093 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
0094                                              || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
0095
0096 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
0097                                                  || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
0098
0099 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
0100                                            || ((__VALUE__) == LL_USART_PHASE_2EDGE))
0101
0102 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
0103                                               || ((__VALUE__) == LL_USART_POLARITY_HIGH))
0104
0105 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
0106                                             || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
0107
0108 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
0109                                          || ((__VALUE__) == LL_USART_STOPBITS_1) \
0110                                          || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
0111                                          || ((__VALUE__) == LL_USART_STOPBITS_2))
0112
0113 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
0114                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
0115                                           || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
0116                                           || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
0117
0118 /**
0119   * @}
0120   */
0121
0122 /* Private function prototypes -----------------------------------------------*/
0123
0124 /* Exported functions --------------------------------------------------------*/
0125 /** @addtogroup USART_LL_Exported_Functions
0126   * @{
0127   */
0128
0129 /** @addtogroup USART_LL_EF_Init
0130   * @{
0131   */
0132
0133 /**
0134   * @brief  De-initialize USART registers (Registers restored to their default values).
0135   * @param  USARTx USART Instance
0136   * @retval An ErrorStatus enumeration value:
0137   *          - SUCCESS: USART registers are de-initialized
0138   *          - ERROR: USART registers are not de-initialized
0139   */
0140 ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
0141 {
0142   ErrorStatus status = SUCCESS;
0143
0144   /* Check the parameters */
0145   assert_param(IS_UART_INSTANCE(USARTx));
0146
0147   if (USARTx == USART1)
0148   {
0149     /* Force reset of USART clock */
0150     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
0151
0152     /* Release reset of USART clock */
0153     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
0154   }
0155   else if (USARTx == USART2)
0156   {
0157     /* Force reset of USART clock */
0158     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
0159
0160     /* Release reset of USART clock */
0161     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
0162   }
0163   else if (USARTx == USART3)
0164   {
0165     /* Force reset of USART clock */
0166     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
0167
0168     /* Release reset of USART clock */
0169     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
0170   }
0171   else if (USARTx == UART4)
0172   {
0173     /* Force reset of UART clock */
0174     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
0175
0176     /* Release reset of UART clock */
0177     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
0178   }
0179   else if (USARTx == UART5)
0180   {
0181     /* Force reset of UART clock */
0182     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
0183
0184     /* Release reset of UART clock */
0185     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
0186   }
0187   else if (USARTx == USART6)
0188   {
0189     /* Force reset of USART clock */
0190     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
0191
0192     /* Release reset of USART clock */
0193     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
0194   }
0195   else if (USARTx == UART7)
0196   {
0197     /* Force reset of UART clock */
0198     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
0199
0200     /* Release reset of UART clock */
0201     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
0202   }
0203   else if (USARTx == UART8)
0204   {
0205     /* Force reset of UART clock */
0206     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
0207
0208     /* Release reset of UART clock */
0209     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
0210   }
0211 #if defined(UART9)
0212   else if (USARTx == UART9)
0213   {
0214     /* Force reset of UART clock */
0215     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
0216
0217     /* Release reset of UART clock */
0218     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
0219   }
0220 #endif /* UART9 */
0221 #if defined(USART10)
0222   else if (USARTx == USART10)
0223   {
0224     /* Force reset of USART clock */
0225     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10);
0226
0227     /* Release reset of USART clock */
0228     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10);
0229   }
0230 #endif /* USART10 */
0231   else
0232   {
0233     status = ERROR;
0234   }
0235
0236   return (status);
0237 }
0238
0239 /**
0240   * @brief  Initialize USART registers according to the specified
0241   *         parameters in USART_InitStruct.
0242   * @note   As some bits in USART configuration registers can only be written when
0243   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
0244   *         this function. Otherwise, ERROR result will be returned.
0245   * @note   Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
0246   * @param  USARTx USART Instance
0247   * @param  USART_InitStruct pointer to a LL_USART_InitTypeDef structure
0248   *         that contains the configuration information for the specified USART peripheral.
0249   * @retval An ErrorStatus enumeration value:
0250   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
0251   *          - ERROR: Problem occurred during USART Registers initialization
0252   */
0253 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
0254 {
0255   ErrorStatus status = ERROR;
0256   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
0257
0258   /* Check the parameters */
0259   assert_param(IS_UART_INSTANCE(USARTx));
0260   assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue));
0261   assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
0262   assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
0263   assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
0264   assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
0265   assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
0266   assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
0267   assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
0268
0269   /* USART needs to be in disabled state, in order to be able to configure some bits in
0270      CRx registers */
0271   if (LL_USART_IsEnabled(USARTx) == 0U)
0272   {
0273     /*---------------------------- USART CR1 Configuration ---------------------
0274      * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
0275      * - DataWidth:          USART_CR1_M bits according to USART_InitStruct->DataWidth value
0276      * - Parity:             USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
0277      * - TransferDirection:  USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
0278      * - Oversampling:       USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
0279      */
0280     MODIFY_REG(USARTx->CR1,
0281                (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
0282                 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
0283                (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
0284                 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
0285
0286     /*---------------------------- USART CR2 Configuration ---------------------
0287      * Configure USARTx CR2 (Stop bits) with parameters:
0288      * - Stop Bits:          USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
0289      * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
0290      */
0291     LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
0292
0293     /*---------------------------- USART CR3 Configuration ---------------------
0294      * Configure USARTx CR3 (Hardware Flow Control) with parameters:
0295      * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
0296      *   USART_InitStruct->HardwareFlowControl value.
0297      */
0298     LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
0299
0300     /*---------------------------- USART BRR Configuration ---------------------
0301      * Retrieve Clock frequency used for USART Peripheral
0302      */
0303     if (USARTx == USART1)
0304     {
0305       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
0306     }
0307     else if (USARTx == USART2)
0308     {
0309       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0310     }
0311     else if (USARTx == USART3)
0312     {
0313       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0314     }
0315     else if (USARTx == UART4)
0316     {
0317       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0318     }
0319     else if (USARTx == UART5)
0320     {
0321       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0322     }
0323     else if (USARTx == USART6)
0324     {
0325       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
0326     }
0327     else if (USARTx == UART7)
0328     {
0329       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0330     }
0331     else if (USARTx == UART8)
0332     {
0333       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE);
0334     }
0335 #if defined(UART9)
0336     else if (USARTx == UART9)
0337     {
0338       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
0339     }
0340 #endif /* UART9 */
0341 #if defined(USART10)
0342     else if (USARTx == USART10)
0343     {
0344       periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE);
0345     }
0346 #endif /* USART10 */
0347     else
0348     {
0349       /* Nothing to do, as error code is already assigned to ERROR value */
0350     }
0351
0352     /* Configure the USART Baud Rate :
0353        - prescaler value is required
0354        - valid baud rate value (different from 0) is required
0355        - Peripheral clock as returned by RCC service, should be valid (different from 0).
0356     */
0357     if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
0358         && (USART_InitStruct->BaudRate != 0U))
0359     {
0360       status = SUCCESS;
0361       LL_USART_SetBaudRate(USARTx,
0362                            periphclk,
0363                            USART_InitStruct->PrescalerValue,
0364                            USART_InitStruct->OverSampling,
0365                            USART_InitStruct->BaudRate);
0366
0367       /* Check BRR is greater than or equal to 16d */
0368       assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
0369     }
0370
0371     /*---------------------------- USART PRESC Configuration -----------------------
0372      * Configure USARTx PRESC (Prescaler) with parameters:
0373      * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value.
0374      */
0375     LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue);
0376   }
0377   /* Endif (=> USART not in Disabled state => return ERROR) */
0378
0379   return (status);
0380 }
0381
0382 /**
0383   * @brief Set each @ref LL_USART_InitTypeDef field to default value.
0384   * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
0385   *                         whose fields will be set to default values.
0386   * @retval None
0387   */
0388
0389 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
0390 {
0391   /* Set USART_InitStruct fields to default values */
0392   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
0393   USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
0394   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
0395   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
0396   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
0397   USART_InitStruct->TransferDirection   = LL_USART_DIRECTION_TX_RX;
0398   USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
0399   USART_InitStruct->OverSampling        = LL_USART_OVERSAMPLING_16;
0400 }
0401
0402 /**
0403   * @brief  Initialize USART Clock related settings according to the
0404   *         specified parameters in the USART_ClockInitStruct.
0405   * @note   As some bits in USART configuration registers can only be written when
0406   *         the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
0407   *         this function. Otherwise, ERROR result will be returned.
0408   * @param  USARTx USART Instance
0409   * @param  USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
0410   *         that contains the Clock configuration information for the specified USART peripheral.
0411   * @retval An ErrorStatus enumeration value:
0412   *          - SUCCESS: USART registers related to Clock settings are initialized according
0413   *                     to USART_ClockInitStruct content
0414   *          - ERROR: Problem occurred during USART Registers initialization
0415   */
0416 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
0417 {
0418   ErrorStatus status = SUCCESS;
0419
0420   /* Check USART Instance and Clock signal output parameters */
0421   assert_param(IS_UART_INSTANCE(USARTx));
0422   assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
0423
0424   /* USART needs to be in disabled state, in order to be able to configure some bits in
0425      CRx registers */
0426   if (LL_USART_IsEnabled(USARTx) == 0U)
0427   {
0428     /* Ensure USART instance is USART capable */
0429     assert_param(IS_USART_INSTANCE(USARTx));
0430
0431     /* Check clock related parameters */
0432     assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
0433     assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
0434     assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
0435
0436     /*---------------------------- USART CR2 Configuration -----------------------
0437      * Configure USARTx CR2 (Clock signal related bits) with parameters:
0438      * - Clock Output:                USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
0439      * - Clock Polarity:              USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
0440      * - Clock Phase:                 USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
0441      * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
0442      */
0443     MODIFY_REG(USARTx->CR2,
0444                USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
0445                USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
0446                USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
0447   }
0448   /* Else (USART not in Disabled state => return ERROR */
0449   else
0450   {
0451     status = ERROR;
0452   }
0453
0454   return (status);
0455 }
0456
0457 /**
0458   * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
0459   * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
0460   *                              whose fields will be set to default values.
0461   * @retval None
0462   */
0463 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
0464 {
0465   /* Set LL_USART_ClockInitStruct fields with default values */
0466   USART_ClockInitStruct->ClockOutput       = LL_USART_CLOCK_DISABLE;
0467   USART_ClockInitStruct->ClockPolarity     = LL_USART_POLARITY_LOW;            /* Not relevant when ClockOutput =
0468                                                                                   LL_USART_CLOCK_DISABLE */
0469   USART_ClockInitStruct->ClockPhase        = LL_USART_PHASE_1EDGE;             /* Not relevant when ClockOutput =
0470                                                                                   LL_USART_CLOCK_DISABLE */
0471   USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT;  /* Not relevant when ClockOutput =
0472                                                                                   LL_USART_CLOCK_DISABLE */
0473 }
0474
0475 /**
0476   * @}
0477   */
0478
0479 /**
0480   * @}
0481   */
0482
0483 /**
0484   * @}
0485   */
0486
0487 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */
0488
0489 /**
0490   * @}
0491   */
0492
0493 #endif /* USE_FULL_LL_DRIVER */
0494
0495